1374HVI 概述
4.5A, 500kHz Step-Down Switching Regulator 4.5A , 500kHz的降压型开关稳压器
1374HVI 数据手册
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PDF下载LT1374
4.5A, 500kHz Step-Down
Switching Regulator
U
FEATURES
DESCRIPTIO
■
Constant 500kHz Switching Frequency
TheLT®1374isa500kHzmonolithicbuckmodeswitching
regulator. A 4.5A switch is included on the die along with
allthenecessaryoscillator,controlandlogiccircuitry.High
switchingfrequencyallowsaconsiderablereductioninthe
sizeofexternalcomponents.Thetopologyiscurrentmode
for fast transient response and good loop stability. Both
fixed output voltage and adjustable parts are available.
■
High Power 16-Pin TSSOP Package Available
■
Uses All Surface Mount Components
Inductor Size Reduced to 1.8µH
■
■
■
■
■
■
Saturating Switch Design: 0.07Ω
Effective Supply Current: 2.5mA
Shutdown Current: 20µA
Cycle-by-Cycle Current Limiting
Easily Synchronizable
Aspecialhighspeedbipolarprocessandnewdesigntech-
niquesachievehighefficiencyathighswitchingfrequency.
Efficiency is maintained over a wide output current range
by using the output to bias the circuitry and by utilizing a
supply boost capacitor to saturate the power switch.
U
APPLICATIO S
■
Portable Computers
TheLT1374isavailableinstandard7-pinDD,TO-220,fused
lead SO-8 and 16-pin exposed pad TSSOP packages. Full
cycle-by-cycle short-circuit protection and thermal shut-
downareprovided.Standardsurfacemountexternalparts
may be used, including the inductor and capacitors. There
is the optional function of shutdown or synchronization. A
shutdownsignalreducessupplycurrentto20µA.Synchro-
nizationallowsanexternallogiclevelsignaltoincreasethe
■
Battery-Powered Systems
■
Battery Chargers
Distributed Power
■
internal oscillator from 580kHz to 1MHz.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
5V Buck Converter
Efficiency vs Load Current
D2
100
CMDSH3 OR FMMD914
V
V
= 5V
OUT
IN
= 10V
95
90
85
80
75
70
L = 10µH
C2
0.27µF
L1**
5µH
BOOST
OUTPUT**
5V, 4.25A
INPUT
V
V
IN
SW
6V TO 25V
+
C3*
LT1374-5 BIAS
10µF TO
50µF
DEFAULT
= ON
SHDN
SENSE
GND
V
C
C1
+
D1
100µF, 10V
SOLID
C
C
MBRS330T3
1.5nF
TANTALUM
* RIPPLE CURRENT RATING ≥ I /2
OUT
1374 TA01
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
LOAD CURRENT (A)
** INCREASE L1 TO 10µH FOR LOAD CURRENTS ABOVE 3.5A AND TO 20µH ABOVE 4A
SEE APPLICATIONS INFORMATION
1374 TA02
1374fb
1
LT1374
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
Input Voltage
FB Pin Current (Adjustable Part)............................ 1mA
SENSE Voltage (Fixed 5V Part) ................................. 7V
SYNC Pin Voltage ..................................................... 7V
Operating Junction Temperature Range
LT1374C............................................... 0°C to 125° C
LT1374I ........................................... –40°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
LT1374 ............................................................... 25V
LT1374HV .......................................................... 32V
BOOST Pin Voltage ................................................. 38V
BOOST Pin Above Input Voltage ............................. 15V
SHDN Pin Voltage..................................................... 7V
BIAS Pin Voltage ...................................................... 7V
FB Pin Voltage (Adjustable Part)............................ 3.5V
U W
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PACKAGE/ORDER I FOR ATIO
ORDER
PART NUMBER
ORDER
PART NUMBER
FRONT VIEW
7
6
5
4
3
2
1
FB OR SENSE*
BOOST
LT1374CR
LT1374CS8
V
TAB
IS
IN
LT1374CR-5
LT1374CR-SYNC
LT1374CS8-5
LT1374CS8-SYNC
GND
GND
V
SW
SYNC OR SHDN*
TOP VIEW
V
C
LT1374CR-5 SYNC
LT1374HVCR
LT1374IR
LT1374CS8-5 SYNC
R PACKAGE
7-LEAD PLASTIC DD
1
2
3
4
8
7
6
5
V
V
SW
SYNC
OR SHDN*
IN
LT1374HVCS8
LT1374IS8
BOOST
FB OR
SENSE*
TJMAX = 125°C, θJA = 30°C/ W
V
C
WITH PACKAGE SOLDERED TO 0.5 SQUARE INCH
COPPER AREA OVER BACKSIDE GROUND PLANE
OR INTERNAL POWER PLANE. θJA CAN VARY
FROM 20°C/W TO >40°C/W DEPENDING ON
MOUNTING TECHNIQUES
LT1374IR-5
LT1374IS8-5
FGND
BIAS
LT1374IR-SYNC
LT1374IR-5 SYNC
LT1374HVIR
LT1374IS8-SYNC
LT1374IS8-5 SYNC
LT1374HVIS8
S8 PACKAGE
8-LEAD PLASTIC SO
θJA = 80°C/ W WITH FUSED (FGND)
GROUND PIN CONNECTED TO GROUND
PLANE OR LARGE LANDS
ORDER
PART NUMBER
S8 PART MARKING
TOP VIEW
1374
13745
1374I
1374I5
GND
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
LT1374CFE
LT1374IFE
V
SW
1374SN 374ISN
3745SN 74I5SN
1374HV 1374HVI
V
V
SW
IN
V
IN
SYNC
SHDN
BOOST
FB/SENSE
NC
V
C
TAB IS
GND
ORDER
PART NUMBER
FRONT VIEW
BIAS
GND
FB OR SENSE*
7
6
5
4
3
2
1
GND
BOOST
V
IN
FE16 PACKAGE
16-LEAD PLASTIC TSSOP
LT1374CT7
LT1374CT7-5
LT1374IT7
GND
V
SW
SHDN
θJA = 40°C/ W
EXPOSED PAD SOLDERED TO
GROUND PLANE
V
C
T7 PACKAGE
7-LEAD PLASTIC TO-220
LT1374IT7-5
TJMAX = 125°C, θJA = 50°C/ W, θJC = 4°C/ W
*Default is the adjustable output voltage device with FB pin and shutdown function. Option -5 replaces FB with SENSE pin for fixed 5V output applications.
-SYNC replaces SHDN with SYNC pin for applications requiring synchronization. Consult LTC Marketing for parts specified with wider operating
temperature ranges.
1374fb
2
LT1374
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating tempera-
ture range, otherwise specifications are at TJ = 25°C. VIN = 15V, VC = 1.5V, Boost = VIN + 5V, switch open, unless otherwise noted.
PARAMETER
CONDITIONS
All Conditions
All Conditions
MIN
TYP
MAX
UNITS
Feedback Voltage (Adjustable)
2.39
2.36
2.42
2.45
2.48
V
V
●
●
Sense Voltage (Fixed 5V)
4.94
4.90
5.0
5.06
5.10
V
V
SENSE Pin Resistance
7
10
14
kΩ
Reference Voltage Line Regulation
5V ≤ V ≤ 25V (5V ≤ V ≤ 32V for LT1374HV)
0.01
0.03
%/V
IN
IN
Feedback Input Bias Current
Error Amplifier Voltage Gain
Error Amplifier Transconductance
●
●
0.5
400
2
µA
(Notes 2, 8)
200
∆I (V ) = ±10µA (Note 8)
1500
1000
2000
2700
3100
µMho
µMho
C
V Pin to Switch Current Transconductance
5.3
225
225
0.9
2.1
6
A/V
µA
µA
V
C
Error Amplifier Source Current
Error Amplifier Sink Current
V
V
= 2.1V or V
= 2.7V or V
= 4.4V
= 5.6V
●
●
140
140
320
320
FB
SENSE
FB
SENSE
V Pin Switching Threshold
C
Duty Cycle = 0
V Pin High Clamp
C
V
Switch Current Limit
V Open, V = 2.1V or V
C
= 4.4V, DC ≤ 50%
●
4.5
8.5
A
FB
SENSE
Slope Compensation (Note 9)
Switch On Resistance (Note 7)
DC = 80%
0.8
0.07
A
I
= 4.5A
0.1
Ω
Ω
SW
●
●
0.13
Maximum Switch Duty Cycle
Switch Frequency
V
FB
= 2.1V or V
= 4.4V
90
86
93
93
%
%
SENSE
V Set to Give 50% Duty Cycle
C
460
440
500
540
560
kHz
kHz
●
●
●
●
●
Switch Frequency Line Regulation
Frequency Shifting Threshold on FB Pin
Minimum Input Voltage (Note 3)
Minimum Boost Voltage (Note 4)
Boost Current (Note 5)
5V ≤ V ≤ 25V, (5V ≤ V ≤ 32V for LT1374HV)
0
0.15
1.3
5.5
3.0
%/V
V
IN
IN
∆f = 10kHz
0.8
1.0
5.0
2.3
V
I
≤ 4.5A
V
SW
I
I
= 1A
= 4.5A
●
●
20
90
35
140
mA
mA
SW
SW
V
Supply Current (Note 6)
V
BIAS
V
BIAS
V
SHDN
= 5V
= 5V
●
●
0.9
3.2
20
1.4
4.0
mA
mA
IN
BIAS Supply Current (Note 6)
Shutdown Supply Current
= 0V, V ≤ 25V, V = 0V, V Open
50
75
µA
µA
IN
SW
C
●
V
= 0V, V ≤ 32V, V = 0V, V Open
30
75
µA
µA
SHDN
IN
SW
C
●
●
100
Lockout Threshold
V Open
C
2.3
2.38
2.46
V
Shutdown Thresholds
V Open Device Shutting Down
●
●
0.13
0.25
0.37
0.45
0.60
0.7
V
V
C
Device Starting Up
Synchronization Threshold
Synchronizing Range
●
1.5
2.2
V
kHz
kΩ
580
1000
SYNC Pin Input Resistance
40
regulated so that the reference voltage and oscillator frequency remain
constant. Actual minimum input voltage to maintain a regulated output will
depend on output voltage and load current. See Applications Information.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Gain is measured with a V swing equal to 200mV above the
C
switching threshold level to 200mV below the upper clamp level.
Note 3: Minimum input voltage is not measured directly, but is guaranteed
by other tests. It is defined as the voltage where internal bias lines are still
1374fb
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LT1374
ELECTRICAL CHARACTERISTICS
Note 5: Boost current is the current flowing into the boost pin with the pin
Note 8: Transconductance and voltage gain refer to the internal amplifier
exclusive of the voltage divider. To calculate gain and transconductance,
refer to the SENSE pin on the fixed voltage parts. Divide values shown by
held 5V above input voltage. It flows only during switch on time.
Note 6: V supply current is the current drawn when the BIAS pin is held
IN
the ratio V /2.42.
at 5V and switching is disabled. If the BIAS pin is unavailable or open
OUT
circuit, the sum of V and BIAS supply currents will be drawn by the V
Note 9: Slope compensation is the current subtracted from the switch
current limit at 80% duty cycle. See Maximum Output Load Current in the
Applications Information section for further details.
IN
IN
pin.
Note 7: Switch on resistance is calculated by dividing V to V voltage
IN
SW
by the forced current (4.5A). See Typical Performance Characteristics for
the graph of switch voltage at other currents.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Switch Voltage Drop
Switch Peak Current Limit
Feedback Pin Voltage
2.430
2.425
2.420
2.415
2.410
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
500
450
400
350
300
250
200
150
100
50
125°C
25°C
TYPICAL
MINIMUM
–40°C
0
–25
0
25
50
75
125
2
–50
100
0
1
3
4
5
0
20
80
100
40
60
DUTY CYCLE (%)
TEMPERATURE (°C)
SWITCH CURRENT (A)
1374 G03
1374 G18
1374 G02
Shutdown Pin Bias Current
Standby and Shutdown Thresholds
Shutdown Supply Current
25
20
500
400
300
200
8
2.40
2.36
2.32
0.8
V
= 0V
SHDN
CURRENT REQUIRED TO FORCE SHUTDOWN
(FLOWS OUT OF PIN). AFTER SHUTDOWN,
CURRENT DROPS TO A FEW µA
STANDBY
15
10
5
START-UP
AT 2.38V STANDBY THRESHOLD
(CURRENT FLOWS OUT OF PIN)
0.4
4
SHUTDOWN
0
0
0
0
5
10
15
20
25
50
TEMPERATURE (°C)
100 125
50
100 125
–50 –25
0
25
75
–50 –25
0
25
75
INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
1374 G06
1374 G04
1374 G05
1374fb
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LT1374
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Supply Current
Error Amplifier Transconductance
Error Amplifier Transconductance
2500
2000
1500
1000
500
70
60
50
40
30
20
10
0
3000
2500
2000
1500
1000
500
200
150
100
50
PHASE
V
IN
= 25V
GAIN
V
IN
= 10V
V
C
C
OUT
12pF
R
OUT
200k
–3
V
2 × 10
(
)
FB
ERROR AMPLIFIER EQUIVALENT CIRCUIT
= 50Ω
0
R
LOAD
0
–50
–50 –25
0
25
50
75 100 125
1k
1M
0
0.1
0.2
SHUTDOWN VOLTAGE (V)
0.3
0.4
100
10k 100k
FREQUENCY (Hz)
10M
JUNCTION TEMPERATURE (°C)
1374 G09
1374 G07
1374 G08
Minimum Input Voltage
with 5V Output
Frequency Foldback
Switching Frequency
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
550
500
400
300
200
100
0
540
530
520
510
500
490
480
470
460
450
MINIMUM
STARTING
VOLTAGE
SWITCHING
FREQUENCY
MINIMUM
RUNNING
VOLTAGE
FEEDBACK PIN
CURRENT
1
10
100
1000
–25
0
25
50
75
125
–50
100
0
0.5
1.0
1.5
2.0
2.5
LOAD CURRENT (mA)
TEMPERATURE (°C)
FEEDBACK PIN VOLTAGE (V)
1374 G12
1374 G11
1374 G10
Maximum Load Current
at VOUT = 10V
Maximum Load Current
at VOUT = 3.3V
Maximum Load Current
at VOUT = 5V
4.5
4.0
3.5
3.0
4.5
4.0
3.5
3.0
4.5
4.0
3.5
3.0
L = 20µH
V
OUT
= 10V
L = 20µH
L = 20µH
L = 10µH
L = 10µH
L = 10µH
L = 5µH
L = 5µH
L = 5µH
V
OUT
= 3.3V
5
V
OUT
= 5V
5
0
5
10
INPUT VOLTAGE (V)
15
20
25
0
10
INPUT VOLTAGE (V)
15
20
25
0
10
15
20
25
INPUT VOLTAGE (V)
1374 G13
1374 G14
1374 G15
1374fb
5
LT1374
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VC Pin Shutdown Threshold
BOOST Pin Current
Inductor Core Loss
100
1.0
0.1
20
12
8
1.4
DUTY CYCLE = 100%
V
= 5V, V = 10V, I
= 1A
OUT
SHUTDOWN
IN
OUT
90
80
70
60
50
40
30
20
10
0
1.2
1.0
0.8
0.6
0.4
4
2
1.2
0.8
TYPE 52
POWDERED IRON
Kool Mµ®
0.4
PERMALLOY
µ = 125
0.2
0.01
0.001
CORE LOSS IS
INDEPENDENT OF LOAD
CURRENT UNTIL LOAD CURRENT FALLS
LOW ENOUGH FOR CIRCUIT TO GO INTO
DISCONTINUOUS MODE
0.12
0.08
0.04
0.02
3
0
1
2
4
5
0
5
10
15
20
25
–25
0
25
50
75
125
–50
100
SWITCH CURRENT (A)
INDUCTANCE (µH)
JUNCTION TEMPERATURE (°C)
1374 G16
1374 G11
1374 G01
U
U
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PI FU CTIO S
FB/SENSE: The feedback pin is the input to the error
amplifier which is referenced to an internal 2.42V source.
An external resistive divider is used to set the output
voltage. The fixed voltage (-5) parts have the divider
included on-chip and the FB pin is used as a SENSE pin,
connected directly to the 5V output. Three additional
functions are performed by the FB pin. When the pin
voltage drops below 1.7V, switch current limit is reduced.
Below 1.5V the external sync function is disabled. Below
1V,switchingfrequencyisalsoreduced.SeeFeedbackPin
Function section in Applications Information for details.
pins of the 16-lead TSSOP package must be shorted
together on the PC board.
GND: The GND pin connection needs consideration for
tworeasons. First, itactsasthereferencefortheregulated
output, so load regulation will suffer if the “ground” end of
the load is not at the same voltage as the GND pin of the
IC. This condition will occur when load current or other
currents flow through metal paths between the GND pin
and the load ground point. Keep the ground path short
between the GND pin and the load and use a ground plane
when possible. The second consideration is EMI caused
by GND pin current spikes. Internal capacitance between
the VSW pin and the GND pin creates very narrow (<10ns)
current spikes in the GND pin. If the GND pin is connected
to system ground with a long metal trace, this trace may
radiate excess EMI. Keep the path between the input
bypass and the GND pin short.
BOOST: The BOOST pin is used to provide a drive voltage,
higher than the input voltage, to the internal bipolar NPN
power switch. Without this added voltage, the typical
switch voltage loss would be about 1.5V. The additional
boost voltage allows the switch to saturate and voltage
loss approximates that of a 0.07Ω FET structure. Effi-
ciency improves from 75% for conventional bipolar de-
signs to > 89% for these new parts.
V
SW: The switch pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the switch
pin negative during switch off time. Negative voltage is
clampedwiththeexternalcatchdiode. Maximumnegative
switch voltage allowed is –0.8V. Both VSW pins of the
16-lead TSSOP package must be shorted together on the
PC board.
VIN: This is the collector of the on-chip power NPN switch.
Thispinpowerstheinternalcircuitryandinternalregulator
whentheBIASpinisnotpresent.AtNPNswitchonandoff,
high dI/dt edges occur on this pin. Keep the external
bypass and catch diode close to this pin. All trace induc-
tance on this path will create a voltage spike at switch off,
addingtotheVCE voltageacrosstheinternalNPN.BothVIN
1374fb
6
LT1374
U
U
U
PI FU CTIO S
SYNC: (Excludes T7 package) The sync pin is used to
synchronize the internal oscillator to an external signal. It
is directly logic compatible and can be driven with any
signal between 10% and 90% duty cycle. The synchroniz-
ing range is equal to initial operating frequency, up to
1MHz.ThispinreplacesSHDNon-SYNCoptionparts.See
Synchronizing section in Applications Information for
details.
used for frequency compensation, but can do double duty
as a current clamp or control loop override. This pin sits
at about 1V for very light loads and 2V at maximum load.
It can be driven to ground to shut off the regulator, but if
driven high, current must be limited to 4mA.
BIAS: (SO-8 and FE16 Packages) The BIAS pin is used to
improve efficiency when operating at higher input volt-
ages and light load current. Connecting this pin to the
regulated output voltage forces most of the internal cir-
cuitrytodrawitsoperatingcurrentfromtheoutputvoltage
rather than the input supply. This is a much more efficient
way of doing business if the input voltage is much higher
than the output. Minimum output voltage setting for this
mode of operation is 3.3V. Efficiency improvement at
VIN = 20V, VOUT = 5V, and IOUT = 25mA is over 10%.
SHDN: The shutdown pin is used to turn off the regulator
and to reduce input drain current to a few microamperes.
Actually, this pin has two separate thresholds, one at
2.38V to disable switching, and a second at 0.4V to force
complete micropower shutdown. The 2.38V threshold
functions as an accurate undervoltage lockout (UVLO).
This can be used to prevent the regulator from operating
until the input voltage has reached a predetermined level.
NC: No Connect. Leave floating or solder to any node.
VC: The VC pin is the output of the error amplifier and the
input of the peak switch current comparator. It is normally
W
BLOCK DIAGRA
The LT1374 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
twofeedbackloopsthatcontrolthedutycycleofthepower
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscilla-
tor pulse which sets the RS flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
itmucheasiertofrequencycompensatethefeedbackloop
and also gives much quicker transient response.
Most of the circuitry of the LT1374 operates from an
internal 2.9V bias line. The bias regulator normally draws
power from the regulator input pin, but if the BIAS pin is
connected to an external voltage higher than 3V, bias
powerwillbedrawnfromtheexternalsource(typicallythe
regulated output voltage). This will improve efficiency if
the BIAS pin voltage is lower than regulator input voltage.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
thantheinputvoltage,allowingtheswitchtosaturate.This
boosted voltage is generated with an external capacitor
and diode. Two comparators are connected to the shut-
down pin. One has a 2.38V threshold for undervoltage
lockout and the second has a 0.4V threshold for complete
shutdown.
1374fb
7
LT1374
W
BLOCK DIAGRA
0.01Ω
INPUT
+
–
CURRENT
SENSE
2.9V BIAS
REGULATOR
INTERNAL
CC
BIAS*
AMPLIFIER
VOLTAGE GAIN = 20
V
SLOPE COMP
BOOST
Σ
0.9V
500kHz
OSCILLATOR
S
R
SYNC
Q1
POWER
SWITCH
R
DRIVER
CIRCUITRY
CURRENT
COMPARATOR
S
FLIP-FLOP
+
–
SHUTDOWN
COMPARATOR
–
+
V
SW
0.4V
FREQUENCY
SHDN
SHIFT CIRCUIT
3.5µA
FOLDBACK
CURRENT
LIMIT
Q2
+
–
CLAMP
–
FB
LOCKOUT
COMPARATOR
+
ERROR
V
C
AMPLIFIER
2.38V
2.42V
g
= 2000µMho
m
GND
*BIAS PIN IS AVAILABLE ONLY ON THE S0-8 AND FE16 PACKAGES
1374 BD
Figure 1. Block Diagram
W U U
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APPLICATIO S I FOR ATIO
FEEDBACK PIN FUNCTIONS
Please read the following if divider resistors are increased
above the suggested values.
The feedback (FB) pin on the LT1374 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design. The fixed 5V LT1374-5 has internal divider resis-
tors and the FB pin is renamed SENSE, connected directly
to the output.
R2 V − 2.42
(
)
OUT
R1=
2.42
Table 1
OUTPUT
VOLTAGE
(V)
R1
(NEAREST 1%)
(k
% ERROR AT OUTPUT
DUE TO DISCREET 1%
RESISTOR STEPS
R2
(k
Ω
4.99
4.99
4.99
4.99
4.99
4.99
4.99
4.99
)
Ω)
3
3.3
5
1.21
1.82
5.36
7.32
11.5
15.8
19.6
26.1
+0.23
+0.08
+0.39
–0.5
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
6
8
–0.04
+0.83
–0.62
+0.52
10
12
15
1374fb
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More Than Just Voltage Feedback
foldback operation. Again, it is nearly transparent to the
userundernormalloadconditions.Theonlyloadsthatmay
be affected are current source loads which maintain full
loadcurrentwithoutputvoltagelessthan50%offinalvalue.
In these rare situations the feedback pin can be clamped
above 1.5V with an external diode to defeat foldback cur-
rent limit. Caution: clamping the feedback pin means that
frequency shifting will also be defeated, so a combination
of high input voltage and dead shorted output may cause
the LT1374 to lose control of current limit.
The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
ThisisdonetocontrolpowerdissipationinboththeICand
in the external diode and inductor during short-circuit
conditions. A shorted output requires the switching regu-
lator to operate at very low duty cycles, and the average
current through the diode and inductor is equal to the
short-circuitcurrentlimitoftheswitch(typically6Aforthe
LT1374, foldingbacktolessthan3A). Minimumswitchon
time limitations would prevent the switcher from attaining
a sufficiently low duty cycle if switching frequency were
maintained at 500kHz, so frequency is reduced by about
5:1 when the feedback pin voltage drops below 1V (see
FrequencyFoldbackgraph). Thisdoesnotaffectoperation
with normal load conditions; one simply sees a gear shift
in switching frequency during start-up as the output
voltage rises.
The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 1V, Q1 begins to
conduct current and reduces frequency at the rate of
approximately 5kHz/µA. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pull 150µA out of the FB pin with 0.6V on the pin (RDIV
≤ 4k). The net result is that reductions in frequency and
current limit are affected by output voltage divider imped-
ance. Although divider impedance is not critical, caution
should be used if resistors are increased beyond the
suggested values and short-circuit conditions will occur
with high input voltage. High frequency pickup will
increase and the protection accorded by frequency and
current foldback will decrease.
In addition to lower switching frequency, the LT1374 also
operates at lower switch current limit when the feedback
pin voltage drops below 1.7V. Q2 in Figure 2 performs this
function by clamping the VC pin to a voltage less than its
normal 2.1V upper clamp level. This foldback current limit
greatly reduces power dissipation in the IC, diode and
inductorduringshort-circuitconditions.Externalsynchro-
nization is also disabled to prevent interference with
LT1374
V
SW
TO FREQUENCY
OUTPUT
5V
SHIFTING
1.6V
Q1
ERROR
AMPLIFIER
2.4V
+
R1
R3
1k
R4
1k
FB
+
–
R5
5k
Q2
R2
5k
TO SYNC CIRCUIT
V
C
GND
1374 F02
Figure 2. Frequency and Current Limit Foldback
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MAXIMUM OUTPUT LOAD CURRENT
Note that there is less load current available at the higher
input voltage because inductor ripple current increases.
This is not always the case. Certain combinations of
inductor value and input voltage range may yield lower
available load current at the lowest input voltage due to
reduced peak switch current at high duty cycles. If load
current is close to the maximum available, please check
maximum available current at both input voltage
extremes. To calculate actual peak switch current with a
given set of conditions, use:
Maximum load current for a buck converter is limited by
the maximum switch current rating (IP) of the LT1374.
This current rating is 4.5A up to 50% duty cycle (DC),
decreasing to 3.7A at 80% duty cycle. This is shown
graphically in Typical Performance Characteristics and as
shown in the formula below:
IP = 4.5A for DC ≤ 50%
IP = 3.21 + 5.95(DC) – 6.75(DC)2 for 50% < DC < 90%
DC = Duty cycle = VOUT/VIN
VOUT V − V
(
)
IN
OUT
Example: with VOUT = 5V, VIN = 8V; DC = 5/8 = 0.625, and;
ISW(MAX) = 3.21 + 5.95(0.625) – 6.75(0.625)2 = 4.3A
ISW PEAK =IOUT
+
(
)
2 L f V
( )( )( )
IN
For lighter loads where discontinuous operation can be
used, maximum load current is equal to:
Current rating decreases with duty cycle because the
LT1374hasinternalslopecompensationtopreventcurrent
mode subharmonic switching. For more details, read Ap-
plicationNote19.TheLT1374isalittleunusualinthisregard
because it has nonlinear slope compensation which gives
better compensation with less reduction in current limit.
2
I
f L V
IN
( ) ( )( )(
)
P
IOUT(MAX)
=
Discontinuous mode 2 V
V − V
(
)(
)
OUT
IN
OUT
Example: with L = 1.2µH, VOUT = 5V, and VIN(MAX) = 15V,
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
finite inductor size, maximum load current is reduced by
one-half peak-to-peak inductor current. The following
formula assumes continuous mode operation, implying
that the term on the right is less than one-half of IP.
2
4.5 500 •103 1.2 •10−6 15
(
)
( )
IOUT MAX
=
= 1.82A
(
)
2 5 15 − 5
( )(
)
The main reason for using such a tiny inductor is that it is
physically very small, but keep in mind that peak-to-peak
inductorcurrentwillbeveryhigh. Thiswillincreaseoutput
ripplevoltage.Iftheoutputcapacitorhastobemadelarger
to reduce ripple voltage, the overall circuit could actually
wind up larger.
V
V − V
IN OUT
(
OUT)(
)
IOUT(MAX)
=
IP −
Continuous Mode
2 L f V
( )( )( )
IN
For the conditions above and L = 3.3µH,
5 8 − 5
( )(
)
CHOOSING THE INDUCTOR AND OUTPUT CAPACITOR
IOUT MAX) = 4.3 −
(
2 3.3 •10−6 500•103
8
( )
For most applications the output inductor will fall in the
range of 3µH to 20µH. Lower values are chosen to reduce
physical size of the inductor. Higher values allow more
output current because they reduce peak current seen by
the LT1374 switch, which has a 4.5A limit. Higher values
also reduce output ripple voltage, and reduce core loss.
GraphsintheTypicalPerformanceCharacteristicssection
show maximum output load current versus inductor size
andinputvoltage. Asecondgraphshowscorelossversus
=4.3 − 0.57= 3.73A
AtVIN =15V, dutycycleis33%, soIP isjustequaltoafixed
4.5A, and IOUT(MAX) is equal to:
5 15 − 5
( )(
)
4.5 −
2 3.3 •10−6 500•103 15
( )
= 4.5 −1= 3.5A
inductor size for various core materials.
1374fb
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core next to a magnetic storage media, for instance!
Thisisatoughdecisionbecausetherodsorbarrelsare
temptingly cheap and small and there are no helpful
guidelines to calculate when the magnetic field radia-
tion will be a problem.
When choosing an inductor you might have to consider
maximum load current, core and copper losses, allowable
component height, output voltage ripple, EMI, fault cur-
rent in the inductor, saturation, and of course, cost. The
following procedure is suggested as a way of handling
thesesomewhatcomplicatedandconflictingrequirements.
4. Start shopping for an inductor (see representative
surface mount units in Table 2) which meets the
requirements of core shape, peak current (to avoid
1. Choose a value in microhenries from the graphs of
maximumloadcurrentandcoreloss.Choosingasmall
inductor may result in discontinuous mode operation
at lighter loads, but the LT1374 is designed to work
well in either mode. Keep in mind that lower core loss
means higher cost, at least for closed core geometries
like toroids. The core loss graphs show both absolute
lossandpercentlossfora5Woutput,soactualpercent
losses must be calculated for each situation.
Table 2
SERIES
RESIS-
CORE
MATER- HEIGHT
IAL
VENDOR/
PART NO.
VALUE
DC
CORE
(
µ
H) (Amps) TYPE TANCE(
Ω
)
(mm)
Coiltronics
CTX2-1
2
4.1
4.4
3.5
3.4
4.6
3.3
Tor
Tor
Tor
Tor
Tor
Tor
0.011
KMµ
KMµ
KMµ
52
4.2
6.4
6.4
4.2
4.8
6.4
CTX5-4
5
8
2
2
5
0.019
0.020
0.014
0.012
0.027
CTX8-4
Assume that the average inductor current is equal to
load current and decide whether or not the inductor
must withstand continuous fault conditions. If maxi-
mum load current is 0.5A, for instance, a 0.5A inductor
may not survive a continuous 4.5A overload condition.
Dead shorts will actually be more gentle on the induc-
tor because the LT1374 has foldback current limiting.
CTX2-1P
CTX2-3P
52
CTX5-4P
52
Sumida
CDRH125
CDRH125
CDRH125
CDRH125
Coilcraft
10
12
15
18
4.0
3.5
3.3
3.0
SC
SC
SC
SC
0.025
0.027
0.030
0.034
Fer
Fer
Fer
Fer
6
6
6
6
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be significantly higher than output current, espe-
cially with smaller inductors and lighter loads, so don’t
omit this step. Powdered iron cores are forgiving
because they saturate softly, whereas ferrite cores
saturate abruptly. Other core materials fall somewhere
in between. The following formula assumes continu-
ous mode of operation, but it errs only slightly on the
high side for discontinuous mode, so it can be used for
all conditions.
DT3316-222
DT3316-332
DT3316-472
Pulse
2.2
3.3
4.7
5
5
3
SC
SC
SC
0.035
0.040
0.045
Fer
Fer
Fer
5.1
5.1
5.1
PE-53650
PE-53651
PE-53652
PE-53653
Dale
4
5
4.8
5.4
5.5
5.1
Tor
Tor
Tor
Tor
0.017
0.018
0.022
0.032
Fer
Fer
Fer
Fer
9.1
9.1
10
9
16
10
VOUT V − V
(
)
IN
OUT
IHSM-4825
IHSM-4825
IHSM-5832
IHSM-5832
IHSM-7832
Tor = Toroid
2.7
4.7
10
5.1
4.0
4.3
3.5
3.8
Open
Open
Open
Open
Open
0.034
0.047
0.053
0.078
0.054
Fer
Fer
Fer
Fer
Fer
5.6
5.6
7.1
7.1
7.1
IPEAK =IOUT +
2 f L V
( )( )( )
IN
VIN = Maximum input voltage
f = Switching frequency, 500kHz
15
22
3. Decide if the design can tolerate an “open” core geom-
etry like a rod or barrel, with high magnetic field
radiation, orwhetheritneedsaclosedcorelikeatoroid
to prevent EMI problems. One would not want an open
SC = Semi-closed geometry
Fer = Ferrite core material
52 = Type 52 powdered iron core material
KMµ = Kool Mµ
1374fb
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saturation),averagecurrent(tolimitheating),andfault
current(iftheinductorgetstoohot, wireinsulationwill
melt and cause turn-to-turn shorts). Keep in mind that
allgoodthingslikehighefficiency,lowprofile,andhigh
temperature operation will increase cost, sometimes
dramatically. Get a quote on the cheapest unit first to
calibrate yourself on price, then ask for what you really
want.
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true, and type TPS capacitors are
speciallytestedforsurgecapability,butsurgeruggedness
is not a critical issue with the output capacitor. Solid
tantalum capacitors fail during very high turn-on surges,
which do not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead shorted, do not harm the capacitors.
5. After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the Linear Technology’s applica-
tions department if you feel uncertain about the final
choice. They have experience with a wide range of
inductor types and can tell you about the latest devel-
opments in low profile, surface mounting, etc.
Unlike the input capacitor, RMS ripple current in the
output capacitor is normally low enough that ripple cur-
rent rating is not an issue. The current waveform is
triangular with a typical value of 200mARMS. The formula
to calculate this is:
Output Capacitor Ripple Current (RMS):
Output Capacitor
0.29 V
V − V
IN OUT
(
OUT)(
)
The output capacitor is normally chosen by its Effective
Series Resistance (ESR), because this is what determines
output ripple voltage. At 500kHz, any polarized capacitor
is essentially resistive. To get low ESR takes volume, so
physically smaller capacitors have high ESR. The ESR
range for typical LT1374 applications is 0.05Ω to 0.2Ω. A
typical output capacitor is an AVX type TPS, 100µF at 10V,
with a guaranteed ESR less than 0.1Ω. This is a “D” size
surface mount solid tantalum capacitor. TPS capacitors
are specially constructed and tested for low ESR, so they
give the lowest ESR for a given volume. The value in
microfarads is not particularly critical, and values from
22µF to greater than 500µF work well, but you cannot
cheat mother nature on ESR. If you find a tiny 22µF solid
tantalumcapacitor, itwillhavehighESR, andoutputripple
voltage will be terrible. Table 3 shows some typical solid
tantalum surface mount capacitors.
IRIPPLE RMS
=
(
)
L f V
( )( )( )
IN
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becomingavailableinsmallercasesizes.Thesearetempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor’s ESR
generatesaloop“zero”at5kHzto50kHzthatisinstrumen-
tal in giving acceptable loop phase margin. Ceramic
capacitors remain capacitive to beyond 300kHz and usu-
allyresonatewiththeirESLbeforeESRbecomeseffective.
They are appropriate for input bypassing because of their
highripplecurrentratingsandtoleranceofturn-onsurges.
Linear Technology plans to issue a design note on the use
of ceramic capacitors in the near future.
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
OUTPUT RIPPLE VOLTAGE
E Case Size
ESR (Max.,
Ω
)
Ripple Current (A)
0.7 to 1.1
0.4
AVX TPS, Sprague 593D
AVX TAJ
0.1 to 0.3
0.7 to 0.9
Figure 3 shows a typical output ripple voltage waveform
for the LT1374. Ripple voltage is determined by the high
frequency impedance of the output capacitor, and ripple
current through the inductor. Peak-to-peak ripple current
through the inductor into the output capacitor is:
D Case Size
AVX TPS, Sprague 593D
C Case Size
0.1 to 0.3
0.2 (typ)
0.7 to 1.1
0.5 (typ)
AVX TPS
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CATCH DIODE
V
V − V
IN OUT
(
OUT)(
)
IP-P
=
The suggested catch diode (D1) is a 1N5821 Schottky, or
its Motorola equivalent, MBR330. It is rated at 3A average
forward current and 30V reverse voltage. Typical forward
voltage is 0.5V at 3A. The diode conducts current only
during switch off time. Peak reverse voltage is equal to
regulatorinputvoltage.Averageforwardcurrentinnormal
operation can be calculated from:
V
L f
( )( )( )
IN
For high frequency switchers, the sum of ripple current
slew rates may also be relevant and can be calculated
from:
dI
dt
V
IN
L
Σ
=
IOUT V − V
(
)
IN
OUT
IDAVG
=
Peak-to-peak output ripple voltage is the sum of a triwave
created by peak-to-peak ripple current times ESR, and a
square wave created by parasitic inductance (ESL) and
ripple current slew rate. Capacitive reactance is assumed
to be small compared to ESR or ESL.
V
IN
This formula will not yield values higher than 3A with
maximumloadcurrentof4.25Aunlesstheratioofinputto
output voltage exceeds 3.4:1. The only reason to consider
a larger diode is the worst-case condition of a high input
voltageandoverloaded(notshorted)output. Undershort-
circuit conditions, foldback current limit will reduce diode
current to less than 2.6A, but if the output is overloaded
anddoesnotfalltolessthan1/3ofnominaloutputvoltage,
foldback will not take effect. With the overloaded condi-
tion, output current will increase to a typical value of 5.7A,
determined by peak switch current limit of 6A. With
VIN = 15V, VOUT = 4V (5V overloaded) and IOUT = 5.7A:
dI
dt
VRIPPLE = I
ESR + ESL Σ
(
P-P)(
) (
)
Example: withVIN =10V,VOUT =5V,L=10µH,ESR=0.1Ω,
ESL = 10nH:
5 10 − 5
( )(
)
IP-P
=
= 0.5A
10 10 •10−6 500 •103
( )
5.7 15 − 4
(
)
dI
dt
10
Σ
=
= 106
I
=
= 4.18A
D AVG
(
)
10 •10−6
15
VRIPPLE = 0.5A 0.1 + 10 •10−9 106
This is safe for short periods of time, but it would be
prudent to check with the diode manufacturer if continu-
ous operation under these conditions must be tolerated.
(
)(
)
= 0.05 + 0.01= 60mVP-P
BOOST PIN CONSIDERATIONS
Formostapplications, theboostcomponentsarea0.27µF
capacitor and a FMMD914 diode. The anode is connected
to the regulated output voltage and this generates a
voltage across the boost capacitor nearly identical to the
regulated output. In certain applications, the anode may
instead be connected to the unregulated input voltage.
This could be necessary if the regulated output voltage is
very low (< 3V) or if the input voltage is less than 5V.
Efficiency is not affected by the capacitor value, but the
capacitor should have an ESR of less than 1Ω to ensure
1374fb
V
OUT AT
IOUT = 1A
20mV/DIV
0.5A/DIV
V
OUT AT
IOUT = 50mA
INDUCTOR
CURRENT
AT IOUT = 1A
INDUCTOR
CURRENT
AT IOUT = 50mA
0.5µs/DIV
1374 F03
Figure 3. LT1374 Ripple Voltage Waveform
13
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that it can be recharged fully under the worst-case condi-
tion of minimum input voltage. Almost any type of film or
ceramic capacitor will work fine.
I
/50 VOUT / V
(
)(
)
OUT
IN
CMIN
=
f V −3V
( )(
)
OUT
WARNING! Peak voltage on the BOOST pin is the sum of
unregulated input voltage plus the voltage across the
boost capacitor. This normally means that peak BOOST
pin voltage is equal to input voltage plus output voltage,
but when the boost diode is connected to the regulator
input, peak BOOST pin voltage is equal to twice the input
voltage. Be sure that BOOST pin voltage does not exceed
its maximum rating.
f = Switching frequency
VOUT = Regulated output voltage
VIN = Minimum input voltage
This formula can yield capacitor values substantially less
than 0.27µF, but it should be used with caution since it
does not take into account secondary factors such as
capacitor series resistance, capacitance shift with tem-
perature and output overload.
For nearly all applications, a 0.27µF boost capacitor works
just fine, but for the curious, more details are provided
here. The size of the boost capacitor is determined by
switch drive current requirements. During switch on time,
draincurrentonthecapacitorisapproximatelyIOUT/50.At
peakloadcurrentof4.25A,thisgivesatotaldrainof85mA.
Capacitor ripple voltage is equal to the product of on time
and drain current divided by capacitor value;
∆V = (tON)(85mA/C). To keep capacitor ripple voltage to
less than 0.6V (a slightly arbitrary number) at the worst-
case condition of tON = 1.8µs, the capacitor needs to be
0.27µF. Boost capacitor ripple voltage is not a critical
parameter, but if the minimum voltage across the capaci-
tor drops to less than 3V, the power switch may not
saturate fully and efficiency will drop. An approximate
formula for absolute minimum capacitor value is:
SHUTDOWN FUNCTION AND
UNDERVOLTAGE LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1374. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
loadtothesourceandcancausethesourcetocurrentlimit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
R
FB
LT1374
IN
OUTPUT
V
SW
INPUT
2.38V
+
–
STANDBY
R
HI
3.5µA
+
SHDN
+
–
TOTAL
SHUTDOWN
R
LO
C1
0.4V
GND
1374 F04
Figure 4. Undervoltage Lockout
1374fb
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input rises back to 13.5V. ∆V is therefore 1.5V and
Threshold voltage for lockout is about 2.38V, slightly less
than the internal 2.42V reference voltage. A 3.5µA bias
current flows out of the pin at threshold. This internally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shut-
down current is not an issue, the error due to this current
can be minimized by making RLO 10k or less. If shutdown
currentisanissue, RLO canberaisedto100k, buttheerror
due to initial bias current and changes with temperature
should be considered.
VIN = 12V. Let RLO = 25k.
25k 12 − 2.38 1.5/5 +1 + 1.5
(
)
)
[
]
RHI =
2.38 − 25k 3.5µA
(
25k 10.41
(
)
=
= 114k
2.29
R =114k 5/1.5 = 380k
(
)
FB
R = 10k to 100k 25k suggested
(
)
LO
SWITCH NODE CONSIDERATIONS
RLO V − 2.38V
(
)
IN
RHI =
For maximum efficiency, switch rise and fall times are
made as short as possible. To prevent radiation and high
frequency resonance problems, proper layout of the com-
ponents connected to the switch node is essential. B field
(magnetic) radiation is minimized by keeping catch diode,
switch pin, and input bypass capacitor leads as short as
possible. E field radiation is kept low by minimizing the
length and area of all traces connected to the switch pin
and BOOST pin. A ground plane should always be used
under the switcher circuitry to prevent interplane cou-
pling. A suggested layout for the critical components is
shown in Figure 5. Note that the feedback resistors and
compensation components are kept as far as possible
from the switch node. Also note that the high current
groundpathofthecatchdiodeandinputcapacitorarekept
very short and separate from the analog ground line.
2.38V −RLO 3.5µA
(
)
VIN = Minimum input voltage
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capaci-
tance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired in
the undervoltage lockout point, a resistor RFB can be
added to the output node. Resistor values can be calcu-
lated from:
RLO V − 2.38 ∆V/V +1 + ∆V
(
)
IN
OUT
[
]
RHI =
2.38 −R2 3.5µA
(
)
Thehighspeedswitchingcurrentpathisshownschemati-
cally in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, catch diode, and input capacitor is
the only one containing nanosecond rise and fall times. If
you follow this path on the PC layout, you will see that it is
irreducibly short. If you move the diode or input capacitor
away from the LT1374, get your resumé in order. The
other paths contain only some combination of DC and
500kHz triwave, so are much less critical.
R = R V /∆V
(
HI)(
)
FB
OUT
25k suggested for RLO
VIN = Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless
1374fb
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LT1374
APPLICATIONS INFORMATION
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CONNECT TO
GROUND PLANE
MINIMIZE LT1374, C3, D1 LOOP
V
IN
C3
D1
C5
GND
C6
V
OUT
1
TAKE OUTPUT
DIRECTLY FROM
END OF OUTPUT
CAPACITOR
GND
L1
U1
C1
R3
R2
D2
CONNECT TO
GROUND PLANE
PLACE FEEDTHROUGHS
AROUND GND PIN FOR GOOD
THERMAL CONDUCTIVITY
C4
KELVIN SENSE
KEEP FB AND V COMPONENTS
C
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
V
OUT
13745 F05a
Figure 5a. Suggested Layout (Topside Only Shown) SO-8
1374fb
16
LT1374
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SOLDER EXPOSED PAD AND
USE FEEDTHROUGHS FOR
BETTER THERMAL CONDUCTIVITY
KEEP FB AND V
C
COMPONENTS AWAY
FROM HIGH FREQUENCY,
HIGH CURRENT
GND
C3
V
IN
COMPONENTS
C4 C2 R3
KELVIN
SENSE
OUTPUT
D2
R2 R1 C1
V
OUT
D1
C1
1374 F05b
Figure 5b. Suggested Layout (Topside Only Shown) TSSOP
1374fb
17
LT1374
APPLICATIONS INFORMATION
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MINIMIZE LT1374 C3, D1 LOOP
CONNECT TO GND PLANE
C3
D1
V
OUT
V
IN
TAKE OUTPUT
DIRECTLY FROM
END OF OUTPUT
CAPACITOR
L1
PLACE FEEDTHROUGHS
AROUND GND TAB,
C3, D1 FOR GOOD
THERMAL
D2
V
OUT
C4
R2
CONDUCTIVITY
C5
C6
C
C2
KELVIN SENSE
V
OUT
C
C
7
6
5
4
3 2 1
R3
U1
R
C
TAB IS GND
GND
1374 F05c
KEEP FB AND V COMPONENTS
C
AWAY FROM ANY HIGH FREQUENCY,
HIGH CURRENT CMPONENTS OR PATHS
Figure 5c. Suggested Layout (Topside Only Shown) DD
SWITCH NODE
L1
5V
HIGH
FREQUENCY
CIRCULATING
PATH
V
IN
LOAD
1374 F06
Figure 6. High Speed Switching Path
1374fb
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PARASITIC RESONANCE
Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schot-
tky diodes have very high “Q” junction capacitance that
can ring for many cycles when excited at high frequency.
Iftotalleadlengthfortheinputcapacitor, diodeandswitch
path is 1 inch, the inductance will be approximately 25nH.
At switch off, this will produce a spike across the NPN
output device in addition to the input voltage. At higher
currents this spike can be in the order of 10V to 20V or
higher with a poor layout, potentially exceeding the abso-
lute max switch voltage. The path around switch, catch
diode and input capacitor must be kept as short as
possibletoensurereliableoperation.Whenlookingatthis,
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT1374 has special circuitry inside which
mitigates this problem, but negative voltages over 1V
lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.
RISE AND FALL
WAVEFORMS ARE
SUPERIMPOSED
(PULSE WIDTH IS
NOT 120ns)
5V/DIV
20ns/DIV
1374 F07
Figure 7. Switch Node Resonance
5V/DIV
SWITCH NODE
VOLTAGE
INDUCTOR
CURRENT
100mA/DIV
20ns/DIV
1375/76 F11
0.5µs/DIV
1374 F08
Figure 8. Discontinuous Mode Ringing
current fed back into the input supply. The capacitor also
forces switching current to flow in a tight local loop,
minimizing EMI.
A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time (see Figure 8). Switch and diode capacitance reso-
nate with the inductor to form damped ringing at 1MHz to
10 MHz. This ringing is not harmful to the regulator and it
hasnotbeenshowntocontributesignificantlytoEMI. Any
attempt to damp it with a resistive snubber will degrade
efficiency.
Do not cheat on the ripple current rating of the Input
bypass capacitor, but also don’t get hung up on the value
in microfarads. The input capacitor is intended to absorb
all the switching current ripple, which can have an RMS
value as high as one half of load current. Ripple current
ratings on the capacitor must be observed to ensure
reliable operation. In many cases it is necessary to parallel
two capacitors to obtain the required ripple rating. Both
capacitors must be of the same value and manufacturer to
guaranteepowersharing. Theactualvalueofthecapacitor
in microfarads is not particularly important because at
500kHz, any value above 5µF is essentially resistive. RMS
ripple current rating is the critical parameter. Actual RMS
current can be calculated from:
INPUT BYPASSING AND VOLTAGE RANGE
Input Bypass Capacitor
Step-down converters draw current from the input supply
in pulses. The average height of these pulses is equal to
load current, and the duty cycle is equal to VOUT/VIN. Rise
and fall time of the current is very fast. A local bypass
capacitor across the input supply is necessary to ensure
proper operation of the regulator and minimize the ripple
2
IRIPPLE RMS =IOUT VOUT V − V
/V
IN
(
)
IN
OUT
(
)
1374fb
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The term inside the radical has a maximum value of 0.5
when input voltage is twice output, and stays near 0.5 for
a relatively wide range of input voltages. It is common
practice therefore to simply use the worst-case value and
assumethatRMSripplecurrentisonehalfofloadcurrent.
At maximum output current of 4.5A for the LT1374, the
input bypass capacitor should be rated at 2.25A ripple
current. Note however, that there are many secondary
considerations in choosing the final ripple current rating.
These include ambient temperature, average versus peak
load current, equipment operating schedule, and required
product lifetime. For more details, see Application Notes
19 and 46, and Design Note 95.
Larger capacitors may be necessary when the input volt-
age is very close to the minimum specified on the data
sheet. Small voltage dips during switch on time are not
normallyaproblem, butatverylowinputvoltagetheymay
cause erratic operation because the input voltage drops
below the minimum specification. Problems can also
occur if the input-to-output voltage differential is near
minimum. The amplitude of these dips is normally a
function of capacitor ESR and ESL because the capacitive
reactance is small compared to these terms. ESR tends to
be the dominate term and is inversely related to physical
capacitor size within a given capacitor type.
SYNCHRONIZING (Available as -SYNC Option)
Input Capacitor Type
The LT1374-SYNC has the SHDN pin replaced with a
SYNC pin, which is used to synchronize the internal
oscillator to an external signal. The SYNC input must pass
from a logic level low, through the maximum synchroni-
zation threshold with a duty cycle between 10% and 90%.
The input can be driven directly from a logic level output.
The synchronizing range is equal to initial operating fre-
quency up to 1MHz. This means that minimum practical
sync frequency is equal to the worst-case high self-
oscillating frequency (550kHz), not the typical operating
frequency of 500kHz. Caution should be used when syn-
chronizing above 700kHz because at higher sync frequen-
cies the amplitude of the internal slope compensation
used to prevent subharmonic switching is reduced. This
type of subharmonic switching only occurs at input volt-
ages less than twice output voltage. Higher inductor
values will tend to eliminate this problem. See Frequency
Compensation section for a discussion of an entirely
different cause of subharmonic switching before assum-
ing that the cause is insufficient slope compensation.
ApplicationNote19hasmoredetailsonthetheoryofslope
compensation.
Some caution must be used when selecting the type of
capacitor used at the input to regulators. Aluminum
electrolytics are lowest cost, but are physically large to
achieve adequate ripple current rating, and size con-
straints (especially height), may preclude their use.
Ceramic capacitors are now available in larger values, and
their high ripple current and voltage rating make them
ideal for input bypassing. Cost is fairly high and footprint
may also be somewhat large. Solid tantalum capacitors
would be a good choice, except that they have a history of
occasionalspectacularfailureswhentheyaresubjectedto
large current surges during power-up. The capacitors can
short and then burn with a brilliant white light and lots of
nasty smoke. This phenomenon occurs in only a small
percentage of units, but it has led some OEM companies
to forbid their use in high surge applications. The input
bypass capacitor of regulators can see these high surges
when a battery or high capacitance source is connected.
Several manufacturers have developed a line of solid
tantalum capacitors specially tested for surge capability
(AVX TPS series for instance, see Table 3), but even these
units may fail if the input voltage surge approaches the
maximum voltage rating of the capacitor. AVX recom-
mends derating capacitor voltage by 2:1 for high surge
applications. The highest voltage rating is 50V, so 25V
may be a practical upper limit when using solid tantalum
capacitors for input bypassing.
At power-up, when VC is being clamped by the FB pin (see
Figure2,Q2),thesyncfunctionisdisabled.Thisallowsthe
frequency foldback to operate in the shorted output con-
dition. During normal operation, switching frequency is
controlledbytheinternaloscillatoruntiltheFBpinreaches
1.5V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
1374fb
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LT1374
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THERMAL CALCULATIONS
Thermal resistance for LT1374 package is influenced by
the presence of internal or backside planes. With a full
plane under the 16-lead TSSOP package, thermal resis-
tance will be about 40°C/W. To calculate die temperature,
use the proper thermal resistance number for the desired
package and add in worst-case ambient temperature:
Power dissipation in the LT1374 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current,andinputquiescentcurrent.Thefollowingformu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
TJ = TA + θJA (PTOT
)
WiththeTSSOP16package(θJA =40°C/W), atanambient
temperature of 50°C,
Switch loss:
TJ = 50 + 40 (0.87) = 85°C
2
R
I
V
OUT
(
) (
)
SW OUT
For the DD package with a good copper plane under the
device, thermal resistance will be about 30°C/W. For the
conditions above:
P
=
+ 24ns I
V
f
(
)( )( )
SW
OUT IN
V
IN
Boost current loss:
TJ = 50 + 30 (0.87) = 76°C
2
V
I
/50
(
)
OUT OUT
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
P
=
BOOST
V
IN
Quiescent current loss:
FREQUENCY COMPENSATION
2
VOUT 0.002
(
)
Loop frequency compensation of switching regulators
can be a rather complicated problem because the reactive
components used to achieve high efficiency also intro-
duce multiple poles into the feedback loop. The inductor
and output capacitor on a conventional step-down con-
verter actually form a resonant tank circuit that can exhibit
peaking and a rapid 180° phase shift at the resonant
frequency. Bycontrast, theLT1374usesa“currentmode”
architecture to help alleviate phase shift created by the
inductor. The basic connections are shown in Figure 9.
Figure 10 shows a Bode plot of the phase and gain of the
power section of the LT1374, measured from the VC pin to
the output. Gain is set by the 5.3A/V transconductance of
the LT1374 power section and the effective complex
impedance from output to ground. Gain rolls off smoothly
above the 600Hz pole frequency set by the 100µF output
capacitor. Phase drop is limited to about 70°. Phase
recoversandgainlevelsoffatthezerofrequency(≈16kHz)
set by capacitor ESR (0.1Ω).
P =V 0.001 + V
0.005 +
(
)
(
)
Q
IN
OUT
V
IN
RSW = Switch resistance (≈0.07)
24ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with VIN = 10V, VOUT = 5V and IOUT = 3A:
2
0.07 3
5
(
)( ) ( )
PSW
=
+ 24 •10−9 3 10 500•103
( )( )
10
= 0.32 + 0.36 = 0.68W
2
5
3/50
( ) (
)
PBOOST
=
= 0.15W
10
2
5
0.002
( ) (
)
P =10 0.001 +5 0.005 +
= 0.04W
(
)
(
)
Q
10
Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W.
1374fb
21
LT1374
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and staying there. The overall loop has a gain of 74dB at
low frequency, rolling off to unity-gain at 100kHz. Phase
showsatwo-polecharacteristicuntiltheESRoftheoutput
capacitor brings it back above 10kHz. Phase margin is
about 75° at unity-gain.
Error amplifier transconductance phase and gain are
shown in Figure 11. The error amplifier can be modeled
as a transconductance of 2000µMho, with an output
impedance of 200kΩ in parallel with 12pF. In all practical
applications, the compensation network from VC pin to
ground has a much lower impedance than the output
impedance of the amplifier at frequencies above 500Hz.
This means that the error amplifier characteristics them-
selvesdonotcontributeexcessphaseshifttotheloop,and
the phase/gain characteristics of the error amplifier sec-
tion are completely controlled by the external compensa-
tion network.
Analog experts will note that around 4.4kHz, phase dips
very close to the zero phase margin line. This is typical of
switching regulators, especially those that operate over a
wide range of loads. This region of low phase is not a
problem as long as it does not occur near unity-gain. In
practice, the variability of output capacitor ESR tends to
dominate all other effects with respect to loop response.
Variations in ESR will cause unity-gain to move around,
but at the same time phase moves with it so that adequate
phase margin is maintained over a very wide range of ESR
(≥ ±3:1).
In Figure 12, full loop phase/gain characteristics are
shown with a compensation capacitor of 1.5nF, giving the
erroramplifierapoleat530Hz,withphaserollingoffto90°
LT1374
3000
2500
2000
1500
1000
500
200
150
100
50
CURRENT MODE
POWER STAGE
m
V
SW
FB
OUTPUT
PHASE
GAIN
ERROR
g
= 5.3A/V
AMPLIFIER
R1
R2
–
ESR
C1
+
V
C
2.42V
C
R
OUT
12pF
OUT
200k
+
V
2 × 10–3
(
)
FB
V
C
GND
ERROR AMPLIFIER EQUIVALENT CIRCUIT
= 50Ω
0
R
C
R
C
F
LOAD
1k
–50
C
C
100
10k
100k
1M
10M
FREQUENCY (Hz)
1374 F11
1374 F09
Figure 9. Model for Loop Response
Figure 11. Error Amplifier Gain and Phase
40
20
0
40
80
60
200
150
100
50
V
V
I
= 10V
IN
= 5V
= 2A
OUT
OUT
GAIN
GAIN
0
40
–40
–80
–120
PHASE
20
PHASE
V
V
C
C
= 10V
OUT
OUT
–20
–40
IN
0
0
= 5V, I
= 2A
= 100µF, 10V, AVX TPS
= 1.5nF, R = 0, L = 10µH
OUT
C
C
–20
–50
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
1374 F10
1374 F12
Figure 10. Response from VC Pin to Output
Figure 12. Overall Loop Characteristics
1374fb
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What About a Resistor in the Compensation Network?
R G
V − V
ESR 2.4
( )( MA)(
OUT)(
)(
)
C
IN
It is common practice in switching regulator design to
add a “zero” to the error amplifier compensation to
increase loop phase margin. This zero is created in the
external network in the form of a resistor (RC) in series
with the compensation capacitor. Increasing the size of
this resistor generally creates better and better loop
stability, but there are two limitations on its value. First,
the combination of output capacitor ESR and a large
value for RC may cause loop gain to stop rolling off
altogether, creating a gain margin problem. An approxi-
mate formula for RC where gain margin falls to zero is:
VC(RIPPLE
=
)
V L f
( )( )( )
IN
GMA = Error amplifier transconductance (2000µMho)
If a computer simulation of the LT1374 showed that a
series compensation resistor of 3k gave best overall loop
response, with adequate gain margin, the resulting VC pin
ripple voltage with VIN = 10V, VOUT = 5V, ESR = 0.1Ω,
L = 10µH, would be:
3k 2 •10−3 10 − 5 0.1 2.4
( )
(
)( )(
)
VC(RIPPLE
=
= 0.144V
)
10 10 •10−6 500 •103
VOUT
R Loop Gain = 1 =
(
)
C
G
(
G
ESR 2.42
MP)( MA)(
)(
)
This ripple voltage is high enough to possibly create
subharmonic switching. In most situations a compromise
value (<2k in this case) for the resistor gives acceptable
phase margin and no subharmonic problems. In other
cases, the resistor may have to be larger to get acceptable
phaseresponse, andsomemeansmustbeusedtocontrol
ripple voltage at the VC pin. The suggested way to do this
istoaddacapacitor(CF)inparallelwiththeRC/CC network
on the VC pin. Pole frequency for this capacitor is typically
set at one-fifth of switching frequency so that it provides
significant attenuation of switching ripple, but does not
addunacceptablephaseshiftatloopunity-gainfrequency.
With RC = 3k,
GMP = Transconductance of power stage = 5.3A/V
GMA = Error amplifier transconductance = 2(10–3)
ESR = Output capacitor ESR
2.42 = Reference voltage
With VOUT = 5V and ESR = 0.03Ω, a value of 6.5k for RC
wouldyieldzerogainmargin, sothisrepresentsanupper
limit. There is a second limitation however which has
nothing to do with theoretical small signal dynamics.
This resistor sets high frequency gain of the error ampli-
fier, including the gain at the switching frequency. If
switching frequency gain is high enough, output ripple
voltage will appear at the VC pin with enough amplitude
to muck up proper operation of the regulator. In the
marginal case, subharmonic switching occurs, as evi-
denced by alternating pulse widths seen at the switch
node. In more severe cases, the regulator squeals or
hisses audibly even though the output voltage is still
roughly correct. None of this will show on a theoretical
Bode plot because Bode is an amplitude insensitive
analysis. TestshaveshownthatifripplevoltageontheVC
is held to less than 100mVP-P, the LT1374 will be well
behaved. The formula below will give an estimate of VC
ripple voltage when RC is added to the loop, assuming
that RC is large compared to the reactance of CC at
500kHz.
5
5
CF =
=
= 531pF
( )( )( ) 2π 500 •103 3k
2π f R
C
( )
How Do I Test Loop Stability?
The “standard” compensation for LT1374 is a 1.5nF
capacitor for CC, with RC = 0. While this compensation will
work for most applications, the “optimum” value for loop
compensationcomponentsdepends,tovariousextent,on
parameters which are not well controlled. These include
inductor value (±30% due to production tolerance, load
1374fb
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LT1374
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current and ripple current variations), output capacitance
(±20% to ±50% due to production tolerance, tempera-
ture, aging and changes at the load), output capacitor ESR
(±200% due to production tolerance, temperature and
aging), and finally, DC input voltage and output load
current . This makes it important for the designer to check
outthefinaldesigntoensurethatitis“robust”andtolerant
of all these variations.
After verifying that the setup is working correctly, I start
varying load current and input voltage to see if I can find
any combination that makes the transient response look
suspiciously “ringy.” This procedure may lead to an ad-
justment for best loop stability or faster loop transient
response. Nearly always you will find that loop response
looks better if you add in several kΩ for RC. Do this only
if necessary, because as explained before, RC above 1k
may require the addition of CF to control VC pin ripple.
If everything looks OK, I use a heat gun and cold spray on
the circuit (especially the output capacitor) to bring out
any temperature-dependent characteristics.
I check switching regulator loop stability by pulse loading
the regulator output while observing transient response at
the output, using the circuit shown in Figure 13. The
regulator loop is “hit” with a small transient AC load
current at a relatively low frequency, 50Hz to 1kHz. This
causes the output to jump a few millivolts, then settle back
totheoriginalvalue,asshowninFigure14. Awellbehaved
loop will settle back cleanly, whereas a loop with poor
phase or gain margin will “ring” as it settles. The number
ofringsindicatesthedegreeofstability, andthefrequency
of the ringing shows the approximate unity-gain fre-
quency of the loop. Amplitude of the signal is not particu-
larlyimportant, aslongastheamplitudeisnotsohighthat
the loop behaves nonlinearly.
Keep in mind that this procedure does not take initial
component tolerance into account. You should see fairly
cleanresponseunderallloadandlineconditionstoensure
that component variations will not cause problems. One
note here: according to Murphy, the component most
V
OUT AT
I
OUT = 500mA
BEFORE FILTER
VOUT AT
I
OUT = 500mA
10mV/DIV
5A/DIV
AFTER FILTER
The output of the regulator contains both the desired low
frequency transient information and a reasonable amount
of high frequency (500kHz) ripple. The ripple makes it
difficult to observe the small transient, so a two-pole,
100kHz filter has been added. This filter is not particularly
critical; even if it attenuated the transient signal slightly,
this wouldn’t matter because amplitude is not critical.
VOUT AT
IOUT = 50mA
AFTER FILTER
LOAD PULSE
THROUGH 50Ω
f ≈ 780Hz
0.2ms/DIV
1374 F14
Figure 14. Loop Stability Check
RIPPLE FILTER
470Ω
4.7k
TO X1
OSCILLOSCOPE
PROBE
SWITCHING
REGULATOR
+
100µF TO
1000µF
3300pF
330pF
50Ω
ADJUSTABLE
INPUT SUPPLY
ADJUSTABLE
DC LOAD
TO
OSCILLOSCOPE
SYNC
100Hz TO 1kHz
100mV TO 1V
P-P
1374 F13
Figure 13. Loop Stability Test Circuit
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LT1374
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likely to be changed in production is the output capacitor,
because that is the component most likely to have manu-
facturer variations (in ESR) large enough to cause prob-
lems. It would be a wise move to lock down the sources of
the output capacitor in production.
Inverting regulators differ from buck regulators in the
basicswitchingnetwork. Currentisdeliveredtotheoutput
as square waves with a peak-to-peak amplitude much
greater than load current. This means that maximum load
current will be significantly less than the LT1374’s 4.5A
maximumswitchcurrent, evenwithlargeinductorvalues.
The buck converter in comparison, delivers current to the
output as a triangular wave superimposed on a DC level
equal to load current, and load current can approach 4.5A
withlargeinductors.Outputripplevoltageforthepositive-
to-negative converter will be much higher than a buck
converter. Ripple current in the output capacitor will also
be much higher. The following equations can be used to
calculateoperatingconditionsforthepositive-to-negative
converter.
A possible exception to the “clean response” rule is at very
light loads, as evidenced in Figure 14 with ILOAD = 50mA.
Switching regulators tend to have dramatic shifts in loop
response at very light loads, mostly because the inductor
currentbecomesdiscontinuous.Onecommonresultisvery
slow but stable characteristics. A second possibility is low
phase margin, as evidenced by ringing at the output with
transients. The good news is that the low phase margin at
lightloadsisnotparticularlysensitivetocomponentvaria-
tion, so if it looks reasonable under a transient test, it will
probably not be a problem in production. Note that fre-
quency of the light load ringing may vary with component
tolerance but phase margin generally hangs in there.
Maximum load current:
V
V
(
)(
)
IN OUT
I −
V
V −
0.35
(
)(
)
P
OUT IN
2 V
+ V f L
(
)( )( )
OUT
IN
POSITIVE-TO-NEGATIVE CONVERTER
I
=
MAX
V
+V − 0.35 V
+ V
F
(
)(
)
OUT
IN
OUT
The circuit in Figure 15 is a classic positive-to-negative
topology using a grounded inductor. It differs from the
standard approach in the way the IC chip derives its
feedback signal, however, because the LT1374 accepts
onlypositivefeedbacksignals,thegroundpinmustbetied
to the regulated negative output. A resistor divider to
ground or, in this case, the sense pin, then provides the
proper feedback voltage for the chip.
IP = Maximum rated switch current
VIN = Minimum input voltage
VOUT = Output voltage
VF = Catch diode forward voltage
0.35 = Switch voltage drop at 4.5A
Example: with VIN(MIN) = 5.5V, VOUT = 5V, L = 10µH,
VF =0.5V,IP =4.5A:IMAX =2A.Notethatthisequationdoes
not take into account that maximum rated switch current
(IP) on the LT1374 is reduced slightly for duty cycles
above 50%. If duty cycle is expected to exceed 50% (input
voltage less than output voltage), use the actual IP value
from the Electrical Characteristics table.
D1
CMDSH-3
C2
0.27µF
L1*
5µH
INPUT
5.5V TO
20V
BOOST
V
V
IN
SW
LT1374-5
SENSE
+
C3
10µF TO
50µF
Operating duty cycle:
GND
V
C
C1
+
100µF
10V TANT
×2
C
C
C
V
OUT + VF
D2
MBRS330T3
DC =
R
V − 0.3 + VOUT + VF
OUTPUT**
IN
–5V, 1.8A
* INCREASE L1 TO 10µH OR 20µH FOR HIGHER CURRENT APPLICATIONS.
SEE APPLICATIONS INFORMATION
** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE
AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION
(This formula uses an average value for switch loss, so it
may be several percent in error.)
1374 F15
Figure 15. Positive-to-Negative Converter
1374fb
25
LT1374
U
W U U
APPLICATIONS INFORMATION
With the conditions above:
5 + 0.5
lowest value of inductance that can be used, but in some
cases (lower output load currents) it may give a value that
creates unnecessarily high output ripple voltage. A com-
promise value is often chosen that reduces output ripple.
As you can see from the graph, large inductors will not
give arbitrarily low ripple, but small inductors can give
high ripple.
DC =
= 51%
5.5 − 0.3 + 5 + 0.5
This duty cycle is close enough to 50% that IP can be
assumed to be 4.5A.
The difficulty in calculating the minimum inductor size
needed is that you must first know whether the switcher
will be in continuous or discontinuous mode at the critical
point where switch current is 4.5A. The first step is to use
the following formula to calculate the load current where
the switcher must use continuous mode. If your load
current is less than this, use the discontinuous mode
formula to calculate minimum inductor needed. If load
current is higher, use the continuous mode formula.
OUTPUT DIVIDER
If the adjustable part is used, the resistor connected to
VOUT (R2) should be set to approximately 5k. R1 is
calculated from:
R2 V
– 2.42
(
)
OUT
R1=
2.42
INDUCTOR VALUE
Output current where continuous mode is needed:
Unlike buck converters, positive-to-negative converters
cannot use large inductor values to reduce output ripple
voltage. At 500kHz, values larger than 25µH make almost
no change in output ripple. The graph in Figure 16 shows
peak-to-peak output ripple voltage for a 5V to –5V con-
verter versus inductor value. The criteria for choosing the
inductor is therefore typically based on ensuring that peak
switch current rating is not exceeded. This gives the
2
V
2 I
( ) ( P)
IN
ICONT
=
4 V + V
V + V + V
IN OUT F
(
OUT)(
)
IN
Minimum inductor discontinuous mode:
2 V
I
(
OUT)( OUT
)
LMIN
=
2
f I
( )( P)
250
5V TO – 5V CONVERTER
OUTPUT CAPACITOR’S
ESR = 0.05Ω
Minimum inductor continuous mode:
200
V
V
OUT
( )(
)
IN
150
LMIN
=
I
= 1A
LOAD
V
+ VF
(
)
OUT
100
50
0
2 f V + V
I −I
1+
( )(
)
IN
OUT
P
OUT
V
IN
I
= 0.25A
LOAD
For the example above, with maximum load current of 1A:
0
5
10
15
20
INDUCTOR SIZE (µH)
2
2
)
1374 F16
5.5 4.5
(
) (
I
=
= 1.15A
CONT
4 5.5 + 5 5.5 +5 +0.5
Figure 16. Ripple Voltage on Positive-to-Negative Converter
(
)(
)
1374fb
26
LT1374
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APPLICATIONS INFORMATION
This says that discontinuous mode can be used and the
minimum inductor needed is found from:
somewhat higher ripple current, especially in discontinu-
ous mode. The exact formulas are very complex and
appear in Application Note 44, pages 30 and 31. For our
purposes here I have simply added a fudge factor (ff). The
value for ff is about 1.2 for higher load currents and
L ≥10µH. It increases to about 2.0 for smaller inductors at
lower load currents.
2 5 1
( )( )
LMIN
=
= 1µH
2
500 •103 4.5
(
)
Inpractice,theinductorshouldbeincreasedbyabout30%
over the calculated minimum to handle losses and varia-
tionsinvalue. Thissuggestsaminimuminductorof1.3µH
for this application, but looking at the ripple voltage chart
showsthatoutputripplevoltagecouldbereducedbyafac-
toroftwobyusinga15µHinductor.Thereisnoruleofthumb
heretomakeafinaldecision.Ifmodestrippleisneededand
the larger inductor does the trick, go for it. If ripple is non-
critical use the smaller inductor. If ripple is extremely criti-
cal, a second filter may have to be added in any case, and
the lower value of inductance can be used. Keep in mind
thattheoutputcapacitoristheothercriticalfactorindeter-
mining output ripple voltage. Ripple shown on the graph
(Figure16)iswithtwoparallelcapacitor’sESRof0.1Ω.This
isreasonableforAVXtypeTPS“D”or“E”sizesurfacemount
solid tantalum capacitors, but the final capacitor chosen
must be looked at carefully for ESR characteristics.
VOUT
Capacitor IRMS = ff I
( )( OUT
ff = Fudge factor (1.2 to 2.0)
Diode Current
)
V
IN
Average diodecurrentisequaltoloadcurrent. Peak diode
current will be considerably higher.
Peak diode current:
Continuous Mode =
V + V
V
V
(
)
(
)(
)
IN
OUT
IN OUT
I
+
OUT
V
2 L f V + V
IN
( )( )(
)
IN
OUT
2 I
V
OUT
(
)(
)
OUT
Ripple Current in the Input and Output Capacitors
Discontinuous Mode =
L f
( )( )
Positive-to-negativeconvertershavehighripplecurrentin
both the input and output capacitors. For long capacitor
lifetime, the RMS value of this current must be less than
the high frequency ripple current rating of the capacitor.
The following formula will give an approximate value for
RMS ripple current. This formula assumes continuous
mode and large inductor value. Small inductors will give
Keep in mind that during start-up and output overloads,
average diode current may be much higher than with
normalloads.Careshouldbeusedifdiodesratedlessthan
3A are used, especially if continuous overload conditions
must be tolerated.
1374fb
27
LT1374
APPLICATIONS INFORMATION
U
W U U
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663,
Exposed Pad Variation BB)
4.95 – 5.05*
(.196 – .204)
3.8
(.149)
16 1514 13 12 1110
9
6.60 ±0.10
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
4.50 ±0.10
3.0
6.25 – 6.50
(.118) (.246 – .256)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD
1.15
(.0453)
MAX
4.30 – 4.48*
(.169 – .176)
0° – 8°
0.65
(.0256)
BSC
0.50 – 0.70
(.020 – .028)
0.105 – 0.180
(.0041 – .0071)
0.05 – 0.15
(.002 – .006)
FE16 TSSOP 1101
0.195 – 0.30
(.0077 – .0118)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
1374fb
28
LT1374
U
PACKAGE DESCRIPTION
R Package
7-Lead Plastic DD Pak
(LTC DWG # 05-08-1462)
0.060
(1.524)
TYP
0.390 – 0.415
(9.906 – 10.541)
0.060
(1.524)
0.165 – 0.180
(4.191 – 4.572)
0.256
(6.502)
0.045 – 0.055
(1.143 – 1.397)
15° TYP
+0.008
0.004
–0.004
0.060
(1.524)
0.059
(1.499)
TYP
0.183
(4.648)
0.330 – 0.370
(8.382 – 9.398)
+0.203
–0.102
0.102
(
)
0.095 – 0.115
(2.413 – 2.921)
0.075
(1.905)
0.040 – 0.060
(1.016 – 1.524)
0.026 – 0.036
(0.660 – 0.914)
0.050 ± 0.012
(1.270 ± 0.305)
0.300
(7.620)
0.013 – 0.023
(0.330 – 0.584)
+0.012
0.143
–0.020
+0.305
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
3.632
(
)
–0.508
R (DD7) 0396
1374fb
29
LT1374
U
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.053 – 0.069
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
1374fb
30
LT1374
U
PACKAGE DESCRIPTION
T7 Package
7-Lead Plastic TO-220 (Standard)
(LTC DWG # 05-08-1422)
0.165 – 0.180
(4.191 – 4.572)
0.147 – 0.155
(3.734 – 3.937)
DIA
0.390 – 0.415
(9.906 – 10.541)
0.045 – 0.055
(1.143 – 1.397)
0.230 – 0.270
(5.842 – 6.858)
0.570 – 0.620
(14.478 – 15.748)
0.620
(15.75)
TYP
0.460 – 0.500
(11.684 – 12.700)
0.330 – 0.370
(8.382 – 9.398)
0.700 – 0.728
(17.780 – 18.491)
0.095 – 0.115
(2.413 – 2.921)
0.152 – 0.202
(3.860 – 5.130)
0.260 – 0.320
(6.604 – 8.128)
0.013 – 0.023
(0.330 – 0.584)
0.040 – 0.060
(1.016 – 1.524)
0.026 – 0.036
(0.660 – 0.914)
0.135 – 0.165
(3.429 – 4.191)
0.155 – 0.195
(3.937 – 4.953)
T7 (TO-220) (FORMED) 1197
1374fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
31
LT1374
U
TYPICAL APPLICATION
Dual Output SEPIC Converter
losses. C4 provides a low impedance path to maintain an
equal voltage swing in L1B, improving regulation. In a
flybackconverter,duringswitchontime,alltheconverter’s
energyisstoredinL1Aonly, sincenocurrentflowsinL1B.
At switch off, energy is transferred by magnetic coupling
into L1B, powering the –5V rail. C4 pulls L1B positive
duringswitchontime, causingcurrenttoflow, andenergy
to build in L1B and C4. At switch off, the energy stored in
both L1B and C4 supply the –5V rail. This reduces the
current in L1A and changes L1B current waveform from
square to triangular. For details on this circuit see Design
Note 100.
The circuit in Figure 17 generates both positive and
negative 5V outputs with a single piece of magnetics. The
two inductors shown are actually just two windings on a
standard BH Electronics inductor. The topology for the 5V
output is a standard buck converter. The –5V topology
would be a simple flyback winding coupled to the buck
converter if C4 were not present. C4 creates the SEPIC
(Single-Ended Primary Inductance Converter) topology
which improves regulation and reduces ripple current in
L1. Without C4, the voltage swing on L1B compared to
L1A would vary due to relative loading and coupling
C2
0.27µF
D2
CMDSH-3
BOOST
INPUT
OUTPUT
5V
V
V
SW
IN
6V TO 25V
L1A*
LT1374-5 BIAS
SENSE
6.8µH
SHDN
GND
V
C
+
+
C1**
100µF
R
C
10V TANT
+
C3
22µF
470Ω
D1
MBRD340
C
C
35V TANT
0.01µF
GND
+
C5**
100µF
10V TANT
C4**
4.7nF
* L1 IS A SINGLE CORE WITH TWO WINDINGS
BH ELECTRONICS #501-0726
L1B*
D3
MBRD340
** TOKIN IE475ZY5U-C304
†
OUTPUT
IF LOAD CAN GO TO ZERO, AN OPTIONAL
†
–5V
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
1374 F17
Figure 17. Dual Output SEPIC Converter
RELATED PARTS
PART NUMBER
LT1074/LT1076
LTC®1148
LTC1149
DESCRIPTION
COMMENTS
Step-Down Switching Regulators
40V Input, 100kHz, 5A and 2A
External FET Switches
High Efficiency Synchronous Step-Down Switching Regulator
High Efficiency Synchronous Step-Down Switching Regulator
High Efficiency Step-Down and Inverting DC/DC Converter
Step-Down Switching Regulator
External FET Switches
LTC1174
0.5A, 150kHz Burst Mode® Operation
PDIP LT1076
LT1176
LT1370
High Efficiency DC/DC Converter
42V, 6A, 500kHz Switch
LT1371
High Efficiency DC/DC Converter
35V, 3A, 500kHz Switch
LT1372/LT1377
LTC1735
500kHz and 1MHz High Efficiency 1.5A Switching Regulators
High Efficiency Step-Down Converter
Boost Topology
External Switches, Very High Efficiency
1.25MHz, 3A, 25V Input, SO-8 and TSSOP16 Packages
200kHz, 1.5A, 60V Input, SO-8 and GN16 Packages
1.25MHz, 1.5A, 25V Input, MS8 Package
LT1765
3A Step-Down Switching Regulator
LT1766
1.5A Step-Down Switching Regulator
LT1767
1.5A Step-Down Switching Regulator
Burst Mode is a registered trademark of Linear Technology Corporation.
1374fb
LT/TP 0102 1.5K REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 1998
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