LSH32 [LOGIC]
32-bit Cascadable Barrel Shifter; 32位级联桶形移位
| 型号： | LSH32 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | 32-bit Cascadable Barrel Shifter |
| 文件： | 总9页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LSH32
32-bit Cascadable Barrel Shifter
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The LSH32 is a 32-bit high speed
shifter designed for use in floating
point normalization, word pack/
unpack, field extraction, and similar
applications. It has 32 data inputs,
and 16 output lines. Any shift
configured such that any contiguous
16-bit field (including wraparound of
the 32 inputs) may be presented to the
output pins under control of the shift
code field (wrap mode). Alterna-
tively, the wrap feature may be
❑ 32-bit Input, 32-bit Output Multi-
plexed to 16 Lines
❑ Full 0-31 Position Barrel Shift
Capability
❑ Integral Priority Encoder for 32-bit
Floating Point Normalization
configuration of the 32 inputs, includ- disabled, resulting in zero or sign bit
ing circular (barrel) shifting, left shifts fill, as appropriate (fill mode). The
with zero fill, and right shift with sign shift code control assignments and the
❑ Sign-Magnitude or Two’s Comple-
ment Mantissa Representation
❑ 32-bit Linear Shifts with Sign or
extend are possible. In addition, a
built-in priority encoder is provided
to aid floating point normalization.
resulting input to output mapping for
the wrap mode are shown in Table 1.
Zero Fill
❑ Independent Priority Encoder
Outputs for Block Floating Point
Essentially the LSH32 is configured as
a left shift device. That is, a shift code
of 000002 results in no shift of the
input field. A code of 000012 provides
an effective left shift of 1 position, etc.
When viewed as a right shift, the shift
code corresponds to the two’s com-
plement of the shift distance, i.e., a
shift code of 111112 (–110) results in a
right shift of one position, etc.
❑ 68-pinPLCC, J-Lead
SHIFT ARRAY
The 32 inputs to the LSH32 are
applied to a 32-bit shift array. The 32
outputs of this array are multiplexed
down to 16 lines for presentation at
the device outputs. The array may be
LSH32 BLOCK DIAGRAM
When not in the wrap mode, the
LSH32 fills bit positions for which
there is no corresponding input bit.
The fill value and the positions filled
depend on the RIGHT/LEFT (R/L)
direction pin. This pin is a don’t care
input when in wrap mode. For left
shifts in fill mode, lower bits are filled
with zero as shown in Table 2. For
right shifts, however, the SIGN input
is used as the fill value. Table 3
SIGN
I31-I0
32
32:5
PRIORITY
ENCODE
32
5
32-bit
BARREL
SHIFT
SI4-SI0
depicts the bits to be filled as a
function of shift code for the right shift
case. Note that the R/L input changes
only the fill convention, and does not
affect the definition of the shift code.
RIGHT/LEFT
FILL/WRAP
ARRAY
16
16
NORM
In fill mode, as in wrap mode, the shift
code input represents the number of
shift positions directly for left shifts,
but the two’s complement of the shift
code results in the equivalent right
shift. However, for fill mode the R/L
input can be viewed as the most
2:1
16
5
SO
4
-SO
0
Y
15-Y
0
OE MS/LS
Special Arithmetic Functions
08/16/2000–LDS.32-Q
1
LSH32
DEVICES INCORPORATED
32-bit Cascadable Barrel Shifter
significant bit of a 6-bit two’s comple-
ment shift code, comprised of R/L
TABLE 1. WRAP MODE SHIFT CODE DEFINITIONS
concatenated with the SI4–SI0 lines.
Thus a positive shift code (R/L = 0)
results in a left shift of 0–31 positions,
and a negative code (R/L = 1) a right
shift of up to 32 positions. The LSH32
can thus effectively select any contigu-
ous 32-bit field out of a (sign extended
and zero filled) 96-bit "input."
Shift Code Y31 Y30 Y29
••• Y16 Y15
••• Y2 Y1 Y0
00000
00001
00010
I31 I30 I29
I30 I29 I28
I29 I28 I27
I28 I27 I26
••• I16 I15
••• I15 I14
••• I14 I13
••• I13 I12
••• I2
••• I1
••• I0
I1
I0
I0
I31
I31 I30
00011
••• I31 I30 I29
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
I0
•••
•
•
•
OUTPUT MULTIPLEXER
01111
10000
10001
I16 I15 I14
I15 I14 I13
I14 I13 I12
I13 I12 I11
••• I1
••• I0
••• I19 I18 I17
••• I18 I17 I16
••• I17 I16 I15
••• I16 I15 I14
The shift array outputs are applied to
a 2:1 multiplexer controlled by the
MS/LS select line. This multiplexer
makes available at the output pins
either the most significant or least
significant 16 outputs of the shift
array.
I31
••• I31 I30
••• I30 I29
10010
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•
•
I3
I2
I1
I0
•
I2
I1
I0
•
I1
•••
•
•
•••
•
•
I5
I4
I3
I2
•
I4
I3
I2
I1
11100
11101
11110
11111
••• I20 I19
••• I19 I18
••• I18 I17
••• I17 I16
••• I6
••• I5
••• I4
••• I3
PRIORITY ENCODER
I0
The 32-bit input bus drives a priority
encoder which is used to determine
the first significant position for
I31
I31 I30
purposes of normalization. The
priority encoder produces a five-bit
code representing the location of the
first non-zero bit in the input word.
Code assignment is such that the
priority encoder output represents the
number of shift positions required to
left align the first non-zero bit of the
input word. Prior to the priority
encoder, the input bits are individu-
ally exclusive OR’ed with the SIGN
input. This allows normalization in
floating point systems using two’s
complement mantissa representation.
A negative value in two’s complement
representation will cause the exclusive
OR gates to invert the input data to
the encoder. As a result the leading
significant digit will always be "1."
This affects only the encoder inputs;
the shift array always operates on the
raw input data. The priority encoder
function table is shown in Table 4.
TABLE 2. FILL MODE SHIFT CODE DEFINITIONS — LEFT SHIFT
Shift Code Y31 Y30 Y29
••• Y16 Y15
••• Y2 Y1 Y0
00000
00001
00010
I31 I30 I29
I30 I29 I28
I29 I28 I27
I28 I27 I26
••• I16 I15
••• I15 I14
••• I14 I13
••• I13 I12
••• I2
••• I1
••• I0
I1
I0
0
I0
0
0
00011
•
•••
•••
0
•
0
•
0
•
•
•
•
•••
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
I0
0
•••
•••
•••
•••
•
0
0
0
•
0
0
0
•
0
0
0
01111
10000
10001
I16 I15 I14
I15 I14 I13
I14 I13 I12
I13 I12 I11
••• I1
••• I0
•••
0
0
10010
•
•••
•••
0
•
0
•
•••
•••
0
•
0
•
0
•
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•
•
I3
I2
I1
I0
•
I2
I1
I0
0
•
I1
I0
0
•••
•••
•••
•••
•••
•
0
0
0
0
•
0
0
0
0
•••
•••
•••
•••
•••
•
0
0
0
0
•
0
0
0
0
•
0
0
0
0
11100
11101
11110
11111
0
Special Arithmetic Functions
08/16/2000–LDS.32-Q
ffs2
LSH32
DEVICES INCORPORATED
32-bit Cascadable Barrel Shifter
NORMALIZE MULTIPLXER
TABLE 3. FILL MODE SHIFT CODE DEFINITIONS — RIGHT SHIFT
The NORM input, when asserted
Shift Code Y31 Y30 Y29
••• Y16 Y15
••• Y2 Y1 Y0
results in the priority encoder output
driving the internal shift code inputs
directly. It is exactly equivalent to
routing the SO4–SO0 outputs back to
the SI4–SI0 inputs. The NORM input
provides faster normalization of 32-bit
data by avoiding the delay associated
with routing the shift code off chip.
When using the NORM function, the
LSH32 should be placed in fill mode,
with the R/L input low.
00000
00001
00010
S
S
S
S
S
S
S
S
S
•••
•••
•••
S
S
S
S
S
S
•••
•••
•••
S
S
S
S
S I31
S I31 I30
00011
•
S
•
S
•
S
•
•••
•••
S
•
S
•
••• I31 I30 I29
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•
•
S
S
S
•
S
S
S
•
S
S
S
•••
•••
•••
•
•
•••
•
•
•
01111
10000
10001
S
S
••• I19 I18 I17
••• I18 I17 I16
••• I17 I16 I15
••• I16 I15 I14
S I31
••• I31 I30
••• I30 I29
APPLICATIONS EXAMPLES
10010
S
S
S
Normalization of mantissas up to 32
bits can be accomplished directly by a
single LSH32. The NORM input is
asserted, and fill mode and left shift
are selected. The normalized mantissa
is then available at the device output
in two 16-bit segments, under the
control of the output data multiplexer
select, the MS/LS.
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•
•
S
S
S
•
S
S
•
S
S
•••
•
•
•••
•
•
I5
I4
I3
I2
•
I4
I3
I2
I1
11100
11101
11110
11111
••• I20 I19
••• I19 I18
••• I18 I17
••• I17 I16
••• I6
••• I5
••• I4
••• I3
S I31
S I31 I30
If it is desirable to avoid the necessity
of multiplexing output data in 16-bit
segments, two LSH32 devices can be
used in parallel. Both devices receive
the same input word, with the MS/LS
select line of one wired high, and the
other low. Each device will then
independently determine the shift
distance required for normalization,
and the full 32 bits of output data will
be available simultaneously.
TABLE 4. PRIORITY ENCODER FUNCTION TABLE
I31 I30 I29 ••• I16 I15 ••• I2
I1
I0 Shift Code
1
0
0
•
X
1
0
•
X
X
1
•
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
X
X
X
•
X
X
X
•
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
X
X
X
•
X
X
X
•
X
X
X
•
00000
00001
00010
•
•
•
•
•
•
•
•
•
•
0
0
0
•
0
0
0
•
0
0
0
•
1
0
0
•
X
1
0
•
X
X
X
•
X
X
X
•
X
X
X
•
01111
10000
10001
•
•
•
•
•
•
•
•
•
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
X
1
0
11110
11111
11111
Special Arithmetic Functions
08/16/2000–LDS.32-Q
3
LSH32
DEVICES INCORPORATED
32-bit Cascadable Barrel Shifter
LONG-WORD NORMALIZATION
(MULTIPLE CYCLES)
slices, including the first. The excep-
tion is that all SI4 lines are grounded,
limiting the shift distance to 16
clock normalization requiring shifts
longer than 16 bits can be accom-
plished by a bank-select technique
described below.
Normalization of floating point
positions. The shift distance required
for normalization is produced by the
priority encoder in the most signifi-
cant slice. The priority encoder will
produce the shift code necessary to
normalize the input word if the
leading non-zero digit is found in the
upper 16 bits. If this is the case, the
number of shift positions necessary to
accomplish normalization is placed on
the SO4–SO0 outputs for use by all
slices, and the appropriate 0–15 bit
shift is accomplished. If the upper 16
bits are all zero, then the maximum
shift of 15 places is executed. Single
mantissas longer than 32 bits can be
accomplished by cascading LSH32
units. When cascading for normaliza-
tion, the device inputs are overlapped
such that each device lower in priority
than the first shares 16 inputs with its
more significant neighbor. Fill mode
and left shift are selected, however,
internal normalization (NORM) is not
used. The most significant result half
of each device is enabled to the
SINGLE CYCLE LONG-WORD
NORMALIZATION
An extension of the above concept is a
single clock normalization of long
words (potentially requiring shifts of
more than 15 places). The arrange-
ment of LSH32s required is shown in
Figure 1. Cascading of LSH32 units is
accomplished by connecting the SI3–
SI0 input lines of each unit to the SO3–
SO0 outputs of the most significant
device in the row as before. Essen-
output. The shift out (SO4–SO0) lines
of the most significant slice are
connected to the shift in lines of all
FIGURE 1. SINGLE CYCLE LONG-WORD NORMALIZATION USING LSH32S
I
63-I48
I
47-I32
I
31-I16
I
15-I
0
0
MSBs
4
4
4
4
5
5
5
5
4
4
4
4
4
4
LSH32
LSH32
SI3-0
LSH32
SI3-0
LSH32
SI3-0
SI3-0
SO4-0
OE
OE
OE
OE
SI
4
PRIORITY
I
47-I32
I
31-I16
I
15-I
0
0
ENCODE
2:4
LSH32
LSH32
SI3-0
LSH32
SI3-0
DECODE
SI3-0
SO4-0
OE
OE
0
OE
SI
4
I
31-I16
I15-I0
LSH32
LSH32
SI3-0
SI3-0
SO4-0
OE
OE
SI
4
I
16-I
0
0
LSH32
SO4-0
OE
SI3-0
SI
4
Y
63-Y48
Y
47-Y32
Y
31-Y16
Y15-Y0
Special Arithmetic Functions
08/16/2000–LDS.32-Q
ffs4
LSH32
DEVICES INCORPORATED
32-bit Cascadable Barrel Shifter
tially the LSH32s are arranged in
multiple rows or banks such that the
inputs to successive rows are left-
shifted by 16 positions. The outputs
of each row are multiplexed onto a
three-state bus. The normalization
problem then reduces to selecting
from among the several banks that
one which has the first non-zero bit
of the input value among its 16 most
significant positions. If the most
significant one in the input file was
within the upper 16 locations of a
given bank, the SO4 output of the
The number of shift positions can be
BLOCK FLOATING POINT
determined simply by concatenation
of the SO3–SO0 outputs of the most
significant slice in the selected row
with the encoded Output Enable-bits
determining the row number. Note
that lower rows need not be fully
populated. This is because they
represent left shifts in multiples of 16
positions, and the lower bits of the
output word will be zero filled. In
order to accomplish this zero fill, the
least significant device in each row is
always enabled, and the row select is
With a small amount of external logic,
block floating point operations are
easily accomplished by the LSH32.
Data resulting from a vector operation
are applied to the LSH32 with the
NORM-input deasserted. The SO4–
SO0 outputs fill then represent the
normalization shift distance for each
vector element in turn. By use of an
external latch and comparator, the
maximum shift distance encountered
across all elements in the vector is
saved for use in the next block opera-
tion (or block normalization). During
this subsequent pass through the data,
the shift code saved from the previous
pass is applied uniformly across all
elements of the vector. Since the
LSH32 is not used in the internal
normalize mode, this operation can be
pipelined, thereby obtaining the
desired shift distance for the next pass
while simultaneously applying the
normalization required from the
previous pass.
most significant slice in that bank will instead connected to the SI4 input.
be low. Single clock normalization
can thus be accomplished simply by
enabling onto the three-state output
bus the highest priority bank in which containing that device is not selected.
this condition is met. In this way the
input word will be normalized
This will force the shift length of the
least significant device to a value
greater than 15 whenever the row
This results in zero fill being accom-
plished by the equivalently positioned
slice in a higher bank, as shown in the
diagram.
regardless of the number of shift
positions required to accomplish this.
Special Arithmetic Functions
08/16/2000–LDS.32-Q
5
LSH32
DEVICES INCORPORATED
32-bit Cascadable Barrel Shifter
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
4.75 V ≤ VCC ≤ 5.25 V
4.50 V ≤ VCC ≤ 5.50 V
Active Operation, Commercial
Active Operation, Military
–55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
VOH
VOL
VIH
Parameter
Test Condition
Min
Typ
Max Unit
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 8.0 mA
2.4
V
0.4
VCC
0.8
V
V
2.0
0.0
VIL
(Note 3)
V
IIX
Ground ≤ VIN ≤ VCC (Note 12)
Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6)
±20
±20
µA
µA
IOZ
Output Leakage Current
VCC Current, Dynamic
VCC Current, Quiescent
ICC1
ICC2
10
30 mA
1.5 mA
(Note 7)
Special Arithmetic Functions
08/16/2000–LDS.32-Q
ffs6
LSH32
DEVICES INCORPORATED
32-bit Cascadable Barrel Shifter
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LSH32–
*
42
32
20
Symbol Parameter
Min
Max
Min
Max
Min
Max
tIY
I, SIGN Inputs to Y Outputs
42
32
20
tIYN
tISO
tSIY
tMSY
tDIS
tENA
I, SIGN Inputs to Y Outputs, Normalize Mode
I, SIGN Inputs to SO Outputs
75
55
52
28
20
20
60
42
40
24
20
20
20
20
20
15
15
15
SI, RIGHT/LEFT to Y Outputs
MS/LS Select to Y Outputs
Three-State Output Disable Delay (Note 11)
Three-State Output Enable Delay (Note 11)
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
LSH32–
*
50
*
40
*
30
Symbol Parameter
Min
Max
Min
Max
Min
Max
tIY
I, SIGN Inputs to Y Outputs
50
40
30
tIYN
tISO
tSIY
tMSY
tDIS
tENA
I, SIGN Inputs to Y Outputs, Normalize Mode
I, SIGN Inputs to SO Outputs
85
65
62
32
22
22
75
52
52
26
20
20
58
42
40
24
17
17
SI, RIGHT/LEFT to Y Outputs
MS/LS Select to Y Outputs
Three-State Output Disable Delay (Note 11)
Three-State Output Enable Delay (Note 11)
SWITCHING WAVEFORMS
I
31-I0
SIGN
SI4-SI
0
RIGHT/LEFT
MS/LS
tIY, tIYN
SO
4
-SO
0
0
t
MSY
tISO
Y
31-Y
t
SIY
OE
t
DIS
t
ENA
HIGH IMPEDANCE
Y
31-Y
0
*DISCONTINUED SPEED GRADE
Special Arithmetic Functions
08/16/2000–LDS.32-Q
7
LSH32
DEVICES INCORPORATED
32-bit Cascadable Barrel Shifter
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point
11. For the tENA test, the transition is
ationoftheseproductsatvaluesbeyond output reference levels of 1.5 V (except
those indicated in the Operating Condi-
with datasheet loads. For the tDIS test,
the transition is measured to the
tDIS test), and input levels of nominally
tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a ±200mV level from the measured
maximum rating conditions for ex- resistive divider which provides for steady-state output voltage with
tended periods may affect reliability.
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec-
ification include internal circuitry de-
signedto protect the chipfrom damag-
ing substrate injection currents and ac-
cumulationsofstaticcharge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-
bridge with upper and lower current to-1 and 1-to-Z tests.
sources of IOH and IOL respectively,
12. These parameters are only tested at
and a balancing voltage of 1.5 V may be
the high temperature extreme, which is
used. Parasitic capacitance is 30 pF
the worst case for leakage current.
minimum, and may be distributed.
FIGURE A. OUTPUT LOADING CIRCUIT
stress values.
pulses and fast turn-on/turn-off times.
Asaresult, caremustbeexercisedinthe
testing of this device. The following
measures are recommended:
S1
DUT
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
I
OL
VTH
CL
I
OH
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
FIGURE B. THRESHOLD LEVELS
t
ENA
tDIS
tion will not be adversely affected, how-
ever, input current levels will be well in and the tester common, and device
should be installed between device VCC
OE
0
1.5 V
1.5 V
excess of 100 mA.
ground and tester common.
Z
Z
3.5V Vth
1.5 V
1.5 V
V
OL*
0.2 V
0.2 V
0
1
Z
Z
4. Actualtestconditionsmayvaryfrom
b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified. socket or contactor fingers.
V
OH*
1
0V Vth
VOL*
Measured VOL with IOH = –10mA and IOL = 10mA
5. Supply current for a given applica- c. Input voltages should be adjusted to
V
OH* Measured VOH with IOH = –10mA and IOL = 10mA
tioncanbeaccuratelyapproximatedby:
compensateforinductivegroundand VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
2
NCV F
4
where
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirementsofallparts. Responsesfrom
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximumsinceworst-caseoperationof
anydevicealwaysprovidesdatawithin
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
Special Arithmetic Functions
08/16/2000–LDS.32-Q
ffs8
LSH32
DEVICES INCORPORATED
32-bit Cascadable Barrel Shifter
ORDERING INFORMATION
68-pin
68-pin
1
2
3
4
5
6
7
8
9
10
11
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I
I
30
31
GND
I
I
29
30
I
I
28
27
I
I
26
25
I
I
24
23
I
I
22
21
I
I
20
19
I
I
18
17
I
I
16
I14
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I
I
I
I
I
I
I
I
I
I
I
I
I
I
13
12
11
10
9
B
SIGN
I
31
15 GND GND
SO
SO
SO
SO
SO
4
3
2
1
0
C
SO
SO
SO
4
2
0
SIGN
I
I
12
10
I
I
13
11
D
E
F
G
H
J
SO
3
1
8
7
Top
Top View
Through Package
(i.e., Component Side Pinout)
SO
I
8
6
4
2
0
I
9
7
5
3
1
NORM
6
View
SI
SI
SI
SI
SI
R/L
F/W
31/15
4
3
2
1
0
5
SI
SI
SI
4 NORM
I
I
I
I
I
I
I
I
4
3
2
SI
3
1
2
1
0
SI
0
V
V
CC
CC
F/W R/L
Y
K
L
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Y31/15
Y
30/14
29/13
Y
28/12
27/11
Y
26/10
Y
24/8
23/7
Y
22/6
21/5
Y
20/4
19/3
Y
18/2
Y
16/0
V
CC
VCC
Y
Y
Y
25/9
Y
Y
Y
Y17/1 OE MS/LS
Discontinued Package
Plastic J-Lead Chip Carrier
(J2)
Ceramic Pin Grid Array
(G1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
32 ns
20 ns
LSH32JC32
LSH32JC20
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Special Arithmetic Functions
08/16/2000–LDS.32-Q
9
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