LF48908JC50 [LOGIC]
Video Convolver ; 视频卷积器\n
| 型号： | LF48908JC50 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | Video Convolver
|
| 文件： | 总16页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LF48908
Two Dimensional Convolver
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The LF48908 is a high-speed two
dimensional convolver that imple-
ments a 3 x 3 kernel convolution at
real-time video rates. Programmable
row buffers are located on-chip,
cycle. The FRAME signal resets all
data registers without affecting the
control and coefficient registers.
❑ 40 MHz Data and Computation
Rate
❑ Nine Multiplier Array with 8-bit
Data and 8-bit Coefficient Inputs
Pixel and coefficient input data are
both 8-bits and can be either signed or
unsigned integers. Image data should
be in a raster scan non-interlaced
format. The LF48908 can internally
store images as wide as 1024 pixels for
the 3 x 3 convolution. By using
external row buffers and multiple
LF48908s, longer pixel rows can be
used and convolutions with larger
kernel sizes can be performed. Out-
put data is 20-bits and this guarantees
no overflow for kernel sizes up to 4 x 4.
A separate cascade input is used as
the data input for summing results
from multiple LF48908s. It can also
function as the data input path when
external line buffers are used.
❑ Separate Cascade Input and Output
eliminating the need for external data
storage. Each row buffer can store up
to 1024 pixels. Two internal register
banks are provided allowing two
separate sets of filter coefficients to be
stored simultaneously. Adaptive filter
operations are possible when both
register banks are used. An on-chip
ALU is provided, allowing real-time
arithmetic and logical pixel point
operations to be performed on the
image data. The 3 x 3 convolver
comprises nine 8 x 8-bit multipliers,
various pipeline registers, and sum-
mers. A complete sum-of-products
operation is performed every clock
Ports
❑ On-board Programmable Row
Buffers
❑ Two Coefficient Mask Registers
❑ On-board 8-bit ALU
❑ Two’s Complement or Unsigned
Operands
❑ Replaces Harris HSP48908
❑ DECC SMD No. 5962-93007
❑ Package Styles Available:
• 84-pin Plastic LCC, J-Lead
• 100-pin Plastic Quad Flatpack
FIGURE 1. LF48908 BLOCK DIAGRAM
16
CASI15-0
8
DIN7-0
8
ROW
BUFFERS
CIN9-0
ALU
3
A
2-0
LD
CS
20
3 x 3
DOUT19-0
CONVOLVER
8
CASO7-0
CLK
HOLD
EALU
RESET
FRAME
OE
CONTROL
LOGIC
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LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
FIGURE 2. LF48908 FUNCTIONAL BLOCK DIAGRAM
ALU
7-0
8
15-8
8
DIN7-0
8
8
8
ROW
BUFFER
ROW
CASO7-0
BUFFER
8
7-0
CIN9-0
2:1
2:1
ALU
REGISTER
10
I
F
C
3
A2-0
CONTROL
LOGIC
LD
CS
H
E
B
G
D
A
CLK
HOLD
EALU
RESET
FRAME
OE
16
20
20
CASI15-0
SHIFT
0
20
DOUT19-0
NOTE: NUMBERS IN REGISTER INDICATE
NUMBER OF PIPELINE DELAYS.
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LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
SIGNAL DEFINITIONS
Power
CASO7-0 — Cascade Output
A2-0 — Control Logic Address Lines
The data presented on CASO7-0 is the
A2-0 determines which Control Logic
internal ALU output delayed by twice Register will receive the CIN9-0 data.
the programmed internal row buffer
VCC and GND
length.
+5 V power supply. All pins must be
connected.
CS — Chip Select
When CS is LOW, data can be loaded
into the Control Logic Registers.
When CS is HIGH, data can not be
loaded and the register contents will
not be changed.
Controls
Clock
RESET — Reset Control
CLK — Master Clock
When RESET is LOW, all internal
circuitry is reset, all outputs are forced
LOW, all Control Logic Registers are
loaded with their default values
(which is 0 for each one except the
ALU Microcode Register which has a
default value of “0000011000”), and all
other internal registers are loaded
with a “0”.
The rising edge of CLK strobes all
enabled registers except for the
Control Logic Registers.
LD — Load Strobe
If CS and LD are LOW, the data
present on CIN9-0 will be latched into
the Control Logic Register addressed
by A2-0 on the rising edge of LD.
Inputs
DIN7-0 — Pixel Data Input
DIN7-0 is the 8-bit registered pixel
data input port. Data is latched on the
rising edge of CLK.
FUNCTIONAL DESCRIPTION
FRAME — New Frame Input Control
The LF48908, a two-dimensional
When asserted, FRAME signals the
start of a new frame. When FRAME is
LOW, all internal circuitry is reset
except for the ALU Microcode, Row
Length, Initialization, Coefficient, and
ALU Registers.
convolver, executes convolutions using
internal row buffers to reduce design
complexity and board space require-
ments. 8-bit image data, in raster scan,
non-interlace format, is convolved with
one of two internal, 3 x 3 user-
programable filter kernels. Two 1024 x 8-
bit row buffers provide the data delay
needed to perform two-dimensional
convolutions on a single chip. The result
output of 20-bits allows for word growth
during the convolution operation.
CIN9-0 — Coefficient and Control Logic
Register Input
CIN7-0 is used to load the Coefficient
Registers or can be used to provide a
second operand input to the ALU.
CIN8-0 is used to load the Initializa-
tion Register. CIN9-0 is used to load
the ALU Microcode and Row Buffer
Length Registers. The Control Regis-
ter Address Lines, A2-0, determine
which register will receive the CIN
data. The CIN data is loaded into the
addressed register by using the CS
and LD control inputs.
EALU — Enable ALU Register Input
When HIGH, data on CIN7-0 is latched
into the ALU Register on the next
rising edge of CLK. When LOW, data
on CIN7-0 will not be latched into the
ALU Register and the register con-
tents will not be changed.
The input data path (DIN7-0) provides
access to an 8-bit ALU. This allows
point operations to be performed on
the incoming data stream before
reaching the row buffers and the
convolver. The length of these buffers
is programmable for use in various
video formats without the need for
additional external delay.
HOLD — Hold Control
CASI15-0 — Cascade Input
The HOLD input is used to disable
CLK from all of the internal circuitry.
HOLD is latched on the rising edge of
CLK and takes effect on the next rising
edge of CLK. When HOLD is HIGH,
CLK will have no effect on the
The cascade input is used when
multiple LF48908s are cascaded
together or when external row buffers
are needed. This allows convolutions
of larger kernels or longer row sizes.
This device is configured by loading
the coefficent data (filter kernels) and
row buffer length through the
LF48908 and all internal data will
remain unchanged.
Outputs
coefficent data path (CIN7-0). Internal
registers are addressed using the A2-0
address lines. Chip Select (CS) and
Load Strobe (LD) complete the
configuration interface which may be
controlled by standard microproces-
sors without additional external logic.
DOUT19-0 — Data Output
OE — Output Enable
DOUT19-0 is the 20-bit registered data
output port.
When OE is LOW, DOUT19-0 is
enabled for output. When OE is
HIGH, DOUT19-0 is placed in a high-
impedance state.
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LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
The filtered image data is output on
the Data Output bus (DOUT19-0). This taken from the ALU Register. The
bus is registered with three-state
drivers to facilatate use on a standard
microprocessor system bus.
data path, while the “B” operand is
multiplier array. The Cascade Output
(CASO7-0) provides a 2X row delay of
the input data allowing for cascading
of LF48908s to handle larger frames
and/or kernel sizes. If more than 1024
delay stages are needed, it is possible
to use external row buffers and bypass
ALU Register is loaded using CIN7-0
and EALU. With EALU HIGH, data
from CIN7-0 is loaded into the ALU
Register on the rising edge of CLK.
With EALU LOW, the data is held in
the ALU Register. Since CIN7-0 is also the internal row buffers. Bit 0 of the
used to load the Control Logic Regis-
ters, it is possible to overwrite data in
Data Input
Image data is input to the 3 x 3
Initialization Register determines if
internal or external row buffers are
convolver using DIN7-0. Data present
on DIN7-0 is latched into a program-
mable pipeline delay on the rising
edge of CLK. The programmable
pipeline delay (1 to 4 clock cycles)
allows for synchronization of input
data when multiple LF48908s are
cascaded together to perform larger
convolutions. This delay is pro-
gramed via the Initialization Register
(see Table 3). The image data format,
those registers if CS and LD are active used. If Bit 0 is a “0”, the internal row
when loading the ALU Register.
Therefore, special care must be taken
to ensure that CS and LD are not
active when writing to the ALU
Register.
buffers are used. If Bit 0 is a “1”, the
internal row buffers are bypassed and
external row buffers may be used.
3 x 3 Multiplier Array
The multiplier array comprises nine
8 x 8-bit multipliers. The active
Coefficient Register supplies the
coefficents to each of the multipliers,
while the pixel data comes from the
data input path and row buffers. The
array forms a sum-of-products result
as defined by the equation listed in
Figure 3.
Programmable Row Buffers
The two internal row buffers provide
unsigned or two’s complement, is also the delay needed to perform the two-
controlled by this register.
dimensional convolution. The row
buffers function like 8-bit serial shift
registers with a user-programmable
delay from 1 to 1024 stages (it is
possible to select delay stages of 1 or
2, but this leads to meaningless results
for a 3 x 3 kernel convolution). The
row buffer length is set via the Row
Length Register (see Row Length
Register Section). The row buffers are
connected in series to provide the
proper pixel information to the
Coefficient data is input to the 3 x 3
convolver using either of two Coef-
ficient Registers (CREG0 or CREG1).
The Coefficient Registers are loaded
through CIN7-0 using the A2-0, CS, and
LD controls. The coefficient data
format, unsigned or two’s comple-
ment, is determined by the Initializa-
tion Register.
CONTROL LOGIC
Four sets of registers, the ALU Micro-
code, Row Length, Initialization, and
Coefficient, define the Control Logic
section. These registers are updated
Arithmetic Logic Unit
FIGURE 3. MULTIPLIER ARRAY OUTPUT
The input data path ALU with shifter
allows pixel point operations to be
performed on the incoming image.
These operations include arithmetic
functions, logical masking, and left/
right shifts. The 10-bit ALU Micro-
code Register controls the various
operations. The three upper bits
control the shift amount and direction
while the seven lower bits determine
the arithmetic or logical operation.
The shift operation is performed on
the output of the ALU. This shift
operation is independent of the
arithmetic or logical operation of the
ALU.
PIXEL INPUT DATA
FILTER KERNEL
P1
P4
P7
P2
P5
P8
P3
P6
P9
A
D
G
B
E
H
C
F
I
MULTIPLIER ARRAY OUTPUT = A(P1) + B(P2) + C(P3)
+ D(P4) + E(P5) + F(P6)
Tables 1 and 2 show the operations of
the ALU Microcode Register. The “A”
operand comes from the DIN input
+ G(P7) + H(P8) + I(P9)
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LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
FIGURE 4. LF48908 CONTROL LOGIC BLOCK DIAGRAM
ENCR1
ENCR0
CAS
3
A2-0
ADDRESS
DECODE
LD
CR1
CR0
CS
LMC
EOR
10
10
10
9
CIN9-0
ALU MICROCODE REGISTER
ALU MICROCODE
ROW LENGTH
LMC
EOR
CAS
ROW LENGTH REGISTER
9
8
8-0
7-0
INITIALIZATION REGISTER
INITIALIZATION DATA
COEFFICIENT REGISTER 0
F0 E0 D0
I0
H0
G0
C0
B0
A0
CR0
OE
OE
OE
OE
OE
OE
OE
OE
OE
8
8
8
8
8
8
8
8
8
I
H
G
ENCR1
ENCR0
S
R
Q
Q
F
E
D
C
B
A
8
7-0
OE
OE
OE
OE
OE
OE
OE
OE
OE
I1
H1
G1
F1
E1
D1
C1
B1
A1
CR1
COEFFICIENT REGISTER 1
through the CIN bus using A2-0, CS,
Row Length Register
be loaded within 1024 CLK cycles. If
the Row Length Register is not loaded
within 1024 CLK cycles, the register
will automatically be loaded with a “0”.
and LD (see Figure 4). All the Control
Logic Registers are set to their default
values when RESET is active. FRAME
does not affect the values in these
registers.
The value stored in the Row Length
Register determines the number of
delay stages for each row buffer. The
number of delay stages should be set
equal to the row length of the input
image. The Row Length Register may
be loaded with the values 0 through
1023 (0 represents 1024 delay stages).
It is possible to program the row
buffers to have 1 or 2 delay stages, but
this will lead to meaningless results
for a 3 x 3 convolution. This register is
loaded through CIN9-0 using the A2-0,
CS, and LD controls. Once the Row
Length Register has been loaded, a
new value can not be loaded until the
LF48908 has been reset. This is done
by asserting RESET. After RESET goes
HIGH, the Row Length Register must
Initialization Register
The Initialization Register configures
various functions of the device
ALU Microcode Register
Operation of the ALU and shifter are
determined by the value stored in the
ALU Microcode Register. This 10-bit
instruction word is divided into two
fields. The lower seven bits define the
arithmetic and logical operations of the
ALU. The upper three bits specify shift
distance and direction. Tables 1 and 2
detail the various instruction words.
This register is loaded through CIN9-0
using the A2-0, CS, and LD controls.
Also see Arithmetic Logic Unit section.
including: input data delay, input
data format, coefficent data format,
output rounding, cascade mode, and
cascade input shift (see Table 3). This
register is loaded through CIN8-0
using the A2-0, CS, and LD controls.
Coefficient Registers - CREG0, CREG1
The Coefficient Registers are used to
store the filter coefficients for the
multiplier array. Each Coefficient
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DEVICES INCORPORATED
Two Dimensional Convolver
TABLE 1. ALU SHIFT OPERATIONS
ALU MICROCODE REGISTER
REGISTER BIT
TABLE 2. ALU LOGICAL AND ARITHMETIC OPERATIONS
ALU MICROCODE REGISTER
REGISTER BIT
9
0
0
0
0
1
1
1
1
8
0
0
1
1
0
0
1
1
7
0
1
0
1
0
1
0
1
OPERATION
No Shift (Default)
Shift Right 1
Shift Right 2
Shift Right 3
Shift Left 1
6
0
1
0
0
1
1
0
1
1
0
0
0
0
1
1
1
1
0
1
5
0
1
0
1
1
0
1
0
0
0
0
1
1
0
1
1
0
1
0
4
0
1
1
0
0
1
1
0
0
0
1
0
1
1
0
1
0
1
0
3
0
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
0
1
2
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
OPERATION
Logical (00000000)
Logical (11111111)
Logical (A) (Default)
Logical (B)
Logical (A)
Shift Left 2
Logical (B)
Shift Left 3
Arithmetic (A + B)
Arithmetic (A – B)
Arithmetic (B – A)
Logical (A AND B)
Logical (A AND B)
Logical (A AND B)
Logical (A OR B)
Logical (A OR B)
Logical (A OR B)
Logical (A NAND B)
Logical (A NOR B)
Logical (A XOR B)
Logical (A XNOR B)
Not Valid
Register can hold nine 8-bit values.
This allows two different 3 x 3 filter
kernels to be stored simultaneously on
the LF48908. The outputs of CREG0
and CREG1 are connected to the
coefficient inputs of the multiplier
array (A through I). The register used
to supply the coefficient data is
determined by the address written to
the Address Decoder. If a “101” is
written to the Address Decoder,
CREG0 will provide the coefficient
data. If a “110” is written to the
Address Decoder, CREG1 will be used.
It is possible to switch between the
two Coefficient Registers in real time.
This facilitates adaptive filtering
operations. It is important to remem-
ber to meet the tLCS timing specifica-
tion when switching the Coefficient
Registers. When a Coefficient Register
is selected to supply data to the
multiplier array (one of the registers is
always selected), all of its outputs are
enabled simultaneously. When RESET
is asserted, CREG0 is the default
register selected to supply the coeffi-
cient data.
loaded is determined by the data on
A2-0 during the load operation. If
CREG0 is to be loaded, “010” must be
placed on A2-0 during the load opera-
tion. If CREG1 is to be loaded, “011”
latched into the addressed register
when LD goes HIGH. To select a
Coefficient Register (CREG0 or
CREG1) to send data to the multiplier
array, the appropriate address must be
must be placed on A2-0. If desired, the placed on A2-0, and CS and LD must
Coefficient Register that is not being
used to send data to the multiplier
array can be loaded with coefficient
data while the LF48908 is in active
operation.
be asserted. When LD goes HIGH, the
addressed register will begin supply-
ing coefficient data to the multiplier
array. Table 4 lists all of the register
addresses.
The Control Logic Registers can be
modified during active operation of
the LF48908. If this is done, it is very
important to meet the tLCS timing
specification. This is to ensure that the
outputs of the Control Logic Registers
have enough time to change before the
next rising edge of CLK. If tLCS is not
met, unexpected results may occur on
DOUT19-0 for one clock cycle. There
are two situations in which tLCS may
Address Decoder
The Address Decoder is used to load
the Control Logic Registers and to
determine which Coefficient Register
sends data to the multiplier array. To
load a Control Logic Register, the
address of the register must be placed
on A2-0, the data to be written must be
placed on the CIN bus, and CS and
LD must be asserted. The data is
CREG0 and CREG1 are loaded
through CIN7-0 using the A2-0, CS, and
LD controls. The nine coefficient
values are presented on CIN7-0 one by
one, in order from A to I. As each
value is placed on CIN7-0, it is latched
into the selected Coefficient Register
using CS and LD. The register to be
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LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
be ignored. If the LF48908 is not in
active operation or if the innactive
Coefficient Register is being written to
during active operation.
TABLE 4. CONTROL LOGIC
ADDRESS MAP
TABLE 3. INITIALIZATION REGISTER
BIT
FUNCTION
0
CASCADE MODE
A2-0
FUNCTION
0
Multiplier input from internal row buffers
Multiplier input from external buffers
INPUT DATA DELAY
000
Load Row Buffer Length
Register
Cascade Operation
1
001
010
011
100
101
Load ALU Microcode Register
Load Coefficient Register 0
Load Coefficient Register 1
Load Initialization Register
The Cascade Input lines (CASI15-0)
and Cascade Output lines (CASO7-0)
are used to allow convolutions of
kernel sizes larger than 3 x 3. The
Cascade Input lines are also used to
allow convolutions on row lengths
longer than 1024 pixels. The Cascade
Mode Bit (Bit 0) of the Initialization
Register determines the function of
the Cascade Input lines. If the Cas-
cade Mode Bit is a “0”, then the
2
1
0
1
0
1
0
0
1
1
No data delay registers used
One data delay register used
Two data delay registers used
Three data delay registers used
INPUT DATA FORMAT
Unsigned integer format
Two’s complement format
COEFFICIENT DATA FORMAT
Unsigned integer format
Two’s complement format
OUTPUT ROUNDING
Select Coefficient Register 0
for Internal Processing
3
0
1
4
0
1
110
111
Select Coefficient Register 1
for Internal Processing
No Operation
Cascade Input lines are to be used to
cascade multiple LF48908s together to
perform convolutions of larger kernel
sizes. CASI15-0 will be left shifted (by
an amount determined by bits 7 and 8
of the Initialization Register) and then
added to DOUT19-0. Cascading is
accomplished by connecting CASO7-0
and DOUT19-0 of one LF48908 to
DIN7-0 and CASI15-0 respectively of
another LF48908. If the Cascade
Mode Bit is a “1”, then the Cascade
Input lines are to be used with exter-
nal row buffers to allow for longer
row lengths. In this mode, the Cas-
cade Input lines are split into two 8-bit
data busses (CASI15-8 and CASI7-0)
which are fed directly into the multi-
plier array.
6
0
0
1
1
8
0
0
1
1
5
0
1
0
1
7
0
1
0
1
No rounding
Round to 16 bits (i.e. DOUT19-4)
Round to 8 bits (i.e. DOUT19-12)
Not valid
CASI15-0 INPUT SHIFT
No shift
Shift CASI15-0 left two
Shift CASI15-0 left four
Shift CASI15-0 left eight
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DEVICES INCORPORATED
Two Dimensional Convolver
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... –0.5 V to VCC + 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
4.75 V ≤ VCC ≤ 5.25 V
4.50 V ≤ VCC ≤ 5.50 V
Active Operation, Commercial
Active Operation, Military
–55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
Min
Typ
Max Unit
VOH
VOL
VIH
Output High Voltage
VCC = Min., IOH = –400 µA
VCC = Min., IOL = 2.0 mA
2.8
V
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
0.4
VCC
0.8
V
V
2.0
0.0
VIL
(Note 3)
V
IIX
Ground ≤ VIN ≤ VCC (Note 12)
Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6)
±10
±10
µA
µA
IOZ
Output Leakage Current
VCC Current, Dynamic
VCC Current, Quiescent
Input Capacitance
Output Capacitance
ICC1
ICC2
CIN
COUT
110 mA
(Note 7)
500
10
µA
pF
pF
TA = 25°C, f = 1 MHz
TA = 25°C, f = 1 MHz
12
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DEVICES INCORPORATED
Two Dimensional Convolver
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LF48908–
50
31
25
Symbol Parameter
tCYC
Min
Max
Min
Max
Min
Max
Cycle Time
tPWH Clock Pulse Width High
50
31
25
20
20
14
0
12
13
13
0
8
8
tPWL
tDS
tDH
tCS
tCH
tES
tEH
tD
Clock Pulse Width Low
Data Input Setup Time
Data Input Hold Time
8
0
CIN7-0 Setup Time
16
0
14
0
10
0
CIN7-0 Hold Time
EALU Setup Time
14
0
12
0
10
0
EALU Hold Time
Output Delay
22
22
32
16
16
28
15
15
8
tENA
tDIS
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
SWITCHING WAVEFORMS: CONVOLVER DATA I/O
tCYC
tPWL
tPWH
CLK
tDS
tCS
tES
tDH
tCH
tEH
DIN7-0
CASI15-0
CIN7-0
(ALU REG DATA)
EALU
OE
tD
tD
tDIS
tENA
CASO7-0
DOUT19-0
HIGH IMPEDANCE
Video Imaging Products
08/9/2000–LDS.48908-J
9
LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
LF48908–
*
50
*
37
*
25
Symbol Parameter
tCYC
Min
Max
Min
Max
Min
Max
Cycle Time
tPWH Clock Pulse Width High
50
37
25
20
20
17
0
15
15
16
0
8
8
tPWL
tDS
tDH
tCS
tCH
tES
tEH
tD
Clock Pulse Width Low
Data Input Setup Time
Data Input Hold Time
8
0
CIN7-0 Setup Time
20
0
17
0
10
0
CIN7-0 Hold Time
EALU Setup Time
17
0
15
0
10
0
EALU Hold Time
Output Delay
28
28
40
19
19
35
15
15
8
tENA
tDIS
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
SWITCHING WAVEFORMS: CONVOLVER DATA I/O
tCYC
tPWL
tPWH
CLK
tDS
tCS
tES
tDH
tCH
tEH
DIN7-0
CASI15-0
CIN7-0
(ALU REG DATA)
EALU
OE
tD
tD
tDIS
tENA
CASO7-0
DOUT19-0
HIGH IMPEDANCE
*DISCONTINUED SPEED GRADE
Video Imaging Products
08/9/2000–LDS.48908-J
10
LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LF48908–
50
31
25
Symbol Parameter
Min
Max
Min
Max
Min
Max
tLPW
tLCS
tCDS
tCDH
tAS
LD Pulse Width
20
12
8
LD Setup Time (Applies only during active operation)
Configuration Data Setup Time
Configuration Data Hold Time
Address Setup Time
30
16
0
25
14
0
15
10
0
13
0
13
0
10
0
tAH
Address Hold Time
tCSS
tCSH
CS Setup Time
0
0
0
CS Hold Time
0
0
0
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
LF48908–
*
50
*
37
*
25
Symbol Parameter
Min
Max
Min
Max
Min
Max
tLPW
tLCS
tCDS
tCDH
tAS
LD Pulse Width
20
15
8
LD Setup Time (Applies only during active operation)
Configuration Data Setup Time
Configuration Data Hold Time
Address Setup Time
37
20
0
30
17
0
15
10
0
15
0
15
0
10
0
tAH
Address Hold Time
tCSS
tCSH
CS Setup Time
0
0
0
CS Hold Time
0
0
0
SWITCHING WAVEFORMS: CONFIGURATION DATA
CLK
t
LPW
tLCS*
LD
t
CDS
tCDH
CIN9-0
t
AS
tAH
A2-0
t
CSS
tCSH
CS
*applies only when the LF48908 is in active operation.
*DISCONTINUED SPEED GRADE
Video Imaging Products
08/9/2000–LDS.48908-J
11
LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LF48908–
50
31
25
Symbol Parameter
Min
Max
Min
Max
Min
Max
tHS
tHH
HOLD Setup Time
HOLD Hold Time
12
11
9
1
50
25
50
1
31
21
31
0
8
tFPW FRAME Pulse Width
FRAME Setup Time
tRPW RESET Pulse Width
tFS
20
8
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
LF48908–
*
50
*
37
*
25
Symbol Parameter
Min
Max
Min
Max
Min
Max
tHS
tHH
HOLD Setup Time
HOLD Hold Time
14
13
9
2
50
30
50
2
37
25
37
0
8
tFPW FRAME Pulse Width
FRAME Setup Time
tFS
20
8
tRPW RESET Pulse Width
SWITCHING WAVEFORMS: CONTROL SIGNALS
CLK
tHS
tHH
tHS
HOLD
FRAME
RESET
tFPW
tFS
tRPW
*DISCONTINUED SPEED GRADE
Video Imaging Products
08/9/2000–LDS.48908-J
12
LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with
11. For the tENA test, the transition is
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point
ationoftheseproductsatvaluesbeyond output reference levels of 1.5 V (except
those indicated in the Operating Condi-
tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a ±200mV level from the measured
maximum rating conditions for ex- resistive divider which provides for steady-state output voltage with
with datasheet loads. For the tDIS test,
the transition is measured to the
tDIS test), and input levels of nominally
tended periods may affect reliability.
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec-
ification include internal circuitry de-
signedto protect the chipfrom damag-
ing substrate injection currents and ac-
cumulationsofstaticcharge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-
bridge with upper and lower current to-1 and 1-to-Z tests.
sources of IOH and IOL respectively,
12. These parameters are only tested at
and a balancing voltage of 1.5 V may be
the high temperature extreme, which is
used. Parasitic capacitance is 30 pF
the worst case for leakage current.
minimum, and may be distributed.
FIGURE A. OUTPUT LOADING CIRCUIT
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
Asaresult, caremustbeexercisedinthe
testing of this device. The following
measures are recommended:
S1
DUT
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how-
ever, input current levels will be well in and the tester common, and device
excess of 100 mA.
I
OL
V
TH
C
L
I
OH
FIGURE B. THRESHOLD LEVELS
t
ENA
tDIS
should be installed between device VCC
OE
0
1.5 V
1.5 V
ground and tester common.
Z
Z
3.5V Vth
1.5 V
1.5 V
V
OL*
0.2 V
0.2 V
0
1
Z
Z
4. Actualtestconditionsmayvaryfrom
those designated but operation is guar- must be brought directly to the DUT
anteed as specified. socket or contactor fingers.
b. Ground and VCC supply planes
V
OH*
1
0V Vth
VOL*
Measured VOL with IOH = –10mA and IOL = 10mA
V
OH* Measured VOH with IOH = –10mA and IOL = 10mA
5. Supply current for a given applica- c. Input voltages should be adjusted to
tioncanbeaccuratelyapproximatedby:
compensateforinductivegroundand VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
2
NCV F
where
4
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirementsofallparts. Responsesfrom
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximumsinceworst-caseoperationof
anydevicealwaysprovidesdatawithin
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 20 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
Video Imaging Products
08/9/2000–LDS.48908-J
13
LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
ORDERING INFORMATION
84-pin
11 10
12
9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
GND
CLK
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
CASO6
CASO7
DOUT0
DOUT1
DOUT2
GND
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
VCC
VCC
Top
View
HOLD
LD
CS
DOUT8
GND
A2
A1
DOUT9
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
GND
A0
EALU
CASI15
CASI14
CASI13
CASI12
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Plastic J-Lead Chip Carrier
(J3)
Speed
0°C to +70°C — COMMERCIAL SCREENING
50 ns
31 ns
25 ns
LF48908JC50
LF48908JC31
LF48908JC25
–40°C to +85°C — COMMERCIAL SCREENING
Video Imaging Products
08/9/2000–LDS.48908-J
14
LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
ORDERING INFORMATION
100-pin
CIN1
CIN2
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
CASO5
NC
CASO6
CASO7
DOUT0
DOUT1
DOUT2
GND
NC
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
GND
GND
CLK
VCC
VCC
HOLD
LD
CS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
VCC
VCC
DOUT8
GND
Top
View
A2
A1
A0
GND
DOUT9
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
GND
GND
DOUT15
DOUT16
EALU
CASI15
CASI14
CASI13
CASI12
NC
NC
CASI11
Plastic Quad Flatpack
(Q2)
Speed
0°C to +70°C — COMMERCIAL SCREENING
31 ns
25 ns
LF48908QC31
LF48908QC25
–40°C to +85°C — COMMERCIAL SCREENING
Video Imaging Products
08/9/2000–LDS.48908-J
15
LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
ORDERING INFORMATION
84-pin
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
CIN
CIN
CIN
CIN
2
5
6
8
CIN
CIN
CIN
CIN
0
3
4
7
DIN
7
1
DIN
5
6
DIN
DIN
DIN
2
3
4
DIN
1
OE CASO
GND CASO
1
2
CASO
3
CASO
4
5
7
2
4
9
CASO
DOUT
DOUT
6
0
1
CIN
DIN
CASO
0
GND CASO
CASO
DIN0
VCC
DOUT
GND
Top View
Through Package
(i.e., Component Side Pinout)
CLK GND CIN
9
DOUT
DOUT
3
7
DOUT
DOUT
DOUT
DOUT
5
A1
VCC HOLD
6
8
CS
A2
LD
VCC GND DOUT
A0
EALU
DOUT11 DOUT10
DOUT14 DOUT12
CASI15 CASI13
CASI
CASI
CASI
5
4
3
CASI2 CASI1
K
L
CASI14 CASI11 CASI10 CASI
7
6
VCC FRAME DOUT19 DOUT16 GND DOUT13
CASI12 CASI
9
CASI
8
CASI
RESET CASI0 GND DOUT18 DOUT17 DOUT15
Discontinued Package
Ceramic Pin Grid Array
(G6)
Speed
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Video Imaging Products
08/9/2000–LDS.48908-J
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