L9D125G80BG4I8 [LOGIC]
2.5 Gb, DDR - SDRAM Integrated Module; 2.5 GB， DDR - SDRAM集成模块
| 型号： | L9D125G80BG4I8 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | 2.5 Gb, DDR - SDRAM Integrated Module |
| 文件： | 总45页 (文件大小：6016K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Benefits
FEATURES
53% SPACE savings vs. Monolithic,
TSOPII-66 solution
DDR SDRAM Data Rate = 200, 250,
266, and 333 Mbps
DQS edge-aligned with data for
READ; center-aligned with data for
WRITE
Reduced I/O routing (34%)
Package:
DLL to align DQx and DQSLx,
DQSHx transitions with CLKx
Reduced trace length providing
improved/reduced parasitic capaci-
tance
• 25mm x 25mm, Encapsulated
Plastic Ball Grid array (PBGA), 219
balls, 1.27mm pitch.
Four internal banks for concurrent
operation
Impedance matched (60ohm) pack-
2.5V ±0.2V Core Power supply
aging
One data mask per byte, IMOD con-
tains (10) bytes
2.5V ±0.2V I/O Power supply
(SSTL_2 compatible)
High TCE organic laminate inter-
poser
Programmable IOL/IOH Option
Auto PRECHARGE option
Differential Clock inputs (CLKx,
CLKx\)
Suitable for High Reliability applica-
tions
Commands entered on each positive
CLKx edge
Auto REFRESH and SELF
REFRESH Modes
Internal pipelined double-data-
rate (DDR) Architecture; two data
accesses per clock cycle
Available in INDUSTRIAL,
EXTENDED and Mil-Temp ranges
Organized as 16M x 72/80
Programmable Burst Length:
2, 4, or 8
Weight: LOGIC Devices, Inc.
L9D125G80BG4 = 2.75 grams
Bidirectional data strobe (DQSLx,
DQsHx) per byte transmitted/
received with data
typical
i.e. source-synchronous data capture
*Note: This integrated product and/or its specifications are subject to change without notice.
Latest document should be retrieved from LDI prior to your design consideration.
IMOD SOLUTION
MONOLITHIC SOLUTION
S
A
V
I
N
G
S
O
P
T
I
O
N
S
11.9
11.9
11.9
11.9
11.9
25mm
22.3
25mm
625mmꢀ
53%
34%
AREA
I/O
5 X 265mmꢀ = 1328mmꢀ PLUS
5 X 66 pins = 320 pins total
219 Balls/Locations
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
L9D125G80BG4, DDR1 SIGNAL LOCATION DIAGRAM
1
2
3
4
5
6
7
A9
A0
A2
A12
8
9
10
A8
11
12
13
DQ16
DQ18
DQ20
DQ22
DQML1
WE1\
CS1\
14
15
16
DQ0
DQ2
DQ4
DQ5
DQ14
DQ12
DQ10
DQ8
DQ15
DQ13
DQ11
DQ9
VSS
VSS
VCC
VSS
VSS
VCC
A10
A7
A11
A6
VCCQ VCCQ
DQ17
DQ19
DQ21
DQ23
VSS
DQ31
DQ29
DQ27
DQ26
NC
VSS
A
B
C
D
E
F
A
B
C
D
E
F
DQ1
DQ3
DQ6
A1
VCC
VSS
VSS
VCC
VSS
DQ30
DQ28
DQ25
DQ24
A5
A4
A3
VCCQ VCCQ
RFU
BA0
RFU
BA1
RFU
VSS
DQ7 DQML0 VCC DQMH0 DQSH3 DQSL0 DQSH0
DQSL1 DQSH1
Vref
CAS0\
CS0\
VSS
WE0\
RAS0\
VSS
VCC
VCC
VCC
VCC
VCC
VCC
CLK0 DQSL3
RAS1\
CAS1\
VCC
VSS DQMH1 CLK1
CKE0
VCCQ
VCCQ
CS3\
CLK0\
VSS
VSS
VSS
VSS
VSS
VSS
CLK1\
VCCQ
VCCQ
RAS2\
WE2\
CKE1
VCC
G
H
J
G
H
J
VSS
VSS
VSS
VSS
VCC
VSS
VCC
CLK3\
NC
CKE3
CLK3
DQSL4
CLK2\
CKE2
CS2\
CAS2\
K
L
K
L
CAS3\ RAS3\
DQSL2 CLK2
DQ56 DQMH3 VCC
WE3\ DQML3 CKE4 DQMH4 CLK4
CAS4\
DQ71
DQ69
DQ67
DQ65
9
WE4\
RAS4\
CS4\ DQMH2 VSS
DQML2 DQ39
M
N
P
R
T
M
N
P
R
T
DQ57
DQ60
DQ62
VSS
1
DQ58
DQ59
DQ61
DQ63
2
DQ55
DQ53
DQ51
DQ49
3
DQ54 DQSH4 CLK4\
DQ73
DQ75
DQ77
DQ72
DQ74
DQ76
DQ78
8
DQ70 DQML4 DQSH2 DQ41
DQ40
DQ42
DQ44
DQ46
14
DQ37
DQ36
DQ34
DQ32
15
DQ38
DQ35
DQ33
VCC
16
DQ52
DQ50
VSS
VCC
VSS
VCC
DQ68
DQ66
DQ64
10
VCC
VSS
VSS
11
VCC
VSS
VSS
12
DQ43
DQ45
DQ47
13
DQ48 VCCQ VCCQ DQ79
4
5
6
7
Address
V + (I/O Power)
NC
UNPOPULATED
Level REF
V + (Core Power)
CNTRL
VSS
Data IO
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
F
u n c t io n a l
Bl o c k
Dia g r a m
VCCQ
VCC
VRef
VSS
A0-A12, BA0-1
A, BA
A, BA
A, BA
A, BA
A, BA
VSS VRef VCC VCCQ
DQ
•
•
0
DQ
•
•
0
CS0\
RAS0\
CAS0\
CKE0
CLK0
CLK0\
WE0\
DQML0
DQMH0
DQSL0
DQSH0
•
•
DQ
7
8
DQ
7
8
D0
DQ
DQ
•
•
•
•
•
•
DQ 15
DQ 15
VSS VRef VCC VCCQ
DQ 16
•
•
•
DQ
•
•
0
CS1\
RAS1\
CAS1\
CKE1
CLK1
CLK1\
WE1\
DQML1
DQMH1
DQSL1
DQSH1
•
DQ 23
DQ
7
8
D1
DQ 24
•
•
•
DQ
•
•
•
DQ 31
DQ 15
VSS VRef VCC VCCQ
DQ 32
•
•
•
DQ
•
•
0
CS2\
RAS2\
CAS2\
CKE2
CLK2
CLK2\
WE2\
DQML2
DQMH2
DQSL2
DQSH2
•
DQ 39
DQ
7
8
D2
DQ 40
•
•
•
DQ
•
•
•
DQ 47
DQ 15
VSS VRef VCC VCCQ
DQ 48
•
•
•
DQ
•
•
0
CS3\
RAS3\
CAS3\
CKE3
CLK3
CLK3\
WE3\
DQML3
DQMH3
DQSL3
DQSH3
•
DQ 55
DQ
7
8
D3
DQ 56
•
•
•
DQ
•
•
•
DQ 63
DQ 15
VSS VRef VCC VCCQ
DQ 64
•
•
•
DQ
•
•
0
CS4\
RAS4\
CAS4\
CKE4
CLK4
CLK4\
WE4\
DQML4
DQMH4
DQSL4
DQSH4
•
DQ 71
DQ
7
8
D4
DQ 72
•
•
•
DQ
•
•
•
DQ 79
DQ 15
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Pin/Ba l l lo c a t io n s /DeFinitions a n D Fu n c t io n a l De s c r iP t io n
BGA Locations
Symbol
Type
Description
F4, F16, G5, G15, K1,
Clock: CKx and CKx\ are differential clock inputs. All address and control input signals are
CNTL. Input
CKX,CKX\
K12, L2, L13, N6, M8
G4, G16, K2, K13, M6
sampled on the crossing of the positive edge of CKx and negative edge of CKx\. Output data
(DQ’s and DQS) is referenced to the crossings of the differential clock inputs.
Clock Enable: CKE controls the clock inputs. CKE High enables, CKE Low disables the clock
input pins. Driving CKE Low provides PRECHARGE POWER-DOWN. CKE is synchronous
for POWER-DOWN entry and exit, and for SELF-REFRESH entry CKE is asynchronous for
SELF-REFRESH exit and disabling the outputs. CKE must be maintained High throughout
READ and WRITE accesses. Input buffers are disabled during POWER-DOWN, input buffers
are disabled during SELF-REFRESH. CKE is an SSTL-2 input but will detect an LVCMOS
LOW level after VCC is applied.
CNTL. Input
CKEx
G1, G13, K4, K16, M12
Chip Select: CSx\ enables the COMMAND register(s) of each of the five (5) integrated
words. All commands are masked (registered) HIGH with CSx\ driven true. CSx\ provides for
external word/bank selection on systems with multiple banks. CSx\ is considered part of the
COMMAND CODE.
CNTL. Input
CSX\
F12, G2, K15, L5, M11
F1, G12, L4, L16, M9
F2, F13, L15, M4, M10
E2, E4, E13, F15, M2,
M5, M7, M13, M15, N11
Row Address Strobe: Command input along with CASx\ and WEx\
CNTL. Input
CNTL. Input
CNTL. Input
CNTL. Input
RASX\
CASX\
WEX\
Column Address Strobe: Command input along with RASx\ and WEx\
WRITE (word): Command input along with CASx\ and RASx\
Input Data Mask: DQM is an input mask signal for WRITE operations. Input Data is masked
when DQML/Hx is sampled HIGH at time of a WRITE access DQML/Hx is sampled on both
edges of DQSL/Hx.
DQMLX,
DQMHX
E5, E6, E7, E10, E11,
F5, K5, L12, N5, N12
E12
Data Strobe: Output flag on READ data and Input flag on WRITE data. DQS is edge-aligned
with READ data, centered in WRITE data operations.
DQSLX,
DQSHX
Vref
Reference Voltage
Level REF
Input
A7, A8, A9, A10, B7, B8,
B9, B10, C7, C8, C9,
C10, D7
Address input: Provide the ROW address for ACTIVE commands and the COLUMN address
and AUTO PRE-CHARGE bit (A10) for READ/WRITE commands to select one location out of
the total array within a selected bank A10 sampled during a PRE-CHARGE command deter-
mines whether the PRE-CHARGE applies to one bank or all banks. The address inputs also
provide the OP-CODE during a MODE REGISTER SET command.
A0-A12
E8, E9
Bank Address input: define which BANK is active during a READ, WRITE, or PRE-CHARGE
command.
Input
BA0, BA1
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Pin/Ba l l lo c a t io n s /DeFinitions a n D Fu n c t io n a l De s c r iP t io n co n t in u e D
BGA Locations
D8, D9, D10
Symbol
RFU
Type
Description
Reserved Future Use: Pins reserved for future Address and Bank Select inputs
Input
A2, A3, A4, A13, A14,
A15, B1, B2, B3, B4,
B13, B14, B15, B16, C1,
C2, C3, C4, C13, C14,
C15, C16, D1, D2, D3,
D4, D13, D14, D15, D16,
E1, E16, M1, M16, N1,
N2, N3, N4, N7, N8, N9,
N10, N13, N14, N15,
N16, P1, P2, P3, P4, P7,
P8, P9, P10, P13, P14,
P15, P16, R1, R2, R3,
R4, R7, R8, R9, R10,
R13, R14, R15, R16, T2,
T3, T4, T7, T8, T9, T10,
T13, T14, T15
Data I/O
Input/Output
DQ0-DQ79
B11, B12, C5, C6, E3,
F3, G3, H3, H12, H16,
J3, J12, J16, K3, L3, M3,
P11, P12, R5, R6, T16
A11, A12, D5, D6, H4,
H15, J4, J15, T5, T6
A5, A6, A16, B5, B6,
C11, C12, D11, D12,
E14, F14, G14, H1, H2,
H5, H13, H14, J1, J2, J5,
J13, J14, K14, L14, M14,
P5, P6, R11, R12, T1,
T11, T12
Core Power
Supply
VCC
I/O Power
Supply
Supply
VCCQ
VSS
Ground (Digital)
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High Performance, Integrated Memory Module Product
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PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
FUNCTIONAL DESCRIPTION
GENERAL DESCRIPTION
The LOGIC Devices, 2.5Gb, DDR SDRAM IMOD, is one member of its
Integrated Module family. This family of Integrated memory modules
contains DDR3/DDR2 and DDR device definitions in three package foot-
prints including this 25mm2, a 16mm x 22mm package and a 25mm x
32mm footprint. This device, a high speed CMOS random-access, inte-
grated memory device based on use of (5) silicon devices each contain-
ing 536,870,912 bits. Each chip is internally configured as a quad-bank
SDRAM. Each of the chips 134, 217, 728 bit banks is organized as 8,192
rows by 1024 columns by 16bits. Each of the Silicon devices equates to
a WORD or DUAL-BYTES, each BYTE containing Data Mask and Data
Strobes.
READ and WRITE accesses to the DDR SDRAM are burst oriented; accesses
start at a selected location and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the registration of an ACTIVE
command which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to select the
bank and row to be accessed (BA0 and BA1 select the bank, A0-A12 select the
row). The address bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location for the burst access.
Prior to normal operation, the IMOD must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions and device operation.
The 2.5Gb DDR IMOD uses the double-data-rate (DDR) architecture to
achieve high-speed operation. The double-data-rate architecture is a
2n-prefetch architecture with an interface designed to transfer two data
words per clock cycle via the I/O pins. A single READ or WRITE access
for the 2.5Gb DDR IMOD effectively consists of a single 2n-bit wide, one
clock cycle transfer at the internal DRAM core and two corresponding
n-bit wide, one-half-clock cycle data transfers at the DQ (I/O) pins.
A bidirectional data strobe (DQSLx, DQSHx) is transmitted externally,
along with data, for use in data capture at the end-point receiver. DQSLx,
DQSHx are strobes transmitted by the DDR SDRAM during READ opera-
tions and by the memory controller during WRITE operations. Each
strobe, DQSLx, DQSHx control each of two bytes contained within each
of the (5) silicon chips contained in LDI’s IMOD.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner.
Operational procedures other than those specified may result in undefined
operation. Power must first be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the System VTT). VTT must be applied after VCCQ to avoid
device latch-up, which may cause permanent damage to the device. VREF
can be applied after VCCQ but is expected to be nominally coincident with VTT.
Except for CKE, inputs are not recognized as valid until after FREF is applied.
CKE during power-up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven in normal operation
(by a READ access). After all power supply and reference voltages are stable,
and the clock is stable, the IMOD requires a 200us delay prior to applying an
executable command.
The 2.5Gb DDR SDRAM operated from a differential clock (CLKx, CLKx\);
the crossing of CLKx going HIGH and CLKx\ going LOW will be referred
to as the positive edge of CLK. Commands (address and control signals)
are registered at every positive edge of CLK. Input data is registered on
both edges of DQS, and output data is referenced to both edges of DQS,
as well as to both edges of CLK.
Once the 200us delay has been satisfied, a DESELECT or NOP command
should be applied, and CKE should be brought HIGH. Following the NOP com-
mand, a PRECHARGE ALL command should be applied. Next a LOAD MODE
REGISTER command should be issued for the extended mode register (BA1
LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1 both LOW) to reset the
DLL and to program the operating parameters. Two-hundred clock cycles are
required between the DLL reset and any READ command. A PRECHARGE
ALL command should then be applied, placing the device in the all banks idle
state.
READ and WRITE accesses to the DDR memory are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident with the READ
or WRITE command are used to select the bank and the starting column
location for the burst access.
The DDR IMOD provides for programmable READ or WRITE burst
lengths of 2, 4, or 8 locations. An AUTO-PRECHARGE function may be
enabled to provide a self-timed row PRECHARGE that is initiated at the
end of the burst access.
Once in the idle state, two AUTO PRECHARGE cycles must be performed
t
( RFC must be satisfied). Additionally, a LOAD MODE REGISTER command
for the mode register with the reset DLL bit deactivated (i.e. to program operat-
ing parameters without resetting the DLL) is required. Following these require-
ments, the DDR IMOD is ready for normal operation.
The pipelined, multi-banked architecture of the DDR SDRAM architecture
allows for concurrent operations, therefore providing high effective band-
width, by hiding row PRECHARGE and activation time.
An AUTO REFRESH mode is provided, along with a power-saving power-
down mode.
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High Performance, Integrated Memory Module Product
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PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
mo D e re g is t e r
Bu r s t le n g t h
Bu r s t t y P e
READ and WRITE accesses to the DDR IMOD
are burst oriented, with the burst length being
programmable, as shown in Figure 3. The
burst length determines the maximum number
of column locations that can be accessed for a
given READ or WRITE command. Burst lengths
of 2, 4, or 8 locations are available for both the
sequential and interleaved burst types.
The MODE REGISTER is used to define the spe-
cific mode of operation of the DDR IMOD. This
definition includes the selection of a burst length,
a burst type, a CAS latency as shown in Figure
2 and the operating mode, as shown in Figure 3.
The MODE REGISTER is programmed via the
MODE REGISTER SET command (with BA0=0
and BA1=0) and will retain the stored information
until it is programmed again or the device real-
izes a loss of power (except for bit A8 which is
self clearing).
Accesses within a given burst may be pro-
grammed to be either sequential or interleaved;
this is referred to as the burst type and is selected
via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the
starting column address, as shown in Table 1.
Reserved states should not be used, as unknown
operation or incompatibility issues with future
version may result.
Reprogramming the MODE REGISTER will not
alter the contents of the memory, provided it is
performed correctly. The MODE REGISTER
must be loaded (reloaded) when all banks are idle
and no bursts are in progress, and the controller
must wait the specified time before initiating the
subsequent operation. Violating either of these
requirements will result in unspecified operation.
MODE REGISTER bits A0-A2 specify the burst
length, A3 specifies the type of burst (sequential
or interleaved), A4-A6 specify the CAS latency,
and A7-A12 specify the operating mode.
When a READ or WRITE command is issued,
a block of columns equal to the burst length is
effectively selected. All accesses for that burst
take place within this block, meaning that the
burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-Ai
when the burst length is set to two; by A2-Ai when
the burst length is set to four and by A3-Ai when
the burst length is set to eight. The remaining
(least significant) address bits are used to select
the starting location within the block. The pro-
grammed burst length applies to both the READ
and WRITE bursts.
ta B l e 1: Bu r s t DeFinition
Order of Accesses within a Burst
Burst Length Starting Column Address Type = Sequential
Type = Interleaved
Notes
1. For a burst length of two, A1-Ai selects
a two-data-element block; A0 selects the
starting column within the block.
2
A0
0
0-1
1-0
0-1
1-0
1
2. For a burst length of four, A2-Ai selects
a four-data-element block; A0-1 selects the
starting column within the block.
4
A1
0
A0
0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0
1
3. For a burst length of eight, A3-Ai selects
an eight-data-element block; A0-2 selects
the starting column within the block.
1
0
1
1
8
A2
0
A1
0
A0
0
4. Whenever a boundary of the block is
reached within a given sequence above,
the following access wraps within the block.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
READ LATENCY
Table 2 - Ca s la t e n c y
Allowable Operating Frequency (MHz)
The READ latency is the delay in clock cycles, between the registration of
a READ command and the availability of the first bit of output data. The
latency can be set to 2 or 2.5 clocks.
Speed
-10
-8
CAS Latency = 2
CAS Latency = 2.5
≤100
≤ 83
≤100
≤125
NA
If a READ command is registered at clock edge [n], and the latency is
[m] clocks, the data will be available by clock edge [n+m]. Table 2 indi-
cates the operating frequencies at which each CAS latency setting can
be used.
≤125
-75
-6
≤133
≤166
Reserved states should not be used as unknown operation or incompat-
ibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12, each set to zero, and bits A0-A6, set to the desired
values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12, each set to zero, bit A8 set to one, and bits A0-A6, set to
the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should
always be followed by a LOAD MODE REGISTER command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because
unknown operation or incompatibility from future versions may result.
EXTENDED MODE REGISTER
The EXTENDED MODE REGISTER controls functions beyond those controlled by the MODE REGISTER; these additional functions are DLL enable/disable,
output drive strength, and QFC#. These functions are controlled via the bits shown in Figure 4. The EXTENDED MODE REGISTER command to the MODE
REGISTER (with BA0=1, BA1=0) and the register will retain the stored information until it is programmed again or the device realizes loss of power. The
enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the MODE REGISTER (BA0=BA1=LOW) to reset the DLL.
The EXTENDED MODE REGISTER must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
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REGISTER DEFINITION
Fig u r e 1 - mo D e re g is t e r DeFinition
BA1 BA0 An . . . A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
1
n
n + 2 n + 1
. . .
9
8
7
6
5
4
3
2
1
0
Mode register
(Mx)
Operating mode
0
0
CAS Latency BT Burst length
M2 M1 M0 Burst Length
Mode Register Definition
Base mode register
Extended mode register
Reserved
Mn + 1
Mn + 2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
0
1
0
1
0
0
1
1
M3
0
Burst Type
Sequential
Interleaved
4
8
Reserved
1
Reserved
Reserved
Reserved
Reserved
Mn . . . M9 M8 M7 M6–M0 Operating Mode
0
0
–
0
0
–
0
0
–
0
1
–
0
0
–
Valid
Valid
–
Normal operation
Normal operation/reset DLL
All other states reserved
M6 M5 M4
CAS Latency
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
2.5
Reserved
Note: 1. n is the most significant row address bit
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REGISTER DEFINITION
Fig u r e 2 - ca s e la t e n c y
T0
T1
T2
T2n
T3
T3n
CK#
CK
Comman d
READ
NOP
NOP
NOP
CL = 2
DQS
DQ
T0
T1
T2
T2n
T3
T3n
CK#
CK
Comman d
READ
NOP
NOP
NOP
CL = 2.5
DQS
DQ
T0
T1
T2
T3
T3n
CK#
CK
Comman d
READ
NOP
NOP
NOP
CL = 3
DQS
DQ
Transitioning Data
t
Don’t Care
Note:
BL = 4 in the cases shown; shown with nominal AC, tDQSCK, andtDQSQ.
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REGISTER DEFINITION
Fig u r e 3 - ex t e n D e D mo D e re g is t e r
BA1 BA0 An . . . A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
1
n + 2 n + 1 n . . .
9
8
7
6
5
4
3
2
1
0
Extended mode
register (Ex)
Operating Mode
0
1
DSDLL
DLL
E0
0
1
Enable
Disable
Mn + 2 Mn + 1 Mode Register Definition
0
0
1
1
0
1
0
1
Base mode register
Extended mode register
Reserved
2
Drive Strength
Normal
E1
0
1
Reduced
Reserved
3
En . . . E9 E8 E7 E6 E5 E4 E3 E2 E1, E0 Operating Mode
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
Valid
–
Reserved
Reserved
Notes: 1. n is the most significant row addres.s bit.
2. The reduced drive strength option is available only on Design Revision F and K.
3. The QFC# option is not supported.
ou t P u t Dr iv e st r e n g t h
Dll en a B l e /Dis a B l e
The DLL must be enabled for normal operation. The DLL enable is required
during power-up initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debug or evaluation. When the
device exits SELF REFRESH mode, the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
The normal full drive strength for all outputs are specified to be SSTL2,
Class II. The DDR IMOD supports an option for reduced drive. This option
is intended for the support of the lighter load and/or point-to-point environ-
ments. The selection of the reduced drive strength will alter the DQs and
DQSs from SSTL2, Class II drive strength to a reduced drive strength, which
is approximately 54% of the SSTL, Class II drive strength.
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REGISTER DEFINITION
co m m a n D s
The TRUTH TABLE (below) provides a quick reference of available commands, followed by a written description of each command.
tr u t h ta B l e
Notes
Name (Function)
CSx\
RASx\
CASx\
WEx\
ADDR
H
X
X
X
X
1,9
Deselect (NOP)
L
L
L
L
L
L
L
L
H
L
H
H
L
H
H
H
L
X
Bank/Row
Bank/Column
Bank/Column
X
1,9
1,3
1,4
1,4
1,8
1,5
6,7
1,2
No Operation (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ burst)
WRITE (select bank and column and start WRITE burst)
BURST TERMINATE
H
H
H
L
L
H
H
L
L
L
Code
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (enter soft refresh mode)
LOAD MODE REGISTER
L
H
L
X
L
L
OP Code
tr u t h ta B l e - Dm oP e r a t io n
Notes
Name (Function)
DQMLx, DQMHx
DQSLx, DQSHx
L
Valid
1,10
WRITE ENABLE
H
X
1,10
WRITE INHIBIT
NOTES:
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if
CKE is LOW.
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A12 define the op-code to be written to the selected MODE
REGISTER BA0, BA1 select either the MODE REGISTER or the
EXTENDED MODE REGISTER.
7. Internal REFRESH counter controls row addressing; all inputs and I/Os
are “Don’t Care” except for CLE.
8. Applies only to READ bursts with AUTO PRECHARGE disabled. This
command is undefined (and should not be used) for READ burst with
AUTO PRECHARGE enabled.
3. A0-A12 provide row addresses, and BA0, BA1 provide bank addresses.
4. A0-A9 provide column address; A10 HIGH enables the AUTO
PRECHARGE feature (non-persistent), while A10 LOW disables the
AUTO PRECHARGE feature; BA0, BA1 provide bank address.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask WRITE data; provided coincident with the corresponding
data.
5. A10 LOW; BA0, BA1 determine the bank being PRECHARGED. A10
HIGH all banks PRECHARGED and BA0, BA1 or “Don’t Care”.
De s e l e c t
The DESELECT function (CSx\=HIGH) prevents new commands from being executed by the DDR IMOD. The IMOD is effectively deselected. Operations
already in progress are not affected.
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REGISTER DEFINITION
Ac t iv e
no oP e r a t io n (noP)
The ACTIVE command is used to open (or activate) a row in a particular
bank for a subsequent access. The value on the BA0, BA1 inputs selects
the bank and the address provided on inputs A0-A12, selects the row. This
row remains active (or opens) for accesses until a PRECHARGE command
is issued to that bank. A PRECHARGE command must be issued before
opening a different row in the same bank.
The NO OPERATION command is used to perform a NOP to the selected
DDR Silicon within the IMOD (CSx\=LOW). This prevents unwanted com-
mands from being registered during idle or wait states. Operations already
in progress are not affected.
Lo a D mo D e re g is t e r
The MODE REGISTER is loaded via inputs A0-A12. The LOAD MODE REG-
ISTER command can only be issued when all banks idle and a subsequent
t
executable command cannot be issued until MRD is met.
ac t iv a t in g a sP e c iF ic ro w in a sP e c iF ic Ba n k
CK#
CK
CKE HIGH
CS#
RAS#
CA S#
WE#
Address
Row
Bank
BA0, BA1
Don’t Care
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re a D
The READ command is used to initiate a burst READ access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided
on inputs A0-A9 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE
is selected, the row being accessed will be PRECHARGED at the end of the READ burst; If AUTO PRECHARGE is not selected, the row will remain open for
subsequent accesses.
reaD co m m a n D
CK#
CK
CKE
CS#
HIGH
RAS#
CAS#
WE#
Col
Address
EN AP
DISAP
A10
BA0, BA1
Bank
Don’t Care
Note:
EN AP = enable auto precharge
DIS AP = disable auto precharge.
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wr it e
The WRITE command is used to initiate a burst WRITE access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided
on inputs A0-A9 selects the starting column location. The value on the input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRE-
CHARGE is selected, the row being accessed will be AUTO PRECHARGED at the end of the WRITE burst; If AUTO PRECHARGE is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQ lines is written to the memory array subject to DQMLx, DQMHx for each WORD. If a
given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will
be ignored, and a WRITE will not be executed to that byte column location.
write co m m a n D
CK#
CK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address
A10
Col
EN AP
DIS AP
Bank
BA0, BA1
Don’t Care
Note:
EN AP = enable auto precharge
DIS AP = disable auto precharge..
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Pr e c h a r g e
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank or banks will be available for a
t
subsequent row access a specified time ( RP) after the PRECHARGE command is issued. Except in the case of concurrent auto PRECHARGE, where a
READ or WRITE command to a different bank is allowed as long as it does not violate any other timing parameters. Input A10 determines whether one or all
banks are to be PRECHARGED and in the case where only one bank is to be PRECHARGED, inputs BA0, BA1 select the bank. In all other cases BA0, BA1
are treated as “Don’t Care”. Once a bank has been PRECHARGED, it is in the idle state and must be activated prior to any READ or WRITE commands being
issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the
process of PRECHARGING.
Precharge co m m a n D
CK#
CK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address
All banks
A10
One bank
BA0, BA1
Bank1
Don’t Care
Note:
1. If A10 is HIGH, bank address becomes “Don’t Care.”
au t o Pr e c h a r g e
AUTO PRECHARGE is a feature which performs the same individual bank PRECHARGE function described prior, but without requiring an explicit command.
This is accomplished by using A10 to enable the command/function in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/
row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE is
non-persistent in that it is either enabled or disabled for each individual READ or WRITE command. The device supports concurrent AUTO PRECHARGE if
the command to the other bank does not interrupt the data transfer to the current bank.
AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. This earliest valid stage is determined as if an explicit
t
PRECHARGE command was issued at the earliest possible time without violating RAS (MIN).
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AB s o l u t e ma x im u m ra t in g s
Bu r s t te r m in a t e
Parameter
MIN
MAX UNITS
+3.6V
V
VCC Supply Voltage relative to VSS
The BURST TERMINATE command is used to truncate READ bursts.
The most recently registered READ command prior to the BURST TER-
MINATE command will be truncated. The open page which the READ
burst was terminated from, remains open.
-1.0V
+3.6V
V
VCCQ I/O Supply Voltage relative to VSS
VREF and inputs Voltage relative to VSS
I/O pins Voltage relative to VSS
Storage Temperature
-1.0V
-1.0V
-0.5V
-55
+3.6V
V
VCCQ + 0.5V
+150
V
Au t o re F r e s h
C
50
mA
Short circuit current
−−
AUTO REFRESH is used during normal operations of the IMOD and is
analogous to CASx\-BEFORE-RASx\ (CBR) REFRESH in conventional
DRAMs. This command is non-persistent so it must be issued each time
a REFRESH is required.
Ca P a c it a n c e
The addressing is generated by the internal REFRESH controller. This
makes the address bits “Don’t Care” during an AUTO REFRESH com-
mand. Each DDR die within the IMOD, requires AUTO REFRESH cycles
at an average of 7.8125 us (maximum).
Parameter
SYMBOL
MAX UNITS
pF
5
Input Capacitance [CKx\CKx\]
C
l1
pF
30
Addresses, BA0-1
C
A
To allow for improved efficiency in scheduling and switching between
tasks, some flexibility in the absolute REFRESH interval is provided. A
maximum of eight AUTO REFRESH commands can be posted to any
given DDR die, meaning that the maximum absolute interval between any
AUTO REFRESH command is 9 x 7.8125uS (70.3uS). This maximum
absolute interval is to allow future support for DLL updates internal to the
DDR SDRAM die.
pF
Input Capacitance [All other Input Pins]
DQ line
C
7
12
pF
8
C
10
Although not a JEDEC requirement, to provide for future functionality
enhancements, CKEx must be active (HIGH) during the AUTO REFRESH
period. The AUTO REFRESH period begins when the AUTO REFRESH
t
command is registered and ends RFC later.
Se l F re F r e s h
The SELF REFRESH command can be used to retain data in the DDR
IMOD even if the rest of the system is powered down. When in the SELF
REFRESH mode, the DDR IMOD retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH com-
mand except CKEx is disabled (LOW). The DLL is automatically enabled
upon entering SELF REFRESH (200 clock cycles must then occur before
a READ command can be issued). Input signals except CLEx are “Don’t
Care” during SELF REFRESH.
The procedure for exiting SELF REFRESH requires a sequence of com-
mands. First, CLKx must be stable prior to CKEx going back to HIGH.
Once CLEx is HIGH, the DDR die must have a NOP command issued
t
for XSNR, because time is required for the completion of any internal
REFRESH in progress.
A simple algorithm for meeting both REFRESH and DLL requirements is
to apply NOPs for 200 clock cycles before applying any other command.
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Dc el e c t r ic a l ch a r a c t e r is t ic s a n D oP e r a t in g co n D it io n s (no t e s 1, 6)
VCC, VCCQ=+2.5V±0.2V;-55°C≤TA≤+125°C
Parameter
Symbol
MIN
TYP
MAX
UNITS
VCC
2.3
2.5
2.7
Supply Voltage
V
V
V
V
VCCQ
VREF
VTT
VIH
VIL
2.3
2.5
0.50 x VCCQ
VREF
2.7
I/O Supply Voltage
0.49 x VCCQ
VREF - 0.04
0.51 x VCCQ
VREF + 0.04
I/O Reference Voltage
I/O Termination Voltage
Input High Voltage
Input Low Voltage
II
-2
-5
+2
+5
Input Leakage Current:
Any input 0V≤VIN≤VCC, VREF pin 0V≤VIN≤1.35V
All other pins not under test = 0V
Output Leakage Current:
DQ lines disabled; 0V≤VOUT≤VCCQ
Full Drive Output Option
uA
uA
IOZ
IOH
IOL
IOH
IOL
-16.8
+16.8
-9
−−
−−
−−
−−
mA
mA
mA
mA
Reduced Drive Output Option
Ambient Operating Temperature
+9
TA
TA
TA
-40
-40
-55
25
25
25
85
Industrial = “I”
Extended = “E”
Mil-Temp = “M”
°C
°C
°C
105
125
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icc oP e r a t in g sP e c iF ic a t io n l i m i t s a n D co n D it io n s (no t e s 1-5, 10, 12, 14)
VCC, VCCQ=+2.5V±0.2V;-55°C≤TA≤+125°C
333 Mbps 266/250 Mbps
200 Mbps
@CL=2
520
Parameter
Symbol
ICC0
@CL=2.5
@CL=2
600
Units
mA
640
OPERATING current: One bank active - precharge
t
t
t
t
t
t
CL= CK(MIN), RC= RC(MIN), RAS= RAS MIN(ICC); DQ, DQM, DQS inputs
changing once per clock cycle; Address and Control inputs changing once
every two clock cycles
650
25
ICC1
ICC2P
ICC2F
790
25
710
25
mA
mA
mA
OPERATING current: One bank active - READ - precharge current
t
t
t
t
Active-Read-Precharge; Burst=2; RC= RC(MIN); CK= CK(MIN); IOUT=0mA;
Address and control inputs changing once per clock cycle (notes: 22, 48)
Precharge POWER-DOWN current
t
t
All banks idle; POWER-DOWN mode; CK= CK(MIN), CKE=LOW (notes: 23,
32, 50)
195
225
225
IDLE STANDBY current
t
t
CS\=HIGH; All banks idle; POWER-DOWN mode; CK= CK(MIN);
CKE=HIGH; Address and other Control inputs changing once per clock cycle;
VSS=VREF for DQ, DQS and DM (note: 51)
150
200
ICC3P
175
175
mA
mA
ACTIVE POWER-DOWN, STANDBY current
t
t
One bank active; POWER-DOWN mode; CK= CK(MIN), CKE=LOW (notes:
23, 32, 50)
ICC3N
225
225
ACTIVE STANDBY current
t
t
CS\=HIGH; CKE=HIGH; One bank Active Precharge; RC= RAS(MAX);
t
t
CK= CK(MIN); DQ, DQM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per cycle (note: 22)
OPERATING current Burst=2 READS
245
ICC4R
ICC4W
350
300
mA
mA
Continuous Burst; One bank active; Address and Control inputs changing
t
t
once per clock cycle; CK= CK(MIN); IOUT=0mA cycle (notes: 22, 48)
OPERATING current Burst=2 WRITES
775
1250
1025
Continuous Burst; One bank active; Address and Control inputs changing
t
t
once per clock cycle; CK= CK(MIN); DQ, DQM and DQS inputs changing
twice per clock cycle (note: 22)
t
t
1400
50
REF= RC (MIN) (notes: 27, 50)
mA
mA
mA
mA
ICC5
ICC5A
ICC6
1450
50
1450
50
AUTO REFRESH current
t
t
REF=7.8125us (notes: 27, 50) = RC (MIN)
25
25
25
SELF REFRESH current; CKE=≤0.2V
1700
ICC7
2000
1925
OPERATING current
t
t
Four bank interleaving READS (BL=4) with AUTO PRECHARGE; RC= RC
t
t
(MIN); CK= CK (MIN); Address and Control inputs change only during
ACTIVE READ or WRITE commands (notes: 22, 49)
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ac el e c t r ic a l sP e c iF ic a t io n s a n D re c o m m e n D oP e r a t in g ch a r a c t e r is t ic s (no t e s 1-5, 14-17, 33)
-6, 333 Mbps
-75, 266 [250]Mbps
-8, 250 [200]Mbps
-10, 200 [167] Mbps
167 MHz,
133 MHz
125 MHz
100 MHz
CLKx CL = 2.5
CLKx CL = 2.5 [2]
CLKx CL = 2.5 [2]
CLKx CL = 2.5 [2]
Parameter
Symbol MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
ns
CLK
CLK
ns
AC
-0.8
0.45
0.45
8
-0.8
0.45
0.45
10
0.8
0.55
0.55
13
-0.7
0.45
0.45
6
0.7
0.55
0.55
13
-0.75
0.45
0.45
7.5
0.75
0.55
0.55
13
0.8
0.55
0.55
13
Access window of DQs from CLKx / CLKx\
CLKx High level Width
t
t
t
CH
t
CL
CK
CK
CLKx Low level Width
t
t
t
CL=2.5
Clock Cycle Time
ns
CL=2
10
15
7.5
13
10
13
13
13
ns
DH
0.6
0.6
2
0.6
0.6
0.45
0.45
1.75
-0.6
0.35
0.35
0.5
DQ and DM Input Hold Time relative to DQS
DQ and DM Input Setup Time relative to DQS
DQ and DM Input Pulse Width
t
ns
DS
0.5
t
ns
DIPW
2
1.75
-0.75
0.35
0.35
t
ns
DQSCK
-0.8
0.35
0.35
-0.8
0.35
0.35
0.8
0.6
0.75
0.8
Access window of DQs from CLKx / CLKx\
DQS Input HIGH Pulse Width
t
t
t
CLK
CLK
ns
DQSH
t
DQSL
DQS Input LOW Pulse Width
t
DQSQ
0.6
0.45
1.25
0.5
0.6
DQS-DQ Skew, DQS to last DQ valid, per grp.
t
t
t
t
CLK
CLK
CLK
ns
DQSS
0.75
0.2
0.75
0.2
1.25
0.75
0.2
0.75
0.2
1.25
1.25
WRITE command to first DQS latching transition
DQS falling edge to CLKx rising - setup time
DQS falling edge to CLKx rising - hold time
Half Clock period
t
DSS
t
DSH
0.2
0.2
0.2
0.2
t
t
t
t
t
t
t
t
t
HP
CH, CL
CH, CL
CH, CL
CH, CL
t
ns
HZ
0.8
0.7
0.75
0.8
Data-Out HIGH impedance window from CLKx / CLKx\
Data-Out LOW impedance window from CLKx / CLKx\
Address and Control Input hold time
Address and Control Input setup time
Address and Control Input hold time
Address and Control Input setup time
Load Mode Register
t
ns
LZ
-0.8
1.1
1.1
1.1
1.1
-0.8
1.1
1.1
1.1
1.1
-0.70
0.75
0.75
0.8
-0.75
0.9
0.9
1
t
ns
IHF
t
ns
ISF
t
HIS
t
ISS
0.8
1
t
ns
ns
MRD
16
t
16
t
12
t
15
t
t
t
t
t
t
HP- QHS
HP- QHS
HP- QHS
HP- QHS
QH
DQ-DQS hold. DQS to first DQ to go non-valid
Data Hold skew factor
t
ms
ms
ms
ns
QHS
1
0.55
0.75
1
t
RAS
RAP
40
20
70
80
20
20
40
120000
42
15
70000
40
120000
120000
ACTIVE to PRECHARGE command
ACTIVE to READ with AUTO PRECHARGE command
ACTIVE to ACTIVE/AUTO REFRESH command per.
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
t
20
70
20
65
t
RC
60
t
t
ns
RFC
80
72
75
ns
RCD
20
15
20
t
ns
RP
20
15
20
t
t
t
CLK
CLK
ns
RPRC
0.9
0.4
15
0.9
0.4
15
1.1
0.6
0.9
0.4
12
1.1
0.6
0.9
0.4
15
1.1
0.6
1.1
0.6
DQS READ Preamble
t
RPST
DQS READ Postamble
t
RRD
ACTIVE bank to ACTIVE bank b command
DQS WRITE Preamble
t
t
CLK
ns
WPRC
0.25
0
0.25
0
0.25
0
0.25
0
t
WPRCS
DQS READ Preamble Setup Time
LOGIC Devices Incorporated
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High Performance, Integrated Memory Module Product
20
Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
ac el e c t r ic a l sP e c iF ic a t io n s a n D re c o m m e n D oP e r a t in g ch a r a c t e r is t ic s (no t e s 1-5, 14-17, 33)
-6, 333 Mbps
-75, 266 [250]Mbps
-8, 250 [200]Mbps
-10, 200 [167] Mbps
167 MHz,
133 MHz
125 MHz
100 MHz
CLKx CL = 2.5
CLKx CL = 2.5 [2]
CLKx CL = 2.5 [2]
CLKx CL = 2.5 [2]
Parameter
Symbol MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
0.4
0.4
0.4
0.6
0.4
0.6
DQS WRITE Postamble
CLK
ns
WPST
t
12
15
15
15
WRITE Recovery Time
WR
t
t
1
t
1
t
1
t
1
t
Internal WRITE to READ command delay
Data Valid Output Window
CLK
us
WTR
t
t
t
t
na
QH- DQSQ
QH- DQSQ
QH- DQSQ
QH- DQSQ
t
70.3
53
70.3
53
REFRESH to REFRESH command Interval (Industrial)
REFRESH to REFRESH command Interval (Extended)
REFRESH to REFRESH command Interval (Mil-Temp)
Average Periodic REFRESH Interval (Industrial)
Average Periodic REFRESH Interval (Extended)
Average Periodic REFRESH Interval (Mil-Temp)
Terminating delay reference to VDD
us
REFC
REFC
REFC
70.3
35
70.3
53
t
us
t
35
35
us
7.8
3.9
5.9
3.9
35
t
t
t
7.8
5.9
3.9
7.8
5.9
3.9
us
REFI
REFI
REFI
7.8
5.9
3.9
us
us
t
0
0
0
0
ns
VTD
t
75
75
80
80
Exit Self REFRESH to non-READ Command
Exit Self REFRESH to READ Command
ns
XSNR
XSRD
t
t
200
200
200
200
CLK
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
ac sP e c iF ic a t io n no t e s
V/ns, functionality is uncertain.
1.All voltages referenced to VSS
16. The CK/CK# input reference level (for timing referenced to CK/CK#) is
the point at which CK and CK# cross; the input reference level for signals
other than CK/CK# is VREF.
2.Tests for AC timing, IDD, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related speci-
fications and the device operation are guaranteed for the full voltage range
specified.
17. Inputs are not recognized as valid until VREF stabilizes. Once initialized,
including self refresh mode, VREF must be powered within specified range.
Exception: during the period before VREF stabilizes, CKE < 0.3 × VDD is
recognized as LOW.
3. Outputs (except for IDD measurements) measured with equivalent load:
50Ω
Reference
Output
(VOUT)
point
18. The output timing reference level, as measured at the timing reference
point (indicated in Note 3), is VTT.
30pF
t
t
19. HZ and LZ transitions occur in the same access time windows as data
valid transitions. These parameters are not referenced to a specific voltage
level, but specify when the device output is no longer driving (High-Z) or
begins driving (Low-Z).
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing
point for CK/CK#), and parameter specifications are guaranteed for the spec-
ified AC input levels under normal use conditions. The minimum slew rate
for the input signals used to test the device is 1 V/ns in the range between
VIL(AC) and VIH(AC).
20. The intent of the “Don’t Care” state after completion of the postamble
is the DQS-driven signal should either be HIGH, LOW, or High-Z, and that
any signal transition within the input switching region must follow valid input
requirements. That is, if DQS transitions HIGH (above VIH[DC] MIN) then it
5. The AC and DC input level specifications are as defined in the SSTL_2
standard (that is, the receiver will effectively switch as a result of the signal
crossing the AC input level and will remain in that state as long as the signal
does not ring back above [below] the DC input LOW [HIGH] level).
t
must not transition LOW (below VIH[DC] prior to DQSH [MIN]).
21. This is not a device limit. The device will operate with a negative value,
but system performance could be degraded due to bus turnaround.
6. All speeds may not be offered on all device grades. Refer to “Ordering
Information” for availability.
22. It is recommended that DQS be valid (HIGH or LOW) on or before the
WRITE command. The case shown (DQS going from High-Z to logic LOW)
applies when no WRITEs were previously in progress on the bus. If a previ-
ous WRITE was in progress, DQS could be HIGH during this time, depending
7. VREF is expected to equal VDDQ/2 of the transmitting device and to track
variations in the DC level of the same. Peak-to-peak noise (noncommon
mode) on VREF may not exceed ±2% of the DC value. Thus, from VDDQ/2,
VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise.
This measurement is to be taken at the nearest VREF bypass capacitor.
t
on DQSS.
t
t
t
23. MIN ( RC or RFC) for IDD measurements is the smallest multiple of CK
t
that meets the minimum absolute value for the respective parameter. RAS
(MAX) for IDD measurements is the largest multiple of CK that meets the
maximum absolute value for RAS.
t
t
8. VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, it is expected to be set equal to VREF, and it must track
variations in the DC level of VREF.
24. The refresh period is 64ms. This equates to an average refresh rate
of 7.8125μs (15.625μs for 128Mb DDR). However, an AUTO REFRESH
command must be asserted at least once every 70.3μs (140.6μs for 128Mb
DDR); burst refreshing or posting by the DRAM controller greater than 8
REFRESH cycles is not allowed.
9. VID is the magnitude of the difference between the input level on CK and
the input level on CK#.
10. The value of VIX and VMP is expected to equal VDDQ/2 of the transmitting
device and must track variations in the DC level of the same.
25. The I/O capacitance per DQS and DQ byte/group will not differ by more
than this maximum amount for any given device.
11. IDD is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle times.
t
26. The data valid window is derived by achieving other specifications: HP
t
t
t
t
t
t
( CK/2), DQSQ, and QH ( QH = HP - QHS). The data valid window derates
in direct proportion to the clock duty cycle and a practical data valid window
can be derived. The clock is allowed a maximum duty cycle variation of 45/55,
because functionality is uncertain when operating beyond a 45/55 ratio. 27.
Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with
DQ0–DQ7; x16 = LDQS with DQ0–DQ7 and UDQS with DQ8–DQ15.
12. Enables on-chip refresh and address counters.
13. IDD specifications are tested after the device is properly initialized and is
averaged at the defined cycle rate.
14. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V,
VREF = VSS, f = 100MHz, TA= 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-
peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they
are matched in loading.
28. This limit is actually a nominal value and does not result in a fail value.
CKE is HIGH during the REFRESH command period ( RFC [MIN]), else CKE
is LOW (that is, during standby).
t
15. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If
t
the slew rate is less than 0.5 V/ns, timing must be derated: IS has an addi-
tional 50ps per each 100 mV/ns reduction in slew rate from the 500 mV/ns.
t
IH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5
LOGIC Devices Incorporated
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
ac sP e c iF ic a t io n no t e s
29. To maintain a valid level, the transitioning edge of the input must:
Fig u r e 4 - Fu l l Dr iv e Pu l l -Do w n ch a r a c t e r is t ic s
a. Sustain a constant slew rate from the current AC level
through to the target AC level, VIL(AC) or VIH(AC).
160
140
120
100
80
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at
least the target DC level, VIL(DC) or VIH(DC).
30. The input capacitance per pin group will not differ by more than this maxi-
mum amount for any given device.
60
40
31. CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured
differentially).
20
0
32. DQ and DM input slew rates must not deviate from DQS by more than
0.0
0.5
1.0
1.5
2.0
2.5
10%. If the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be der-
ated: 50ps must be added to DS and DH for each 100 mV/ns reduction in
VOUT (V)
t
t
slew rate.
33. VDD must not vary more than 4% if CKE is not active while any bank is
active.
Fig u r e 5 - Fu l l Dr iv e Pu l l -uP ch a r a c t e r is t ic s
0
-20
34. The clock is allowed up to ±150ps of jitter. Each timing parameter is
allowed to vary by the same amount.
-40
t
t
t
-60
35. HP (MIN) is the lesser of CL (MIN) and CH (MIN) actually applied to the
device CK and CK# inputs, collectively, during bank active.
-80
-100
-120
-140
-160
-180
-200
36. READs and WRITEs with auto precharge are not allowed to be issued
until RAS (MIN) can be satisfied prior to the internal PRECHARGE com-
mand being issued.
t
37. Any positive glitch must be less than 1/3 of the clock cycle and not more
than +400mV or 2.9V, whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either –300mV or 2.2V, whichever
is more positive. The average cannot be below the +2.5V minimum.
0.0
0.5
1.0
V
1.5
DDQ - VOUT (V)
2.0
2.5
38. Normal output drive curves:
a. The full driver pull-down current variation from MIN to MAX
process; temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 4.
39. Reduced output drive curves:
a. The full driver pull-down current variation from MIN to MAX
process; temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 6.
b. The driver pull-down current variation, within nominal voltage
and temperature limits, is expected, but not guaranteed,
to lie within the inner bounding lines of the V-I curve of
Figure 4.
b. The driver pull-down current variation, within nominal voltage
and temperature limits, is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I curve of Figure 6.
c. The full driver pull-up current variation from MIN to MAX
process; temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 5.
c. The full driver pull-up current variation from MIN to MAX
process; temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 7.
d. The driver pull-up current variation within nominal limits of
voltage and temperature is expected, but not guaranteed, to
lie within the inner bounding lines of the V-I curve of Figure 5.
d. The driver pull-up current variation, within nominal voltage and
temperature limits, is expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of Figure 7.
e. The full ratio variation of MAX to MIN pull-up and pull-down
current should be between 0.71 and 1.4 for drain-to-source
voltages from 0.1V to 1.0V at the same voltage and temperature.
e. The full ratio variation of the MAX-to-MIN pull-up and pull-
down current should be between 0.71 and 1.4 for device
drain-to-source voltages from 0.1V to 1.0V at the same voltage
and temperature.
f. The full ratio variation of the nominal pull-up to pull-down
current should be unity ±10% for device drain-to-source
LOGIC Devices Incorporated
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
ac sP e c iF ic a t io n no t e s
f. The full ratio variation of the nominal pull-up to pull-down
current should be unity ±10%, for device drain-to-source
voltages from 0.1V to 1.0V.
45. During initialization, VDDQ, VTT, and VREF must be equal to or less than
VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power-up,
even if VDD/VDDQ are 0V, provided a minimum of 42Ω of series resistance is
used between the VTT supply and the input pin.
Fig u r e 6 - re D u c e D Dr iv e Pu l l -Do w n ch a r a c t e r is t ic s
80
70
60
50
40
30
20
10
0
46. The current LDI part operates below 83 MHz (slowest specified JEDEC
operating frequency). As such, future die may not reflect this option.
47. When an input signal is HIGH or LOW, it is defined as a steady state logic
HIGH or LOW.
48. Random address is changing; 50% of data is changing at every transfer.
49. Random address is changing; 100% of data is changing at every trans-
fer.
50. CKE must be active (HIGH) during the entire time a REFRESH com-
mand is executed. That is, from the time the AUTO REFRESH command
2.0
2.5
0.0
0.5
1.0
1.5
t
is registered, CKE must be active at each rising clock edge, until RFC has
V
OUT (V)
been satisfied.
51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid HIGH or
LOW logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address
and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are
similar, IDD2F is “worst case.”
Fig u r e 7 - re D u c e D Dr iv e Pu l l -uP ch a r a c t e r is t ic s
0
-10
-20
-30
-40
-50
-60
-70
-80
52. Whenever the operating frequency is altered, not including jitter, the DLL
is required to be reset followed by 200 clock cycles before any READ com-
mand.
53. This is the DC voltage supplied at the DRAM and is inclusive of all noise
up to 20 MHz. Any noise above 20 MHz at the DRAM generated from any
source other than that of the DRAM itself may not exceed the DC voltage
range of 2.6V ±100mV.
t
54. The -6 speed grades will operate with RAS (MIN) = 40ns and
t
RAS (MAX) = 120,000ns at any slower frequency.
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
40. The voltage levels used are derived from a minimum VDD level and the
referenced test load. In practice, the voltage levels obtained from a properly
terminated bus will provide significantly different voltage values.
41. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width ≤ 3ns, and
the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot:
VIL (MIN) = –1.5V for a pulse width ≤ 3ns, and the pulse width can not be
greater than 1/3 of the cycle rate.
42. VDD and VDDQ must track each other.
t
t
t
t
43. HZ (MAX) will prevail over DQSCK (MAX) + RPST (MAX) condition. LZ
t
t
(MIN) will prevail over DQSCK (MIN) + RPRE (MAX) condition.
t
t
44. RPST end point and RPRE begin point are not referenced to a specific
t
voltage level but specify when the device output is no longer driving ( RPST)
or begins driving ( RPRE).
t
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
AC Switching diagrams reference 16 bits, LDI’s IMOD contains (5) 16 bit devices totaling 80 bits
Fig u r e 8 - re a D Bu r s t
T0
T1
NOP
T2
T2n
T3
T3n
T4
T5
CK#
CK
READ
NOP
NOP
NOP
NOP
Command
Address
Bank a,
Col n
CL = 2
DQS
DQ
DO
n
T0
T1
T2
T2n
T3
T3n
T4
T5
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
Command
Address
Bank a,
Col n
CL = 2.5
DQS
DQ
DO
n
T0
T1
T2
T3
T3n
T4
T4n
T5
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
Command
Address
Bank a,
Col n
CL = 3
DQS
DQ
DO
n
Transitioning Data
Don’t Care
Notes: 1. DO n = data-out from column n.
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Shown with nominal tAC, tDQSCK, andtDQSQ.
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 9 - co n s e c u t iv e re a D Bu r s t
T0
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
Command
Address
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col n
Bank,
Col b
CL = 2
DQS
DQ
DO
n
DO
b
T0
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
Command
Address
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col n
Bank,
Col b
CL = 2.5
DQS
DQ
DO
n
DO
b
T0
T1
T2
T3
T3n
T4
T4n
T5
T5n
CK#
CK
Command
Address
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col n
Bank,
Col b
CL = 3
DQS
DQ
DO
n
DO
b
Transitioning Data
Don’t Care
Notes: 1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order follow-
ing DO b.
5. Shown with nominal tAC, tDQSCK, andtDQSQ.
6. Example applies only when READ commands are issued to same device.
LOGIC Devices Incorporated
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 10 - no n c o n s e c u t iv e re a D Bu r s t
T0
T1
NOP
T2
T2n
T3
T3n
T4
T5
T5n
T6
CK#
CK
Comman d
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col n
Bank,
Col b
Address
CL = 2
DQS
DQ
DO
n
DO
b
T0
T1
T2
T2n
T3
T3n
T4
T5
T5n
T6
CK#
CK
Comman d
READ
NOP
NOP
READ
NOP
NOP
NOP
Bank,
Col n
Bank,
Col b
Address
CL = 2.5
DQS
DQ
DO
n
DO
b
T4n
T0
T1
T2
T3
T3n
T4
T5
T6
CK#
CK
Comman d
READ
NOP
NOP
READ
NOP
NOP
NOP
Bank,
Col n
Bank,
Col b
Address
CL = 3
DQS
DQ
DO
n
DO
b
Transitioning Data
Don ’t Care
Notes: 1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order follow-
ing DO b.
5. Shown with nominal tAC, tDQSCK, andtDQSQ.
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 11 - ra n D o m re a D ac c e s s e s
T0
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
Comman d
Address
READ
READ
READ
READ
NOP
NOP
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
CL = 2
DQS
DQ
DO
n
DO
n'
DO
x
DO
x'
DO
b
DO
b'
DO
g
T0
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
Command
Address
READ
READ
READ
READ
NOP
NOP
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
CL = 2.5
DQS
DQ
DO
n
DO
n'
DO
x
DO
x'
DO
b
DO
b'
T0
T1
T2
T3
T3n
T4
T4n
T5
T5n
CK#
CK
Command
Address
READ
READ
READ
READ
NOP
NOP
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
CL = 3
DQS
DQ
DO
n
DO
n'
DO
x
DO
x'
DO
b
DO
b'
Transitioning Data
Don’t Care
Notes: 1. DO n (or x or b or g) = data-out from column n (or column x (or column b or column g).
2. BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL= 8, the following burst interrupts the previous).
3. n', x', b', or g' indicate the next data-out following DO n, DO x, DO b, or DOg, respectively.
4. READs are to an active row in any bank .
5. Shown with nominal tAC, tDQSCK, andtDQSQ.
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 12 - te r m in a t in g a re a D Bu r s t
T0
T1
T2
T2n
T3
T4
T5
CK#
CK
1
Command
READ
BST
NOP
NOP
NOP
NOP
a
Bank
Col
n
,
Address
CL = 2
DQS
DQ
DO
n
T0
T1
T2
T2n
T3
T4
T5
CK#
CK
1
BST
READ
NOP
NOP
NOP
NOP
Command
Address
Bank a,
Col n
CL = 2.5
DQS
DQ
DO
n
T0
T1
T2
T3
T3n
T4
T5
CK#
CK
1
BST
Command
Address
READ
NOP
NOP
NOP
NOP
Bank a,
Col n
CL = 3
DQS
DQ
DO
n
Transitioning Data
Don’t Care
Notes: 1. Page remains open.
2. DO n = data-out from column n.
3. BL = 4.
4. Subseqent element of data-out appears in the programmed order following DO n.
5. Shown with nominal tAC, tDQSCK, andtDQSQ.
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 13 - re a D t o wr it e
T0
T1
T2
T2n
T3
T4
T4n
T5
T5n
CK#
CK
1
Command
Address
READ
NOP
WRITE
NOP
NOP
BST
Bank,
Col n
Bank,
Col b
t
DQSS
(NOM)
CL = 2
DQS
DO
n
DI
b
DQ
DM
T0
T1
T2
T2n
T3
T3n
T4
T5
T5n
CK#
CK
1
Command
Address
READ
NOP
NOP
WRITE
NOP
BST
Bank,
Col n
Bank,
Col b
t
DQSS
(NOM)
CL = 2.5
DQS
DO
n
DI
b
DQ
DM
T0
T1
T2
T3
T3n
T4
T5
T5n
CK#
CK
1
READ
BST
NOP
NOP
WRITE
NOP
Command
Address
Bank a,
Col n
t
DQSS
(NOM)
CL = 3
DQS
DO
n
DI
b
DQ
DM
Transitioning Data
Don’t Care
Notes: 1. Page remains open.
2. DO n = data-out from column n; DI b = data-in from column b .
3. BL = 4 (applies for bursts of 8 as well; if BL = 2, the BURST command shown can be NOP).
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal tAC, tDQSCK, andtDQSQ.
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 14 - re a D t o Pr e c h a r g e
T0
T1
T2
T2n
T3
T3n
T4
T5
CK#
CK
Command
Address
READ
NOP
PRE
NOP
NOP
ACT
Bank a,
Col n
Bank a,
(a or all)
Bank a,
Row
t
CL = 2
RP
DQS
DQ
DO
n
T0
T1
T2
T2n
T3
T3n
T4
T5
CK#
CK
Command
Address
READ
NOP
PRE
NOP
NOP
ACT
Bank a,
Col n
Bank a,
(a or all)
Bank a,
Row
t
RP
CL = 2.5
DQS
DQ
DO
n
T0
T1
T2
T3
T3n
T4
T4n
T5
CK#
CK
Command
Address
READ
NOP
PRE
NOP
NOP
ACT
Bank a,
Col n
Bank a,
(a or all)
Bank a,
Row
t
RP
CL = 3
DQS
DQ
DO
n
Transitioning Data
Don’t Care
Notes: 1. Provided tRAS (MIN) is met, a READ command with auto precharge enabled would cause a
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DOn.
5. Shown with nominal tAC, tDQSCK, andtDQSQ.
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
assumed that tRAS (MIN) is met.
7. An ACTIVE command to the same bank is only allowed if tRC (MIN) is met.
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 15 - Ba n k re a D wit h o u t Pr e c h a r g e
T1
T0
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
CK#
CK
t
t
t
t
t
CL
IS IH
CK
CH
CKE
t
t
IS IH
1
1
2
1
3
1
1
NOP
Command
NOP
ACT
NOP
READ
NOP
PRE
NOP
ACT
Row
t
t
IS IH
Col n
Row
Address
A10
t
t
IS IH
All banks
One bank
4
Row
Row
t
t
IS IH
5
BA0, BA1
Bank x
Bank x
Bank x
Bank x
t
t
t
CL = 2
RCD
3
t
RP
RAS
RC
DM
t
t
Case 1: AC
(
MIN) and DQSCK
(
MIN)
t
t
tRPRE
DQSCK(MIN)
RPST
DQS
t
LZ(MIN)
DO
n
DQ
t
t
AC
LZ
(MIN)
(MIN)
t
t
MAX) and DQSCK(MAX)
Case 2: AC
(
t
t
t
RPST
RPRE DQSCK (MAX)
DQS
DO
n
DQ
t
t
AC (MAX)
HZ (MAX)
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. The PRECHARGE command can only be applied at T5 if tRAS (MIN) is met.
4. Disable auto precharge.
5. “Don’t Care” if A10 is HIGH at T5.
6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in
the programmed order.
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
t
t
Fig u r e 16 - Da t a ou t P u t timing – DQsQ, Qh, a n D Da t a va l iD win D o w
T1
T2
T2n
T3
T3n
T4
CK#
CK
1
1
1
1
1
1
HP
t
t
t
t
t
t
HP
HP
HP
HP
HP
2
2
t
t
DQSQ
2
2
t
t
DQSQ
DQSQ
DQSQ
3
LDQS
4
DQ (last data valid)
4
4
4
4
4
DQ
DQ
DQ
DQ
DQ
4
DQ
4
DQ (first data no longer valid)
5
5
5
5
QH
t
t
t
t
QH
QH
QH
4
4
DQ (last data valid)
T2
T2
T2n
T2n
T3
T3n
DQ (first data no longer vali d)
T3
T3
T3n
T3n
6
DQ0–DQ7 and LDQS Collectively
T2
T2n
Data valid
window
Data valid
window
Data valid
window
Data valid
window
2
2
2
DQSQ
t
t
t
2
t
DQSQ
DQSQ
DQSQ
3
7
UDQS
DQ (last data valid)
7
7
7
7
7
DQ
DQ
DQ
DQ
DQ
7
7
DQ
DQ (first data no longer vali d)
5
5
5
5
QH
t
t
t
t
QH
QH
QH
7
7
6
DQ (last data valid)
T2
T2
T2n
T2n
T3
T3n
T3n
DQ (first data no longer vali d)
T3
DQ8–DQ15 and UDQS Collectively
T2
T2n
T3
T3n
Data valid
window
Data valid
window
Data valid
window
Data valid
window
t
Notes: 1. tHP is the lesser of CL or tCH clock transition collectively when a bank is active.
2. tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transition, and ends with the last valid DQ transition.
3. DQ transitioning after DQS transition define the tDQSQ window. LDQS defines the lower
byte, and UDQS defines the upper byte.
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5. tQH is derived from tHP:tQH = tHP -tQHS.
6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 17 - Da t a ou t P u t timing - ac a n D tDQsck
t
1
T1
T2
T3
T3n
T4
T4n
T5
T5n
T2n
T6
T0
CK#
CK
t
HZ (MAX)
t
t
2
t
2
DQSCK (MAX)
DQSCK (MAX)
2
t
2
t
DQSCK (MIN)
DQSCK (MIN)
LZ (MIN)
t
t
RPST
RPRE
3
DQS or LDQS/UDQS
DQ (last data valid)
DQ (first data valid)
T2
T2
T2
T2n
T2n
T2n
T3n
T3n
T4
T4
T4
T4n
T5
T5
T5n
T5n
T5n
T3
T3
T3
T4n
T4n
4
All DQ values collectively
T5
T3n
t
t
5
t 5
AC (MAX)
LZ (MIN)
AC (MIN)
t
HZ (MAX)
Notes: 1. READ command with CL = 2 issued at T0.
2. tDQSCK is the DQS output window relative to CK and is the “long term” component of the
DQS skew.
t
3. DQ transitioning after DQS transition define the DQSQ window.
4. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
5. tAC is the DQ output window relative to CK and is the “long term” component of DQ skew.
6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.
7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 18 - wr it e Bu r s t
T0
T1
T2
T2n
T3
CK#
CK
Command
WRITE
NOP
NOP
NOP
Bank a,
Col b
Address
t
DQSS (NOM)
DQS
t
DQSS
DI
b
DQ
DM
t
DQSS (MIN)
DQS
t
DQSS
DI
b
DQ
DM
t
DQSS (MAX)
DQS
t
DQSS
DI
b
DQ
DM
Transitioning Data
Don’t Care
Notes: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 19 - co n s e c u t iv e wr it e t o wr it e
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CK#
CK
WRITE
NOP
WRITE
NOP
NOP
NOP
Command
Address
Bank,
Col b
Bank,
Col n
t
DQSS (NOM)
DQS
t
DQSS
DI
b
DI
n
DQ
DM
Transitioning Data
Don’t Care
Notes: 1. DI b (or n) = data-in from column b (or column n).
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 20 - no n c o n s e c u t iv e wr it e t o wr it e
T0
T1
T1n
T2
T2n
T3
T4
T4n
T5
T5n
CK#
CK
WRITE
NOP
NOP
WRITE
NOP
NOP
Command
Address
Bank,
Col b
Bank,
Col n
t
t
DQSS
DQSS (NOM)
DQS
DI
b
DI
n
DQ
DM
Transitioning Data
Don’t Care
Notes: 1. DI b (or n) = data-in from column b (or column n).
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
Fig u r e 21 - ra n D o m wr it e cy c l e s
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
WRITE
WRITE
WRITE
WRITE
Command
Address
WRITE
NOP
Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col a
Bank,
Col g
t
DQSS (NOM)
DQS
DI
b
DI
b'
DI
x
DI
x'
DI
n
DI
n'
DI
a
DI
a'
DI
g
DI
g'
DQ
DM
Transitioning Data
Don’t Care
Notes: 1. DI b (or x or n or a or g) = data-in from column b (or column x, or column n, or column a, or
column g).
2. b', x', n', a' or g' indicate the next data-in following DO b, DO x, DOn, DO a, or DO g,
respectively.
3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown.
4. Each WRITE command may be to any bank.
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 22 - wr it e t o re a D un in t e r r u P t e D
T6
T6n
T0
T1
T1n
T2
T2n
T3
T4
T5
CK#
CK
Command
WRITE
NOP
NOP
NOP
t
READ
NOP
NOP
WTR
Bank a,
Col b
Bank a,
Col n
Address
t
t
DQSS (NOM)
DQSS
CL = 2
DQS
DI
b
DO
n
DQ
DM
t
t
DQSS
DQSS (MIN)
DQS
CL = 2
DI
b
DO
n
DQ
DM
t
t
DQSS
DQSS (MAX)
DQS
CL = 2
DI
b
DO
n
DQ
DM
Transitioning Data
Don’t Care
Notes: 1. DI b = data-in for column b; DO n = data-out for column n.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same device. However, the READ and WRITE
commands may be to different devices, in which case tWTR is not required, and the READ
command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
LOGIC Devices Incorporated
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 23 - wr it e t o re a D in t e r r u P t in g
T6
T6n
T0
T1
T1n
T2
T2n
T3
T3n
T4
T5
T5n
CK#
CK
Command
WRITE
NOP
NOP
t
READ
NOP
NOP
NOP
WTR
Bank a,
Col b
Bank a,
Col n
Address
t
t
DQSS (NOM)
DQSS
CL = 2
DQS
DI
b
DO
n
DQ
DM
t
t
DQSS
DQSS (MIN)
DQS
CL = 2
DI
b
DO
n
DQ
DM
t
t
DQSS
DQSS (MAX)
DQS
CL = 2
DI
b
DO
n
DQ
DM
Transitioning Data
Don’t Care
Notes: 1. DI b = data-in for column b; DO n = data-out for column n.
2. An interrupted burst of 4 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 is used, DM and DQS are required at T3 and T3n because the READ
command will not mask these two data elements.
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High Performance, Integrated Memory Module Product
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Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 24 - wr it e t o re a D , oD D nu m B e r o F Da t a , in t e r r u P t in g
T5n
T6
T6n
T0
T1
T1n
T2
T2n
T3
T3n
T4
T5
CK#
CK
Command
WRITE
NOP
NOP
READ
NOP
NOP
NOP
t
WTR
Bank a,
Col b
Bank a,
Col n
Address
t
t
t
t
t
t
DQSS (NOM)
DQS
DQSS
DQSS
DQSS
CL = 2
CL = 2
CL = 2
DI
b
DO
n
DQ
DM
DQSS (MIN)
DQS
DI
b
DO
n
DQ
DM
DQSS (MAX)
DQS
DI
b
DO
n
DQ
DM
Transitioning Data
Don’t Care
Notes: 1. DI b = data-in for column b; DO n = data-out for column n.
2. An interrupted burst of 4 is shown; one data element is written.
3. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not
the last two data elements).
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 is used, DM and DQS are required at T3–T3n because the READ command
will not mask these data elements.
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High Performance, Integrated Memory Module Product
40
Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 25 - wr it e t o Pr e c h a r g e - un in t e r r u P t e D
T6
T0
T1
T1n
T2
T2n
T3
T4
T5
CK#
CK
Command
PRE
WRITE
NOP
NOP
NOP
NOP
NOP
t
t
RP
WR
Bank a,
Col b
Bank,
Address
(a or all)
t
t
t
t
t
t
DQSS (NOM)
DQS
DQSS
DQSS
DQSS
DI
b
DQ
DM
DQSS (MIN)
DQS
DI
b
DQ
DM
DQSS (MAX)
DQS
DI
b
DQ
DM
Transitioning Data
Don’t Care
Notes: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE
and WRITE commands may be to different devices, in which case t
WR is not required and
the PRECHARGE command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
41
Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 26 - wr it e t o Pr e c h a r g e - in t e r r u P t in g
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
CK#
CK
Command
WRITE
NOP
NOP
NOP
NOP
NOP
PRE
t
t
RP
WR
Bank a,
Col b
Bank,
Address
(a or all)
t
t
t
t
t
t
DQSS (NOM)
DQSS
DQSS
DQSS
DQS
DI
b
DQ
DM
DQSS (MIN)
DQS
DI
b
DQ
DM
DQSS (MAX)
DQS
DI
b
DQ
DM
Transitioning Data
Don’t Care
Notes: 1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 8 is shown; two data elements are written.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T4 and T4n (nominal case) to register DM.
7. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
42
Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Fig u r e 27 - Da t a in P u t timing
1
T0
T1
T1n
T2
T2n
T3
CK#
CK
t
2
3
2
3
DQSS
t
t
t
t
DSS
DSH
DSS
DSH
DQS
t
t
t
t t
DQSH WPST
WPRES WPRE
DQSL
DI
b
DQ
DM
t
t
DH
DS
Transitioning Data
Don’t Care
Notes: 1. WRITE command issued at T0.
t
2. tDSH (MIN) generally occurs during DQSS (MIN).
3. tDSS (MIN) generally occurs during tDQSS (MAX).
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
5. DI b = data-in from column b.
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
43
Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
me c h a n ic a l Dr a w in g
25 ± ± 0.1
2.35 ± ± 0.1
0.60 ± ± 0 ꢀ
19.05 ± ± 0.
SQ
25 ± ± 0.1
1.27
± ± 0.
1.75 ± ± 0..
1.27 ± ± 0.
219 X 0.76 ± ± 0 1
8.89 ± ± 0.
SQ
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
44
Feb 2, 2009 LDS-L9D125G80BG4-C
PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
or D e r in g in F o r m a t io n
Part Number
L9D125G80BG4I6
L9D125G80BG4E6
L9D125G80BG4M6
Core FREQ.
166 MHz
Data Transfer Rate
333 Mbps
Package
Grade
INDUSTRIAL
EXTENDED
MIL-TEMP
25mm2-219 PBGA
25mm2-219 PBGA
25mm2-219 PBGA
333 Mbps
166 MHz
333 Mbps
166 MHz
266 Mbps
266 Mbps
266 Mbps
L9D125G80BG4I75
L9D125G80BG4E75
L9D125G80BG4M75
25mm2-219 PBGA
25mm2-219 PBGA
25mm2-219 PBGA
133 MHz
133 MHz
133 MHz
INDUSTRIAL
EXTENDED
MIL-TEMP
250 Mbps
250 Mbps
250 Mbps
L9D125G80BG4I8
L9D125G80BG4E8
L9D125G80BG4M8
25mm2-219 PBGA
25mm2-219 PBGA
25mm2-219 PBGA
125 MHz
125 MHz
125 MHz
INDUSTRIAL
EXTENDED
MIL-TEMP
200 MHz
200 MHz
200 MHz
L9D125G80BG4I10
L9D125G80BG4E10
L9D125G80BG4M10
25mm2-219 PBGA
25mm2-219 PBGA
25mm2-219 PBGA
100 MHz
100 MHz
100 MHz
INDUSTRIAL
EXTENDED
MIL-TEMP
re v is io n his t o r y
Revision
Engineer
Issue Date Description Of Change
INITIATE
DH/JM
11/12/2008
01/21/2009
A
Pgs 1, 45: Change all incidences of “LBGA” to “PBGA”, revise wording to Plastic Ball Grid Array
Pgs 4,5: Revision to include ball E12, Vref in Pin/Ball Locations/Definitions Section
Pg 8 : Changes to allowable frequency parameters (CAS =2) in CAS latency table (speed -10
changes from ≤75 to ≤ 83, -75 changes from ≤100 to ≤125, -6 changes from ≤133 to NA)
Pg 19: Revise CL parameter (333 Mbps: change CL from 2 to 2.5)
DH/JM
B
Pg 20, 21: AC chart specs changes for 167 MHz, correct tLZ min. from -.0.07 to -0.70
Pg 44: Correction to mechanical drawing
CM/JM
02/02/2009
C
LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its
products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant informa-
tion before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out
of the application or use of any product or circuit described herein. In no event shall any liability exceed the product purchase price. Products of
LOGIC Devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursu-
ant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical compo-
nents in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user.
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
45
Feb 2, 2009 LDS-L9D125G80BG4-C
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