MCMA700P1600CA [LITTELFUSE]

Silicon Controlled Rectifier,;
MCMA700P1600CA
型号: MCMA700P1600CA
厂家: LITTELFUSE    LITTELFUSE
描述:

Silicon Controlled Rectifier,

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MCMA700P1600CA  
=
VRRM  
ITAV  
VT  
2x1600V  
700A  
Thyristor Module  
=
=
1.11V  
Phase leg  
Part number  
MCMA700P1600CA  
Backside: isolated  
3
1
2
6
7
5
4
ComPack  
Features / Advantages:  
Applications:  
Package:  
Thyristor for line frequency  
Planar passivated chip  
Long-term stability  
Line rectifying 50/60 Hz  
Softstart AC motor control  
DC Motor control  
Isolation Voltage:  
Industry standard outline  
RoHS compliant  
V~  
4800  
Direct Copper Bonded Al2O3-ceramic  
Power converter  
AC power control  
Lighting and temperature control  
Soldering pins for PCB mounting  
Base plate: Copper  
internally DCB isolated  
Advanced power cycling  
Phase Change Material available  
Disclaimer Notice  
Information furnished is believed to be accurate and reliable. However, users should independently  
evaluate the suitability of and test each product selected for their own applications. Littelfuse products are not designed for,  
www.littelfuse.com/disclaimer-electronics.  
and may not be used in, all applications. Read complete Disclaimer Notice at  
IXYS reserves the right to change limits, conditions and dimensions.  
Data according to IEC 60747and per semiconductor unless otherwise specified  
20191217d  
© 2019 IXYS all rights reserved  
MCMA700P1600CA  
Ratings  
Rectifier  
Symbol  
VRSM/DSM  
Definition  
Conditions  
min. typ. max. Unit  
TVJ = 25°C  
TVJ = 25°C  
TVJ = 25°C  
TVJ = 125°C  
TVJ = 25°C  
1700  
1600  
2
V
V
max. non-repetitive reverse/forward blocking voltage  
max. repetitive reverse/forward blocking voltage  
VRRM/DRM  
IR/D  
VR/D =1600 V  
VR/D =1600 V  
IT = 700 A  
IT =1400 A  
IT = 700 A  
IT =1400 A  
TC = 85°C  
180° sine  
mA  
reverse current, drain current  
40 mA  
forward voltage drop  
1.16  
V
V
V
V
A
A
V
VT  
1.41  
1.11  
1.41  
700  
TVJ  
=
°C  
125  
average forward current  
RMS forward current  
TVJ = 140°C  
TVJ = 140°C  
ITAV  
IT(RMS)  
VT0  
1100  
0.82  
threshold voltage  
for power loss calculation only  
slope resistance  
0.4 mΩ  
0.05 K/W  
K/W  
rT  
RthJC  
RthCH  
Ptot  
thermal resistance junction to case  
thermal resistance case to heatsink  
0.02  
TC = 25°C  
TVJ = 45°C  
VR = 0 V  
2300  
19.0  
20.5  
16.2  
17.4  
W
kA  
kA  
kA  
kA  
total power dissipation  
max. forward surge current  
t = 10 ms; (50 Hz), sine  
t = 8,3 ms; (60 Hz), sine  
t = 10 ms; (50 Hz), sine  
t = 8,3 ms; (60 Hz), sine  
t = 10 ms; (50 Hz), sine  
t = 8,3 ms; (60 Hz), sine  
t = 10 ms; (50 Hz), sine  
t = 8,3 ms; (60 Hz), sine  
VR = 400V f = 1 MHz  
tP = 30 µs  
ITSM  
TVJ = 140°C  
VR = 0 V  
value for fusing  
TVJ = 45°C  
VR = 0 V  
I²t  
1.81 MA²s  
1.75 MA²s  
1.30 MA²s  
1.27 MA²s  
pF  
TVJ = 140°C  
VR = 0 V  
junction capacitance  
TVJ = 25°C  
TC = 140°C  
876  
CJ  
240  
120  
40  
W
W
W
PGM  
max. gate power dissipation  
tP = 300 µs  
PGAV  
average gate power dissipation  
critical rate of rise of current  
TVJ = 140°C; f = 50 Hz  
repetitive, IT =2100 A  
100 A/µs  
(di/dt)cr  
1
tP = 200 µs;diG /dt =  
IG = 1A; V = VDRM  
V = VDRM  
A/µs;  
non-repet., IT = 700 A  
TVJ = 140°C  
500 A/µs  
critical rate of rise of voltage  
gate trigger voltage  
1000 V/µs  
(dv/dt)cr  
VGT  
RGK = ∞; method 1 (linear voltage rise)  
VD = 6 V  
TVJ = 25°C  
TVJ = -40°C  
TVJ = 25°C  
TVJ = -40°C  
TVJ = 140°C  
2
3
V
V
gate trigger current  
VD = 6 V  
300 mA  
400 mA  
IGT  
gate non-trigger voltage  
gate non-trigger current  
latching current  
VD = VDRM  
tp = 30 µs  
0.25  
V
VGD  
IGD  
IL  
10 mA  
TVJ = 25°C  
400 mA  
IG  
=
1A; diG/dt =  
1 A/µs  
1 A/µs  
holding current  
VD = 6 V RGK = ∞  
TVJ = 25°C  
TVJ = 25°C  
300 mA  
IH  
gate controlled delay time  
VD = ½ V  
2
µs  
tgd  
DRM  
IG  
=
1A; diG/dt =  
turn-off time  
VR = 100 V; IT = 700A; V = VDRM TVJ =125 °C  
di/dt = 10 A/µs dv/dt = 50 V/µs µs  
350  
µs  
tq  
tp = 200  
IXYS reserves the right to change limits, conditions and dimensions.  
Data according to IEC 60747and per semiconductor unless otherwise specified  
20191217d  
© 2019 IXYS all rights reserved  
MCMA700P1600CA  
Ratings  
Package ComPack  
Symbol  
IRMS  
Definition  
Conditions  
min. typ. max. Unit  
per terminal  
1200  
140  
125  
125  
A
°C  
°C  
°C  
g
RMS current  
-40  
-40  
-40  
TVJ  
virtual junction temperature  
Top  
operation temperature  
storage temperature  
Tstg  
500  
Weight  
3
12  
5
Nm  
MD  
mounting torque  
terminal torque  
M
14 Nm  
T
terminal to terminal  
terminal to backside  
21.0  
18.0  
4800  
4000  
mm  
mm  
V
dSpp/App  
dSpb/Apb  
creepage distance on surface | striking distance through air  
t = 1 second  
V
isolation voltage  
ISOL  
50/60 Hz, RMS; IISOL 1 mA  
t = 1 minute  
V
Part description  
M = Module  
C = Thyristor (SCR)  
M = Thyristor  
Assembly Line  
Circuit Diagram  
A = (up to 1800V)  
700 = Current Rating [A]  
P = Phase leg  
Date Code  
Part No.  
yywwA  
YYYYYYYYYYY  
2D Matrix  
1600 = Reverse Voltage [V]  
CA = ComPack  
Ordering  
Standard  
Ordering Number  
Marking on Product  
MCMA700P1600CA  
Delivery Mode  
Quantity Code No.  
513835  
MCMA700P1600CA  
Box  
3
TVJ =140°C  
Equivalent Circuits for Simulation  
* on die level  
Thyristor  
V0  
I
R0  
threshold voltage  
slope resistance *  
0.82  
0.21  
V
V0 max  
R0 max  
mΩ  
IXYS reserves the right to change limits, conditions and dimensions.  
Data according to IEC 60747and per semiconductor unless otherwise specified  
20191217d  
© 2019 IXYS all rights reserved  
MCMA700P1600CA  
Outlines ComPack  
21.2  
7.2  
66.0 +0.0  
-0.7  
0.2  
5.0  
0.3  
27.25  
label  
A
baseplate typ. 100 µm convex  
over 54.5 mm before mounting  
baseplate typ. 100 µm convex  
over 62.5 mm before mounting  
61.0  
92.0 +0.5  
-0.3  
Optional accessories for modules  
Keyed gate/cathode twin plugs with  
wire length = 350 mm, gate = white, cathode = red  
0.5  
107  
Type ZY 180L (L = Left for pin pair 4/5)  
Type ZY 180R (R = Right for pin pair 6/7)  
UL 758,  
style 3751  
48.0  
0.5  
39.5  
A (2:1)  
M10x16 (3x)  
18.0  
0.8  
80,0  
93,5  
3
1
2
6 7  
5 4  
IXYS reserves the right to change limits, conditions and dimensions.  
Data according to IEC 60747and per semiconductor unless otherwise specified  
20191217d  
© 2019 IXYS all rights reserved  
MCMA700P1600CA  
Thyristor  
1400  
16000  
14000  
12000  
107  
VR = 0 V  
50 Hz, 80% VRRM  
1200  
1000  
IT  
I2t  
800  
TVJ = 45°C  
TVJ = 45°C  
106  
ITSM  
10000  
[A]  
[A]  
600  
[A2s]  
TVJ = 140°C  
TVJ = 125°C  
400  
200  
0
TVJ = 140°C  
140°C  
8000  
TVJ = 25°C  
6000  
105  
0.4 0.6 0.8 1.0 1.2 1.4 1.6  
0.01  
0.1  
1
1
2
3
4
5 6 7 8 910  
VT [V]  
t [s]  
t [ms]  
Fig. 3 I2t versus time (1-10 s)  
Fig. 2 Surge overload current  
ITSM: crest value, t: duration  
Fig. 1 Forward characteristics  
100  
10  
100.0  
10.0  
1400  
PGM = 240 W; tp  
120 W; tp = 300 µs  
PGAV = 40 W  
= 30 µs  
1200  
1000  
800  
dc =  
1
0.5  
0.4  
0.33  
0.17  
0.08  
TVJ = 125°C  
VG  
tgd  
ITAVM  
[V]  
600  
400  
200  
0
lim.  
typ.  
[µs]  
[A]  
1
1.0  
IGT (TVJ  
IGT (TVJ  
=
=
-40°C)  
25°C)  
IGD (TVJ = 140°C)  
0.1  
0.1  
0.01  
0.01  
0.1  
1 10  
0.10  
1.00  
IG [A]  
10.00  
0
40  
80  
120  
160  
IG [A]  
Tcase [°C]  
Fig. 6 Max. forward current at  
case temperature  
Fig. 5 Gate controlled delay time tgd  
Fig. 4 Gate voltage & gate current  
0.06  
dc =  
1
0.5  
0.4  
0.33  
0.17  
0.08  
1000  
i
Rthi (K/W)  
0.0020  
0.0080  
0.0130  
0.0370  
ti (s)  
0.05  
0.04  
0.03  
RthHA  
1
2
3
4
0.0150  
0.0800  
0.2200  
0.3800  
0.05  
0.10  
0.20  
0.30  
0.40  
0.50  
800  
Ptot  
ZthJC  
600  
[W]  
400  
[K/W]  
0.02  
200  
0
0.01  
0.00  
1
10  
100  
t [ms]  
Fig. 8 Transient thermal impedance junction to case  
1000  
10000  
0
200 400 600 800  
0
40  
80  
Tamb [°C]  
120  
160  
IT(AV) [A]  
Fig. 7a Power dissipation versus direct output current  
Fig. 7b and ambient temperature  
IXYS reserves the right to change limits, conditions and dimensions.  
Data according to IEC 60747and per semiconductor unless otherwise specified  
20191217d  
© 2019 IXYS all rights reserved  

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