LTC4557EUD#TRPBF [Linear]
LTC4557 - Dual SIM/Smart Card Power Supply and Interface; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC4557EUD#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC4557 - Dual SIM/Smart Card Power Supply and Interface; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C |
| 文件： | 总12页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4557
Dual SIM/Smart Card
Power Supply and Interface
U
FEATURES
DESCRIPTIO
TheLTC®4557providespowerconversionandsignallevel
translation needed for 2.5G and 3G cellular telephones to
interface with 1.8V or 3V subscriber identity modules
(SIMs). The part meets all requirements for 1.8V and 3V
SIMs. The part contains LDO regulators to power 1.8V or
3V SIM cards from a 2.7V to 5.5V input. The output
voltages can be set using the two voltage selection pins
and up to 50mA of load current can be supplied.
■
Power Management and Signal Level Translators
for Two SIM Cards or Smart Cards
■
Independent 1.8V/3V VCC Control for Both Cards
■
Automatic Level Translation
ISO7816, ETSI and EMV Compatible
■
■
Dynamic Pull-Ups Deliver Fast Signal Rise Times*
■
Built-In Fault Protection Circuitry
■
Automatic Activation/Deactivation Sequencing
Circuitry
Internal level translators allow controllers operating with
supplies as low as 1.2V to interface with 1.8V or 3V smart
cards. Battery life is maximized by a low operating current
of less than 100µA and a shutdown current of less than
1µA. Board area is minimized by the low profile 3mm ×
3mm × 0.75mm leadless QFN package.
■
Low Operating/Shutdown Current
■
>10kV ESD on SIM Card Pins
■
Compatible with EMV Fault Tolerance Requirements
■
Available in 16-LUead (3mm × 3mm) QFN Package
APPLICATIO S
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
GSM and 3G Cellular Phones
*U.S. Patent No. 6,356,140
■
Wireless P.O.S. Terminals
■
Multiple SAM Card Interface
U
TYPICAL APPLICATIO
DV
V
BATT
CC
1.2V TO 4.4V 3V TO 6V
DV
CC
0.1µF
0.1µF
Deactivation Sequence
DV
V
CC
BATT
I/OA
C7
C2
C3
C1
CLKIN
RSTIN
DATA
I/O
RSTX
RSTA
CLKA
RST
CLK
1.8V/3V
SIM
5V/DIV
CARD
CLKX
5V/DIV
V
V
CC
CCA
GND
µCONTROLLER
LTC4557
1µF
1µF
C5
GND
I/OX
5V/DIV
C1
C3
C2
C7
V
CCX
V
V
CC
CCB
2V/DIV
ENABLE
M0
CLKB
CLK
RST
I/O
1.8V/3V
SMART
CARD
4557 G07
C
= 1µF
10µs/DIV
VCCX
RSTB
I/OB
M1
GND
C5
4557 TA01
4557f
1
LTC4557
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
NUMBER
VBATT, DVCC, DATA, RSTIN, CLKIN,
ENABLE, M0, M1 to GND............................ –0.3V to 6V
I/OA, CLKA, RSTA........................ –0.3V to VCCA + 0.3V
I/OB, CLKB, RSTB........................ –0.3V to VCCB + 0.3V
ICCA,B (Note 4) ...................................................... 80mA
16 15 14 13
LTC4557EUD
V
1
2
3
4
12 M0
11 M1
CCB
DV
CC
17
V
BATT
CLKIN
10
9
V
CCA,B Short-Circuit Duration ......................... Indefinite
V
RSTIN
CCA
Operating Temperature Range (Note 3) .. –40°C to 85°C
Storage Temperature Range ................... –65°C to 125°
5
6
7
8
UD PART MARKING
LAHP
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
TJMAX = 125°C, θJA = 68°C/W, θJC = 42°C/W
EXPOSED PAD (PIN 17) IS GND
(MUST BE SOLDERED TO PCB)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 1.8V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Power Supply
V
Operating Voltage
Operating Current
●
2.7
5.5
V
BATT
I
V
V
= 3V, V
= 1.8V, V
= 0V, I
= I = 0µA
CCB
●
●
65
65
100
100
µA
µA
VBATT
CCA
CCA
CCB
CCA
= 0V, I
= I
CCB
= 0µA
CCB
CCA
DV Operating Voltage
●
●
●
1.2
5.5
10
1
V
µA
µA
CC
I
I
I
Operating Current
Shutdown Current
Shutdown Current
6
DVCC
DVCC
VBATT
0.1
●
●
0.4
0.1
2.5
1.0
µA
µA
DV = 0V
CC
SIM Card Supplies
V
Output Voltage
3V Mode, 0mA < I
1.8V Mode, 0mA < I
< 50mA
CCA,B
●
●
2.75
1.65
3.0
1.8
3.25
1.95
V
V
CCA,B
< 3OmA
CCA,B
Channel Turn-On Time
I
= 0mA,
ENABLE to
I
●
1.3
2.5
ms
CCA,B
OA/B
CLKA, CLKB
V
V
Low Level Output Voltage
High Level Output Voltage
Sink Current = –200µA (Note 2)
Source Current = 200µA (Note 2)
●
●
0.2
V
V
OL
OH
V
V
–
–
CCA,B
0.2
Rise, Fall Time
Loaded with 33pF (10% to 90%) (Note 2)
(Note 2)
●
●
16
ns
CLKA, CLKB Frequency
10
MHz
RSTA, RSTB
V
V
Low Level Output Voltage
High Level Output Voltage
Sink Current = –200µA (Note 2)
Source Current = 200µA (Note 2)
●
●
0.2
V
V
OL
OH
CCA,B
0.2
Rise, Fall Time
Loaded with 33pF (10% to 90%) (Note 2)
●
100
ns
4557f
2
LTC4557
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 1.8V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I/OA, I/OB
V
OL
V
OH
Low Level Output Voltage
High Level Output Voltage
Sink Current = –1mA (V
= 0V) (Note 2)
●
●
0.3
V
V
DATA
Source Current = 20µA (V
(Note 2)
= V
)
0.85 •
DATA
DVCC
V
CCA,B
Rise Time
Loaded with 33pF (10% to 90%) (Note 2)
= 0V (Note 2)
●
●
200
5
500
10
ns
Short-Circuit Current
V
mA
DATA
DATA
V
OL
V
OH
Low Level Output Voltage
High Level Output Voltage
Sink Current = –500µA (V
Source Current = 20µA (V
= 0V)
●
●
0.3
V
V
I/OA,B
= V
)
0.8 •
DV
I/OA,B
CCA,B
CC
Rise Time
Loaded with 33pF (10% to 90%)
●
200
500
ns
RSTIN, CLKIN, ENABLE, M0, M1
V
Low Input Threshold
●
●
●
0.15 •
V
V
IL
DV
CC
V
IH
High Input Threshold
0.85 •
DV
CC
Input Current (I , I )
–1
1
µA
IH IL
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: This specification applies to both 1.8V and 3V smart cards.
Note 3: The LTC4557E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 4: Based on long term current density limitations.
4557f
3
LTC4557
U W
TYPICAL PERFOR A CE CHARACTERISTICS
I/O X Short-Circuit Current
vs Temperature
VBATT Quiescent Current
(IVBATT – ICC) vs Load Current
No Load Supply Current vs VBATT
80
75
70
65
60
55
140
120
100
80
6.0
5.5
5.0
4.5
4.0
T
= 25°C
BATT
T
I
= 25°C
CCA CCB
V
V
= V
= 5.5V
BATT
A
V
A
DVCC
CCX
= 3.1V
= I
= 0µA
= 3V
DROPOUT
V
CCX
= 3V
60
40
V
= 1.8V
CCX
20
0
2.7 3.1 3.5 3.9 4.3
4.7 5.1 5.5
10
100
1000
10000
100000
–40
–15
10
35
60
85
LOAD CURRENT (µA)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
4557 G03
4557 G01
4557 G02
VBATT Shutdown Current
vs Supply Voltage
DVCC Shutdown Current
vs Supply Voltage
3.0
2.5
2.0
1.5
0.7
V
DVCC
= 1.8V
V
A
= 5.5V
BATT
T
= –40°C TO 85°C
0.6
0.5
T
= –40°C
A
T
A
= 25°C
0.4
0.3
0.2
0.1
1.0
0.5
0
T
= 85°C
A
0
4.3
5.1
5.5
2.7 3.1
3.5 3.9
4.7
5.2 5.6
1.2
2.4
3.2 3.6
4
4.4 4.8
1.6
2
2.8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
4557 G04
4557 G05
Deactivation Sequence,
CVCCX = 1µF
Data – I/O Channel, CL = 40pF
I/0X
1V/DIV
RSTX
5V/DIV
CLKX
5V/DIV
DATA
1V/DIV
I/OX
5V/DIV
V
CCX
2V/DIV
4557 G06
4557 G07
C
= 40pF
200ns/DIV
C
= 1µF
VCCX
10µs/DIV
L
4557f
4
LTC4557
U
U
U
PI FU CTIO S
DVCC (Pin 2): Power. Reference voltage for the control
DATA (Pin 8): Input/Output. Microcontroller side data I/O
pin. The DATA pin provides the bidirectional communica-
tion path to both cards. Only one of the cards may be
selected to communicate via the DATA pin. The pin pos-
sesses a dynamically activated pull-up current source,
allowing the controller to use an open-drain output. The
current source maintains a HIGH state. This pin is held
HIGH by a weak pull-up when the ENABLE pin is LOW.
logic.
VBATT (Pin 3): Power. Supply voltage for the analog
sections of the LTC4557.
VCCA/VCCB (Pins 4, 1): Card Socket. The VCCA/VCCB pins
should be connected to the VCC pins of the respective card
sockets. The activation of the VCCA/VCCB pins is controlled
by the M0, M1 and ENABLE inputs. They can be set to 0V,
1.8V or 3V. Only one of the two, either VCCA or VCCB, may
be active at a time.
RSTIN (Pin 9): Input. The RSTIN pin supplies the reset
signal to the cards. It is level shifted and transmitted
directly to the RST pin of the selected card.
CLKA/CLKB (Pins 5, 16): Card Socket. The CLKA/CLKB
pins should be connected to the CLK pins of the respective
cardsockets.TheCLKA/CLKBsignalsarederivedfromthe
CLKIN pin. They provide a level shifted CLKIN signal to the
selected card. The CLKA/CLKB pins are gated off until
VCCA/VCCB attain their correct values.
CLKIN (Pin 10): Input. The CLKIN pin supplies the clock
signal to the cards. It is level shifted and transmitted
directly to the CLK pin of the selected card.
M0/M1 (Pins 12, 11): Inputs. The M0 and M1 pins select
which set of SIM/smart card pins are active and at which
voltage level they operate. The truth table for these pins
follows:
RSTA/RSTB (Pins 6, 15): Card Socket. The RSTA/RSTB
pinsshouldbeconnectedtotheRSTpinsoftherespective
card sockets. The RSTA/RSTB signals are derived from
theRSTINpin. Whenacardisselected, itsRSTpinfollows
RSTIN. The RSTA/RSTB pins are gated off until VCCA/VCCB
attain their correct values.
M1
0
M0
0
SELECTED CARD/VOLTAGE
Card A/1.8V
0
1
Card A/3V
1
0
Card B/1.8V
1
1
Card B/3V
I/OA, I/OB (Pins 7, 14): Card Socket. The I/OA, I/OB pins
connect to the I/O pins of the respective card sockets.
Whenacardisselected, itsI/Opintransmits/receivesdata
to/from the DATA pin. The I/OA, I/OB pins are gated off
until VCCA/VCCB attain their correct values.
ENABLE (Pin 13): Input. The ENABLE pin shuts down the
chip when LOW.
EXPOSED PAD (Pin 17): Chip Ground. This ground pad
must be soldered directly to a PCB ground plane.
4557f
5
LTC4557
W
BLOCK DIAGRA
DV
V
CC
BATT
3
2
V
CCA
4
LDOA
LDOB
1
V
CCB
DV
CC
14
I/OB
I/OA
7
6
RSTA
15 RSTB
CLKA
5
16 CLKB
DV
CC
DATA
8
9
RSTIN
CONTROL
LOGIC
CLKIN 10
17
13
12
11
4557 BD
GND
ENABLE M0 M1
4557f
6
LTC4557
U
OPERATIO
TheLTC4557featurestwoindependentsmartcardchan-
nels. Only one of these channels may operate at a time.
Each channel is able to output two voltage levels: 1.8V
and 3V. The channel selection and voltage selection are
controlled by the ENABLE, M0 and M1 pins as shown in
Table 1.
When a card socket is selected, it becomes a candidate to
drive data on the DATA pin and likewise receive data from
the DATA pin. When a card socket is deselected, the
voltage on its I/OA,B pin will be disabled and set to LOW.
If both cards are deselected, a weak pull-up ensures that
the DATA pin is held HIGH.
Table 1. Channel and Voltage Truth Table
Dynamic Pull-up Current Sources
ENABLE
M1
0
M0
0
SELECTED CARD/VOLTAGE
Card A/1.8V
The current sources on the bidirectional pins (DATA/
I/OA,B) are dynamically activated to achieve a fast rise
time with a relatively small static current. Once a bidirec-
tional pin is relinquished, a small start-up current begins
tochargethenode. Anedgeratedetectordeterminesifthe
pin is released by comparing its slew rate with an internal
reference value. If a valid transition is detected, a large
pull-up current enhances the edge rate on the node. The
higher slew rate corroborates the decision to charge the
node thereby affecting a dynamic form of hysteresis.
1
1
1
1
0
0
1
Card A/3V
1
0
Card B/1.8V
1
1
Card B/3V
X
X
A and B Disabled
Bidirectional Channels
Thebidirectionalchannelsarelevelshiftedtotheappropri-
ate VCCA,B voltages at the I/OA,B pins. An NMOS pass
transistor performs the level shifting. The gate of the
NMOS transistor is biased such that the transistor is
completely off when both sides have relinquished the
channel. If one side of the channel asserts a LOW, then the
transistor will convey the LOW to the other side. Note that
current passes from the receiving side of the channel to
the transmitting side. The low output voltage of the receiv-
ingsidewillbedependentuponthevoltageatthetransmit-
ting side plus the IR drop of the pass transistor.
Reset Channels
When a card is selected, the reset channel provides a level
shifted path from the RSTIN pin to the RSTA,B pin. When
a card is deselected its reset pin is pulled LOW.
LOCAL
SUPPLY
V
REF
+
I
START
–
dv
dt
4557 F01
BIDIRECTIONAL
PIN
Figure 1. Dynamic Pull-Up Current Source
4557f
7
LTC4557
U
OPERATIO
Activation/Deactivation
3. The I/O channel is disabled and the I/O pin is brought
LOW approximately 9µs after the ENABLE is brought
LOW.
Activation and deactivation sequencing is handled by
built-in circuitry. The activation sequence is initiated by
bringingtheENABLEpinHIGH. Theactivationsequenceis
outlined below:
4. VCC will be depowered after the I/O pin is brought LOW.
The activation or deactivation sequences will take place
every time a card socket is enabled or disabled.
1. The RST, CLK and I/O pins are held LOW.
2. VCC is enabled.
Fault Protection
3. After VCC is stable at its selected level, The I/O and RST
channels are enabled.
The VCC, I/O, RST and CLK pins are all protected against
short-circuit faults. While there are no logic outputs to
indicate that a fault has occurred, these pins will be able
to tolerate the fault condition until it has been removed.
4. The clock channel is enabled on the rising edge of the
second clock cycle after the I/O pin is enabled.
The deactivation sequence is initiated by bringing the
ENABLE pin LOW. The deactivation sequence is outlined
below:
TheVCCA,B, I/OA,B, andRSTA,Bpinspossessfaultprotec-
tion circuitry which will limit the current available to the
pins. Each VCC pin is capable of supplying approximately
90mA (typ) before the output voltage is reduced.
1. The reset channel is disabled and RST is brought LOW.
The CLKA,B pins are designed to tolerate faults by reduc-
ing the current drive capability of their output stages. After
a fault is detected by the internal fault detection logic, the
logic waits for a fault detection delay to elapse before
reducing the current drive capability of the output stage.
2. TheclockchannelisdisabledandtheCLKpinisbrought
LOW two clock cycles after ENABLE is brought LOW. If
the clock is not running, the clock channel will be
disabled approximately 9µs after the ENABLE pin is
brought LOW.
4557f
8
LTC4557
W U U
APPLICATIO S I FOR ATIO
U
10kV ESD Protection
capacitors can be compared directly by case size rather
than specified value for a desired minimum capacitance.
All smart card pins (CLKA,B, RSTA,B, I/OA,B, VCCA,B and
GND) can withstand over 10kV of human body model ESD
in-situ. In order to ensure proper ESD protection, careful
board layout is required. The GND pad should be tied
directlytoagroundplane.TheVCCA,Bcapacitorsshouldbe
located very close to the VCCA,B pins and tied immediately
to the ground plane.
The VCCA,B outputs should be bypassed to GND with a 1µF
capacitor. VBATT should be bypassed with a 0.1µF ceramic
capacitor. Capacitors should be placed as close to the
LTC4557 as possible for improved ESD tolerance.
The following capacitors are recommended for use with
the LTC4557:
Capacitor Selection
TYPE
VALUE CASE SIZE MURATA PART NUMBER
C
V
,
X5R
1µF
0603
GRM188R60J105KA01
VCC
CCA/B
Atotaloffourcapacitorsarerequiredforproperbypassing
of the LTC4557. An input bypass capacitor is required at
VBATT andDVCC. Outputbypasscapacitorsarerequiredon
each of the smart card VCCA,B pins. Due to their extremely
low equivalent series resistance (ESR), only multilayer
ceramic chip capacitors should be used to ensure proper
stability and ESD protection.
C
DV
,
X5R
0.1µF
0402
GRM155R61A104KA01
DVCC
CC
Compliance Testing
Inductance due to long leads on type approval equipment
can cause ringing and overshoot that leads to testing
problems. Small amounts of capacitance and damping
resistors can be included in the application without com-
promising the normal electrical performance of the
LTC4557 or smart card system. Generally a 100Ω resistor
and a 20pF capacitor will accomplish this as shown in
Figure 2.
There are several types of ceramic capacitors available
each having considerably different characteristics. For
example,X7R/X5Rceramiccapacitorshaveexcellentvolt-
age and temperature stability but relatively low packing
density. Y5V ceramic capacitors have apparently higher
packing density but poor performance over their rated
voltage or temperature ranges. Under certain voltage and
temperature conditions Y5V and X7R/X5R ceramic
1µF
C1
V
CCX
0.1µF
100Ω
100Ω
100Ω
20pF
CLKX
C3
C2
C7
SMART
CARD
SOCKET
LTC4557
20pF
RSTX
20pF
I/OX
C5
4557 F02
Figure 2. Additional Components for Improved Compliance Testing
4557f
9
LTC4557
W U U
U
APPLICATIO S I FOR ATIO
Shutdown Modes
Ultralow Shutdown Current
The LTC4557 can enter a low current shutdown mode by
one of two methods. First, the ENABLE pin can be brought
LOW by the controller to directly shut down the part. The
other way is to lower DVCC below 1.2V, at which point the
power-on-reset circuit automatically puts the part into
shutdown mode.
In either of the two shutdown modes, the shutdown
current is less than 1µA. For applications that require
virtually zero shutdown current, the DVCC pin can be
grounded. This will reduce the VBATT current to well under
a single microampere.
4557f
10
LTC4557
U
PACKAGE DESCRIPTIO
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
1.45 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
R = 0.115
(4 SIDES)
TYP
0.75 ± 0.05
3.00 ± 0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
1.45 ± 0.10
(4-SIDES)
(UD) QFN 0603
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4557f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC4557
U
TYPICAL APPLICATIO
DV
V
BATT
CC
1.2V TO 4.4V 3V TO 6V
DV
CC
C4
C3
2
3
0.1µF
0.1µF
DV
V
BATT
CC
C7
C2
C3
C1
10
5
6
7
4
CLKIN
RSTIN
DATA
CLKA
RSTA
I/OA
CLK
RST
I/O
9
8
1.8V/3V
SIM
CARD
V
V
CC
CCA
C1
1µF
GND
µCONTROLLER
LTC4557
17
C5
GND
C2
1µF
1
C1
C3
C2
C7
V
V
CC
CCB
13
12
11
16
15
14
ENABLE
M0
CLKB
CLK
RST
I/O
1.8V/3V
SMART
CARD
RSTB
I/OB
M1
GND
C5
4557 TA02
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OUT
LTC1515
50mA, 650kHz, Step-Up/Down Charge Pump with
Power On Reset
V : 2.7V to 10V, V
IN
= 3.3V or 5V, I = 60µA, I < 1µA, SO-8
Q SD
LTC1555/LTC1556
LTC1555L
SIM Power Supply and Level Translator for 3V/5V SIM Cards
V : 2.7V to 10V, V
= 3V/5V, Frequency = 650kHz, I = 60µA,
Q
IN
I
< 1µA, SSOP16, SSOP20
SD
SIM Power Supply and Level Translator for 3V/5V SIM Cards
V : 2.6V to 6.6V, V
IN
= 3V/5V, Frequency = 1MHz, I = 40µA,
OUT
Q
I
< 1µA, SSOP16
SD
LTC1555L-1.8
LTC1755/LTC1756
LTC1955
SIM Power Supply and Level Translator for
1.8V/3V/5V SIM Cards
V : 2.6V to 6.6V, V
= 1.8V/3V/5V, Frequency = 1MHz,
IN
OUT
I = 32µA, I < 1µA, SSOP16
Q
SD
Smart Card Interface with Serial Control for 3V/5V
Smart Card Applications
V : 2.7V to 7V, V
= 3V/5V, I = 60µA, I < 1µA, SSOP16,
IN
OUT Q SD
SSOP24
Dual Smart Card Interface with Serial Control for 1.8V/3V/5V
Smart Card Applications
V : 3V to 6V, V
IN
= 1.8V/3V, I = 200µA, I < 1µA, QFN32
OUT Q SD
LTC1986
SIM Power Supply for 3V/5V SIM Cards
V : 2.6V to 4.4V, V
= 3V/5V, Frequency = 900kHz, I = 14µA,
OUT Q
IN
I
< 1µA, ThinSOT
SD
LTC3250-1.5
LTC3251
250mA, 1.5MHz, High Efficiency Step-Down Charge Pump
85% Efficiency, V : 3.1V to 5.5V, V
= 1.2V/1.5V, I = 35µA,
OUT Q
IN
I
< 1µA, ThinSOT
SD
500mA, 1MHz to 16MHz, Spread Spectrum Step-Down
Charge Pump
85% Efficiency, V : 3.1V to 5.5V, V : 0.9V to 1.6V, 1.2V/1.5V,
IN OUT
I = 9µA, I < 1µA, MS10
Q
SD
LTC4555
LTC4556
SIM Power Supply and Level Translator for 1.8V/3V SIM Cards V : 3V to 6V, V
= 1.8V/3V, I = 40µA, I < 1µA, QFN16
OUT Q SD
IN
Smart Card Interface with Serial Control for 1.8V/3V/5V
V : 2.7V to 5.5V, V
QFN24
= 1.8V/3V/5V, I = 250µA, I < 1µA,
OUT Q SD
IN
4557f
LT/TP 0204 1K • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004
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