LTC4304CMS#TRPBF [Linear]
LTC4304 - Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C;型号: | LTC4304CMS#TRPBF |
厂家: | Linear |
描述: | LTC4304 - Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C |
文件: | 总36页 (文件大小:759K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM2883
2
SPI/Digital or I C µModule
Isolator with Adjustable 12.5V
and 5V Regulated Power
DescripTion
FeaTures
n
UL Rated 6-Channel Logic Isolator: 2500V
The LTM®2883 is a complete galvanic digital µModule®
isolator.Noexternalcomponentsarerequired.Asingle3.3V
or 5V supply powers both sides of the interface through
an integrated, isolated DC/DC converter. A logic supply
pin allows easy interfacing with different logic levels from
1.62V to 5.5V, independent of the main supply.
RMS
UL Recognized
File #E151738
®
n
Isolated Adjustable DC Power:
3V to 5V at Up to 30mA
12ꢀ5V at Up to 20mA
n
n
n
n
No External Components Required
2
SPI (LTM2883-S) or I C (LTM2883-I) Options
High Common Mode Transient Immunity: 30kV/μs
High Speed Operation:
2
Available options are compliant with SPI and I C (master
mode only) specifications.
The isolated side includes 12.5V and 5V nominal power
supplies, each capable of providing more than 20mA of
loadcurrent.Eachsupplymaybeadjustedfromitsnominal
value using a single external resistor.
10MHz Digital Isolation
4MHz/8MHz SPI Isolation
2
400kHz I C Isolation
n
n
n
n
n
n
3.3V (LTM2883-3) or 5V (LTM2883-5) Operation
1.62V to 5.5V Logic Supply
Coupled inductors and an isolation power transformer
10kV ESD HBM Across the Isolation Barrier
provide 2500V
of isolation between the input and out-
RMS
Common Mode Working Voltage: 560V
Low Current Shutdown Mode (<10µA)
PEAK
put logic interface. This device is ideal for systems where
the ground loop is broken, allowing for a large common
mode voltage range. Communication is uninterrupted for
common mode transients greater than 30kV/μs.
Low Profile (15mm × 11.25mm × 3.42mm)
BGA Package
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks
and Easy Drive, Hot Swap, SoftSpan and TimerBlox are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners.
applicaTions
2
n
Isolated SPI or I C Interfaces
n
Industrial Systems
Test and Measurement Equipment
n
n
Breaking Ground Loops
Typical applicaTion
Isolated 4MHz SPI Interface
LTM2883-5S
V
CC2
LTM2883 Operating Through 35kV/µs CM Transient
5V AT 20mA
V
CC
AV
5V
CC2
SCK
SD0
SCK2 = SD02
+
V
V
L
12.5V AT 20mA
–12.5V AT 15mA
+
AV
V
ON
–
–
2V/DIV
2V/DIV
AV
SDOE
CS
CS2
SDI2
SCK2
REPETITIVE
COMMON MODE
TRANSIENTS
CS
SDI
CS
SDI
SDI
SCK
SCK
SCK
DO2
SDO
DO1
I2
SDO2
I1
200V/DIV
SDO
SDO
2883 TA01b
20ns/DIV
GND
GND2
2883 TA01a
2883f
1
LTM2883
absoluTe MaxiMuM raTings
(Note 1)
V
to GND .................................................. –0.3V to 6V
Logic Outputs
CC
V to GND .................................................... –0.3V to 6V
L
DO1, DO2, SDO to GND ..............–0.3V to (V + 0.3V)
L
+
V
, AV , AV to GND2 ........................... –0.3V to 6V
O1, SCK2, SDI2, CS2,
SCL2 to GND2 ........................–0.3V to (V
Operating Temperature Range (Note 4)
CC2
CC2
+
V to GND2 ................................................ –0.3V to 16V
+ 0.3V)
CC2
–
–
V , AV to GND2 .........................................0.3V to –16V
Logic Inputs
LTM2883C .........................................0°C ≤ T ≤ 70°C
A
A
DI1, SCK, SDI, CS, SCL, SDA, SDOE,
LTM2883I ..................................... –40°C ≤ T ≤ 85°C
ON to GND..................................–0.3V to (V + 0.3V)
LTM2883H...................................–40°C ≤ T ≤ 105°C
L
A
I1, I2, SDA2,
SDO2 to GND2........................–0.3V to (V
Maximum Internal Operating Temperature............ 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Body Reflow Temperature ............................ 245°C
+ 0.3V)
CC2
pin conFiguraTion
LTM2883-I
LTM2883-S
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
DO2 DNC SCL SDA DI1 GND ON
V
L
SDO DO2 SCK SDI CS SDOE ON
V
L
A
B
C
D
E
F
A
B
C
D
E
F
DO1
GND
V
DO1
GND
V
CC
CC
G
H
J
G
H
J
–
+
–
+
I1
GND2
AV
AV
AV
I1
GND2
AV
AV
AV
CC2
CC2
K
L
K
L
–
+
–
+
I2 DNC SCL2 SDA2 O1
BGA PACKAGE
V
V
V
SDO2 I2 SCK2 SDI2 CS2
V
V
V
CC2
CC2
BGA PACKAGE
32-PIN (15mm × 11.25mm × 3.42mm)
32-PIN (15mm × 11.25mm × 3.42mm)
T
= 125°C, θ = 30°C/W, θ = 15.7°C/W,
T
= 125°C, θ = 30°C/W, θ
= 15.7°C/W,
JMAX
JA
JC(BOTTOM)
= 14.5°C/W
JMAX
JA
JC(BOTTOM)
= 14.5°C/W
θ
= 25°C/W, θ
θ
= 25°C/W, θ
JC(TOP)
JBOARD
JC(TOP)
JBOARD
θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g
θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g
2883f
2
LTM2883
orDer inForMaTion
LTM2883 C
Y
-3
S
#PBF
LEAD FREE DESIGNATOR
PBF = Lead Free
LOGIC OPTION
2
I = Inter-IC (I C) Bus
S = Serial Peripheral Interface (SPI) Bus
INPUT VOLTAGE RANGE
3 = 3V to 3.6V
5 = 4.5V to 5.5V
PACKAGE TYPE
Y = Ball Grid Array (BGA)
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
H = Automotive Temperature Range (–40°C to 105°C)
PRODUCT PART NUMBER
proDucT selecTion guiDe
PART NUMBER
LTM2883-3I
LTM2883-3S
LTM2883-5I
LTM2883-5S
PART MARKING*
LTM2883Y-3I
LTM2883Y-3S
LTM2883Y-5I
LTM2883Y-5S
PACKAGE
INPUT VOLTAGE
3V to 3.6V
LOGIC OPTION
2
BGA
Inter-IC Bus (I C)
BGA
3V to 3.6V
Serial Peripheral Interface Bus (SPI)
2
BGA
4.5V to 5.5V
4.5V to 5.5V
Inter-IC Bus (I C)
BGA
Serial Peripheral Interface Bus (SPI)
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
This product is moisture sensitive. For more information go to: http://www.linear.com/packaging/
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ LTM2883-3 VCC = 3ꢀ3V, LTM2883-5 VCC = 5V, VL = 3ꢀ3V, and GND =
GND2 = 0V, ON = VL unless otherwise notedꢀ Specifications apply to all options unless otherwise notedꢀ
SYMBOL PARAMETER
Input Supplies
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Input Supply Range
Logic Supply Range
Input Supply Current
LTM2883-3
LTM2883-5
3
3.3
5
3.6
5.5
V
V
CC
4.5
l
l
V
L
LTM2883-S
LTM2883-I
1.62
3
5.5
5.5
V
V
5
l
l
l
I
I
ON = 0V
0
25
19
10
35
28
µA
mA
mA
CC
LTM2883-3, ON = V , No Load
L
L
LTM2883-5, ON = V , No Load
l
Logic Supply Current
ON = 0V
0
10
10
µA
µA
µA
L
LTM2883-S, ON = V
L
L
LTM2883-I, ON = V
150
2883f
3
LTM2883
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ LTM2883-3 VCC = 3ꢀ3V, LTM2883-5 VCC = 5V, VL = 3ꢀ3V, and GND =
GND2 = 0V, ON = VL unless otherwise notedꢀ Specifications apply to all options unless otherwise notedꢀ
SYMBOL PARAMETER
Output Supplies
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
Regulated Output Voltage
Output Voltage Operating Range
Line Regulation
No Load
(Note 2)
4.75
3
5
5.25
5.5
V
V
CC2
l
l
l
I
I
I
I
I
= 1mA, MIN ≤ V ≤ MAX
25
8
100
80
mV
mV
mV
LOAD
LOAD
LOAD
LOAD
LOAD
CC
Load Regulation
= 100µA to 20mA
= 100µA to 20mA
= 20mA (Note 2)
= 20mA (Note 2)
= 0V
ADJ Pin Voltage
585
600
1
615
Voltage Ripple
mV
RMS
Efficiency
45
45
%
I
Output Short Circuit Current
Current Limit
V
mA
mA
V
CC2
CC2
l
l
l
l
l
ΔV
= –5%
20
12
CC2
+
V
Regulated Output Voltage
Line Regulation
No Load
12.5
5
13
30
I
I
I
I
I
= 1mA, MIN ≤ V ≤ MAX
mV
mV
mV
LOAD
LOAD
LOAD
LOAD
CC
Load Regulation
= 100µA to 20mA
= 100µA to 20mA
= 20mA (Note 2)
= 20mA (Note 2)
200
1.260
ADJ Pin Voltage
1.170
1.220
3
Voltage Ripple
mV
RMS
Efficiency
45
%
LOAD
+
+
I
Output Short Circuit Current
Current Limit
V = 0V
70
mA
mA
V
+
l
l
l
ΔV = –0.5V
20
–
V
Regulated Output Voltage
Line Regulation
No Load
–12
–12.5
4
–13
15
I
= –1mA, MIN ≤ V ≤ MAX
mV
LOAD
CC
Load Regulation
I
I
= 100µA to 15mA
35
mV
mV
LOAD
LOAD
l
l
= 100µA to 15mA, H-Grade
35
–1.220
2
150
ADJ Pin Voltage
Voltage Ripple
I
I
I
= 100µA to 15mA
= 15mA (Note 2)
= 15mA (Note 2)
–1.184
10
–1.256
mV
LOAD
LOAD
mV
RMS
Efficiency
45
%
LOAD
–
–
I
Output Short-Circuit Current
Current Limit
V = 0V
30
mA
mA
–
+
l
ΔV = 0.5V, V = 1.5mA
15
Logic/SPI
l
l
l
V
ITH
Input Threshold Voltage
ON, DI1, SDOE, SCK, SDI, CS 1.62V ≤ V < 2.35V
0.25 • V
0.33 • V
0.75 • V
0.67 • V
V
V
V
L
L
L
L
L
ON, DI1, SDOE, SCK, SDI, CS 2.35V ≤ V
L
I1, I2, SDO2
0.33 • V
0.67 • V
CC2
CC2
l
I
Input Current
1
µA
mV
V
INL
V
V
Input Hysteresis
Output High Voltage
(Note 2)
150
HYS
OH
l
DO1, DO2, SDO
V – 0.4
L
I
I
= –1mA, 1.62V ≤ V < 3V
= –4mA, 3V ≤ V ≤ 5.5V
LOAD
LOAD
L
L
l
l
O1, SCK2, SDI2, CS2, I
= –4mA
V
CC2
– 0.4
V
V
LOAD
V
Output Low Voltage
Short-Circuit Current
DO1, DO2, SDO
0.4
OL
I
I
= 1mA, 1.62V ≤ V < 3V
LOAD
LOAD
L
= 4mA, 3V ≤ V ≤ 5.5V
L
l
l
O1, SCK2, SDI2, CS2, I
= 4mA
0.4
85
V
LOAD
I
0V ≤ (DO1, DO2, SDO) ≤ V
0V ≤ (O1, SCK2, SDI2, CS2) ≤ V
mA
mA
SC
L
60
CC2
2883f
4
LTM2883
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ LTM2883-3 VCC = 3ꢀ3V, LTM2883-5 VCC = 5V, VL = 3ꢀ3V, and GND =
GND2 = 0V, ON = VL unless otherwise notedꢀ Specifications apply to all options unless otherwise notedꢀ
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C
l
l
V
Low Level Input Voltage
High Level Input Voltage
SCL, SDA
SDA2
0.3 • V
V
V
IL
L
0.3 • V
CC2
l
l
V
SCL, SDA
SDA2
0.7 • V
V
V
IH
L
0.7 • V
CC2
l
I
Input Current
SCL, SDA = V or 0V
1
µA
INL
L
V
V
V
Input Hysteresis
SCL, SDA
SDA2
0.05 • V
mV
mV
HYS
L
0.05 • V
CC2
l
l
Output High Voltage
Output Low Voltage
SCL2, I
= –2mA
V
– 0.4
CC2
L
V
V
OH
LOAD
DO2, I
= –2mA
V – 0.4
LOAD
l
l
l
l
l
SDA, V = 3V, I
= 3mA
= 2mA
0.4
0.4
0.4
0.45
0.55
V
V
V
V
V
OL
L
LOAD
LOAD
= 2mA
DO2, V = 3V, I
L
SCL2, I
LOAD
SDA2, No Load, SDA = 0V, 4.5V ≤ V
< 5.5V
CC2
CC2
SDA2, No Load, SDA = 0V, 3V < V
< 4.5V
0.3
l
C
C
Input Pin Capacitance
Bus Capacitive Load
SCL, SDA, SDA2 (Note 2)
10
pF
IN
B
l
l
l
l
SCL2, Standard Speed (Note 2)
SCL2, Fast Speed
SDA, SDA2, SR ≥ 1V/μs, Standard Speed (Note 2)
SDA, SDA2, SR ≥ 1V/μs, Fast Speed
400
200
400
200
pF
pF
pF
pF
l
l
Minimum Bus Slew Rate
Short-Circuit Current
SDA, SDA2
1
V/µs
I
SDA2 = 0, SDA = V
100
mA
mA
mA
mA
mA
SC
L
0V ≤ SCL2 ≤ V
30
30
CC2
L
0V ≤ DO2 ≤ V
SDA = 0, SDA2 = V
6
CC2
SDA = V , SDA2 = 0
–1.8
L
ESD (HBM) (Note 2)
Isolation Boundary
+
–
(V , V , V , GND2) to (V , V , GND)
10
kV
CC2
CC
L
swiTching characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ LTM2883-3 VCC = 3ꢀ3V, LTM2883-5 VCC = 5V, VL = 3ꢀ3V, and GND =
GND2 = 0V, ON = VL unless otherwise notedꢀ Specifications apply to all options unless otherwise notedꢀ
SYMBOL PARAMETER
Logic
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Maximum Data Rate
10
35
MHz
ns
Ix → DOx, C = 15pF (Note 3)
L
t
t
, t
Propagation Delay
Rise Time
C = 15pF (Figure 1)
L
60
100
PHL PLH
l
l
C = 15pF (Figure 1)
3
20
12.5
35
ns
ns
R
L
LTM2883-I, DO2, C = 15pF (Figure 1)
L
l
l
t
F
Fall Time
C = 15pF (Figure 1)
3
20
12.5
35
ns
ns
L
LTM2883-I, DO2, C = 15pF (Figure 1)
L
SPI
l
l
Maximum Data Rate
Bidirectional Communication (Note 3)
Unidirectional Communication (Note 3)
4
8
MHz
MHz
l
t
t
, t
Propagation Delay
C = 15pF (Figure 1)
35
60
100
50
ns
ns
PHL PLH
L
Output Pulse Width Uncertainty
SDI2, CS2 (Note 2)
–20
PWU
2883f
5
LTM2883
swiTching characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ LTM2883-3 VCC = 3ꢀ3V, LTM2883-5 VCC = 5V, VL = 3ꢀ3V, and GND =
GND2 = 0V, ON = VL unless otherwise notedꢀ Specifications apply to all options unless otherwise notedꢀ
SYMBOL PARAMETER
CONDITIONS
C = 15pF (Figure 1)
MIN
TYP
3
MAX
12.5
12.5
50
UNITS
ns
l
l
l
l
t
t
t
t
Rise Time
R
F
L
Fall Time
C = 15pF (Figure 1)
L
3
ns
, t
Output Enable Time
Output Disable Time
ns
SDOE = ↓, R = 1kΩ, C = 15pF (Figure 2)
PZH PZL
L
L
, t
50
ns
SDOE = ↑, R = 1kΩ, C = 15pF (Figure 2)
PHZ PLZ
L
L
2
I C
l
Maximum Data Rate
Propagation Delay
(Note 3)
SCL → SCL2, C = 15pF (Figure 1)
400
–20
kHz
l
l
l
t
, t
150
150
200
225
250
350
ns
ns
ns
PHL PLH
L
SDA → SDA2, R = Open, C = 15pF (Figure 3)
L
L
SDA2 → SDA, R = 1.1kΩ, C = 15pF (Figure 3)
L
L
t
t
t
Output Pulse Width Uncertainty
Data Hold Time
SDA, SDA2 (Note 2)
50
ns
ns
PWU
HD;DAT
R
(Note 2)
600
Rise Time
SDA2, C = 200pF (Figure 3)
40
40
40
250
300
250
250
ns
ns
ns
ns
L
l
l
l
SDA2, C = 200pF (Figure 3)
L
SDA, R = 1.1kΩ, C = 200pF (Figure 3)
L
L
SCL2, C = 200pF (Figure 1)
L
l
l
l
t
t
Fall Time
SDA2, C = 200pF (Figure 3)
40
40
250
250
250
ns
ns
ns
F
L
SDA, R = 1.1kΩ, C = 200pF (Figure 3)
L
L
SCL2, C = 200pF (Figure 1)
L
l
Pulse Width of Spikes
Suppressed by Input Filter
0
50
ns
SP
Power Supply
Power-Up Time
l
l
l
0.6
0.6
0.6
2
2
2.5
ms
ms
ms
ON = ↑ to V
(Min)
CC2
+
–
ON = ↑ to V (Min)
ON = ↑ to V (Min)
isolaTion characTerisTics TA = 25°Cꢀ
SYMBOL PARAMETER
CONDITIONS
MIN
2500
4400
30
TYP
MAX
UNITS
V
Rated Dielectric Insulation Voltage
1 Minute, Derived from 1 Second Test
1 Second (Note 5)
V
RMS
ISO
V
Common Mode Transient Immunity
Maximum Working Insulation Voltage
LTM2883-3 V = 3.3V, LTM2883-5 V = 5V,
kV/µs
CC
CC
V = ON = 3.3V, V = 1kV, Δt = 33ns (Note 2)
L
CM
V
(Notes 2, 5)
560
400
V
PEAK
IORM
V
RMS
Partial Discharge
V
= 1050V
(Notes 2, 5)
PEAK
5
pC
PD
9
Input to Output Resistance
Input to Output Capacitance
Creepage Distance
(Notes 2, 5)
(Notes 2, 5)
(Note 2)
10
Ω
pF
6
9.48
mm
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: This module includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above specified maximum operating junction
temperature may result in device degradation or failure.
Note 2: Guaranteed by design and not subject to production test.
Note 5: Device considered a 2-terminal device. Pin group A1 through B8
shorted together and pin group K1 through L8 shorted together.
Note 3: Maximum data rate is guaranteed by other measured parameters
and is not tested directly.
2883f
6
LTM2883
TA = 25°C, LTM2883-3 VCC = 3ꢀ3V,
Typical perForMance characTerisTics
LTM2883-5 VCC = 5V, VL = 3ꢀ3V, GND = GND2 = 0V, ON = VL unless otherwise notedꢀ
VCC Supply Current
vs Temperature
Isolated Supplies
Isolated Supplies
vs Equal Load Current
vs Equal Load Current
30
25
20
15
10
14
12
10
8
14
12
10
8
NO LOAD, REFRESH DATA ONLY
LTM2883-3
= 3.3V
LTM2883-5
V
V
CC
= 5V
CC
LTM2883-3
= 3.3V
V
CC
LTM2883-5
V
= 5V
CC
6
6
4
4
V
V
V
V
V
V
CC2
+
–
CC2
+
–
2
2
0
0
–50 –25
0
25
50
75 100 125
0
5
10
15
20
25
0
5
10
15
20
25
30
TEMPERATURE (°C)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2883 G01
2883 G02
2883 G03
VCC2 Line Regulation
vs Load Current
V+ Line Regulation
vs Load Current
V– Line Regulation
vs Load Current
6.0
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
–9.0
–9.5
LTM2883-3
LTM2883-3
CC2
LTM2883-3
+
+
–
–
I
= I = 0A
I
= I = 0A
I
= I = 0A
CC2
5.5
5.0
4.5
4.0
3.5
3.0
2.5
–10.0
–10.5
–11.0
–11.5
–12.0
–12.5
–13.0
V
CC
V
CC
V
CC
V
CC
= 3V
= 3.15V
= 3.3V
= 3.6V
V
CC
V
CC
V
CC
V
CC
= 3V
= 3.15V
= 3.3V
= 3.6V
V
V
V
= 3V
= 3.3V
= 3.6V
CC
CC
CC
9.0
0
10
20
30
40
0
10
20
30
40
50
60
0
10
20
30
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2883 G04
2883 G05
2883 G06
VCC2 Line Regulation
vs Load Current
V+ Line Regulation
vs Load Current
V– Line Regulation
vs Load Current
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
–9.0
–9.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
LTM2883-5
–
LTM2883-5
+
LTM2883-5
+
–
I
= I = 0A
I
= I = 0A
I
= I = 0A
CC2
CC2
–10.0
–10.5
–11.0
–11.5
–12.0
–12.5
–13.0
V
CC
V
CC
V
CC
V
CC
= 4.5V
= 4.75V
= 5V
= 5.5V
V
CC
V
CC
V
CC
V
CC
= 4.5V
= 4.75V
= 5V
V
= 4.5V
= 5V
= 5.5V
CC
CC
CC
V
= 5.5V
V
9.0
0
10
20
30
40
50
60
0
10
20
30
40
0
10
20
30
40
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2883 G08
2883 G09
2883 G07
2883f
7
LTM2883
TA = 25°C, LTM2883-3 VCC = 3ꢀ3V,
Typical perForMance characTerisTics
LTM2883-5 VCC = 5V, VL = 3ꢀ3V, GND = GND2 = 0V, ON = VL unless otherwise notedꢀ
V+ Load Regulation
V– Load Regulation
vs Temperature
VCC2 Load Regulation
vs Temperature
vs Temperature
12.8
12.7
12.6
12.5
12.4
12.3
12.2
5.20
5.15
5.10
5.05
5.00
4.95
4.90
–12.2
+
–
–
I
I
I
I
I
= 1mA
LTM2883-3
I
I
= 1mA
= 15mA
LTM2883-3
+
+
+
+
= 5mA
V
= 3.3V
V
CC2
= 3.3V
CC
CC
+
–
+
= 10mA
= 15mA
= 20mA
I
= I = 0A
–12.3
–12.4
–12.5
–12.6
–12.7
–12.8
I
= I = 0A
LTM2883-3
V
I
= 3.3V
I
I
= 1mA
= 20mA
CC
CC2
CC2
CC2
–
= I = 0A
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2883 G12
2883 G10
2883 G14
V+ Load Regulation
vs Temperature
VCC2 Load Regulation
vs Temperature
V– Load Regulation
vs Temperature
5.20
5.15
5.10
5.05
5.00
4.95
4.90
12.7
12.6
12.5
12.4
12.3
12.2
12.1
–12.2
–12.3
–12.4
–12.5
–12.6
+
–
–
LTM2883-5
I
I
I
I
I
= 1mA
I
I
= 1mA
= 20mA
LTM2883-5
+
+
+
+
V
= 5V
= 5mA
V
CC2
= 5V
CC
CC
+
–
+
I
= I = 0A
= 10mA
= 15mA
= 20mA
I
= I = 0A
LTM2883-5
I
I
= 1mA
= 20mA
V
I
= 5V
CC2
CC2
CC
CC2
–
= I = 0A
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2883 G11
2883 G13
2883 G15
VCC2 Voltage and ICC Current
vs Load Current
VCC2 Efficiency
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0
6
5
4
3
2
1
0
150
125
100
75
+
–
LTM2883-3, V = 3.3V
CC
LTM2883-5, V = 5V
CC
I
= I = 0A
VOLTAGE
EFFICIENCY
I
CURRENT
CC
50
POWER LOSS
25
LTM2883-3, V = 3.3V
CC
+
–
LTM2883-5, V = 5V
CC
I
= I = 0A
40
0
0
10
20
30
0
10
20
30
40
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2883 G16
2883 G17
2883f
8
LTM2883
TA = 25°C, LTM2883-3 VCC = 3ꢀ3V,
Typical perForMance characTerisTics
LTM2883-5 VCC = 5V, VL = 3ꢀ3V, GND = GND2 = 0V, ON = VL unless otherwise notedꢀ
V+ Voltage and ICC Current
vs Load Current
V+ Efficiency
60
50
40
30
20
10
0
1.2
1.0
0.8
0.6
0.4
0.2
0
14
12
10
8
350
300
250
200
150
100
50
–
LTM2883-3, V = 3.3V
LTM2883-5, V = 5V
I
= I = 0A
CC
CC
CC2
VOLTAGE
EFFICIENCY
I
CC
CURRENT
6
POWER LOSS
4
2
LTM2883-3, V = 3.3V
CC
LTM2883-5, V = 5V
CC
–
I
= I = 0A
CC2
0
0
0
10
20
30
40
50
0
10
20
30
40
50
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2883 G18
2883 G19
V– Voltage and ICC Current
vs Load Current
V– Efficiency
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0
–9.0
–9.5
320
280
240
200
160
120
80
LTM2883-3, V = 3.3V
LTM2883-5, V = 5V
CC
LTM2883-3, V = 3.3V
CC
LTM2883-5, V = 5V
CC
CC
–10.0
–10.5
–11.0
–11.5
–12.0
–12.5
–13.0
EFFICIENCY
I
CURRENT
CC
POWER LOSS
40
VOLTAGE
20
0
0
10
20
30
0
10
30
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2883 G20
2883 G21
VCC2 Transient Response
20mA Load Step
V+ Transient Response
20mA Load Step
V– Transient Response
20mA Load Step
+
I
= 1.5mA
+
–
V
V
V
CC2
100mV/DIV
200mV/DIV
200mV/DIV
+
I
–
I
I
CC2
10mA/DIV
10mA/DIV
10mA/DIV
2883 G22
2883 G23
2883 G24
100µs/DIV
100µs/DIV
100µs/DIV
2883f
9
LTM2883
TA = 25°C, LTM2883-3 VCC = 3ꢀ3V,
Typical perForMance characTerisTics
LTM2883-5 VCC = 5V, VL = 3ꢀ3V, GND = GND2 = 0V, ON = VL unless otherwise notedꢀ
VCC2 Ripple
V+ Ripple
V– Ripple
+
–
I
= 1mA
I
= 1mA
2mV/DIV
5mV/DIV
5mV/DIV
+
–
I
= 20mA
I
= 20mA
2883 G25
2883 G26
2883 G27
500ns/DIV
500ns/DIV
500ns/DIV
V
CC2 Noise
V+ Noise
V– Noise
2mV/DIV
2mV/DIV
2mV/DIV
2883 G28
2883 G29
2883 G30
1ms/DIV
1ms/DIV
1ms/DIV
VCC Supply Current
vs Single Channel Data Rate
Logic Input Threshold
vs VL Supply Voltage
Logic Output Voltage
vs Load Current
70
60
50
40
30
20
10
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6.0
5.0
4.0
3.0
2.0
1.0
0
C
C
C
C
= 1nF
V
CC2
= 5V
L
L
L
L
CC
+
–
= 330pF
= 100pF
= 20pF
I
= I = I = 0
V
V
V
= 5.5V
= 3.3V
= 1.62V
L
L
L
INPUT RISING
INPUT FALLING
1k
10k
100k
1M
10M
100M
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
DATA RATE (Hz)
V
SUPPLY VOLTAGE (V)
LOAD CURRENT (mA)
L
2883 G31
2883 G32
2883 G33
2883f
10
LTM2883
TA = 25°C, LTM2883-3 VCC = 3ꢀ3V,
Typical perForMance characTerisTics
LTM2883-5 VCC = 5V, VL = 3ꢀ3V, GND = GND2 = 0V, ON = VL unless otherwise notedꢀ
VCC2 Cross Regulation
vs V+, V– Load
Power On Sequence
5.2
14
13
12
11
10
9
LTM2883-3
ON
V
= 3.3V
CC
CC2
+
I
= 15mA
V
5.1
V
CC2
5V/DIV
5.0
4.9
4.8
8
–
V
V
V
V
CC2
+
–
7
6
2883 G34
200µs/DIV
0
10
20
30
40
LOAD CURRENT (mA)
2883 G35
VCC2 Cross Regulation
vs V+, V– Load
Isolated Supply Efficiency with
Equal Load Current
5.2
5.1
5.0
4.9
4.8
14
13
12
11
10
9
60
50
40
30
20
10
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
LTM2883-5
V
I
= 5V
CC
CC2
= 15mA
EFFICIENCY
8
POWER LOSS
V
CC2
+
7
LTM2883-3, V = 3.3V
CC
LTM2883-5, V = 5V
CC
V
–
V
6
0
10
20
30
40
0
5
10
15
20
25
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2883 G36
2883 G37
V+ Cross Regulation vs V– Load
V+ Cross Regulation vs V– Load
14
13
12
11
10
9
14
13
12
11
10
9
LTM2883-3
LTM2883-5
V = 5V
CC
V
= 3.3V
CC
8
8
+ +
+
–
+
+
+
+
V , I = 10mA
V , I = 10mA
– +
V , I = 10mA
V , I = 10mA
+
+ +
7
7
V , I = 15mA
V , I = 15mA
–
– +
V , I = 15mA
10
LOAD CURRENT (mA)
V , I = 15mA
10 15
LOAD CURRENT (mA)
6
6
0
5
15
20
25
0
5
20
25
30
35
2883 G38
2883 G39
2883f
11
LTM2883
pin FuncTions (LTM2883-I)
Logic Side
The logic state on I2 translates to the same logic state on
DO2. Do not float.
DO2(A1):DigitalOutput,ReferencedtoV andGND.Logic
L
DNC (L2): Do Not Connect Pin. Pin connected internally.
output connected to I2 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
2
SCL2 (L3): Serial I C Clock Output, Referenced to V
CC2
and GND2. Logic output connected to logic side SCL pin
through isolation barrier. Clock is unidirectional from logic
to isolated side. SCL2 has a push-pull output stage, do not
connect an external pull-up device. Under the condition of
an isolation communication failure this output defaults to
a high state.
DNC (A2): Do Not Connect Pin. Pin connected internally.
2
SCL (A3): Serial I C Clock Input, Referenced to V and
L
GND. Logic input connected to isolated side SCL2 pin
throughisolationbarrier. Clockisunidirectionalfromlogic
to isolated side. Do not float.
2
SDA2 (L4): Serial I C Data Pin, Referenced to V
and
CC2
2
SDA (A4): Serial I C Data Pin, Referenced to V and GND.
L
GND2. Bidirectional logic pin connected to logic side SDA
pin through isolation barrier. Output is biased high by a
1.8mA current source. Do not connect an external pull-
up device to SDA2. Under the condition of an isolation
communication failure this output defaults to a high state.
BidirectionallogicpinconnectedtoisolatedsideSDA2pin
through isolation barrier. Under the condition of an isola-
tion communication failure this pin is in a high impedance
state. Do not float.
DI1 (A5): Digital Input, Referenced to V and GND. Logic
L
O1 (L5): Digital Output, Referenced to V
and GND2.
CC2
input connected to O1 through isolation barrier. The logic
state on DI1 translates to the same logic state on O1. Do
not float.
Logic output connected to DI1 through isolation barrier.
Under the condition of an isolation communication failure
O1 defaults to a high state.
GND (A6, B2 to B6): Circuit Ground.
V
(L6): 5V Nominal Isolated Supply Voltage. Internally
CC2
generated from V by an isolated DC/DC converter and
CC
ON (A7): Enable. Enables power and data communica-
tion through the isolation barrier. If ON is high the part is
enabled and power and communications are functional
to the isolated side. If ON is low the logic side is held in
reset, all digital outputs are in a high impedance state, and
the isolated side is unpowered. Do not float.
regulated to 5V. Internally bypassed with 2.2µF.
–
V (L7):–12.5VNominalIsolatedSupplyVoltage.Internally
generated from V by an isolated DC/DC converter and
CC
regulated to –12.5V. Internally bypassed with 1µF.
+
V (L8):12.5VNominalIsolatedSupplyVoltage.Internally
V (A8): Logic Supply. Interface supply voltage for pins
generated from V by an isolated DC/DC converter and
L
CC
DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is
regulated to 12.5V. Internally bypassed with 1µF.
3V to 5.5V. Internally bypassed with 2.2µF.
I1 (K1): Digital Input, Referenced to V
and GND2.
CC2
DO1(B1):DigitalOutput,ReferencedtoV andGND.Logic
Logic input connected to DO1 through isolation barrier.
The logic state on I1 translates to the same logic state on
DO1. Do not float.
L
output connected to I1 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
GND2 (K2 to K5): Isolated Ground.
V
(B7 to B8): Supply Voltage. Operating voltage is 3V
CC
AV
(K6): 5V Nominal Isolated Supply Voltage Adjust.
CC2
to 3.6V for LTM2883-3 and 4.5V to 5.5V for LTM2883-5.
The adjust pin voltage is 600mV referenced to GND2.
Internally bypassed with 2.2µF.
–
AV (K7): –12.5V Nominal Isolated Supply Voltage Adjust.
The adjust pin voltage is –1.22V referenced to GND2.
Isolated Side
+
AV (K8): 12.5V Nominal Isolated Supply Voltage Adjust.
The adjust pin voltage is 1.22V referenced to GND2.
I2 (L1): Digital Input, Referenced to V
Logic input connected to DO2 through isolation barrier.
and GND2.
CC2
2883f
12
LTM2883
pin FuncTions (LTM2883-S)
Logic Side
Isolated Side
SDO2 (L1): Serial SPI Digital Input, Referenced to V
SDO (A1): Serial SPI Digital Output, Referenced to V
CC2
L
and GND2. Logic input connected to logic side SDO pin
through isolation barrier. Do not float.
and GND. Logic output connected to isolated side SDO2
pin through isolation barrier. Under the condition of an
isolation communication failure this output is in a high
impedance state.
I2 (L2): Digital Input, Referenced to V
and GND2.
CC2
Logic input connected to DO2 through isolation barrier.
The logic state on I2 translates to the same logic state on
DO2. Do not float.
DO2(A2):DigitalOutput,ReferencedtoV andGND.Logic
L
output connected to I2 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
SCK2 (L3): Serial SPI Clock Output, Referenced to V
CC2
and GND2. Logic output connected to logic side SCK pin
throughisolationbarrier.Undertheconditionofanisolation
communication failure this output defaults to a low state.
SCK (A3): Serial SPI Clock Input, Referenced to V and
L
GND. Logic input connected to isolated side SCK2 pin
through isolation barrier. Do not float.
SDI2 (L4): Serial SPI Data Output, Referenced to V
CC2
and GND2. Logic output connected to logic side SDI pin
throughisolationbarrier.Undertheconditionofanisolation
communication failure this output defaults to a low state.
SDI(A4):SerialSPIDataInput,ReferencedtoV andGND.
L
Logic input connected to isolated side SDI2 pin through
isolation barrier. Do not float.
CS2 (L5): Serial SPI Chip Select, Referenced to V
and
CC2
CS(A5):SerialSPIChipSelect,ReferencedtoV andGND.
L
GND2.LogicoutputconnectedtologicsideCSpinthrough
isolation barrier. Under the condition of an isolation com-
munication failure this output defaults to a high state.
Logic input connected to isolated side CS2 pin through
isolation barrier. Do not float.
SDOE (A6): Serial SPI Data Output Enable, Referenced to
V
(L6): 5V Nominal Isolated Supply Voltage. Internally
CC2
V and GND. A logic high on SDOE places the logic side
L
generated from V by an isolated DC/DC converter and
CC
SDO pin in a high impedance state, a logic low enables
regulated to 5V. Internally bypassed with 2.2µF.
the output. Do not float.
–
V (L7):–12.5VNominalIsolatedSupplyVoltage.Internally
ON (A7): Enable. Enables power and data communica-
tion through the isolation barrier. If ON is high the part is
enabled and power and communications are functional
to the isolated side. If ON is low the logic side is held in
reset, all digital outputs are in a high impedance state, and
the isolated side is unpowered. Do not float.
generated from V by an isolated DC/DC converter and
CC
regulated to –12.5V. Internally bypassed with 1µF.
+
V (L8):12.5VNominalIsolatedSupplyVoltage.Internally
generated from V by an isolated DC/DC converter and
CC
regulated to 12.5V. Internally bypassed with 1µF.
I1 (K1): Digital Input, Referenced to V
and GND2.
V (A8): Logic Supply. Interface supply voltage for pins
CC2
L
Logic input connected to DO1 through isolation barrier.
The logic state on I1 translates to the same logic state on
DO1. Do not float.
SDI, SCK, SDO, DO1, DO2, CS, and ON. Operating voltage
is 1.62V to 5.5V. Internally bypassed with 2.2µF.
DO1(B1):DigitalOutput,ReferencedtoV andGND.Logic
L
GND2 (K2 to K5): Isolated Ground.
output connected to I1 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
AV
(K6): 5V Nominal Isolated Supply Voltage Adjust.
CC2
The adjust pin voltage is 600mV Referenced to GND2.
–
GND (B2 to B6): Circuit Ground.
AV (K7): –12.5V Nominal Isolated Supply Voltage Adjust.
The adjust pin voltage is –1.22V Referenced to GND2.
V
(B7 to B8): Supply Voltage. Operating voltage is 3V
CC
+
to 3.6V for LTM2883-3 and 4.5V to 5.5V for LTM2883-5.
AV (K8): 12.5V Nominal Isolated Supply Voltage Adjust.
Internally bypassed with 2.2µF.
The adjust pin voltage is 1.22V Referenced to GND2.
2883f
13
LTM2883
block DiagraM
REG
REG
V
V
CC2
CC2
CC
110k
15k
2.2µF
2.2µF
V
L
AV
2.2µF
GND2
GND
+
V
150k
16.2k
16.2k
150k
1µF
+
AV
REG
DC/DC
CONVERTER
–
AV
1µF
ON
REG
–
V
ISOLATED
COMMUNI-
CATIONS
ISOLATED
COMMUNI-
CATIONS
DI1
O1
SDA2
SCL2
I2
INTERFACE
INTERFACE
SDA
SCL
DO2
DO1
I1
2882 BDa
LTM2883-I
REG
REG
V
V
V
CC
L
CC2
CC2
110k
15k
2.2µF
2.2µF
AV
2.2µF
GND2
GND
+
V
150k
16.2k
16.2k
150k
1µF
+
AV
REG
DC/DC
CONVERTER
–
AV
1µF
ON
REG
–
V
SDOE
CS
CS2
SDI2
SCK2
I2
ISOLATED
COMMUNI-
CATIONS
ISOLATED
COMMUNI-
CATIONS
SDI
SCK
DO2
SDO
DO1
INTERFACE
INTERFACE
SDO2
I1
2883 BDb
LTM2883-S
2883f
14
LTM2883
TesT circuiTs
V
L
INPUT
½V
L
0V
OUTPUT
t
t
PHL
PLH
C
L
INPUT
V
OH
90%
10%
10%
90%
OUTPUT
½V
CC2
V
OL
t
t
F
R
V
CC2
0V
INPUT
½V
CC2
OUTPUT
t
t
PHL
PLH
C
L
INPUT
V
OH
90%
10%
10%
90%
OUTPUT
½V
L
V
OL
t
t
F
R
2883 F01
Figure 1ꢀ Logic Timing Measurements
V
L
OR 0V
V
L
SDOE
SDO
SDO
½V
L
R
L
0V
0V
t
t
PHZ
PZH
V
OH
SDO
SDO2 OR
V
CC2
V
V
– 0.5V
+ 0.5V
OH
½V
C
L
t
L
0V
t
PLZ
SDOE
PZL
L
V
L
½V
OL
V
OL
2883 F02
Figure 2ꢀ Logic Enable/Disable Time
V
L
V
L
R
L
SDA
½V
L
0V
SDA2
t
t
PLH
PHL
C
L
SDA
V
OH
30%
70%
30%
SDA2
½V
CC2
70%
V
OL
t
t
R
F
V
L
V
CC2
0V
R
L
SDA2
SDA
½V
CC2
SDA
t
t
PLH
PHL
C
L
SDA2
V
OH
30%
70%
30%
½V
L
70%
V
OL
t
t
R
F
2883 F03
Figure 3ꢀ I2C Timing Measurements
2883f
15
LTM2883
applicaTions inForMaTion
Overview
Performance of the –12.5V supply is enhanced by loading
the 12.5V supply. A load current of 1.5mA is sufficient to
improvestaticanddynamicloadregulationcharacteristics
of the –12.5V output. The increased load allows the boost
regulatortooperatecontinuouslyandinturnimprovesthe
regulation of the inverting charge pump.
The LTM2883 digital µModule isolator provides a gal-
vanically-isolated robust logic interface, powered by an
integrated, regulated DC/DC converter, complete with
decoupling capacitors. The LTM2883 is ideal for use in
networks where grounds can take on different voltages.
Isolation in the LTM2883 blocks high voltage differences,
eliminates ground loops and is extremely tolerant of com-
mon mode transients between ground planes. Error-free
operation is maintained through common mode events
greater than 30kV/μs providing excellent noise isolation.
The internal power solution is sufficient to provide a mini-
+
and V , and 15mA
mum of 20mA of current from V
CC2
–
from V . V and V
are each bypassed with 2.2µF
ceramic capacitors, and V and V are bypassed with 1µF
CC
CC2
+
–
ceramic capacitors.
V Logic Supply
L
Isolator µModule Technology
A separate logic supply pin V allows the LTM2883 to in-
The LTM2883 utilizes isolator µModule technology to
translate signals and power across an isolation barrier.
Signals on either side of the barrier are encoded into
pulses and translated across the isolation boundary using
coreless transformers formed in the µModule substrate.
This system, complete with data refresh, error checking,
safe shutdown on fail, and extremely high common mode
immunity, provides a robust solution for bidirectional
signal isolation. The µModule technology provides the
means to combine the isolated signaling with multiple
regulators and a powerful isolated DC/DC converter in
one small package.
L
terface with any logic signal from 1.62V to 5.5V as shown
in Figure 4. Simply connect the desired logic supply to V .
L
There is no interdependency between V and V ; they
CC
L
may simultaneously operate at any voltage within their
specified operating ranges and sequence in any order. V
is bypassed internally by a 2.2µF capacitor.
L
3V TO 3.6V LTM2883-3
4.5V TO 5.5V LTM2883-5
LTM2883-S
V
CC2
CC2
V
V
CC
L
AV
+
ANY VOLTAGE FROM
1.62V TO 5.5V
V
+
AV
V
DC/DC Converter
–
–
AV
The LTM2883 contains a fully integrated DC/DC converter,
including the transformer, so that no external components
are necessary. The logic side contains a full-bridge driver,
running at 2MHz, and is AC-coupled to a single trans-
former primary. A series DC blocking capacitor prevents
transformersaturationduetodriverdutycycleimbalance.
The transformer scales the primary voltage, and is recti-
fied by a full-wave voltage doubler. This topology allows
for a single diode drop, as in a center tapped full-wave
bridge, and eliminates transformer saturation caused by
secondary imbalances.
ON
SDOE
CS
CS2
SDI2
SCK2
SDI
SCK
EXTERNAL
DEVICE
DO2
SDO
DO1
I2
SDO2
I1
GND
GND2
2883 F04
Figure 4ꢀ VCC and VL Are Independent
TheDC/DCconverterisconnectedtoalowdropoutregula-
tor (LDO) to provide a regulated 5V output.
Hot-Plugging Safely
Caution must be exercised in applications where power
or V ,
An integrated boost converter generates a regulated 14V
supply and a charge pumped –14V supply. These rails are
regulatedto 12.5Vrespectivelybylowdropoutregulators.
is plugged into the LTM2883’s power supplies, V
CC
L
due to the integrated ceramic decoupling capacitors. The
2883f
16
LTM2883
applicaTions inForMaTion
parasitic cable inductance along with the high Q char-
acteristics of ceramic capacitors can cause substantial
ringing which could exceed the maximum voltage ratings
and damage the LTM2883. Refer to Linear Technology Ap-
plication Note 88, entitled Ceramic Input Capacitors Can
Cause Overvoltage Transients for a detailed discussion
and mitigation of this phenomenon.
Table 1ꢀ Voltage Adjustment Formula
OUTPUT
VOLTAGE
RESISTOR (Ax TO Vx) TO RESISTOR (Ax TO GND2) TO
REDUCE OUTPUT
INCREASE OUTPUT
110k • V – 0.6
(
)
66k
VCC2 – 5
CC2
V
CC2
5 – VCC2
150k • V+,V– – 1.22
(
)
183k
V+,V– – 12.5
+
–
V , V
12.5 – V+,V–
Isolated Supply Adjustable Operation
The three isolated power rails may be adjusted by con-
nection of a single resistor from the adjust pin of each
output to its associated output voltage or to GND2. The
pre-configured voltages represent the maximums for
Channel Timing Uncertainty
Multiplechannelsaresupportedacrosstheisolationbound-
arybyencodinganddecodingoftheinputsandoutputs. Up
to three signals in each direction are assembled as a serial
packetandtransferredacrosstheisolationbarrier. Thetime
required to transfer all 3 bits is 100ns maximum, and sets
the limit for how often a signal can change on the opposite
side of the barrier. Encoding transmission is independent
for each data direction. The technique used assigns SCK or
SCL on the logic side, and SDO2 or I2 on the isolated side,
the highest priority such that there is no jitter on the associ-
ated output channels, only delay. This preemptive scheme
will produce a certain amount of uncertainty on the other
isolationchannels.Theresultingpulsewidthuncertaintyon
these low priority channels is typically 6ns, but may vary
up to 44ns if the low priority channels are not encoded
within the same high priority serial packet.
guaranteed performance. Figure 5 illustrates configura-
+
tion of the output power rails for V
= 3.3V, V = 10V,
CC2
–
and V = –10V.
LTM2883-5S
V
CC2
CC2
3.3V
10V
V
V
CC
L
174k
530k
530k
AV
5V
+
V
+
AV
V
ON
–
–
–10V
AV
SDOE
CS
CS2
SDI2
SCK2
SDI
SCK
DO2
SDO
DO1
I2
SDO2
I1
Serial Peripheral Interface (SPI) Bus
GND
GND2
2883 F05
The LTM2883-S provides a SPI compatible isolated inter-
face. The maximum data rate is a function of the inherent
channel propagation delays, channel to channel pulse
width uncertainty, and data direction requirements. Chan-
nel timing is detailed in Figures 5 through 8 and Tables
3 and 4. The SPI protocol supports four unique timing
configurations defined by the clock polarity (CPOL) and
clock phase (CPHA) summarized in Table 2.
Figure 5ꢀ Adjustable Voltage Rails
Todecreasetheoutputvoltagearesistormustbeconnected
from the output voltage pin to the associated adjust pin.
To increase the output voltage connect a resistor to the
adjust pin to GND2. Use the equations listed in Table 1
tocalculatetheresistancesrequiredtoadjusteachoutput.
Table 2ꢀ SPI Mode
TheoutputvoltageadjustmentrangeforV is3Vto5.5V.
CC2
CPOL CPHA
DATA TO (CLOCK) RELATIONSHIP
+
–
AdjustmentrangeforV andV is 1.22Vtoapproximately
0
0
1
1
0
1
0
1
Sample (Rising)
Set-Up (Falling)
Sample (Falling)
Set-Up (Rising)
Sample (Rising)
+
–
13.5V. Operation at low output voltages for V or V may
result in thermal shutdown due to low dropout regulator
power dissipation.
Set-Up (Rising)
Sample (Falling)
Set-Up (Falling)
2883f
17
LTM2883
applicaTions inForMaTion
The maximum data rate for bidirectional communication
is 4MHz, based on a synchronous system, as detailed in
the timing waveforms. Slightly higher data rates may be
achieved by skewing the clock duty cycle and minimiz-
ing the SDO to SCK set-up time, however the clock rate
is still dominated by the system propagation delays. A
discussion of the critical timing paths relative to Figure 6
and 7 follows.
• CS to SCK (master sample SDO, 1st SDO valid)
t
0
t
1
→ t
→ t
≈50ns, CS to CS2 propagation delay
1
Isolated slave device propagation
(response time), asserts SDO2
1+
t
t
→ t
→ t
≈50ns, SDO2 to SDO propagation delay
Set-up time for master SDO to SCK
1
3
3
5
CPHA = 0
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
SDO
INVALID
SDO2
t
0
t
t
t
t
t
5
t
6
t
7
t
9
t
10
t
t
t
t
t
t
t
1
2
3
4
11 12
13
14
15
17
18
t
8
2883 F06
Figure 6ꢀ SPI Timing, Bidirectional, CPHA = 0
CPHA = 1
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
SDO
INVALID
SDO2
t
0
t
t
t
t
t
5
t
6
t
7
t
9
t
10
t
t
t
t
t
t
t
t
1
2
3
4
11 12
13
14
15
16 17
18
t
8
2883 F07
Figure 7ꢀ SPI Timing, Bidirectional, CPHA = 1
2883f
18
LTM2883
applicaTions inForMaTion
• SDI to SCK (master data write to slave)
• SDO to SCK (master sample SDO, subsequent
SDO valid)
t
2
t
5
t
2
→ t
→ t
→ t
≈50ns, SDI to SDI2 propagation delay
≈50ns, SCK to SCK2 propagation delay
4
6
5
t
8
t
8
set-up data transition SDI and SCK
→ t
≈50ns, SDI to SDI2 and SCK to SCK2
propagation delay
10
≥50ns, SDI to SCK, separate packet
non-zero set-up time
t
10
t
10
t
11
SDO2 data transition in response to SCK2
t
4
→ t
≥50ns, SDI2 to SCK2, separate packet
non-zero set-up time
6
→ t ≈50ns, SDO2 to SDO propagation delay
11
→ t Set-up time for master SDO to SCK
12
Table 3ꢀ Bidirectional SPI Timing Event Description
TIME
CPHA
EVENT DESCRIPTION
t
0
0, 1
Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output
enabled, initial data is not equivalent to slave device data output
t to t
t
to t
18
0, 1
0, 1
0
Propagation delay chip select, logic to isolated side, 50ns typical
Slave device chip select output data enable
0
1, 17
t
1
t
2
Start of data transmission, data set-up
1
Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge
Propagation delay of slave data, isolated to logic side, 50ns typical
Slave data output valid, logic side
t to t
0, 1
0, 1
0
1
3
4
t
3
t to t
2
Propagation delay of data, logic side to isolated side
Propagation delay of data and clock, logic side to isolated side
Logic side data sample time, half clock period delay from data set-up transition
Propagation delay of clock, logic to isolated side
Isolated side data sample time
1
t
5
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0
t to t
5
6
t
6
t
8
Synchronous data and clock transition, logic side
Data to clock delay, must be ≤13ns
t to t
7
8
t to t
8
Clock to data delay, must be ≤3ns
9
t to t
8
Propagation delay clock and data, logic to isolated side
Slave device data transition
10
t
t
t
t
t
10, 14
to t
to t
t
to t
15
Propagation delay slave data, isolated to logic side
Slave data output to sample clock set-up time
10
11
13
11, 14
12
Last data and clock transition logic side
1
Last sample clock transition logic side
t
to t
0
Propagation delay data and clock, logic to isolated side
Propagation delay clock, logic to isolated side
13
15
14
1
t
0
Last slave data output transition logic side
1
Last slave data output and data transition, logic side
Propagation delay data, logic to isolated side
t
15
t
17
t
18
to t
1
16
0, 1
0, 1
Asynchronous chip select transition, end of transmission. Disable slave data output logic side
Chip select transition isolated side, slave data output disabled
2883f
19
LTM2883
applicaTions inForMaTion
Maximum data rate for single direction communication,
master to slave, is 8MHz, limited by the systems encod-
ing/decodingschemeorpropagationdelay. Timingdetails
for both variations of clock phase are shown in Figures 8
and 9 and Table 4.
• SDI and SCK set-up data transition occur within the
same data packet. Referencing Figure 6, SDI can pre-
cede SCK by up to 13ns (t → t ) or lag SCK by 3ns
7
8
(t → t ) and not violate this requirement. Similarly in
8
9
Figure 8, SDI can precede SCK by up to 13ns (t → t )
4
5
or lag SCK by 3ns (t → t ).
5
6
Additional requirements to insure maximum data rate
are:
2
Inter-IC Communication (I C) Bus
• CS is transmitted prior to (asynchronous) or within the
2
The LTM2883-I provides an I C compatible isolated inter-
face,Clock(SCL)isunidirectional,supportingmastermode
only, and data (SDA) is bidirectional. The maximum data
same (synchronous) data packet as SDI
CPHA = 0
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
t
0
t
t
t
3
t
4
t
5
t
t
t
9
t
t
12
1
2
7
8
11
t
6
2883 F08
Figure 8ꢀ SPI Timing, Unidirectional, CPHA = 0
CPHA = 1
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
t
0
t
t
t
3
t
4
t
5
t
t
t
9
t
t
t
12
1
2
7
8
10 11
t
6
2883 F09
Figure 9ꢀ SPI Timing, Unidirectional, CPHA = 1
2883f
20
LTM2883
applicaTions inForMaTion
Table 4ꢀ Unidirectional SPI Timing Event Description
TIME
CPHA
0, 1
0, 1
0
EVENT DESCRIPTION
t
Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns
Propagation delay chip select, logic to isolated side
Start of data transmission, data set-up
0
t to t
0
1
3
t
2
1
Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge
Propagation delay of data, logic side to isolated side
Propagation delay of data and clock, logic side to isolated side
Logic side data sample time, half clock period delay from data set-up transition
Clock propagation delay, clock and data transition
Data to clock delay, must be ≤13ns
t to t
2
0
1
t
3
0, 1
0, 1
0, 1
0, 1
0, 1
0
t to t
3
5
5
6
7
t to t
4
t to t
5
Clock to data delay, must be ≤3ns
t to t
5
Data and clock propagation delay
t
8
Last clock and data transition
1
Last clock transition
t to t
8
0
Clock and data propagation delay
9
1
Clock propagation delay
t to t
9
1
Data propagation delay
10
t
11
t
12
0, 1
0, 1
Asynchronous chip select transition, end of transmission
Chip select transition isolated side
2
1.8mA current source provides a pull-up for SDA2. Do not
connect any other pull-up device to SDA2. This current
source is sufficient to satisfy the system requirements for
bus capacitances greater than 200pF in FAST mode and
greater than 400pF in STANDARD mode.
rate is 400kHz which supports fast-mode I C. Timing is
detailed in Figure 10. The data rate is limited by the slave
2
acknowledge setup time (t
), consisting of the I C
SU;ACK
standardminimumsetuptime(t
)of100ns,maximum
SU;DAT
clock propagation delay of 225ns, glitch filter and isolated
data delay of 350ns maximum, and the combined isolated
and logic data fall time of 500ns at maximum bus load-
Additional proprietary circuitry monitors the slew rate on
the SDA and SDA2 signals to manage directional control
across the isolation barrier. Slew rates on both pins must
be greater than 1V/μs for proper operation.
2
ing. The total setup time reduces the I C data hold time
(t
) to a maximum of 125ns, guaranteeing sufficient
HD;DAT
data setup time (t
).
SU;ACK
The logic side bidirectional serial data pin, SDA, requires a
The isolated side bidirectional serial data pin, SDA2,
simplified schematic is shown in Figure 11. An internal
pull-up resistor or current source connected to V . Follow
L
SLAVE ACK
SDA
SDA2
SCL
1
8
9
SCL2
START
STOP
2883 F10
t
PROP
t
t
HD;DAT
t
SU;DAT
SU;ACK
Figure 10ꢀ I2C Timing Diagram
2883f
21
LTM2883
applicaTions inForMaTion
The isolated side clock pin, SCL2, has a weak push-pull
output driver; do not connect an external pull-up device.
1.8mA
GLITCH FILTER
TO
LOGIC
2
SCL2iscompatiblewithI Cdeviceswithoutclockstretch-
SIDE
SDA2
ing. On lightly loaded connections, a 100pF capacitor
from SCL2 to GND2 or RC low-pass filter (R = 500Ω C =
100pF) can be used to increase the rise and fall times and
minimize noise.
FROM
LOGIC
SIDE
2883 F11
Some consideration must be given to signal coupling
between SCL2 and SDA2. Separate these signals on a
printed circuit board or route with ground between. If
Figure 11ꢀ Isolated SDA2 Pin Schematic
the requirements in Figures 12 and 13 for the appropri-
ate pull-up resistor on SDA that satisfies the desired rise
these signals are wired off board, twist SCL2 with V
CC2
time specifications and V maximum limits for FAST and
and/or GND2 and SDA2 with GND2 and/or V , do not
OL
CC2
STANDARD modes. The resistance curves represent the
maximum resistance boundary; any value may be used
to the left of the appropriate curve.
twist SCL2 and SDA2 together. If coupling between SCL2
and SDA2 is unavoidable, place the aforementioned RC
filter at the SCL2 pin to reduce noise injection onto SDA2.
30
RF, Magnetic Field Immunity
V = 3V
V = 3.3V
25
20
15
10
5
V = 3.6V
V = 4.5V TO 5.5V
TheisolatorµModuletechnologyusedwithintheLTM2883
hasbeenindependentlyevaluated,andsuccessfullypassed
the RF and magnetic field immunity testing requirements
per European Standard EN 55024, in accordance with the
following test standards:
EN 61000-4-3
EN 61000-4-8
EN 61000-4-9
Radiated, Radio-Frequency,
Electromagnetic Field Immunity
0
Power Frequency Magnetic Field
Immunity
10
100
(pF)
1000
C
BUS
2883 F12
Pulsed Magnetic Field Immunity
Figure 12ꢀ Maximum Standard Speed Pull-Up Resistance on SDA
Tests were performed using an unshielded test card de-
signed per the data sheet PCB layout recommendations.
Specific limits per test are detailed in Table 5.
10
V = 3V
9
8
7
6
5
4
3
2
1
0
V = 3.3V
V = 3.6V
V = 4.5V TO 5.5V
Table 5ꢀ
TEST
FREQUENCY
80MHz to 1GHz
1.4MHz to 2GHz
2GHz to 2.7GHz
50Hz and 60Hz
60Hz
FIELD STRENGTH
10V/m
EN 61000-4-3 Annex D
3V/m
1V/m
EN 61000-4-8 Level 4
EN 61000-4-8 Level 5
EN 61000-4-9 Level 5
*non IEC method
30A/m
100A/m*
1000A/m
10
100
(pF)
1000
Pulse
C
BUS
2883 F13
Figure 13ꢀ Maximum Fast Speed Pull-Up Resistance on SDA
2883f
22
LTM2883
applicaTions inForMaTion
PCB Layout
anyhighfrequencydifferentialvoltagesandsubstantially
reducing radiated emissions. Discrete capacitance will
notbeaseffectiveduetoparasiticESL.Inaddition,volt-
age rating, leakage, and clearance must be considered
for component selection. Embedding the capacitance
withinthePCBsubstrateprovidesanearidealcapacitor
and eliminates component selection issues; however,
the PCB must be 4 layers. Care must be exercised in
applying either technique to insure the voltage rating
of the barrier is not compromised.
The high integration of the LTM2883 makes PCB layout
very simple. However, to optimize its electrical isolation
characteristics, EMI, and thermal performance, some
layout considerations are necessary.
• Under heavily loaded conditions V and GND current
CC
can exceed 300mA. Sufficient copper must be used
on the PCB to insure resistive losses do not cause the
supply voltage to drop below the minimum allowed
level. Similarly, the V
and GND2 conductors must
CC2
The PCB layout in Figures 14a and 14b shows the low
EMI demo board for the LTM2883. The demo board uses
a combination of EMI mitigation techniques, including
both embedded PCB bridge capacitance and discrete GND
to GND2 capacitors. Two safety rated type Y2 capacitors
are used in series, manufactured by MuRata, part number
GA342QR7GF471KW01L. The embedded capacitor ef-
fectively suppresses emissions above 400MHz, whereas
the discrete capacitors are more effective below 400MHz.
be sized to support any external load current. These
heavy copper traces will also help to reduce thermal
stress and improve the thermal conductivity.
• Inputandoutputdecouplingisnotrequired,sincethese
components are integrated within the package. An ad-
ditional bulk capacitor with a value of 6.8µF to 22µF is
recommended. The high ESR of this capacitor reduces
boardresonancesandminimizesvoltagespikescaused
by hot plugging of the supply voltage. For EMI sensitive
applications,anadditionallowESLceramiccapacitorof
1µF to 4.7µF, placed as close to the power and ground
terminals as possible, is recommended. Alternatively, a
numberofsmallervalueparallelcapacitorsmaybeused
to reduce ESL and achieve the same net capacitance.
EMI performance is shown in Figure 15, measured using
a Gigahertz Transverse Electromagnetic (GTEM) cell and
method detailed in IEC 61000-4-20, Testing and Measure-
ment Techniques – Emission and Immunity Testing in
Transverse Electromagnetic Waveguides.
• Do not place copper on the PCB between the inner col-
umnsofpads. Thisareamustremainopentowithstand
the rated isolation voltage.
• The use of solid ground planes for GND and GND2
is recommended for non-EMI critical applications to
optimize signal fidelity, thermal performance, and to
minimize RF emissions due to uncoupled PCB trace
conduction. The drawback of using ground planes,
where EMI is of concern, is the creation of a dipole
antennastructurewhichcanradiatedifferentialvoltages
formed between GND and GND2. If ground planes are
used it is recommended to minimize their area, and
use contiguous planes as any openings or splits can
exacerbate RF emissions.
• For large ground planes a small capacitance (≤330pF)
from GND to GND2, either discrete or embedded within
the substrate, provides a low impedance current return
path for the module parasitic capacitance, minimizing
TECHNOLOGY
Figure 14aꢀ LTM2883 Low EMI Demo Board Layout
2883f
23
LTM2883
applicaTions inForMaTion
Top Layer
Inner Layer 2
Inner Layer 1
Bottom Layer
Figure 14bꢀ LTM2883 Low EMI Demo Board Layout (DC1748A)
2883f
24
LTM2883
applicaTions inForMaTion
60
50
CISPR 22 CLASS B LIMIT
DC1748A-B
40
30
20
10
DC1748A-A
0
DETECTOR = QuasiPeak
RBW = 120kHz
VBW = 300kHz
SWEEP TIME = 17s
# OF POINTS = 501
–10
–20
–30
0
100 200 300 400 500 600 700 800 9001000
FREQUENCY (MHz)
2883 F15
Figure 15ꢀ LTM2883 Low EMI Demo Board Emissions
Typical applicaTions
0.1µF
12.5V
7
LTM2883-5I
0.1µF
1µF
B8
A8
L8
K8
L7
K7
L6
K6
+
+
–
–
8
12.5V
V
AV
V
5V
V
V
CC
3
2
+
L
1µF
1
8
9
1/2 LTC2055
–12.5V
5V
1.7k
–
AV
–
10
A7
A6
A5
A4
A3
A2
A1
B1
B2
4
V
ON
CC2
6
LT1991
G = 8
1.7k
10V OUT
1
2
3
AV
GND
DI1
CC2
O1
V
CC
L5
L4
L3
L2
L1
K1
K2
LTC2631A-LM12, DAC
1.25V
+
1
2
3
4
8
7
6
5
SDA2
SCL2
DNC
I2
CA0
SCL
SDA
GND
R_SEL
SDA
SCL
SDA
SCL
DNC
DO2
DO1
GND
5
2.5V F.S.
0.1µF
4
µC
V
OUT
–12.5V
REF
5
6
+
V
CC
GND
7
I1
1/2 LTC2055
GND2
2883 F16
–
0.1µF
12.5V
7
0.1µF
2.5V
LTC2301, ADC
10
11
12
1
9
8
7
6
5
4
GND
AD0 REFC
V
DD
0.1µF
8
9
–
AD1
GND
SDA
SCL
V
10µF
1µF
0.1µF
REF
–
10
IN
2
6
LT1991
G = 0.2
+
IN
1
4V F.S.
3
10V IN
GND
2
+
3
5
0.1µF
4
–12.5V
Figure 16ꢀ Isolated I2C 12-Bit, 10V Analog Input and Output
2883f
25
LTM2883
Typical applicaTions
LTM2883-3S
B8
A8
L8
K8
L7
K7
L6
K6
+
+
–
–
V
AV
V
3.3V
V
V
CC
L
10k
1nF
74VC1G123
AV
Cx
Rx/Cx
CLR
A
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
CSB
ON
CC2
CC2
AV
SDOE
CS
L5
L4
L3
L2
L1
K1
K2
1µF
CS2
SDI2
SCK2
I2
CSA
B
Q
MOSI
SCK
SDI
SCK
DO2
SDO
DO1
GND
V
CC
CSA
CSB
SDO2
I1
MISO
µC
GND2
2883 F17
MOSI
SCK
MISO
GND
CSA
CSB
MOSI
SCK
Figure 17ꢀ Isolated SPI Device Expansion
2883f
26
LTM2883
Typical applicaTions
LTM2883-5I
B8
L8
K8
L7
K7
L6
K6
+
+
–
–
V
AV
V
5V
V
V
CC
L
A8
AV
10k
10k
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
CC2
AV
GND
DI1
8.66k
137Ω
CC2
O1
10k
10k
L5
L4
L3
L2
L1
K1
K2
ENABLE
SDA
1
2
3
4
5
10
9
SDA2
SCL2
DNC
I2
SDAOUT
SCLOUT
SDA
SDA
SCL
DNC
DO2
DO1
GND
SDAIN
SCLIN
CONN
ADDR
GND
SCLIN
SCLOUT
8
LTC4302-1
V
CC
7
GPIO2
GPIO1
GPIO2
GPIO1
6
I1
GND2
2883 F18
Figure 18ꢀ Isolated I2C Buffer with Programmable Outputs
2883f
27
LTM2883
Typical applicaTions
LTM2883-5S
B8
A8
L8
K8
L7
K7
L6
K6
+
+
–
–
V
AV
V
5V
V
V
CC
L
1µF
AV
NTC THERMISTORS, MURATA NTSD1WD104, 100k
–t° –t° –t° –t°
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
CC2
CC2
AV
SDOE
CS
V
CC
L5
L4
L3
L2
L1
K1
K2
CS2
SDI2
SCK2
I2
Oz
Oy
Ox
SDI
LTC1799
SCK
DO2
SDO
DO1
GND
µC
–t°
–t°
–t°
–t°
5
4
1
2
3
+
DG4051A
X0
V
1M
OUT
16
3
13
14
15
12
1
Iy
Ix
SDO2
I1
GND
V
X
A
B
C
CC
3.01k
X1
X2
X3
X4
DIV SET
GND
11
10
9
GND2
2883 F19
6
5
ENABLE X5
7
2
V
X6
X7
EE
8
4
TEMPERATURE (°C) FREQUENCY (kHz)
GND
–40
–30
–20
–10
0
1.23
1.46
–t°
–t°
–t°
–t°
1.87
2.58
3.77
LTC1799
+
10
5.67
5
4
1
2
3
DG4051A
20
8.64
V
OUT
1M
16
3
13
14
15
12
1
–t°
–t°
–t°
–t°
30
13.09
19.53
28.47
40.65
55.87
74.45
96.08
119.83
144.73
169.36
X0
X1
X2
X3
X4
GND
V
X
A
B
C
CC
3.01k
40
DIV SET
50
11
10
9
60
70
80
90
100
110
120
6
5
ENABLE X5
7
2
V
X6
X7
EE
8
4
GND
Figure 19ꢀ 16-Channel Isolated Temperature to Frequency Converter
2883f
28
LTM2883
Typical applicaTions
IRF7509
100k
SWITCHED 12.5V
SWITCHED –12.5V
LTM2883-5S
B8
A8
L8
K8
L7
K7
L6
K6
+
+
–
–
IRF7509
V
AV
V
5V
V
V
CC
L
100k
AV
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
CC2
CC2
IRF7509
100k
AV
SDOE
CS
L5
L4
L3
L2
L1
K1
K2
IRLML2402
100k
–12.5V ENABLE
12.5V ENABLE
5V ENABLE
12.5V UV
CS2
SDI2
SCK2
I2
SWITCHED 5V
SDI
SCK
DO2
SDO
DO1
GND
226k
SDO2
I1
–12.5V UV
5V UV
GND2
2883 F20
LTC2902
COMP2
COMP1 COMP4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMP3
196k
20k
0.1µF
V3
V2
V4
V1
CRT
RST
T0
V
REF
10k
V
93.1k
9.53k
PG
GND
T1
RDIS
Figure 20ꢀ Digitally Switched Triple Power Supply with Undervoltage Monitor
2883f
29
LTM2883
Typical applicaTions
0.1µF
12.5V
7
8
9
–
+
10
6
6
6
6
LT1991
G = 8
10V OUTA
10V OUTB
10V OUTC
1
2
3
5
0.1µF
4
–12.5V
0.1µF
5V
0.1µF
0.1µF
1.25V
12.5V
LTM2883-3S
5
3
4
B8
A8
L8
K8
L7
K7
L6
K6
+
+
–
–
7
8
9
+
–
12.5V
V
AV
V
3.3V
V
V
CC
L
1
LTC2054
2
1µF
–
+
10
–12.5V
LT1991
G = 8
LTC2654-L16
AV
1
2
3
A7
A6
A5
A4
A3
A2
A1
B1
B2
15
6
5
V
REFOUT
V
CC
ON
CC2
CC2
3
AV
SDOE
CS
LDAC
CS
REFC
V
5
CC
L5
L4
L3
L2
L1
K1
K2
7
2
0.1µF
CS2
SDI2
SCK2
I2
CS
V
4
OUTA
OUTB
OUTC
OUTD
9
4
MOSI
SCK
SDI
SDI
V
V
–12.5V
8
13
14
1
SCK
DO2
SDO
DO1
GND
SCK
CLR
SDO
µC
11
10
12
V
0.1µF
MISO
SDO2
I1
REFLO
0.1µF
16
GND
12.5V
PORSEL GND
GND2
2883 F21
7
8
9
–
+
10
LT1991
G = 8
1
2
3
5
0.1µF
4
–12.5V
0.1µF
12.5V
7
8
9
–
+
10
LT1991
G = 8
10V OUTD
1
2
3
5
0.1µF
4
–12.5V
Figure 21ꢀ Quad 16-Bit 10V Output Range DAC
2883f
30
LTM2883
Typical applicaTions
LTM2883-5I
B8
A8
L8
K8
L7
K7
L6
K6
+
+
–
–
V
AV
V
5V
V
V
CC
L
1µF
10k
10k
AV
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
CC2
V
CC
AV
GND
DI1
CC2
O1
L5
L4
L3
L2
L1
K1
K2
Ox
SDA2
SCL2
DNC
I2
SDA
SCL
Ix
SDA
SCL
DNC
DO2
DO1
GND
µC
10k
GND
I1
GND2
V
EE
–48V RTN
1k, ×4 IN SERIES
1/4W EACH
453k
7
21
8
9
22
6
INTV
V
IN
FLTIN
SCL
UVL
UVH
ADIN2
OV
CC
16.9k
10
11
19
20
26
1
5
SDAI
SDAO
ALERT
ON
4
3
SS
2
LTC4261CGN
TMR
EN
28
27
23
PGI
PGI0
PG
PWRGD2
PWRGD1
25
24
ADR1
ADR0
ADIN
11.8k
V
SENSE GATE DRAIN RAMP
14 15 16 18
EE
13
+
330µF
100V
1M
1k
100nF
1µF
220nF
10Ω
47nF
V
10nF
100V
OUT
0.1µF
47nF
10k
0.1µF
–48V INPUT
IRF1310NS
0.008Ω
1%
402k
V
EE
2883 F22
Figure 22ꢀ –48V, 200W Hot Swap Controller with Isolated I2C Interface
2883f
31
LTM2883
Typical applicaTions
3.3V
LTM2883-3S
LTC6803-1
CSO
3.3k
3.3k
3.3k
B8
A8
L8
K8
L7
K7
L6
K6
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
+
+
–
–
3.3k
V
AV
V
CSI
SDO
SDI
SCKI
V
V
V
CC
L
1µF
2
SDOI
3
SCKO
4
+
AV
V
A7
A6
A5
A4
A3
A2
A1
B1
B2
5
V
C12
S12
C11
S11
C10
S10
C9
ON
CC2
CC2
MODE
6
AV
SDOE
CS
GPIO2
GPIO1
WDT
MM
V
CC
L5
L4
L3
L2
L1
K1
K2
7
1µF
1µF
CS2
SDI2
SCK2
I2
CS
8
SDI
MOSI
SCK
µC
9
SCK
DO2
SDO
DO1
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
MISO
GND
TOS
SDO2
I1
V
V
V
V
REG
100k
100k
74LVC3G07
S9
REF
GND2
2883 F23
C8
TEMP2
TEMP1
S8
NC
C7
–
V
S7
100k
100k
S1
C1
S2
C2
S3
C3
C6
S6
C5
S5
C4
S4
Figure 23ꢀ 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown
2883f
32
LTM2883
Typical applicaTions
LTM2883-3I
B8
L8
K8
L7
K7
L6
K6
+
+
–
–
0.02Ω
V
AV
V
3.3V
V
V
CC
48V
V
OUT
A8
L
1µF
10k
+
–
AV
SENSE SENSE
V
IN
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
SHDN
100k AT 25°C, 1%
VISHAY 2381 6154.104
CC2
10k
V
CC
AV
GND
DI1
CC2
O1
L5
L4
L3
L2
L1
K1
K2
SDA2
SCL2
DNC
I2
SDA
SDA
SCL
SDA
SCL
DNC
DO2
DO1
GND
ADIN
LTC4151
µC
SCL
ADR0
ADR1
1.37k
1%
GND
I1
GND2
2883 F24
GND
3950
T(°C)=
− 273,−40°C< T <150°C
1000
8.965+LN
−1
N
ADIN
N
IS THE DIGITAL CODE MEASURED
ADIN
BY THE ADC AT THE ADIN PIN
Figure 24. Isolated I2C Voltage, Current and Temperature Power Supply Monitor
2883f
33
LTM2883
Typical applicaTions
LTM2883-5I
B8
L8
K8
L7
K7
L6
K6
+
+
–
–
V
AV
V
5V
V
V
CC
A8
L
10k
0.1µF
10k
AV
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
SHUTDOWN
174k
CC2
0.1µF
AV
GND
DI1
100k
CC2
O1
SHDN1 V
DD
L5
L4
L3
L2
L1
K1
K2
ENABLE
SDA
RESET
SDAIN
SCL
BYP
SDA2
SCL2
DNC
I2
SDA
SCL
DNC
DO2
DO1
GND
SCLIN
SDAOUT
AUTO
INT
DETECT
1/4 LTC4266
INTERRUPT
I1
GND2
AD0
AD1
AD2
CMPD3003
AD3
V
DGND AGND
SENSE GATE OUT
EE
Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T
FB1, FB2: TDK MPZ2012S601A
T1: PULSE H609NL OR COILCRAFT ETH1-230LD
SMAJ58A
1µF
0.25Ω
Q1
–48V
S1B
S1B
0.22µF
FB1
FB2
RJ45
CONNECTOR
1
T1
•
•
•
•
2
3
4
5
6
7
8
10nF
10nF
75Ω
75Ω
PHY
(NETWORK
PHYSICAL
LAYER
•
•
•
•
CHIP)
10nF
10nF
75Ω
75Ω
1nF
2883 F25
Figure 25. One Complete Isolated Powered Ethernet Port
2883f
34
LTM2883
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
/ / b b b
Z
4 . 4 4 5
3 . 1 7 5
1 . 9 0 5
0 . 6 3 5
0 . 6 3 5
0 . 0 0 0
1 . 9 0 5
3 . 1 7 5
4 . 4 4 5
a a a
Z
2883f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTM2883
Typical applicaTion
Precision 4mA to 20mA Sink/Source with Current Monitor
LTM2883-3S
B8
A8
L8
K8
L7
K7
L6
K6
+
+
–
–
V
AV
V
12.5V
SINK
3.3V
V
V
CC
L
LTC2641, DAC
1µF
1
2
3
4
8
7
6
5
7
LTC1050
4
1µF
GND
REF
CS
3
2
75k
+
–
AV
V
DD
1k
6
A7
A6
A5
A4
A3
A2
A1
B1
B2
Si1555DL_N
V
ON
SCK
DIN
V
OUT
CC2
CC2
AV
CLR
SDOE
CS
V
CC
L5
L4
L3
L2
L1
K1
K2
CS2
SDI2
SCK2
I2
CS
0.1µF
0.01µF
SDI
MOSI
SCK
µC
SCK
DO2
SDO
DO1
GND
5V
10
MISO
11
+
–
GND
SDO2
I1
14
3
LTC1100
G = 10
15Ω
0.1%
100k
15
3V
6
GND2
2883 TA02
LTC2452, ADC
LT6660-3
IN OUT
2
7
3
1
3
7
1
8
4
6
5
2
V
REF
CS
CC
+
IN
GND
2
–
0.1µF
SCK
IN
SOURCE
RETURN
0.1µF
SDO GND
–5V
relaTeD parTs
PART NUMBER
LTM2881
DESCRIPTION
COMMENTS
Isolated RS485/RS422 µModule Transceiver Plus Power 20Mbps 2500V
Isolation with Power in LGA/BGA Package
Isolation with Power in LGA/BGA Package
RMS
RMS
LTM2882
Dual Isolated RS232 µModule Transceiver Plus Power
20Mbps 2500V
2
2
LTC4310
Hot-Swappable I C Isolators
Bidirectional I C Communication, Low Voltage Level Shifting
LTC6803
Multistack Battery Monitor
Individual Battery Cell Monitoring of High Voltage Battery Stacks, Multiple
Devices Interconnected via SPI
2
LTC2309/LTC2305/ 12-Bit, 8-/2-/1-Channel, 14ksps SAR ADCs with I C
5V, Internal Reference, Software Compatible Family
LTC2301
2
LTC2631/LTC2630 Single 12-/10-/8-Bit I C or SPI V
10ppm/°C Reference
DACs with
180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Rail-to-Rail Output
OUT
LTC2641/LTC2642 16-/14-/12-Bit V
DACs
±1LSB INL/DNL, 0.5nV • s Glitch, 1μs Settling, 3mm × 3mm DFN
OUT
2
LTC2452/LTC2453 Ultra-Tiny 16-Bit Differential 5.5V ꢀΔ ADCs, SPI/I C
2LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT Packages
LTC1859/LTC1858/ 8-Channel 16-/14-/12-Bit, 100ksps, 10V SoftSpanꢁ
5V Supply, Up to 10V Configurable Unipolar/Bipolar Input Range, Pin
Compatible Family in SSOP-28 package
LTC1857
SAR ADCs with SPI
LTC2487/LTC2486 16-Bit 2- or 4-Channel ꢀΔ ADCs with Easy Driveꢁ Inputs 16-Bit and 24-Bit ꢀΔ ADC Family, Up to 16 Input Channels and Integrated
2
and I C/SPI Interface
Temperature Sensor
2
LTC4303/LTC4304 Hot Swappable I C Bus Buffers
2.7V to 5.5V Supply, Rise Time Acceleration, Stuck Bus Protection,
15kV ESD
LTC1100
LT1991
Zero-Drift Instrumentation Amplifier
Fixed Gain of 10 or 100
Precision, Pin Configurable Gain Difference Amplifier
Gain Range –13 to +14
LTC2054/LTC2055 Micropower Zero-Drift Op Amps
3V/5V/ 5V Supply
2
LTC4151
LTC4261
High Voltage I C Current and Voltage Monitor
Wide Operating Range: 7V to 80V
Floating Topology Allows Very High Voltage Operation
Negative Voltage Hot Swapꢁ Controller with ADC and
I C Monitoring
2
LTC1799
LTC6990
Wide Frequency Range Silicon Oscillator
TimerBloxꢁ Voltage Controlled Oscillator
1kHz to 30MHz
488Hz to 2MHz
2883f
LT 0912 • PRINTED IN USA
36 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号:
SI9130DB
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