LTC4244CGN [Linear]
Rugged, CompactPCI Bus Hot Swap Controllers; 坚固耐用， CompactPCI总线热插拔控制器
| 型号： | LTC4244CGN |
| 厂家： | 
Linear |
| 描述： | Rugged, CompactPCI Bus Hot Swap Controllers |
| 文件： | 总28页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4244/LTC4244-1
Rugged, CompactPCI Bus
Hot Swap Controllers
U
FEATURES
DESCRIPTIO
TheLTC®4244/LTC4244-1areHotSwapTM controllersthat
allow a board to be safely inserted into and removed from
a CompactPCITM bus slot. External N-channel transistors
control the 5V and 3.3V supplies while on-chip switches
■
Controls –12V, 3.3V, 5V and 12V Supplies
■
±14.4V Absolute Maximum Rating for 12VIN
and –12VIN Input Pins
Insensitive to Supply Voltage Transients
■
■
Adjustable Foldback Current Limit with Circuit Breaker control the ±12V supplies. The 3.3V and 5V supplies can
■
■
LOCAL_PCI_RST# Logic On-Chip
PRECHARGE Output Biases I/O Pins During Card
Insertion and Extraction
LTC4244-1 Designed for Applications without –12V
Available in 20-Lead Narrow SSOP Package
be ramped up at an adjustable rate. Electronic circuit
breakers protect all four supplies against overcurrent
faults.Afterthepower-upcycleiscomplete,theTIMERpin
capacitor serves as auxiliary VCC allowing the LTC4244/
LTC4244-1 to function without interruption in the pres-
ence of voltage spikes on the 12VIN supply. The PWRGD
output indicates when all four supplies are within toler-
ance. TheOFF/ONpinisusedtocycleboardpowerorreset
the circuit breaker. The PRECHARGE output can be used
to bias the bus I/O pins during card insertion and extrac-
tion. PCI_RST# is combined on-chip with HEALTHY# in
order to generate LOCAL_PCI_RST#.
■
■
U
APPLICATIO S
■ Hot Board Insertion into CompactPCI Bus
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.
U
TYPICAL APPLICATIO
C8
C9
0.01µF PER
POWER PIN
0.01µF PER
POWER PIN
R2
Q2
5V
IN
0.007Ω IRF7457
V
5V
5A
OUT
5V
+
+
R22
C
C
R1
0.005Ω
Q1
2.7Ω
LOAD(5VOUT)
LONG 5V
3.3V
IRF7457
V
3.3V
7A
3.3V
OUT
IN
R21
1.8Ω
Z3
LOAD(3.3VOUT)
C1
LONG 3.3V
R4
10Ω
R3
10Ω
Z4
C6
0.01µF
C7
0.01µF
R5
1k
0.33µF
Z1
Z2
3.3V
3.3V
SENSE
GATE 3.3V
5V
5V
5V
12V
IN
OUT
IN
SENSE
OUT
V
OUT
12V
V
12V
12V
IN
OUT
+
500mA
–12V
EEIN
C
C
LOAD(12VOUT)
R19 1k
V
OFF/ON
FAULT
BD_SEL#
EEOUT
V
–12V
R20
1.2k
EEOUT
R18 10k
LTC4244
100mA
LOAD(VEEOUT)
+
LONG V(I/O)
R17
10k
TIMER
C2
0.082µF
PWRGD
HEALTHY#
PCI_RST#
R6
RESETIN
10k
V
OUT
3.3V
GND PRECHARGE
RESETOUT
R8 1k
DRIVE
Q3
R15
R16
1Ω
C5
0.01µF
LOCAL_PCI_RST#
R9 24Ω
1Ω
C3 4.7nF
C4
0.01µF
V
IN
3.3V
GROUND
R10 18Ω
R7 12Ω
R11
10k
R12
10k
R13
10Ω
MMBT2222A
1V
±10%
RESET#
I/O DATA LINE 1
I/O #1
I/O PIN 1
PCI
BRIDGE
CHIP
•
•
•
•
•
•
•
•
•
R14
10Ω
I/O #128
I/O DATA LINE 128
I/O PIN 128
Z1, Z2: SMAJ12A Z3, Z4: SMAJ5.0A
4244 F01
Figure 1. Typical Compact PCI Application
42441f
1
LTC4244/LTC4244-1
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
(Notes 1, 2, 3)
PACKAGE/ORDER I FOR ATIO
Supply Voltages
ORDER PART
NUMBER
TOP VIEW
12VIN ................................................................ 14.4V
12V
V
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
12V
V
IN
OUT
V
EEIN .............................................................. –14.4V
EEIN
EEOUT
LTC4244CGN
LTC4244CGN-1
LTC4244IGN
Input Voltages (OFF/ON, RESETIN) ........–0.3V to 13.5V
Output Voltages (FAULT, PWRGD, RESETOUT)
...........................................................–0.3V to 13.5V
Analog Voltages and Currents
5V
OUT
3.3V
OUT
IN
TIMER
3.3V
3.3V
OFF/ON
FAULT
SENSE
LTC4244IGN-1
GATE
5V
PWRGD
GND
SENSE
5VOUT, DRIVE, 5VIN, 3.3VSENSE, 3.3VIN, 3.3VOUT, 5VSENSE
...........................................................–0.3V to 13.5V
PRECHARGE, GATE ....................................... ±20mA
VEEOUT ................................................–14.4V to 0.3V
TIMER, 12VOUT ........................................... –0.3V to 14.4V
Operation Temperature Range
5V
IN
RESETIN
PRECHARGE
DRIVE
RESETOUT 10
GN PACKAGE
20-LEAD PLASTIC SSOP
TJMAX = 140°C, θJA = 135°C/ W
LTC4244C/LTC4244C-1........................... 0°C to 70°C
LTC4244I/LTC4244I-1 ........................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V12VIN = 12V, VEEIN = –12V, V3.3VIN = 3.3V, V5VIN = 5V, unless
otherwise noted.
SYMBOL
PARAMETER
Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
I
V
OFF/ON = 0V
●
4
10
mA
DD
12VIN
V
LKO
Undervoltage Lockout
12V , Ramping Down
●
●
●
●
●
8
4
9
4.25
2.5
–9.25
9.25
10
4.5
2.75
–10.25
10.25
V
V
V
V
V
IN
5V , Ramping Down
IN
3.3V , Ramping Down
2.25
–8.25
8.25
IN
V
EEIN
, Ramping Up (LTC4244 Only)
TIMER, Ramping Down, V
= 6V
12VIN
V
V
Foldback Current Limit Voltage
Circuit Breaker Trip Voltage
V
V
V
V
= (V
= (V
= (V
= (V
– V
– V
), V
), V
= 0V, TIMER = 0V
= 3V, TIMER = 0V
●
●
●
●
11
46
11
46
16
51
16
51
21
56
21
56
mV
mV
mV
mV
FB
FB
FB
FB
FB
5VIN
5VIN
5VSENSE
5VOUT
5VOUT
5VSENSE
– V
– V
), V
), V
= 0V, TIMER = 0V
3.3VIN
3.3VIN
3.3VSENSE
3.3VSENSE
3.3VOUT
3.3VOUT
= 2V, TIMER = 0V
V
CB
V
CB
= (V
= (V
– V ), TIMER = FLOAT
5VSENSE
●
●
45
45
52
52
57
57
mV
mV
CB
5VIN
– V
), TIMER = FLOAT
3.3VSENSE
3.3VIN
t
Overcurrent Fault Response Time (V
(V
– V ) = 100mV, TIMER = FLOAT
5VSENSE
●
●
17
17
25
25
35
35
µs
µs
OC
5VIN
– V
) = 100mV, TIMER = FLOAT
= 2V, TIMER = 0V
GATE
3.3VIN
3.3VSENSE
I
I
GATE Pin Output Current
OFF/ON = 0V, V
●
●
●
●
●
●
–20
20
4
–67
60
–100
100
16
µA
µA
mA
V
GATE(UP)
GATE(DN)
V
GATE
= 5V, OFF/ON = 4V
I
OFF/ON = 0V, V
= 2V, TIMER = FLOAT, FAULT = 0V
8
GATE(FAULT)
GATE
∆V
∆V
∆V
External Gate Voltage
∆V
∆V
∆V
= (V
– V ), I = –1µA
GATE GATE
0.6
225
110
1
GATE
GATE
12VIN
Internal Switch Voltage Drop
= (V
– V ), I = 500mA
12VOUT
600
250
mV
mV
12V
12V
VEE
12VIN
= (V
– V
), I = 100mA
EEIN EE
VEE
EEOUT
42441f
2
LTC4244/LTC4244-1
ELECTRICAL CHARACTERISTICS
otherwise noted.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V12VIN = 12V, VEEIN = –12V, V3.3VIN = 3.3V, V5VIN = 5V, unless
SYMBOL PARAMETER
CONDITIONS
12V = 12V, 12V
MIN
TYP
MAX
UNITS
I
Current Foldback
= 0V, TIMER = 0V
= 10V, TIMER = 0V
= 0V, TIMER = 0V
= –10V, TIMER = 0V
●
●
●
●
–100
–550
50
–360
–850
225
–1000
–1500
350
mA
mA
mA
mA
CL
IN
OUT
OUT
12V = 12V, 12V
IN
V
EEIN
V
EEIN
= –12V, V
= –12V, V
EEOUT
EEOUT
350
610
870
T
Thermal Shutdown Temperature
Power Good Threshold Voltage
Junction Temperature, Ramping Up
150
°C
TS
V
12V , Ramping Down
●
●
●
●
10.8
4.50
2.80
11.1
4.61
2.90
11.4
4.75
3.00
V
V
V
V
TH
OUT
5V , Ramping Down
OUT
3.3V , Ramping Down
OUT
V , Ramping Up, LTC4244 Only
EEOUT
–10.8
–11.1
–11.4
V
V
Logic Input Low Voltage
OFF/ON, RESETIN, FAULT
OFF/ON, RESETIN, FAULT
●
●
0.8
V
V
IL
Logic Input High Voltage
OFF/ON, RESETIN Input Current
2
IH
I
OFF/ON, RESETIN = 0V
OFF/ON, RESETIN = 12V
●
●
±10
±10
µA
µA
IN
RESETOUT, FAULT Leakage
Current
RESETOUT, FAULT = 5V, OFF/ON = 0V, RESETIN = 3.3V
●
±10
µA
PWRGD Output Current
PWRGD = 5V, OFF/ON = 4V
●
●
●
●
±10
100
100
1.5
µA
µA
5V
SENSE
Input Current
5V
SENSE
= 5V, 5V = 0V
OUT
57
56
3.3V
Input Current
3.3V
= 3.3V, 3.3V = 0V
OUT
µA
SENSE
SENSE
5V Input Current
IN
5V = 5V, TIMER = 0V
IN
0.8
mA
3.3V Input Current
3.3V = 3.3V, TIMER = FLOAT
●
●
510
400
700
550
µA
µA
IN
IN
3.3V = 3.3V, TIMER = 0V
IN
5V
Input Current
5V
= 5V, OFF/ON = 0V, TIMER = 0V
●
●
●
107
170
0.1
200
300
10
µA
µA
µA
OUT
OUT
3.3V
Input Current
3.3V
= 3.3V, OFF/ON = 0V, TIMER = 0V
OUT
OUT
PRECHARGE Input Current
TIMER Pin Current
V
= 1V
PRECHARGE
I
OFF/ON = 0V, V
OFF/ON = 5V, V
= 0V
= 5V
●
●
16
25
21
45
26
70
µA
mA
TIMER
TIMER
TIMER
V
TIMER Threshold Voltage
External Timer Voltage
TIMER_HI, (V
TIMER_LO, V
– V ), FAULT = 0V, Ramping Up
TIMER
, Ramping Down
– V ), I = –1µA
TIMER TIMER
●
●
1.3
0.5
1.6
0.8
1.9
1.1
V
V
TIMER
12VIN
TIMER
∆V
∆V = (V
TIMER
●
1
V
TIMER
12VIN
R
DIS
12V
Discharge Resistance
OUT
Discharge Resistance
OFF/ON = 4V
OFF/ON = 4V
OFF/ON = 4V
OFF/ON = 4V
●
●
●
●
440
200
200
390
1000
500
500
Ω
Ω
Ω
Ω
5V
OUT
3.3V
Discharge Resistance
OUT
V
Discharge Resistance
1000
EEOUT
V
V
Output Low Voltage
PWRGD, RESETOUT, FAULT, I = 1mA
= 2V
●
●
0.4
V
V
OL
PRECHARGE Reference Voltage
V
0.95
1
1.05
PXG
DRIVE
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 3: The 12V and V
±15V, respectively, upon hot insertion.
pins will withstand transient surges up to
IN
EEIN
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
42441f
3
LTC4244/LTC4244-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
3.3V and 5V Current Foldback
Profile
12VOUT Current vs 12VOUT
Voltage
VEEOUT Current vs VEEOUT Voltage
60
50
40
30
20
10
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
3.3V
5V
0
1
2
3
4
5
0
2
4
6
8
10
12
0
–2
–4
–6
–8
–10
–12
VOLTAGE (V)
VOLTAGE (V)
VOLTAGE (V)
4244 G01
4244 G02
4244 G03
12V Foldback Current Limit vs
Temperature
12V Internal Switch Voltage Drop
vs Temperature
VEE Foldback Current Limit vs
Temperature
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
0.30
0.25
0.20
0.15
0.10
0.05
0
I
= 550mA
12VOUT
V
= 10V
EEOUT
12V
= 10V
OUT
12V
= 0V
OUT
V
= 0V
EEOUT
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4244 G04
4244 G05
4244 G06
VEE Internal Switch Voltage Drop
vs Temperature
5VIN Foldback Current Limit
Voltage vs Temperature
3.3VIN Foldback Current Limit
Voltage vs Temperature
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
60
50
40
30
20
10
0
60
50
40
30
20
10
0
I
= 100mA
VEEIN
5V
OUT
= 3V
3.3V
= 2V
OUT
5V
= 0V
3.3V
= 0V
OUT
OUT
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4244 G07
4244 G08
4244 G09
42441f
4
LTC4244/LTC4244-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
3.3VIN and 5VIN Circuit Breaker
Trip Voltage vs Temperature
12VIN Supply Current vs
3.3VIN and 5VIN Circuit Breaker
Trip Filter Time vs Temperature
Temperature
52.0
51.8
51.6
51.4
51.2
51.0
50.8
50.6
50.4
50.2
50.0
25.0
24.5
24.0
23.5
23.0
22.5
22.0
21.5
3.94
5V
3.93
3.92
3.91
3.90
3.89
3.88
3.87
IN
3.3V
IN
–50
–25
0
25
50
75
100
100
100
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4244 G10
4244 G11
4244 G12
12VIN Undervoltage Lockout vs
Temperature
5VIN Undervoltage Lockout vs
Temperature
VEEIN Undervoltage Lockout vs
Temperature
9.30
9.25
9.20
9.15
9.10
9.05
9.00
8.95
–9.22
–9.24
–9.26
–9.28
–9.30
–9.32
–9.34
–9.36
4.34
4.32
4.30
4.28
4.26
4.24
4.22
4.20
RAMPING-UP
RAMPING-UP
RAMPING-UP
RAMPING-DOWN
RAMPING-DOWN
RAMPING-DOWN
–50
–25
0
25
50
75
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4244 G13
4244 G14
4244 G15
3.3VIN Undervoltage Lockout vs
Temperature
12VOUT Powergood Threshold
Voltage vs Temperature
VEEIN Powergood Threshold
Voltage vs Temperature
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
11.090
11.085
11.080
11.075
11.070
11.065
11.060
11.055
–11.050
–11.055
–11.060
–11.065
–11.070
–11.075
–11.080
RAMPING-UP
RAMPING-DOWN
–50
–25
0
25
50
75
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4244 G16
4244 G17
4244 G18
42441f
5
LTC4244/LTC4244-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
5VOUT Powergood Threshold
Voltage vs Temperature
3.3VOUT Powergood Threshold
Voltage vs Temperature
Gate Pin Current vs Temperature
4.603
4.602
4.601
4.600
4.599
4.598
4.597
4.596
4.595
4.594
2.902
2.901
2.900
2.899
2.898
2.897
2.896
2.895
2.894
80
60
OFF/ON = 0V
40
20
0
–20
–40
–60
–80
OFF/ON = 4V
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
75
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4244 G19
4244 G20
4244 G21
Gate Pin Fault Current vs
Temperature
Timer Pin Off Current vs
Temperature
Timer Pin On Current vs
Temperature
16
14
12
10
8
20.30
20.25
20.20
20.15
20.10
20.05
60
50
40
30
20
10
0
FAULT = 0V
6
4
2
0
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
–50
–25
0
25
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4244 G22
4244 G23
4244 G24
Timer Threshold Voltage vs
Temperature
Discharge Resistance vs
Temperature
VOL vs Temperature
1.66
1.64
1.62
1.60
1.58
1.56
1.54
1.52
1.50
1.48
1.46
700
600
500
400
300
200
100
0
250
200
150
100
50
12V – V
IN
TIMER
12V
OUT
V
RESETOUT
EEOUT
3.3V
OUT
PWRGD
FAULT
5V
75
OUT
0
–50
–25
0
25
50
75
100
–50
–25
0
25
50
100
–50
–25
0
25
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4244 G25
4244 G26
4244 G27
42441f
6
LTC4244/LTC4244-1
U
U
U
PI FU CTIO S
12VIN (Pin 1): 12V Supply Input. A 0.5Ω switch is con-
nected between 12VIN and 12VOUT with a foldback current
limit.Anundervoltagelockoutcircuitpreventstheswitches
fromturningonwhilethe12VIN pinvoltageislessthan9V.
12VIN also provides power to the LTC4244’s internal VCC
node.
OFF/ON(Pin 5): Digital Input. Connect the CPCI BD_SEL#
signal to the OFF/ON pin. When the OFF/ON pin is pulled
low, the GATE pin is pulled high by a 67µA current source
and the internal 12V and –12V switches are turned on.
When the OFF/ON pin is pulled high, the GATE pin will be
pulledtogroundbya60µAcurrentsourceandthe12Vand
–12V switches turn off.
VEEIN (Pin 2): –12V Supply Input. A 1Ω switch is con-
nected between VEEIN and VEEOUT with a foldback current
limit.Anundervoltagelockoutcircuitpreventstheswitches
from turning on while the VEEIN pin voltage is greater than
–9.25V. The VEEIN undervoltage lockout function is dis-
abled for the LTC4244-1.
FAULT(Pin6):Open-DrainDigitalI/O.FAULTispulledlow
when a current limit fault is detected. Current limit faults
areignoreduntilthevoltageattheTIMERpiniswithin1.6V
of 12VIN. Once the TIMER cycle is complete, FAULT will
pull low and the LTC4244 latches off in the event of an
overcurrent fault. The part will remain in the latched off
state until the OFF/ON pin is cycled high then low. Forcing
the FAULT pin low with an external pull-down will cause
the part to latch into the off state after a 25µs deglitching
time.
5VOUT (Pin 3): 5V Output Sense. The PWRGD pin will not
pulllowuntilthe5VOUT pinvoltageexceeds4.61V.A200Ω
active pull-down discharges 5VOUT to ground when the
power switches are turned off.
TIMER (Pin 4): Current Fault Inhibit Timing Input and
Auxiliary VCC. Connect a capacitor from TIMER to GND.
When the LTC4244 is turned on, a 21µA pull-up current
source is connected to TIMER. Current limit faults will be
ignored until the voltage at the TIMER pin rises to within
1.6V of 12VIN. After the TIMER pin has completed ramp-
ing up, the TIMER capacitor serves as an auxiliary charge
reservoir for VCC in the event the 12VIN pin voltage
momentarilydropsbelowtheundervoltagelockoutthresh-
old voltage. When the LTC4244 is turned off (OFF/ON >
2V),theTIMERpinispulleddowntoGND.AftertheTIMER
pin voltage drops to within 0.8V of GND, the TIMER latch
is reset and the part is ready for another power cycle.
PWRGD (Pin 7): Open-Drain Digital Power Good Output.
Connect the CPCI HEALTHY# signal to the PWRGD pin.
PWRGD remains low while V12VOUT ≥ 11.1V, V3.3VOUT
≥
2.9V, V5VOUT ≥ 4.61V, and VEEOUT ≤ –11.1V. When any of
the supplies falls below its power good threshold voltage,
PWRGD will go high after a 14µs deglitching time.
GND (Pin 8): Device Ground.
RESETIN(Pin9):DigitalInput.ConnecttheCPCIPCI_RST#
signaltotheRESETINpin.PullingtheRESETINpinlowwill
cause RESETOUT to pull low. RESETOUT will also pull low
when PWRGD is high.
42441f
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LTC4244/LTC4244-1
U
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PI FU CTIO S
RESETOUT (Pin 10): Open-Drain Digital Output. Connect
the CPCI_LOCAL_RST# signal to the RESETOUT pin.
RESETOUT is the logical combination of the RESETIN and
PWRGD.
GATE (Pin 15): High Side Gate Drive for the External 3.3V
and 5V N-Channel Pass Transistors. An external series RC
network is required for current limit loop compensation
andsettingtheminimumramp-uptime.Duringpower-up,
the slope of the voltage rise at the GATE is set by the 67µA
current source connected through a Schottky diode to
12VIN and the external capacitor connected to GND (C1 in
Figure 1) or by the 3.3V or 5V current limit and the bulk
capacitance in the 3.3VOUT or 5VOUT supply lines. During
powerdown, theslewrateoftheGATEvoltageissetbythe
60µA current source connected to GND and the external
GATE capacitor (C1 in Figure 1).
DRIVE (Pin 11): Precharge Base Drive Output. Provides
basedriveforanexternalNPNemitter-followerthatinturn
biases the PRECHARGE node.
PRECHARGE (Pin 12): Precharge Monitor Input. An inter-
nalerroramplifierservostheDRIVEpinvoltagetokeepthe
PRECHARGEnodeat1V. SeeApplicationsInformationfor
generating voltages other than 1V. If not used, tie the
PRECHARGE pin to ground.
The voltage at the GATE pin will be modulated to maintain
a constant current when either the 5V or 3.3V supplies go
into current limit. In the event of an overcurrent fault, the
GATE pin is immediately pulled to GND.
5VIN (Pin 13): 5V Supply Sense Input. An undervoltage
lockout circuit prevents the switches from turning on
when the voltage at the 5VIN pin is less than 4.25V.
5VSENSE (Pin 14): 5V Current Limit Sense. With a sense
resistor placed in the supply path between 5VIN and
5VSENSE, the GATE pin voltage will be adjusted to maintain
a constant 51mV across the sense resistor and a constant
current through the switch while the TIMER pin is low. A
foldback feature makes the current limit decrease as the
voltage at the 5VOUT pin approaches GND. When the
TIMER pin is high, the circuit breaker function is enabled.
If the voltage across the sense resistor exceeds 52mV, the
circuit breaker is tripped after a 25µs time delay. In the
event of a short-circuit or large overcurrent transient
condition, the GATE pin voltage will be adjusted to main-
tain a constant 150mV across the sense resistor and a
constant current through the switch.
3.3VSENSE (Pin 16): 3.3V Current Limit Sense. With a
sense resistor placed in the supply path between 3.3VIN
and 3.3VSENSE, the GATE pin voltage will be adjusted to
maintain a constant 51mV across the sense resistor and a
constant current through the switch while the TIMER pin
is low. A foldback feature makes the current limit decrease
as the voltage at the 3.3VOUT pin approaches GND. When
the TIMER pin is high, the circuit breaker function is
enabled. If the voltage across the sense resistor exceeds
52mV,thecircuitbreakeristrippedaftera25µstimedelay.
Intheeventofashort-circuitorlargeovercurrenttransient
condition, the GATE pin voltage will be adjusted to main-
tain a constant 150mV across the sense resistor and a
constant current through the switch.
Ifno3.3Vinputsupplyisavailable,shortthe3.3VSENSE pin
to the 5VIN pin.
42441f
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LTC4244/LTC4244-1
U
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PI FU CTIO S
3.3VIN (Pin 17): 3.3V Supply Sense Input. An undervolt-
age lockout circuit prevents the switches from turning on
when the voltage at the 3.3VIN pin is less than 2.5V. If no
3.3V input supply is available, short the 3.3VIN pin to the
5VIN pin.
VEEOUT (Pin 19): -12V Supply Output. A 1Ω switch is
connectedbetweenVEEIN andVEEOUT.VEEOUT mustbeless
than –11.1V before the PWRGD pin pulls low. The VEEOUT
power good comparator is disabled for the LTC4244-1. A
390Ω active pull-up discharges VEEOUT to ground when
the power switches are turned off.
3.3VOUT (Pin 18): Analog Input Used to Monitor the 3.3V
Output Supply Voltage. The PWRGD pin cannot pull low
untilthe3.3VOUT pinvoltageexceeds2.9V.Ifno3.3Vinput
supply is available, tie the 3.3VOUT pin to the 5VOUT pin. A
200Ω active pull-down discharges 3.3VOUT to ground
when the power switches are turned off.
12VOUT (Pin 20): 12V Supply Output. A 0.5Ω switch is
connected between 12VIN and 12VOUT. 12VOUT must
exceed 11.1V before the PWRGD pin can pull low. A 440Ω
active pull-down discharges 12VOUT to ground when the
power switches are turned off.
42441f
9
LTC4244/LTC4244-1
W
BLOCK DIAGRA
3.3V
3.3V
IN
GND
17
16
15
14
13
8
SENSE
GATE
5V
5V
SENSE
IN
V
CC
5V
+
3.3V
OUT
OUT
67µA
60µA
–
+
–
+
–
+
–
+
+
+
–
–
5V
CURRENT
FAULT
3.3V
CURRENT FAULT
50mV
50mV
+
+
+
–
–
–
–
CP_OFF
TIMER_LO ≥ 50mV
TIMER_HI ≥ 150mV
TIMER_LO ≥ 50mV
TIMER_HI ≥ 150mV
FAULT
6
8µs
RISING
EDGE
DELAY
UVL
MONITOR
V
12V
EEIN
IN
REF
V
CC
21µA
THERMAL
FAULT
TIMER_HI
TIMER
4
25µs
V
CC
5V CURRENT FAULT
3.3V CURRENT FAULT
EE
12V CURRENT FAULT
RISING
EDGE
S
R
Q
V
CURRENT FAULT
V
UVL
DELAY
CC
CP_OFF
Q
46µs
TIMER_HI
FALLING
EDGE
S
R
Q
Q
RESET
DELAY
TIMER_LO
OFF/ON
PWRGD
5
7
V
CC
5V
IN
14µs
FALLING
EDGE
DELAY
THERMAL
SHUTDOWN
THERMAL
FAULT
DRIVE
4R
–
11
RESETOUT
RESETIN
CP_OFF
10
9
R
+
V
CC
PRECHARGE
12
20
REFERENCE
REF
12V CURRENT FAULT
12V SWITCH
CONTROL
THERMAL FAULT
12V
OUT
12V
IN
1
5V
OUT
OUT
3
3.3V
CHARGE
PUMP
CP_OFF
18
POWER GOOD
MONITOR
CP_OFF
V
CC
REF
V
V
EEOUT
EEIN
2
19
4244 BD
CP_OFF
THERMAL FAULT
V
SWITCH
EE
CONTROL
V
CURRENT FAULT
EE
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Hot Circuit Insertion
• Current limit during power up: the supplies are allowed
to power up in current limit. This allows the LTC4244 to
power up boards with widely varying capacitive loads
without tripping the circuit breaker. The maximum
allowable power-up time is adjustable using the TIMER
pin capacitor.
When a circuit board is inserted into a live CompactPCI
(CPCI) bus, the supply bypass capacitors can draw huge
inrush currents from the CPCI power bus as they charge
up. These transient currents can create glitches on the
power bus, causing other boards in the system to reset.
• Internal 12V and –12V power switches.
The LTC4244 is designed to turn a board’s back-end
supply voltages on and off in a controlled manner, allow-
ing the board to be safely inserted or removed from a live
CPCI connector without glitching the system power sup-
plies. It also protects the system supplies from shorts,
prechargesthebusI/Oconnectorpinsduringhotinsertion
and extraction, and monitors the supply voltages.
• PWRGD output: monitors the voltage status of the four
back-end supply voltages.
• PCI_RST# combined on chip with HEALTHY# to create
LOCAL_PCI_RST# output. Simply connect the
PCI_RST# signal to the RESETIN pin and the
LOCAL_PCI_RST# signal to the open-drain RESETOUT
pin.
The LTC4244 is specifically designed for CPCI applica-
tions where the Hot Swap controller resides on the plug-
in board.
• Prechargeoutput:on-chipreferenceanderroramplifier
provide 1V for biasing bus I/O connector pins during
CPCI card insertion and extraction.
LTC4244 Feature Summary
• TIMER/AUX. VCC: After power-up, the TIMER pin ca-
pacitor serves as auxiliary VCC, thus enabling the
LTC4244 to ride out large voltage spikes on the 12VIN
supply without interruption.
• Allows safe insertion and removal from a CPCI back-
plane.
• ControlsallfourCPCIsupplies:-12V, 12V, 3.3Vand5V.
• Adjustable foldback current limit for the 5V and 3.3V
supplies: an adjustable analog current limit with a value
that depends on the output voltage. If the output is
shortedtogroundthecurrentlimitdropstokeeppower
dissipation and supply glitches to a minimum.
• Undervoltage lockout: All four input voltages are pro-
tected by undervoltage lockouts.
• Space saving 20-pin SSOP package.
LTC4244 vs LTC1644
• 12V and –12V circuit breakers: if either supply remains
in analog foldback current limit for more than 25µs, the
circuit breakers will trip, the supplies are turned off and
the FAULT pin is pulled low.
The LTC4244 is pin-for-pin compatible with the LTC1644.
There are, however, some important differences between
the two parts:
• TIMER: The LTC4244’s TIMER pin threshold voltage is
1.6V below V12VIN vs 1V for the LTC1644. After power-
up, the LTC4244’s TIMER pin also doubles as auxiliary
VCC.
• Adjustable 5V and 3.3V circuit breakers: if either supply
exceeds its current limit for more than 25µs, the circuit
breaker will trip, the supplies will be turned off and the
FAULT pin is asserted low. In the event of a short circuit
on either supply, an analog current limit will prevent the
supply current from exceeding three times the circuit
breaker threshold current.
• VEEIN UVL: The LTC4244 has a –9.5V UVL threshold
protecting the VEEIN supply. The LTC1644 has no VEEIN
UVL feature.
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LTC4244/LTC4244-1
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APPLICATIO S I FOR ATIO
• 5VIN UVL Threshold Voltage: The LTC4244’s 5VIN UVL
threshold voltage is 4.25V vs. 2.5V for the LTC1644.
The following is a typical hot insertion sequence:
1. ESD clips make contact.
• VEEOUT PWRGDThresholdVoltage:TheLTC4244VEEOUT
power good threshold voltage is –11.1V vs –10.5V for
the LTC1644.
2. Long power and ground pins make contact and Early
Power is established. The 1V precharge voltage be-
comes valid at this stage of insertion. Power is also
appliedtothepull-upresistorsconnectedtotheFAULT,
PWRGD and OFF/ON pins. All power switches are held
off at this stage of insertion.
• Absolute Maximum Ratings: The LTC4244’s absolute
maximum ratings for the 12VIN and VEEIN pins are
±14.4V, respectively, vs ±13.2V for the LTC1644.
• 5V/3.3V Circuit Breakers: If a short-circuit occurs after
power-up, the LTC4244 actively limits the voltage
dropped across the external 5V and 3.3V sense resis-
tors to 150mV for 25µs before tripping the circuit
breaker.Intheeventeitherthe5Vor3.3Vsenseresistor
voltage exceeds 150mV, the LTC1644 trips the circuit
breaker without delay.
3. Medium length pins make contact. Both FAULT and
PWRGDcontinuetobepulleduphighatthisstageinthe
hotplugsequence, andthepowerswitchesarestillheld
off. The 12V and –12V connector pins also make
contactatthisstage.ZenerclampsZ1andZ2plusshunt
RCsnubbersR16-C5andR15-C4helpprotecttheVEEIN
and 12VIN pins, respectively, from large voltage tran-
sients during hot insertion.
• 5V/3.3VCircuitBreakerThresholdVoltage:TheLTC4244
threshold voltage is 52mV ±5mV vs 55mV ±15mV for
the LTC1644.
Thesignalpinsalsoconnectatthispoint. Theseinclude
theHEALTHY#signal(whichisconnectedtothePWRGD
pin), the PCI_RST# signal (which is connected to the
RESETIN pin) and the I/O connector pins (which are
biased at 1V by the LTC4244’s precharge circuit).
• External Gate Voltage: After power-up, the voltage drop
from the 12VIN pin to the GATE pin is 0.6V for the
LTC4244 vs 50mV for the LTC1644.
4. Short pins make contact. The BD_SEL# signal is con-
nected to the OFF/ON pin. If the BD_SEL# signal is
grounded on the backplane, the plug-in card power-up
cycle begins immediately. System backplanes that do
not ground the BD_SEL# signal will instead have cir-
cuitry that detects when BD_SEL# makes contact with
theplug-inboard. Thesystemlogiccanthencontrolthe
power up process by pulling BD_SEL# low.
Hot Plug Power-Up Sequence
The LTC4244 is specifically designed for hot plugging
CPCI boards. The typical application circuit is shown in
Figure 1.
CPCI Connector Pin Sequence
The staggered lengths of the CPCI male connector pins
ensure that all power supplies are physically connected to
theLTC4244beforeback-endpowerisallowedtorampup
(BD_SEL# assertedlow). The longpins, whichinclude5V,
3.3.V, V(I/O) and GND, mate first. The short BD_SEL# pin
mates last. At least one long 5V power pin must be
connected to the LTC4244 in order for the PRECHARGE
voltage to be available during the insertion sequence.
Power-Up Sequence
The back-end 3.3VOUT and 5VOUT power planes are iso-
lated from the 3.3VIN and 5VIN power planes by external
N-channel pass transistors Q1 and Q2, respectively. Inter-
nal pass transistors isolate the back-end 12VOUT and
VEEOUT power planes from the 12VIN and VEEIN power
planes.
42441f
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LTC4244/LTC4244-1
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Sense resistors R1 and R2 provide current fault detection
and R5 and C1 provide current control loop compensation
as well as ramp rate control for the GATE pin voltage.
Resistors R3 and R4 prevent high frequency oscillations
in MOSFET’s Q1 and Q2.
Power-Down Sequence
When the BD_SEL# signal is pulled high, a power-down
sequence begins (Figure 3).
Internal switches are connected to each of the output
voltage supply pins to discharge the bypass capacitors to
ground. The TIMER pin is immediately pulled low. The
GATE pin is pulled down by a 60µA current source to
preventtheloadcurrentsonthe3.3Vand5Vsuppliesfrom
going to zero instantaneously and glitching the power
supply voltages. When any of the output voltages dips
below its threshold, the HEALTHY# signal pulls high and
LOCAL_PCI_RST# will be asserted low.
A power-up sequence begins when the OFF/ON pin is
pulled low (Figure 2). This enables the pass transistors to
turn on and an internal 21µA current source is connected
to TIMER. Once the pass transistors begin to conduct
current, the supplies will start to power up. Current limit
faults are ignored while the TIMER pin voltage is ramping
up and is less than (12VIN – 1.6V). When all four supply
voltages are within tolerance, HEALTHY# will pull low and
LOCAL_PCI_RST# is free to follow PCI_RST#.
TIMER
10V/DIV
TIMER
10V/DIV
GATE
10V/DIV
GATE
10V/DIV
12V
OUT
12V
10V/DIV
5V
OUT
10V/DIV
5V
OUT
OUT
10V/DIV
3.3V
10V/DIV
3.3V
OUT
OUT
10V/DIV
10V/DIV
V
EEOUT
V
EEOUT
10V/DIV
10V/DIV
BD_SEL#
10V/DIV
BD_SEL#
10V/DIV
HEALTHY#
10V/DIV
HEALTHY#
10V/DIV
LCL_PCI_RST#
10V/DIV
LCL_PCI_RST#
10V/DIV
4244 F03
4244 F02
20ms/DIV
10ms/DIV
Figure 2. Normal Power-Up Sequence
Figure 3. Normal Power-Down Sequence
42441f
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LTC4244/LTC4244-1
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APPLICATIO S I FOR ATIO
Once the power-down sequence is complete, the CPCI
card may be removed from the slot. During extraction, the
precharge circuit continues to bias the bus I/O connector
pins at 1V until the long 5V and 3.3V connector pin
connections are broken.
The maximum power-up time for this condition can be
approximated by:
V
OUT + VTH,MOSFET(MAX) •C1(MAX)
(
<
)
tON
(4)
IGATE(MIN)
GATE Pin Capacitor Selection
where VTH,MOSFET(MAX) is the maximum threshold voltage
of the external 5V or 3.3V MOSFET.
Both the load capacitance and the LTC4244’s GATE pin
capacitor (C1 in Figure 1) affect the ramp rate of the 5VOUT
and 3.3VOUT voltages. The precise relationship can be
expressed as:
In general, the edge rate (dI/dt) at which the back-end 5V
and 3.3V supply currents are turned on can be limited by
increasing the size of C1. Applications that are sensitive to
the edge rate should characterize how varying the size of
C1 reduces dI/dt for the external MOSFET selected for a
particular design.
ILIMIT(5V) –ILOAD(5V)
dVOUT IGATE
(1)
=
or =
or
dt
C1
CLOAD(5VOUT)
In the event of a short-circuit or overcurrent condition, the
LTC4244’s GATE pin can be pulled down within 2µs since
a 1kΩ (R5 in Figure 1) decouples C1 from the gates of the
external MOSFET’s (Q1 and Q2 in Figure 1).
ILIMIT(3.3V) –ILOAD(3.3V)
=
CLOAD(3.3VOUT)
whichever is slowest. The power-up time for any of the
LTC4244’soutputswheretheinrushcurrentisconstrained
by that supply’s foldback current limit can be approxi-
mated as:
TIMER Pin Capacitor Selection
During a power-up sequence, a 21µA current source is
connected to the TIMER pin and current limit faults are
ignored until the voltage ramps to within 1.6V of 12VIN.
This feature allows the part to power up large capacitive
loads using its foldback current limit. The TIMER inhibit
period can be expressed as:
2 •CLOAD •nVOUT
LIMIT(nVOUT) –ILOAD(nVOUT)
ton(nVOUT)
<
(2)
I
Where nVOUT = 5VOUT, 3.3VOUT, 12VOUT or VEEOUT. For
example, if CLOAD=2000µF, ILIMIT(5VOUT) = 6A and
ILOAD(5VOUT) = 5A, the 5VOUT turn-on time will be less than
20ms.
CTIMER • 12V – V
(
)
IN
TIMER
tTIMER
=
(5)
ITIMER
If the value of C1 is large enough that it alone determines
the output voltage ramp rate, then the magnitude of the
inrush current initially charging the load capacitance is:
The timer period should be set longer than the duration of
any inrush current that exceeds the LTC4244’s foldback
current limit but yet be short enough not to exceed the
maximum, safe operating area of the external 5V and 3.3V
pass transistors in the event of a short circuit (see Design
Example). As a design aid, the TIMER period as a function
of the timing capacitor using standard values from 0.1µF
to 0.82µF is shown in Table 1.
CLOAD
I
=
•IGATE
(3)
INRUSH
C1
42441f
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Table 1. tTIMER vs CTIMER
(±10%)
Short-Circuit Protection
C
TIMER
t
t
TIMER(MAX)
TIMER(MIN)
During a normal power-up sequence, if the TIMER pin is
done ramping and any supply is still in current limit all of
the pass transistors will be immediately turned off and
FAULT will be pulled low as shown in Figure 4.
0.1µF
35ms
74ms
0.22µF
0.33µF
0.47µF
0.68µF
0.82µF
77ms
115ms
164ms
238ms
287ms
162ms
243ms
346ms
500ms
603ms
Inordertopreventexcessivepowerdissipationinthepass
transistors and prevent voltage spikes on the supplies
during short-circuit conditions, the current limit on each
supply is designed to be a function of the output voltage.
As the output voltage drops, the current limit decreases.
Unlike a traditional circuit breaker function where large
currents can flow before the breaker trips, the current
foldback feature guarantees that the supply current will be
kept at a safe level.
TheTIMERpinisimmediatelypulledlowwhentheBD_SEL#
pin signal goes high.
Thermal Shutdown
The internal switches for the 12V and –12V supplies are
protected by a thermal shutdown circuit. When the junc-
tiontemperatureofthediereaches150°C, allswitcheswill
be latched off and the FAULT pin will be pulled low.
If either the 12V or –12V supply exceeds current limit
after power-up, the shorted supply’s current will drop
TIMER
10V/DIV
GATE
10V/DIV
12V
OUT
10V/DIV
5V
OUT
10V/DIV
3.3V
OUT
10V/DIV
V
EEOUT
10V/DIV
BD_SEL#
10V/DIV
HEALTHY#
10V/DIV
LCL_PCI_RST#
10V/DIV
FAULT
10V/DIV
4244 F04
20ms/DIV
Figure 4. Power-Up Into a Short on a 3.3V Output
42441f
15
LTC4244/LTC4244-1
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APPLICATIO S I FOR ATIO
immediately to its ILIMIT value. If that supply remains in
currentlimitformorethan25µs, allofthesupplieswillbe
latched off. The 25µs prevents quick current spikes—for
example, fromafanturningon—fromcausingfalsetrips
of the circuit breaker.
resistor. As shown in Figure 1, a sense resistor is con-
nected between 5VIN and 5VSENSE for the 5V supply. For
the 3.3V supply, a sense resistor is connected between
3.3VIN and 3.3VSENSE. The typical current limit and the
foldback current levels are given by Equations 6 and 7:
After power-up, the 5V and 3.3V supplies are protected
from short circuits by dual-level circuit breakers. In the
event that either supply’s current exceeds the nominal
current limit, an internal timer is started. If the supply is
still overcurrent after 25µs, the circuit breaker trips and all
the supplies are turned off (Figure 5). An analog current
limit loop prevents the supply current from exceeding 3×
the nominal current limit in the event of a short circuit
(Figure 6). The LTC4244 will stay in the latched off state
until the OFF/ON pin is cycled high then low or the 12VIN
power supply is cycled low then high.
51mV
RSENSE(nVOUT)
ILIMIT(nVOUT)
=
(6)
(7)
16mV
RSENSE(nVOUT)
IFOLDBACK(nVOUT)
=
where nVOUT = 5VOUT or 3.3VOUT
.
The current limit for the internal 12V switch is set at
850mA folding back to 360mA and the –12V switch at
610mA folding back to 225mA.
The current limit and the foldback current level for the 5V
and 3.3V outputs are both a function of the external sense
GATE
20V/DIV
GATE
20V/DIV
5V
OUT
3.3V
OUT
10V/DIV
5V/DIV
FAULT
5V/DIV
FAULT
5V/DIV
TIMER
20V/DIV
TIMER
20V/DIV
3V – 3V
IN
SENSE
5V – 5V
IN SENSE
500mV/DIV
100mV/DIV
4244 F05
4244 F06
10µs/DIV
10µs/DIV
Figure 5. Overcurrent Fault on 5V Output
Figure 6. Short-Circuit Fault on 3.3V Output
42441f
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Calculating RSENSE
pulled high and the LOCAL_PCI_RST# signal will be
asserted low.
Determining the most appropriate value for the sense
resistorfirstrequiresknowingthemaximumcurrentneeded
by the load under worst-case conditions. Two other pa-
rameters affect the value of the sense resistor. First is the
tolerance of the LTC4244’s circuit breaker threshold volt-
age. The LTC4244’s nominal circuit breaker threshold
voltage is VCB(NOM) = 52mV; however it exhibits ±5mV
tolerance over process and temperature. Second is the
tolerance(RTOL)ofthesenseresistor.Senseresistorsare
available in RTOL’s of ±1%, ±2% and ±5% and exhibit
temperature coefficients of resistance (TCR’s) between
±75ppm/°C and ±100ppm/°C. How the sense resistor
changes as a function of temperature depends on the
I2 • R power being dissipated by it. The power rating of the
sense resistor should accommodate steady-state fault
current levels so that the component is not damaged
before the circuit breaker trips.
Table 3. LOCAL_PCI_RST# Truth Table
PCI_RST#
HEALTHY#
LOCAL_PCI_RST#
LO
LO
HI
LO
HI
LO
LO
HI
LO
HI
HI
LO
Precharge
The PRECHARGE input and DRIVE output pins are in-
tended for use in generating the 1V precharge voltage that
is used to bias the bus I/O connector pins during board
insertion and extraction. The LTC4244 is also capable of
generating precharge voltages other than 1V. Figure 7
shows a circuit that can be used in applications requiring
a precharge voltage of less than 1V. The circuit in Figure 8
can be used for applications that need precharge voltages
greater than 1V.
Table 2 lists ITRIP(MIN) and ITRIP(MAX) versus some sug-
gested values of RSENSE. Table 7 lists manufacturers and
part numbers for these resistor values.
Precharge resistors are used to connect the 1V bias volt-
age to the I/O lines with minimal disturbance. Figure 1
shows the precharge application circuit for 5V signaling.
The precharge resistor requirements are more stringent
for 3.3V and Universal Hot Swap boards. If the total leak-
age current on the I/O line is less 2µA, then a 50k resistor
can be connected directly from the 1V bias voltage to the
I/O line. However, many ICs connected to the I/O lines can
have leakage currents up to 10µA. For these applications,
a 10k resistor is used but must be disconnected when the
board is seated as determined by the state of the BD_SEL#
signal. Figure 9 shows a precharge circuit that uses a bus
switchtoconnecttheindividual10kprechargeresistorsto
theLTC4244’s1VPRECHARGEpin.Theelectricalconnec-
tionismade(busswitchesclosed)whenthevoltageonthe
BD_SEL# pin of the plug-in card is pulled-up to 5VIN,
which occurs just after the long pins have made contact.
The bus switches are electrically disconnected when the
short, BD_SEL# connector pin makes contact and the
Table 2. ITRIP vs RSENSE
R
SENSE
(1% RTOL)
I
I
TRIP(MAX)
TRIP(MIN)
0.005Ω
9.31A
11.5A
0.007Ω
0.011Ω
6.6A
4.2A
8.2A
5.2A
Output Voltage Monitor
The status of all four output voltages is monitored by the
power good function. In addition, the PCI_RST# signal is
logically combined on-chip with the HEALTHY# signal to
create LOCAL_PCI_RST# (see Table 3). As a result,
LOCAL_PCI_RST#willbepulledlowwheneverHEALTHY#
is pulled high independent of the state of the PCI_RST#
signal.
If any of the output voltages drop below the power good
threshold for more than 14µs, the PWRGD pin will be
42441f
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APPLICATIO S I FOR ATIO
LTC4244*
GND PRECHARGE
12
LTC4244*
DRIVE
11
GND
8
PRECHARGE DRIVE
8
12
11
18Ω
4.7nF
1k
5%
18Ω
5%
1k
5%
4.7nF
5%
12Ω
5%
12Ω
5%
R10A
R10B
R10A
R10B
3.3V
IN
3.3V
IN
Q3
Q3
PRECHARGE OUT MMBT2222A
PRECHARGE OUT
MMBT2222A
R10A + R10B
R10A
R10A + R10B
V
=
• 1V
PRECHARGE
V
=
• 1V
PRECHARGE
R10A
4244 F08
*ADDITIONAL DETAILS OMITTED FOR CLARITY
4244 F07
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 8. Precharge Voltage >1V Application Circuit
Figure 7. Precharge Voltage <1V Application Circuit
C9
PCB EDGE
BACKPLANE
CONNECTOR
0.01µF PER
BACKPLANE
CONNECTOR
POWER PIN
5V
IN
13
5
5V
IN
5V
R22
2.7Ω
R20
1.2k
5%
LTC4244*
LONG 5V
BD_SEL#
R19
1k 5%
OFF/ON
GND
PRECHARGE
12
DRIVE
11
Z4
C7
0.01µF
R8
1k 5%
8
R9
24Ω
R10
18Ω 5%
C3 4.7nF
3V
IN
GROUND
Q3
R7
12Ω 5%
R23
51.1k 5%
MMBT2222A
100Ω
0.1µF
Q2
MMBT3906
PRECHARGE OUT
V
IN
DD
1V ±10%
BUS SWITCH
I
= ±55mA
OE
OUT
R24
75k
5%
OUT
OUT
R13
10Ω
5%
R11
10k
5%
R12
10k
5%
I/O
I/O
I/O PIN 1
R14
10Ω
5%
PCI
BRIDGE
CHIP
DATA BUS
UP TO 128 I/O LINES
I/O PIN 128
Z4: SMAJ5.0A
*ADDITIONAL DETAILS OMITTED FOR CLARITY
4244 F09
Figure 9. Precharge Bus Switch Application Circuit for 3.3V and Universal Hot Swap Boards
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U
BD_SEL# voltage drops below 4.4V thus causing the bus
Other CompactPCI Applications
switch OE to be pulled high by Q2.
The LTC4244-1 is designed for CompactPCI designs
where the –12V supply is not being used on the plug-in
board. The VEEOUT power good comparator, VEEIN UVL,
and VEE circuit breaker functions are disabled. The VEEIN
pin should be connected to GND and the VEEOUT pin left
floating if a –12V output is not needed.
The CompactPCI specification assumes that there is a
diodeto3.3VonthecircuitthatisdrivingtheBD_SEL#pin.
The1.2kresistor pull-upto5VIN onthe plug-incard willbe
clamped by the diode to 3.3V. If the BD_SEL# pin is being
driven high, the actual voltage on the pin will be approxi-
mately 3.9V. This is still above the high TTL threshold of
theLTC4244OFF/ONpin, butlowenoughforQ2todisable
the bus switches and thus disconnect the 10k precharge
resistors from the I/O lines. Since the power to the bus
switch is derived from a front-end power plane, a 100Ω
resistor should be placed in series with the power supply
of the bus switch.
If no 3.3V supply input is required, Figure 10 illustrates
how the LTC4244 should be configured: 3.3VSENSE and
3.3VIN are connected to 5VIN and 3.3VOUT is connected to
5VOUT
.
For applications where the BD_SEL# connector pin is
typicallyconnectedtogroundonthebackplane, thecircuit
in Figure 11 allows the LTC4244 to be reset simply by
pressing a pushbutton switch on the CPCI plug in board.
This arrangement eliminates the requirement to extract
andreinserttheCPCIboardinordertoresettheLTC4244’s
circuit breaker.
When the plug-in card is removed from the connector, the
BD_SEL# connection is broken first, and the BD_SEL#
voltage pulls up to 5VIN. This causes Q2 to turn off, which
re-enables the bus switch, and the precharge resistors are
again connected to the LTC4244 PRECHARGE pin for the
remainder of the extraction process.
V(I/O)
PCB EDGE
TIMER/Auxiliary VCC
BACKPLANE BACKPLANE
PUSHBUTTON
CONNECTOR CONNECTOR
1.2k
SWITICH
Once the TIMER pin voltage has ramped to within 1.6V of
12VIN, the auxiliary VCC function is enabled. In the event
the 12VIN supply voltage collapses, the LTC4244 will
continue to draw power from the charge stored on the
TIMER pin capacitor until the internal VCC node drops
below its undervoltage lockout threshold or the 12VIN
supply voltage recovers, whichever happens first.
100Ω
1k
0.25W
BD_SEL#
GROUND
5
8
OFF/ON
LTC4244*
GND
4244 F11
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. BD_SEL# Pushbutton Toggle Switch
PCB EDGE
BACKPLANE BACKPLANE
CONNECTOR CONNECTOR
R2
0.007Ω
Q2
IRF7457
5V
IN
5V
OUT
5V
LONG 5V
C1
0.33µF
R4
10Ω
Z4
R5
1k
17
3.3V
16
13
14
15
18
3
3.3V
5V
5V
GATE 3.3V
5V
IN
SENSE
IN
SENSE
OUT OUT
LTC4244*
8
GND
GROUND
4244 F10
Z4: SMAJ5.0A
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. No 3.3V Supply Application Circuit
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5. The MOSFET package must be able to sustain the
maximum pulse power that occurs in the event the
LTC4244 attempts to power-up either the 5V or 3.3V
back-end supply into a short circuit (see Design Ex-
ample for a sample calculation).
Power MOSFET Selection Criteria
The LTC4244 uses external MOSFETs to limit the 5V and
3.3V supply currents. The following criteria should be
used when selecting these MOSFET’s:
1. The on resistance should be low enough to prevent an
excessive voltage drop across the sense resistor and
the series MOSFET at rated load current given the
amount of gate to source voltage provided by the
LTC4244.
Table 8 lists some power MOSFET’s that can be used with
the LTC4244.
Input Overvoltage Transient Protection
Hot plugging a board into a backplane generates inrush
currents from the backplane power supplies due to the
charging of the plug-in board capacitance. To reduce this
transient current to a safe level, the CPCI Hot Swap
specification restricts the amount of unswitched capaci-
tance used on the input side of the plug-in board. Each
medium or long power pin connected to the CPCI female
connector on the plug-in board is required to have a 10nF
ceramic bypass capacitor to ground. Bulk capacitors are
only allowed on the switched output side of the LTC4244
(5VOUT, 3.3VOUT, 12VOUT, VEEOUT). Some bulk capaci-
tance is allowed on the 5VIN and 3.3VIN Early Power
planes, but only because a current limiting resistor is
assumed to decouple the connector pin from the bulk
capacitance. Circuits normally placed on the unswitched
side Early Power plane (PCI Bridge, for example) need to
to be decoupled by a current limiting resistor.
2. The drain-to-source breakdown voltage should be high
enough for the device to survive overvoltage transients
that may occur during fault conditions (the 5V and 3.3V
transientvoltagelimitersshowninFigure1willlimitthe
maximumdrain-sourcevoltageseenbytheseMOSFET’s
during fault conditions).
3. The MOSFET package must be able to handle the
maximum, steady state power dissipation for the ON
state without exceeding the device’s rated maximum
junction temperature. The MOSFET’s steady-state, dis-
sipated power can be expressed as:
P
ON = IMAX2 • RDS(ON)
(8)
The increase in steady-state junction-to-ambient tem-
perature is given by:
TJ – TA = PON • RθJA
(9)
Disallowing bulk capacitors on the input power pins miti-
gatestheinrushcurrentduringHotSwap. However, italso
tendstocreatearesonantcircuitformedbytheinductance
of the backplane power supply trace in series with the
inductance of the connector pin and the parasitic capaci-
tance of the plug-in board (mainly due to the large power
FET). Upon board insertion, the ringing of this circuit can
exhibit a peak overshoot of 2.5 times the steady-state
voltage (>30V for 12VIN).
4. TheMOSFETpackagemustbeabletodissipatetheheat
resulting from the power pulse during the transition
from off to on. A worst-case approximation for the
magnitude of the power pulse is:
nVOUT • IINRUSH +ILOAD
(
)
POFF-ON
<
(10)
2
where nVOUT = 5VOUT or 3.3VOUT, IINRUSH is the tran-
sient current initially charging the load capacitance and
ILOAD isthesteady-stateloadcurrent.Theduration,tON,
of the power pulse can be expressed as:
Therearetwomethodsforabatingtheeffectsofthesehigh
voltage transients: using voltage limiters to clip the tran-
sient to a safe level and snubber networks. Snubber
networks are series RC networks whose time constants
CLOAD • VOUT
tON
=
(11)
IINRUSH
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LTC4244/LTC4244-1
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APPLICATIO S I FOR ATIO
U
are experimentally determined based on the board’s para-
sitic resonance circuits. As a starting point, the capacitors
in these networks are chosen to be 10× to 100× the power
MOSFET’s COSS under bias. The series resistor is a value
determined experimentally that ranges from 1Ω to 50Ω,
depending on the parasitic resonance circuit. Note that in
all LTC4244 circuit schematics, both transient voltage
limiters and snubber networks have been added to the
12VIN and VEEIN supply rails and should always be used.
Snubber networks are not necessary on the 3.3VIN or the
5VIN supply lines since their absolute maximum voltage
ratings are 13.5V. Transient voltage limiters, however, are
recommended as these devices provide large-scale tran-
sient protection for the LTC4244 in the event of abrupt
changes in supply current. All protection networks should
bemountedveryclosetotheLTC4244’ssupplypinsusing
short lead lengths to minimize trace resistance and induc-
tance. This is shown schematically in Figures 12 and 13
and a recommended layout of the transient protection
devices around the LTC4244 is shown in Figure 14.
R2
0.007Ω
Q2
IRF7457
5V
IN
5V
5V
OUT
5V
R1
0.005Ω
Q1
IRF7457
3V
3V
IN
OUT
3.3V
3.3V
C1
0.047µF
R3
10Ω
R4
10Ω
R5
1k
17
3.3V
16
15
18
13
14
3
3.3V
GATE 3.3V
5V
IN
5V
5V
OUT
IN
SENSE
OUT
SENSE
Z3
Z4
LTC4244*
GND
4244 F12
8
Z3, Z4: SMAJ5.0A
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 12. Place Transient Protection Devices Close to LTC4244’s 5VIN and 3.3VIN Pins
12V
–12V
IN
3.3V
5V
IN
IN
IN
1
2
R13
R14
Z3
12V
V
IN
EEIN
10Ω
10Ω
Z1
Z2
Z4
LTC4244*
GND
C4
0.1µF
C5
0.1µF
VIAS TO
GND PLANE
LTC4244*
Z1
C5
R14
4244 F16
8
Z1, Z2: SMAJ12CA
*ADDITIONAL DETAILS OMITTED FOR CLARITY
C4
4244 F14
Z1
R13
Figure 13. Place Transient Protection Devices
Close to LTC4244’s 12VIN and VEEIN Pins
GND
12V
V
EEIN
IN
*ADDITIONAL DETAILS OMITTED FOR CLARITY
DRAWING IS NOT TO SCALE!
Figure 14. Recommended Layout for Transient Protection
Components
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PCB Layout Considerations
Swap applications where load currents can be 10A, nar-
row PCB tracks exhibit more resistance than wider tracks
and operate at more elevated temperatures. Since the
sheet resistance of 1 ounce copper foil is approximately
For proper operation of the LTC4244’s circuit breaker,
4-wire Kelvin sense connections between the sense resis-
tor and the LTC4244’s 5VIN and 5VSENSE pins and 3.3VIN
and 3.3VSENSE pins are strongly recommended. The PCB
layout should be balanced and symmetrical to minimize
wiring errors. In addition, the PCB layout for the sense
resistors and the power MOSFETs should include good
thermalmanagementtechniquesforoptimaldevicepower
dissipation. A recommended PCB layout for the sense
resistor, the power MOSFET and the GATE drive compo-
nentsaroundtheLTC4244isillustratedinFigure15.InHot
0.45mΩ/ , track resistance and voltage drops add up
o
quickly in high current applications. Thus, to keep PCB
track resistance, voltage drop and temperature to a mini-
mum, the suggested trace width in these applications for
1ouncecopperfoilis0.03”foreachampereofDCcurrent.
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal to
CURRENT FLOW
CURRENT FLOW
TO LOAD
TO LOAD
SENSE
RESISTOR
SO-8
D
D
D
D
G
S
S
S
3.3V
3.3V
3.3V
IN
OUT
W
W
3.3V
VIA/PATH
TO GND
R3
R5
TRACK WIDTH W:
0.03" PER AMPERE
ON 1 OZ Cu FOIL
GATE
C1
LTC4244*
CURRENT FLOW
TO SOURCE
VIA TO
GND PLANE
C
TIMER
GND
W
GND
4244 F15
*ADDITIONAL DETAILS OMITTED FOR CLARITY
DRAWING IS NOT TO SCALE!
Figure 15. Recommended Layout for Power MOSFET, Sense Resistor and GATE Components for the 3.3V Rail
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U
thePCboard.For1ouncecopperfoilplating,ageneralrule
is 1 ampere of DC current per via making sure the via is
properly dimensioned so that solder completely fills the
void. For other plating thicknesses, check with your PCB
fabrication facility.
peraturecurve,thedevice’son-resistancecanbeexpected
toincreasebyabout20%overitsroomtemperaturevalue.
Recalculation of the steady-state values of RON and junc-
tion temperature yields approximately 12.6mΩ and 81°C,
respectively. The I • R drop across the 3.3V sense resistor
and series MOSFET at maximum load current under these
conditions will be less than 124mV.
Design Example
As a design example, consider a CPCI Hot Swap applica-
tion with the following power supply requirements:
The next step is to select appropriate values for C1 and
CTIMER. Assuming that the total current for the 5V supply
is constrained to less than 6A during power-up (6 × 5V
medium length connector pins at 1A per pin), then the
inrush current shouldn’t exceed:
Table 4. Design Example Power Supply Requirements
VOLTAGE
SUPPLY
MAXIMUM DC
SUPPLY CURRENT
LOAD
CAPACITANCE
12V
5V
450mA
5A
100µF
2200µF
2200µF
100µF
IINRUSH < 6A – ILOAD(5VOUT) = 6A – 5A = 1A
(12)
This yields:
3.3V
–12V
7A
100mA
I
GATE(MAX) • 2200µF
C1>
C1>
(13)
IINRUSH(MAX)
The first step is to select the appropriate values of RSENSE
for the 5V and 3.3V supplies. Calculating the value of
RSENSE is based on ILOAD(MAX) and the lower limit for the
circuit breaker threshold voltage (47mV for both the 5V
and 3.3V circuit breakers). If a 1% tolerance is assumed
for the sense resistors, then 5mΩ and 7mΩ resistor
values yield the following minimum and maximum ITRIP
values:
100µA • 2200µF
= 220nF
1A
Hence a C1 value of 330nF ±10% should suffice. The value
of CTIMER for this design example will be constrained by
the duration of the 12V supply inrush current, which
according to Equation 2 is:
Table 5. ITRIP vs RSENSE
2 •CLOAD •12V
LIMIT(MIN) –ILOAD(MAX)
R (1% RTOL)
SENSE
5mΩ
I
I
TRIP(MAX)
TRIP(MIN)
tON(12VOUT)
tON(12VOUT)
<
<
I
9.3A
11.5A
7mΩ
6.6A
8.2A
(14)
2 •100µF •12V
550mA – 450mA
= 24ms
So sense resistor values of 7mΩ and 5mΩ should suffice
for the 5V and 3.3V supplies, respectively.
In order to guarantee that the LTC4244’s TIMER fault
inhibit period is greater than 24ms, the value of CTIMER
should be:
The second step is to select MOSFETs for the 5V and 3.3V
supplies.TheIRF7457’sonresistanceislessthan10.5mΩ
for VGS > 4.5V and a junction temperature of 25°C. Since
the maximum load current requirement for the 3.3V sup-
ply is 7A, the steady-state power the device may be
required to dissipate is 514mW. The IRF7457 has a
junction-to-ambient thermal resistance of 50°C/Watt. If a
maximum ambient temperature of 50°C is assumed, this
yields a junction temperature of 75.7°C. According to the
IRF7457’s Normalized On-Resistance vs Junction Tem-
24ms •ITIMER(MAX)
12V – VTIMER(MAX)
CTIMER
CTIMER
>
>
(15)
24ms • 26µA
12V – 1.9V
= 61.8nF
So a value of 82nF (±10%) should suffice.
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The next step is to verify that the thermal ratings of the
external 5V and 3.3V MOSFETs aren’t being exceeded
during power-up cycles into the designed loads or into a
short circuit.
The duration and magnitude of the power pulse that
results during a short-circuit condition on either the 5V or
3.3VoutputsareafunctionoftheTIMERcapacitorandthe
LTC4244’s foldback current limit. Figure 16 shows the
worst-case power dissipated in the 5V and 3.3V external
FETs vs V5VOUT and V3.3VOUT, respectively. In the case of
the3.3VexternalMOSFET,themaximumdissipatedpower
is24Watts(V3.3VOUT=0.9V).Forthe5VexternalMOSFET,
Theamountofheatinginthe5Vand3.3VMOSFETsduring
anormalpowercycledependsontheLTC4244’sGATEpin
current (refer to Gate Current vs Temperature plot in the
Typical Performance Characteristics section). The magni-
tude of the off-on power pulse that results in maximum
heating of the MOSFETs is given by Equation 10 as:
the maximum dissipated power is 22 Watts (V5VOUT
=
1.75V).Themaximumdurationoftheshort-circuitpower-
pulse is given by Equation 19 as:
nVOUT • IINRUSH(MIN) +ILOAD(nVOUT)
(
)
12V – VTIMER(MIN)
(16)
POFF-ON
where
=
(19)
t
PULSE < CTIMER(MAX) •
2
ITIMER(MIN)
82nF + 8.2nF • 12V – 1.3V
(
<
) (
)
tPULSE
CLOAD
C1(MAX)
16µA
I
=
•IGATE(MIN)
INRUSH(MIN)
(17)
t
PULSE < 60.3ms
The duration of the power-pulse is given by Equation 11
as:
25
20
15
CLOAD •nVOUT
IINRUSH(MIN)
5V R
= 0.007Ω
SENSE
SENSE
tINRUSH
<
3.3V R
= 0.005Ω
(18)
5V MOSFET
Solving these equations for the 5V and 3.3V supplies
yields:
Table 6
10
5
P
t
INRUSH(MAX)
3.3V MOSFET
OFF-ON
5V MOSFET
12.8W
11.8W
90ms
3.3V MOSFET
60ms
0
0
1
2
3
4
5
Under these conditions, the IRF7457 datasheet’s Thermal
Response vs Pulse Duration curve indicates that the
junction-to-ambient temperature will increase by 60°C for
the 5V MOSFET and 46°C for the 3.3V MOSFET.
OUTPUT VOLTAGE (V)
4244 F16
Figure 16. Worst-Case 5V and 3.3V MOSFET
Dissipated Power vs Output Voltage
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TheIRF7457’sThermalResponsevsPulseDurationcurve
indicates that the worst-case increase in junction-to-
ambient temperature during a power-cycle for the 3.3V
MOSFET is less than 96°C while the worst-case increase
in junction-to-ambient temperature for the 5V MOSFET is
less than 88°C.
Transient Voltage Suppressors SMAJ12A and SMAJ5.0A
are supplied by:
Diodes, Incorporated
Westlake Village, CA 91362 USA
Phone: 01 (805) 446-4800
Web Site: http://www.vishay.com or
http://www.diodes.com
Power MOSFET and Sense Resistor Selection
Transistors MMBT2222A and MMBT3906 are supplied
by:
Tables 7 and 8 list current sense resistors and power
MOSFET transistors, respectively, that can be used with
the LTC4244’s circuit breakers. Table 9 lists supplier web
site addresses for discrete components mentioned
throughout the LTC4244 data sheet.
ON Semiconductor
Phoenix, AZ 85008 USA
Phone: 01 (602) 244-6600
Web Site: http://www.onsemi.com
Obtaining Information on Specific Parts
For more information or to request a copy of the
CompactPCIspecification,contactthePCIIndustrialCom-
puter Manufacturers Group at:
PCI Industrial Computer Manufacturers Group
Wakefield, MA 01880 USA
Phone: 01 (718) 224-1239
Web Site: http://www.picmg.com
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Table 7. Sense Resistor Selection Guide
CURRENT LIMIT VALUE
PART NUMBER
DESCRIPTION
MANUFACTURER
1A
LR120601R055F
WSL1206R055
0.055Ω, 0.5W, 1% Resistor
IRC-TT
Vishay Dale
2A
5A
LR120601R028F
WSL1206R028
0.028Ω, 0.5W, 1% Resistor
0.011Ω, 0.5W, 1% Resistor
IRC-TT
Vishay Dale
LR120601R011F
WSL2010R011
IRC-TT
Vishay Dale
7.6A
10A
WSL2512R007
WSL2512R005
0.007Ω, 1W, 1% Resistor
0.005Ω, 1W, 1% Resistor
Vishay Dale
Vishay Dale
Table 8. N-Channel Power MOSFET Selection Guide
CURRENT LIMIT VALUE
PART NUMBER
MMDF3N02HD
MMSF5N02HD
MTB50N06V
IRF7457
DESCRIPTION
Dual N-Channel SO-8, R
MANUFACTURER
ON Semiconductor
ON Semiconductor
ON Semiconductor
International Rectifier
0A to 2A
= 0.1Ω
DS(ON)
2A to 5A
Single N-Channel SO-8, R
= 0.025Ω
DS(ON)
5A to 10A
5A to 10A
Single N-Channel DD-Pak, R
= 0.028Ω
DS(ON)
Single N-Channel SO-8, R
= 0.007Ω
DS(ON)
5A to 10A
Si7880DP
Single N-Channel PowerPAKTM, R
= 0.003 Ω Vishay Siliconix
DS(ON)
PowerPAK is a trademark of Vishay Siliconix
Table 9. Manufacturers’ Web Site
MANUFACTURER
International Rectifier
ON Semiconductor
IRC-TT
WEB SITE
www.irf.com
www.onsemi.com
www.irctt.com
Vishay Dale
www.vishay.com
www.vishay.com
www.diodes.com
Vishay Siliconix
Diodes, Inc.
42441f
26
LTC4244/LTC4244-1
U
PACKAGE DESCRIPTIO
GN Package
20-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.058
(1.473)
REF
.045 ±.005
20 19 18 17 16 15 14 13 12 11
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
1
2
3
4
5
6
7
8
9 10
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
× 45°
(0.38 ± 0.10)
0° – 8° TYP
.0075 – .0098
(0.19 – 0.25)
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
(MILLIMETERS)
2. DIMENSIONS ARE IN
GN20 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
42441f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC4244/LTC4244-1
U
TYPICAL APPLICATIO
C8
C9
0.01µF PER
0.01µF PER
POWER PIN
R2
0.007Ω
Q2
IRF7457
5V
IN
POWER PIN
V
OUT
5V
5V
5A
+
+
R22
C
C
R1
0.005Ω
Q1
2.7Ω
LOAD(5VOUT)
LONG 5V
3.3V
IRF7457
V
OUT
3.3V
IN
3.3V
7A
R21
1.8Ω
Z3
LOAD(3.3VOUT)
C1
LONG 3.3V
R4
10Ω
R3
10Ω
Z4
C7
0.01µF
R5
1k
0.33µF
Z2
3.3V
IN
3.3V
SENSE
GATE 3.3V
OUT
5V
5V
5V
12V
IN
SENSE
OUT
V
OUT
12V
IN
12V
12V
OUT
+
500mA
V
EEIN
C
LOAD(12VOUT)
R19 1k
OFF/ON
FAULT
BD_SEL#
V
R20
1.2k
EEOUT
R18 10k
LTC4244-1
LONG V(I/O)
R17
10k
TIMER
C2
0.082µF
PWRGD
HEALTHY#
PCI_RST#
R6
10k
RESETIN
V
OUT
3.3V
GND PRECHARGE
RESETOUT
R8 1k
DRIVE
Q3
R15
1Ω
C4
LOCAL_PCI_RST#
R9 24Ω
C3 4.7nF
0.01µF
V
IN
3.3V
GROUND
R7 12Ω
R10 18Ω
R11
10k
R12
10k
R13
MMBT2222A
1V
±10%
RESET#
10Ω
I/O DATA LINE 1
I/O #1
I/O PIN 1
PCI
BRIDGE
CHIP
•
•
•
•
•
•
•
•
R14
10Ω
•
I/O #128
I/O DATA LINE 128
I/O PIN 128
Z1, Z2: SMAJ12A Z3, Z4: SMAJ5.0A
4244 F17
Figure 17. Typical LTC4244-1 Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1421
Hot Swap Controller
Dual Supplies from 3V to 12V, Additional –12V
Single Supply Hot Swap in SO-8 from 3V to 12V
Negative High Voltage Supplies from –10V to –80V
Supplies from 9V to 80V, Latch Off/Autoretry
3V to 15V, Overvoltage Protection Up to 33V
3.3V, 5V, 12V, –12V Supplies for PCI Bus
LTC1422
Hot Swap Controller
LT1640AL/LT1640AH
LT1641-1/LT1641-2
LTC1642
Negative Voltage Hot Swap Controllers in SO-8
Positive Voltage Hot Swap Controllers in SO-8
Fault Protected Hot Swap Controller
LTC1643AL/LTC1643AL-1 PCI Bus Hot Swap Controllers
LTC1643AH
LTC1644
LTC1645
LTC1646
LTC1647
LTC4211
LTC4240
LT4250
Compact PCI Bus Hot Swap Controller
2-Channel Hot Swap Controller
3.3V, 5V, ±12V, Local Reset Logic and Precharge
Operates from 1.2V to 12V, Power Sequencing
3.3V, 5V Supplies Only
Dual CompactPCI Hot Swap Controller
Dual Hot Swap Controller
Dual ON Pins for Supplies from 3V to 15V
Hot Swap Controller with Multifunction Current Control
CompactPCI Hot Swap Controller
Single Supply, 2.5V to 16.5V, MSOP
2
I C Interface Allows Control and Readback of Device Functions
–20V to –80V, Active Current Limiting
–48V Hot Swap Controller in SO-8
–48V Hot Swap Controller in SOT-23
LTC4251
Floating Supply, Active Current Limiting and Fast Circuit Breaker
42441f
LT/TP 0204 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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