LTC3809EMS [Linear]
IC 1 A SWITCHING CONTROLLER, 825 kHz SWITCHING FREQ-MAX, PDSO10, PLASTIC, MSOP-10, Switching Regulator or Controller;
| 型号： | LTC3809EMS |
| 厂家： | 
Linear |
| 描述： | IC 1 A SWITCHING CONTROLLER, 825 kHz SWITCHING FREQ-MAX, PDSO10, PLASTIC, MSOP-10, Switching Regulator or Controller 开关 光电二极管 |
| 文件： | 总24页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3809
No RSENSETM, Low EMI,
Synchronous DC/DC Controller
U
FEATURES
DESCRIPTIO
The LTC®3809 is a synchronous step-down switching
regulator controller that drives external complementary
power MOSFETs using few external components. The
constantfrequencycurrentmodearchitecturewithMOSFET
VDS sensing eliminates the need for a current sense
resistor and improves efficiency.
■
No Current Sense Resistor Required
■
Selectable Spread Spectrum Frequency Modulation
for Low Noise Operation
■
Constant Frequency Current Mode Operation for
Excellent Line and Load Transient Response
■
True PLL for Frequency Locking or Adjustment
(Frequency Range: 250kHz to 750kHz)
For noise sensitive applications, the LTC3809 can be ex-
ternallysynchronizedfrom250kHzto750kHz.BurstMode
is inhibited during synchronization or when the SYNC/
MODEpinispulledlowtoreducenoiseandRFinterference.
To further reduce EMI, the LTC3809 incorporates a novel
spread spectrum frequency modulation technique.
■
Wide VIN Range: 2.75V to 9.8V
■
Wide VOUT Range: 0.6V to VIN
■
0.6V ±1.5% Reference
■
Low Dropout Operation: 100% Duty Cycle
Selectable Burst Mode®/Pulse Skipping/Forced
■
Continuous Operation
■
■
■
■
■
■
BurstModeoperationprovideshighefficiencyoperationat
light loads. 100% duty cycle provides low dropout opera-
tion,extendingoperatingtimeinbattery-poweredsystems.
Auxiliary Winding Regulation
Internal Soft-Start Circuitry
Power Good Output Voltage Monitor
Output Overvoltage Protection
Theswitchingfrequencycanbeprogrammedupto750kHz,
allowing the use of small surface mount inductors and
capacitors.
Micropower Shutdown: IQ = 9µA
Tiny Thermally Enhanced Leadless (3mm × 3mm)
DFN and 10-leadUMSOP Packages
The LTC3809 is available in the tiny footprint thermally
enhanced DFN and 10-lead MSOP packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5481178, 5929620, 6580258, 6304066, 5847554,
6611131, 6498466. Other Patents pending.
APPLICATIO S
■
One or Two Lithium-Ion Powered Devices
■
Portable Instruments
■
Distributed DC Power Systems
U
TYPICAL APPLICATIO
Efficiency and Power Loss vs Load Current
100
90
80
70
60
50
10k
High Efficiency, 550kHz Step-Down Converter
EFFICIENCY
V
= 3.3V
IN
V
1k
IN
2.75V TO 9.8V
V
IN
= 4.2V
V
IN
= 5V
10µF
LTC3809
100
10
V
IN
PLLLPF
POWER LOSS
= 4.2V
SYNC/MODE TG
V
IN
59k
2.2µH
47µF
V
OUT
V
FB
SW
2.5V
2A
15k
1
I
TH
BG
187k
FIGURE 10 CIRCUIT
RUN
IPRG
470pF
V
= 2.5V
OUT
GND
0.1
10000
1
10
100
1000
LOAD CURRENT (mA)
3809 TA01
3809 TA01b
3809f
1
LTC3809
W W
U W
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (VIN)........................ –0.3V to 10V
PLLLPF, RUN, SYNC/MODE,
IPRG Voltages .............................. –0.3V to (VIN + 0.3V)
VFB, ITH Voltages...................................... –0.3V to 2.4V
SW Voltage ......................... –2V to VIN + 1V (10V Max)
TG, BG Peak Output Current (<10µs)........................ 1A
Operating Temperature Range (Note 2)... – 40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
Junction Temperature (Note 3)............................ 125°C
Lead Temperature (Soldering, 10 sec)
MSOP Package ................................................. 300°C
U
W U
PACKAGE/ORDER INFORMATION
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
PLLLPF
1
2
3
4
5
10 SW
PLLLPF
1
2
3
4
5
10 SW
SYNC/MODE
9
8
7
6
V
LTC3809EDD
IN
LTC3809EMS
SYNC/MODE
9
8
7
6
V
IN
11
V
TG
FB
V
I
TG
11
FB
I
BG
TH
BG
IPRG
TH
RUN
RUN
IPRG
DD PART
MARKING
MS PART
MARKING
MS PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 130°C/W
LBQY
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND
(MUST BE SOLDERED TO PCB)
EXPOSED PAD (PIN 11) IS GND
(MUST BE SOLDERED TO PCB)
LTBQT
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
Input DC Supply Current
Normal Operation
Sleep Mode
Shutdown
UVLO
(Note 4)
350
105
9
500
150
20
µA
µA
µA
µA
RUN = 0V
V
= UVLO Threshold – 200mV
3
10
IN
Undervoltage Lockout Threshold (UVLO)
V
V
Falling
Rising
●
●
1.95
2.15
2.25
2.45
2.55
2.75
V
V
IN
IN
Shutdown Threshold of RUN Pin
Regulated Feedback Voltage
0.8
1.1
0.6
1.4
0.609
0.04
V
V
(Note 5)
2.75V < V < 9.8V (Note 5)
●
0.591
Output Voltage Line Regulation
Output Voltage Load Regulation
0.01
%/V
IN
I
I
= 0.9V (Note 5)
= 1.7V
0.1
–0.1
0.5
–0.5
%
%
TH
TH
V
Input Current
(Note 5)
9
50
nA
V
FB
Overvoltage Protect Threshold
Measured at V
0.66
0.68
0.7
FB
3809f
2
LTC3809
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
20
MAX
UNITS
mV
V
Overvoltage Protect Hysteresis
Auxiliary Feedback Threshold
Top Gate (TG) Drive Rise Time
Top Gate (TG) Drive Fall Time
Bottom Gate (BG) Drive Rise Time
Bottom Gate (BG) Drive Fall Time
Maximum Current Sense Voltage (∆V
0.325
0.4
40
0.475
C = 3000pF
L
ns
C = 3000pF
L
40
ns
CL = 3000pF
CL = 3000pF
50
ns
40
ns
)
IPRG = Floating (Note 6)
IPRG = 0V (Note 6)
●
●
●
110
70
185
125
85
204
140
100
223
mV
mV
mV
SENSE(MAX)
+
(SENSE – SW)
IPRG = V (Note 6)
IN
Soft-Start Time (Internal)
Oscillator and Phase-Locked Loop
Oscillator Frequency
Time for V to Ramp from 0.05V to 0.55V
0.5
0.74
0.9
ms
FB
Unsynchronized (SYNC/MODE Not Clocked)
PLLLPF = Floating
PLLLPF = 0V
480
260
650
550
300
750
600
340
825
kHz
kHz
kHz
PLLLPF = V
IN
Phase-Locked Loop Lock Range
SYNC/MODE Clocked
Minimum Synchronizable Frequency
Maximum Synchronizible Frequency
200
1000
250
kHz
kHz
750
Phase Detector Output Current
Sinking
Sourcing
f
f
> f
< f
–3
3
µA
µA
OSC
OSC
SYNC/MODE
SYNC/MODE
Spread Spectrum Frequency Range
SYNC/MODE Pull-Down Current
Minimum Switching Frequency
Maximum Switching Frequency
460
635
kHz
kHz
SYNC/MODE = 2.2V
2.6
µA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 2: The LTC3809E is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the –40°C to 85°C operating range are
assured by design characterization, and correlation with statistical process
controls.
Note 5: The LTC3809 is tested in a feedback loop that servos I to a
TH
specified voltage and measures the resultant V voltage.
FB
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 1.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
T = T + (P • θ °C/W)
J
A
D
JA
3809f
3
LTC3809
TYPICAL PERFOR A CE CHARACTERISTICS
U W
TA = 25°C unless otherwise noted.
Maximum Current Sense Voltage
vs ITH Pin Voltage
Efficiency vs Load Current
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
55
50
100
80
60
40
20
0
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
Burst Mode OPERATION
V
= 2.5V
OUT
V
IN
= 5V, V = 2.5V
(I RISING)
OUT
TH
Burst Mode OPERATION
V
= 3.3V
OUT
(I FALLING)
TH
FORCED CONTINUOUS
MODE
BURST MODE
(SYNC/MODE =
PULSE SKIPPING
MODE
V
= 1.2V
OUT
V )
IN
FORCED
CONTINUOUS
(SYNC/MODE = 0V)
V
= 1.8V
OUT
PULSE SKIPPING
(SYNC/MODE = 0.6V)
SYNC/MODE = V
IN
V
= 5V
IN
–20
1
10
100
1k
10k
1
10
100
1k
10k
0.5
1
I
TH
1.5
VOLTAGE (V)
2
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3809 G01
3809 G02
3809 G03
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
V
V
OUT
OUT
200mV/DIV
200mV/DIV
AC COUPLED
AC COUPLED
I
I
L
L
2A/DIV
2A/DIV
3809 G04
3809 G05
100µs/DIV
100µs/DIV
V
V
LOAD
= 3.3V
OUT
V
= 3.3V
IN
IN
= 1.8V
V
= 1.8V
OUT
LOAD
I
= 300mA TO 3A
IN
FIGURE 10 CIRCUIT
I
= 300mA TO 3A
SYNC/MODE = V
SYNC/MODE = 0V
FIGURE 10 CIRCUIT
Start-Up with Internal Soft-Start
Load Step (Pulse Skipping Mode)
V
OUT
200mV/DIV
AC COUPLED
V
OUT
1.8V
500mV/DIV
I
L
2A/DIV
3809 G06
3809 G07
100µs/DIV
200µs/DIV
V
V
LOAD
= 3.3V
OUT
V
R
= 4.2V
IN
IN
= 1.8V
= 1Ω
LOAD
FIGURE 10 CIRCUIT
I
= 300mA TO 3A
FB
FIGURE 10 CIRCUIT
SYNC/MODE = V
3809f
4
LTC3809
U W
TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
Regulated Feedback Voltage
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
1.20
1.15
1.10
1.05
1.00
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
0.606
0.604
0.602
0.600
0.598
0.596
0.594
V
IN
RISING
V
FALLING
IN
40 60
–60 –40 –20
TEMPERATURE (°C)
0
20
80 100
40 60
–60 –40 –20
TEMPERATURE (°C)
40 60
TEMPERATURE (°C)
0
20
80 100
–60 –40 –20
0
20
80 100
3809 G10
3809 G08
3809 G09
SYNC/MODE Pull-Down Current
vs Temperature
Maximum Current Sense
Threshold vs Temperature
Oscillator Frequency
vs Temperature
2.80
2.75
2.70
2.65
2.60
2.55
2.50
2.45
2.40
10
8
135
130
125
120
115
IPRG = FLOAT
6
4
2
0
–2
–4
–6
–8
–10
40 60
–60 –40 –20
TEMPERATURE (°C)
0
20
80 100
40 60
–60 –40 –20
TEMPERATURE (°C)
0
20
80 100
40 60
TEMPERATURE (°C)
–60 –40 –20
0
20
80 100
3809 G12
3809 G13
3809 G11
Oscillator Frequency
vs Input Voltage
Shutdown Quiescent Current
vs Input Voltage
Sleep Current vs Input Voltage
5
4
18
16
14
12
10
8
130
120
110
100
90
3
2
1
0
–1
–2
–3
–4
–5
6
4
80
2
0
70
7
8
7
8
2
3
4
5
6
9
10
2
3
4
5
6
9
10
7
8
2
3
4
5
6
9
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3809 G14
3809 G15
3809 G16
3809f
5
LTC3809
U
U
U
PI FU CTIO S
PLLLPF (Pin 1): Frequency Set/PLL Lowpass Filter. When
synchronizing to an external clock, this pin serves as the
low pass filter point for the phase-locked loop. Normally,
a series RC is connected between this pin and ground.
RUN (Pin 5): Run Control Input. Forcing this pin below
1.1V shuts down the chip. Driving this pin to VIN or
releasing this pin enables the chip to start-up with the
internal soft-start.
Whennotsynchronizingtoanexternalclock,thispinserves
asthefrequencyselectinput. TyingthispintoGNDselects
300kHz operation; tying this pin to VIN selects 750kHz
operation. Floating this pin selects 550kHz operation.
IPRG (Pin 6): Three-State Pin to Select Maximum Peak
Sense Voltage Threshold. This pin selects the maximum
allowed voltage drop between the VIN and SW pins (i.e.,
the maximum allowed drop across the external P-channel
MOSFET). Tie to VIN, GND or float to select 204mV, 85mV
or 125mV respectively.
Connect a 2.2nF capacitor between this pin and GND, and
a 1000pF capacitor between this pin and the SYNC/MODE
when using spread spectrum modulation operation.
BG (Pin 7): Bottom (NMOS) Gate Drive Output. This pin
drivesthegateoftheexternalN-channelMOSFET.Thispin
has an output swing from PGND to VIN.
SYNC/MODE (Pin 2): This pin performs four functions: 1)
auxiliary winding feedback input, 2) external clock syn-
chronization input for phase-locked loop, 3) Burst Mode,
pulse skipping or forced continuous mode select, and 4)
enable spread spectrum modulation operation in pulse
skipping mode. Applying a clock with frequency between
250kHz to 750kHz causes the internal oscillator to phase-
lock to the external clock and disables Burst Mode opera-
tion but allows pulse skipping at low load currents.
TG (Pin 8):Top (PMOS) Gate Drive Output. This pin drives
thegateoftheexternalP-channelMOSFET.Thispinhasan
output swing from PGND to VIN.
VIN (Pin9):ChipSignalPowerSupply.Thispinpowersthe
entire chip, the gate drivers and serves as the positive
input to the differential current comparator.
SW (Pin 10): Switch Node Connection to Inductor. This
pin is also the negative input to the differential current
comparator and an input to the reverse current compara-
tor. Normally this pin is connected to the drain of the
external P-channel MOSFET, the drain of the external
N-channel MOSFET and the inductor.
To select Burst Mode operation at light loads, tie this pin
to VIN. Grounding this pin selects forced continuous
operation, which allows the inductor current to reverse.
Tying this pin to VFB selects pulse skipping mode. In these
cases, the frequency of the internal oscillator is set by the
voltage on the PLLLPF pin. Tying to a voltage between
1.35V to VIN – 0.5V enables spread spectrum modulation
operation. In this case, an internal 2.6µA pull-down cur-
rent source helps to set the voltage at this pin by tying a
resistor with appropriate value between this pin and VIN.
Do not leave this pin floating.
GND (Pin 11): Exposed Pad. The Exposed Pad is ground
and must be soldered to the PCB ground for electrical
contact and optimum thermal performance.
VFB (Pin 3): Feedback Pin. This pin receives the remotely
sensed feedback voltage for the controller from an exter-
nal resistor divider across the output.
ITH (Pin 4): Current Threshold and Error Amplifier Com-
pensation Point. Nominal operating range on this pin is
from 0.7V to 2V. The voltage on this pin determines the
threshold of the main current comparator.
3809f
6
LTC3809
U
U
W
FU CTIO AL DIAGRA
V
IN
C
IN
9
V
IN
6
IPRG
VOLTAGE
REFERENCE
V
REF
0.6V
SLOPE
+
TG
SW
BG
CLK
S
R
8
10
7
MP
+
–
Q
GND
ICMP
UNDERVOLTAGE
LOCKOUT
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
SENSE
L
ANTI-SHOOT-
THROUGH
V
OUT
C
OUT
V
IN
PV
IN
V
IN
MN
UVSD
0.7µA
RUN
5
+
–
FCB
SLEEP
V
IN
+
–
0.15V
t = 1ms
OV
REV
INTERNAL
I
SOFT-START
SS
0.68V
0.54V
BURSTDIS
R
B
GND
11
2
0.3V
+
+
–
BURST DEFEAT
CLOCK DETECT
BURSTDIS
FCB
SYNC/MODE
UV
PHASE
–
V
FB
DETECTOR
0.4V
2.6µA
I
TH
4
3
R
C
V
REF
+
+
–
C
0.6V
SS
C
PLLLPF
1
EAMP
V
FB
V
CO
R
A
CLK
3809 FD
SW
+
–
I
RICMP
REV
GND
3809f
7
LTC3809
U
(Refer to Functional Diagram)
OPERATIO
Main Control Loop
Light Load Operation (Burst Mode Operation,
Continuous Conduction or Pulse Skipping Mode)
(SYNC/MODE Pin)
The LTC3809 uses a constant frequency, current mode
architecture. During normal operation, the top external
P-channel power MOSFET is turned on when the clock
sets the RS latch, and is turned off when the current
comparator (ICMP) resets the latch. The peak inductor
currentatwhichICMPresetstheRSlatchisdeterminedby
the voltage on the ITH pin, which is driven by the output of
theerroramplifier(EAMP).TheVFB pinreceivestheoutput
voltage feedback signal from an external resistor divider.
This feedback signal is compared to the internal 0.6V
reference voltage by the EAMP. When the load current
increases, it causes a slight decrease in VFB relative to the
0.6V reference, which in turn causes the ITH voltage to
increase until the average inductor current matches the
new load current. While the top P-channel MOSFET is off,
thebottomN-channelMOSFETisturnedonuntileitherthe
inductor current starts to reverse, as indicated by the
current reversal comparator IRCMP, or the beginning of
the next cycle.
The LTC3809 can be programmed for either high effi-
ciency Burst Mode operation, forced continuous conduc-
tion mode or pulse skipping mode at low load currents. To
select Burst Mode operation, tie the SYNC/MODE pin to
VIN. To select forced continuous operation, tie the SYNC/
MODE pin to a DC voltage below 0.4V (e.g., GND). Tying
the SYNC/MODE to a DC voltage above 0.4V and below
1.2V (e.g., VFB) enables pulse skipping mode. The 0.4V
threshold between forced continuous operation and pulse
skipping mode can be used in secondary winding regula-
tion as described in the Auxiliary Winding Control Using
SYNC/MODE Pin discussion in the Applications Informa-
tion section.
When the LTC3809 is in Burst Mode operation, the peak
current in the inductor is set to approximately one-fourth
of the maximum sense voltage even though the voltage on
the ITH pin indicates a lower value. If the average inductor
current is higher than the load current, the EAMP will
decrease the voltage on the ITH pin. When the ITH voltage
drops below 0.85V, the internal SLEEP signal goes high
and the external MOSFET is turned off.
Shutdown and Soft-Start (RUN Pin)
The LTC3809 is shut down by pulling the RUN pin low. In
shutdown, all controller functions are disabled and the
chip draws only 9µA. The TG output is held high (off) and
the BG output low (off) in shutdown. Releasing the RUN
pin allows an internal 0.7µA current source to pull up the
RUNpintoVIN.ThecontrollerisenabledwhentheRUNpin
reaches 1.1V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3809 draws.
Theloadcurrentissuppliedbytheoutputcapacitor.Asthe
output voltage decreases, the EAMP increases the ITH
voltage. When the ITH voltage reaches 0.925V, the SLEEP
signal goes low and the controller resumes normal opera-
tion by turning on the external P-channel MOSFET on the
next cycle of the internal oscillator.
The start-up of VOUT is controlled by the LTC3809’s
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal VFB to the internal
soft-start ramp (instead of the 0.6V reference), which
rises linearly from 0V to 0.6V in about 1ms. This allows
the output voltage to rise smoothly from 0V to its final
value while maintaining control of the inductor current.
When the controller is enabled for Burst Mode or pulse
skipping operation, the inductor current is not allowed to
reverse. Hence, the controller operates discontinuously.
3809f
8
LTC3809
U
(Refer to Functional Diagram)
OPERATIO
The reverse current comparator RICMP senses the drain-
to-source voltage of the bottom external N-channel
MOSFET. This MOSFET is turned off just before the
inductor current reaches zero, preventing it from going
negative.
Short-Circuit and Current Limit Protection
The LTC3809 monitors the voltage drop ∆VSC (between
the GND and SW pins) across the external N-channel
MOSFET with the short-circuit current limit comparator.
The allowed voltage is determined by:
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions.Thepeakinductorcurrentisdeterminedbythe
voltageontheITH pin. TheP-channelMOSFETisturnedon
every cycle (constant frequency) regardless of the ITH pin
voltage. In this mode, the efficiency at light loads is lower
than in Burst Mode operation. However, continuous mode
has the advantages of lower output ripple and no noise at
audio frequencies.
∆VSC(MAX) = A • 90mV
where A is a constant determined by the state of the IPRG
pin. Floating the IPRG pin selects A = 1; tying IPRG to VIN
selects A = 5/3; tying IPRG to GND selects A = 2/3.
The inductor current limit for short-circuit protection is
determined by ∆VSC(MAX) and the on-resistance of the
external N-channel MOSFET:
∆VSC(MAX)
RDS(ON)
When the SYNC/MODE pin is clocked by an external clock
source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop), or is set to a DC
voltage between 0.4V and several hundred mV below VIN,
the LTC3809 operates in PWM pulse skipping mode at
light loads. In this mode, the current comparator ICMP
may remain tripped for several cycles and force the
external P-channel MOSFET to stay off for the same
number of cycles. The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuousoperation, exhibitslowoutputrippleaswellas
low audio noise and reduced RF interference as compared
to Burst Mode operation. However, it provides low current
efficiency higher than forced continuous mode, but not
nearlyashighasBurstModeoperation. Duringstart-upor
an undervoltage condition (VFB ≤ 0.54V), the LTC3809
operates in pulse skipping mode (no current reversal
allowed), regardless of the state of the SYNC/MODE pin.
ISC
=
Once the inductor current exceeds ISC, the short current
comparator will shut off the external P-channel MOSFET
until the inductor current drops below ISC.
Output Overvoltage Protection
As further protection, the overvoltage comparator (OVP)
guardsagainsttransientovershoots,aswellasothermore
serious conditions that may overvoltage the output. When
the feedback voltage on the VFB pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
3809f
9
LTC3809
U
(Refer to Functional Diagram)
OPERATIO
Frequency Selection and Phase-Locked Loop
oscillator frequency fOSC (= 550kHz) over a wider range
(460kHz to 635kHz), reducing the peaks of the harmonic
output on a spectral analysis of the output noise. In this
case, a 2.2nF filter cap should be connected between the
PLLLPF pin and GND and another 1000pF cap should be
connected between PLLLPF and the SYNC/MODE pin. The
controller operates in PWM pulse skipping mode at light
loads when spread spectrum modulation is selected. See
thediscussionofSpreadSpectrumModulationwithSYNC/
MODE and PLLLPF Pins in the Applications Information
section.
(PLLLPF and SYNC/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage.
The switching frequency of the LTC3809’s controllers can
be selected using the PLLLPF pin. If the SYNC/MODE is
not being driven by an external clock source, the PLLLPF
can be floated, tied to VIN or tied to GND to select 550kHz,
750kHz or 300kHz, respectively.
Dropout Operation
A phase-locked loop (PLL) is available on the LTC3809 to
synchronize the internal oscillator to an external clock
source that connects to the SYNC/MODE pin. In this case,
a series RC should be connected between the PLLLPF pin
and GND to serve as the PLL’s loop filter. The LTC3809
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the external P-channel MOSFET to the
rising edge of the synchronizing signal.
When the input supply voltage (VIN) approaches the
output voltage, the rate of change of the inductor current
while the external P-channel MOSFET is on
(ON cycle) decreases. This reduction means that the
P-channel MOSFET will remain on for more than one
oscillator cycle if the inductor current has not ramped up
to the threshold set by the EAMP on the ITH pin. Further
reduction in the input supply voltage will eventually cause
the P-channel MOSFET to be turned on 100%; i.e., DC.
The output voltage will then be determined by the input
voltage minus the voltage drop across the P-channel
MOSFET and the inductor.
The typical capture range of the LTC3809’s phase-locked
loop is from approximately 200kHz to 1MHz.
Spread Spectrum Modulation (SYNC/MODE and
PLLLPF Pins)
Undervoltage Lockout
Connecting the SYNC/MODE pin to a DC voltage above
1.35V and several hundred mV below VIN enables spread
spectrum modulation (SSM) operation. An internal 2.6µA
pull-down current source at SYNC/MODE helps to set the
voltage at the SYNC/MODE pin for this operation by tying
a resistor with appropriate value between SYNC/MODE
and VIN. This mode of operation spreads the internal
To prevent operation of the P-channel MOSFET below
safe input voltage levels, an undervoltage lockout is
incorporated in the LTC3809. When the input supply
voltage (VIN) drops below 2.25V, the external P- and
N-channel MOSFETs and all internal circuits are turned
off except for the undervoltage block, which draws only
a few microamperes.
3809f
10
LTC3809
U
(Refer to Functional Diagram)
OPERATIO
Peak Current Sense Voltage Selection and Slope
maximum sense voltage allowed across the external
P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG pin.
Compensation (IPRG Pin)
WhentheLTC3809controllerisoperatingbelow20%duty
cycle, thepeakcurrentsensevoltage(betweentheVIN and
SW pins) allowed across the external P-channel MOSFET
is determined by:
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peaksensevoltagebyascalefactor(SF)givenbythecurve
in Figure 1.
V
ITH – 0.7V
∆VSENSE(MAX) = A •
Thepeakinductorcurrentisdeterminedbythepeaksense
voltage and the on-resistance of the external P-channel
MOSFET:
10
where A is a constant determined by the state of the IPRG
pin. Floating the IPRG pin selects A = 1; tying IPRG to VIN
selects A = 5/3; tying IPRG to GND selects A = 2/3. The
maximum value of VITH is typically about 1.98V, so the
∆VSENSE(MAX)
IPK
=
RDS(ON)
110
100
90
80
70
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3809 F01
Figure 1. Maximum Peak Current vs Duty Cycle
3809f
11
LTC3809
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APPLICATIO S I FOR ATIO
The typical LTC3809 application circuit is shown in
Figure 10. External component selection for the controller
is driven by the load requirement and begins with the
selection of the inductor and the power MOSFETs.
where IRIPPLE is the inductor peak-to-peak ripple current
(see Inductor Value Calculation).
A reasonable starting point is setting ripple current IRIPPLE
to be 40% of IOUT(MAX). Rearranging the above equation
yields:
Power MOSFET Selection
∆VSENSE(MAX)
IOUT(MAX)
5
6
The LTC3809’s controller requires two external power
MOSFETs: a P-channel MOSFET for the topside (main)
switch and a N-channel MOSFET for the bottom (synchro-
nous) switch. The main selection criteria for the power
MOSFETs are the breakdown voltage VBR(DSS), threshold
voltage VGS(TH), on-resistance RDS(ON), reverse transfer
capacitance CRSS, turn-off delay tD(OFF) and the total gate
charge QG.
RDS(ON)MAX
=
•
for Duty Cycle < 20%
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of RDS(ON) to provide the required
amount of load current:
∆VSENSE(MAX)
IOUT(MAX)
5
6
RDS(ON)MAX
=
• SF •
Thegatedrivevoltageistheinputsupplyvoltage.Sincethe
LTC3809 is designed for operation down to low input
voltages, a sublogic level MOSFET (RDS(ON) guaranteed at
VGS = 2.5V) is required for applications that work close to
this voltage. When these MOSFETs are used, make sure
that the input supply to the LTC3809 is less than the
absolute maximum MOSFET VGS rating, which is typically
8V.
whereSFisascalefactorwhosevalueisobtainedfromthe
curve in Figure 1.
These must be further derated to take into account the
significant variation in on-resistance with temperature.
Thefollowingequationisagoodguidefordeterminingthe
required RDS(ON)MAX at 25°C (manufacturer’s specifica-
tion), allowing some margin for variations in the LTC3809
and external component values:
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average load
current IOUT(MAX) is equal to the peak inductor current
minus half the peak-to-peak ripple current IRIPPLE. The
LTC3809’s current comparator monitors the drain-to-
source voltage VDS of the top P-channel MOSFET, which
is sensed between the VIN and SW pins. The peak inductor
current is limited by the current threshold, set by the
voltage on the ITH pin, of the current comparator. The
voltage on the ITH pin is internally clamped, which limits
the maximum current sense threshold ∆VSENSE(MAX) to
approximately 125mV when IPRG is floating (85mV when
IPRG is tied low; 204mV when IPRG is tied high).
∆VSENSE(MAX)
IOUT(MAX) • ρT
5
6
RDS(ON)MAX
=
• 0.9 • SF •
The ρT is a normalizing term accounting for the tempera-
ture variation in on-resistance, which is typically about
0.4%/°C, asshowninFigure2. Junction-to-casetempera-
ture TJC is about 10°C in most applications. For a maxi-
mum ambient temperature of 70°C, using ρ80°C ~ 1.3 in
the above equation is a reasonable choice.
The N-channel MOSFET’s on resistance is chosen based
on the short-circuit current limit (ISC). The LTC3809’s
short-circuitcurrentlimitcomparatormonitorsthedrain-
to-source voltage VDS of the bottom N-channel MOSFET,
which is sensed between the GND and SW pins. The
The output current that the LTC3809 can provide is given
by:
∆VSENSE(MAX)
IRIPPLE
IOUT(MAX)
=
–
RDS(ON)
2
3809f
12
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2.0
1.5
1.0
0.5
0
VOUT
Top P-Channel Duty Cycle =
V
IN
V – VOUT
IN
Bottom N-Channel Duty Cycle =
V
IN
The MOSFET power dissipations at maximum output
current are:
VOUT
V
IN
2
PTOP
=
•IOUT(MAX)2 •ρT •RDS(ON) + 2•V
IN
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
•IOUT(MAX) •CRSS • f
V – VOUT
3809 F02
IN
PBOT
=
•IOUT(MAX)2 •ρT •RDS(ON)
Figure 2. RDS(ON) vs Temperature
V
IN
Both MOSFETs have I2R losses and the PTOP equation
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The bottom MOSFET losses
are greatest at high input voltage or during a short-circuit
when the bottom duty cycle is 100%.
short-circuit current sense threshold ∆VSC is set approxi-
mately 90mV when IPRG is floating (60mV when IPRG is
tied low; 150mV when IPRG is tied high). The on-resis-
tance of N-channel MOSFET is determined by:
∆VSC
ISC(PEAK)
RDS(ON)MAX
=
The LTC3809 utilizes a non-overlapping, anti-shoot-
through gate drive control scheme to ensure that the P-
and N-channel MOSFETs are not turned on at the same
time. To function properly, the control scheme requires
that the MOSFETs used are intended for DC/DC switching
applications. Many power MOSFETs, particularly P-chan-
nel MOSFETs, are intended to be used as static switches
and therefore are slow to turn on or off.
The short-circuit current limit (ISC(PEAK)) should be larger
than the IOUT(MAX) with some margin to avoid interfering
with the peak current sensing loop. On the other hand, in
order to prevent the MOSFETs from excessive heating and
the inductor from saturation, ISC(PEAK) should be smaller
than the minimum value of their current ratings. A reason-
able range is:
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (QG)
less than 25nC to 30nC (at 4.5VGS) and a turn-off delay
(tD(OFF)) of less than approximately 140ns. However, due
to differences in test and specification methods of various
MOSFET manufacturers, and in the variations in QG and
tD(OFF) withgatedrive(VIN)voltage,theP-channelMOSFET
ultimately should be evaluated in the actual LTC3809
application circuit to ensure proper operation.
IOUT(MAX) < ISC(PEAK) < IRATING(MIN)
Therefore,theon-resistanceofN-channelMOSFETshould
be chosen within the following range:
∆VSC
IRATING(MIN)
∆VSC
IOUT(MAX)
< RDS(ON)
<
where ∆VSC is 90mV, 60mV or 150mV with IPRG being
floated, tied to GND or VIN respectively.
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
input supply current. As the input supply voltage in-
creases,iftheinputsupplycurrentincreasesdramatically,
then the likely cause is shoot-through. Note that some
The power dissipated in the MOSFET strongly depends on
its respective duty cycles and load current. When the
LTC3809isoperatingincontinuousmode, thedutycycles
for the MOSFETs are:
3809f
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LTC3809
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APPLICATIO S I FOR ATIO
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
MOSFETsthatdonotworkwellathighinputvoltages(e.g.,
VIN > 5V) may work fine at lower voltages (e.g., 3.3V).
Selecting the N-channel MOSFET is typically easier, since
for a given RDS(ON), the gate charge and turn-on and turn-
off delays are much smaller than for a P-channel MOSFET.
V – VOUT VOUT
IN
Operating Frequency and Synchronization
L ≥
•
fOSC •IRIPPLE
V
IN
The choice of operating frequency, fOSC, is a trade-off
between efficiency and component size. Low frequency
operationimprovesefficiencybyreducingMOSFETswitch-
ing losses, both gate charge loss and transition loss.
However, lowerfrequencyoperationrequiresmoreinduc-
tance for a given amount of ripple current.
Burst Mode Operation Considerations
The choice of RDS(ON) and inductor value also determines
the load current at which the LTC3809 enters Burst Mode
operation. When bursting, the controller clamps the peak
inductor current to approximately:
The internal oscillator for the LTC3809’s controller runs at
a nominal 550kHz frequency when the PLLLPF pin is left
floating and the SYNC/MODE pin is not configured for
spread spectrum operation. Pulling the PLLLPF to VIN
selects 750kHz operation; pulling the PLLLPF to GND
selects 300kHz operation.
∆VSENSE(MAX)
1
4
IBURST(PEAK)
=
•
RDS(ON)
Thecorrespondingaveragecurrentdependsontheamount
of ripple current. Lower inductor values (higher IRIPPLE
)
Alternatively,theLTC3809willphase-locktoaclocksignal
applied to the SYNC/MODE pin with a frequency between
250kHz and 750kHz (see Phase-Locked Loop and Fre-
quency Synchronization).
willreducetheloadcurrentatwhichBurstModeoperation
begins.
The ripple current is normally set so that the inductor
current is continuous during the burst periods. Therefore,
To further reduce EMI, the nominal 550kHz frequency will
be spread over a range with frequencies between 460kHz
and 635kHz when spread spectrum modulation is
enabled (see Spread Spectrum Modulation with
SYNC/MODE and PLLLPF Pins).
IRIPPLE ≤ IBURST(PEAK)
This implies a minimum inductance of:
V – VOUT
fOSC •IBURST(PEAK)
VOUT
V
IN
IN
LMIN
≤
•
Inductor Value Calculation
A smaller value than LMIN could be used in the circuit,
although the inductor current will not be continuous
during burst periods, which will result in slightly lower
efficiency. In general, though, it is a good idea to keep
Given the desired input and output voltages, the inductor
value and operating frequency, fOSC, directly determine
the inductor’s peak-to-peak ripple current:
VOUT V – VOUT
I
RIPPLE comparable to IBURST(PEAK)
.
IN
fOSC •L
IRIPPLE
=
•
V
IN
Inductor Core Selection
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
Once the value of L is known, the type of inductor must be
selected.Highefficiencyconvertersgenerallycannotafford
the core loss found in low cost powdered iron cores, forc-
ingtheuseofmoreexpensiveferrite,molypermalloyorKool
Mµ® cores. Actual core loss is independent of core size for
Kool Mµ is a registered trademark of Magnetics, Inc.
3809f
14
LTC3809
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APPLICATIO S I FOR ATIO
U
a fixed inductor value, but is very dependent on the induc-
tance selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
1/2
VOUT • V – V
(
)
IN
OUT
CINRequiredIRMS ≈IMAX
•
Ferritedesignshaveverylowcorelossesandarepreferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard”, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. Core saturation results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
V
IN
This formula has a maximum value at VIN = 2VOUT, where
RMS = IOUT/2. This simple worst-case condition is com-
I
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethatcapacitormanufacturer’s
ripplecurrentratingsareoftenbasedon2000hoursoflife.
This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet the
size or height requirements in the design. Due to the high
operating frequency of the LTC3809, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when several layers of wire can be used, while
inductors wound on bobbins are generally easier to sur-
face mount. However, designs for surface mount that do
not increase the height significantly are available from
Coiltronics, Coilcraft, Dale and Sumida.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
Schottky Diode Selection (Optional)
⎛
⎝
1
⎞
∆VOUT ≈ IRIPPLE • ESR +
⎜
⎟
⎠
The schottky diode D in Figure 11 conducts current during
the dead time between the conduction of the power
MOSFETs. This prevents the body diode of the bottom
N-channel MOSFET from turning on and storing charge
during the dead time, which could cost as much as 1% in
efficiency. A 1A Schottky diode is generally a good size for
most LTC3809 applications, since it conducts a relatively
small average current. Larger diode results in additional
transition losses due to its larger junction capacitance.
This diode may be omitted if the efficiency loss can be
tolerated.
8• f •COUT
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since IRIPPLE increase with input voltage.
Setting Output Voltage
The LTC3809 output voltage is set by an external feedback
resistor divider carefully placed across the output, as
shown in Figure 3. The regulated output voltage is deter-
mined by:
CIN and COUT Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (VOUT/VIN). To
preventlargevoltagetransients, alowESRinputcapacitor
⎛
⎝
RB ⎞
RA ⎠
VOUT = 0.6V • 1+
⎜
⎟
3809f
15
LTC3809
APPLICATIO S I FOR ATIO
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V
OUT
is an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
R
C
FF
B
LTC3809
V
FB
R
A
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
MODE, is shown in Figure 5 and specified in the electrical
characteristics table. Note that the LTC3809 can only be
synchronizedtoanexternalclockwhosefrequencyiswithin
range of the LTC3809’s internal VCO, which is nominally
200kHzto1MHz.Thisisguaranteed,overtemperatureand
process variations, to be between 250kHz and 750kHz. A
simplified block diagram is shown in Figure 6.
3809 F03
Figure 3. Setting Output Voltage
For most applications, a 59k resistor is suggested for RA.
In applications where minimizing the quiescent current is
critical, RA should be made bigger to limit the feedback
divider current. If RB then results in very high impedance,
it may be beneficial to bypass RB with a 50pF to 100pF
capacitor CFF.
Run and Soft-Start Functions
The LTC3809 has a low power shutdown mode which is
controlled by the RUN pin. Pulling the RUN pin below 1.1V
puts the LTC3809 into a low quiescent current shutdown
mode (IQ = 9µA). Releasing the RUN pin, an internal 0.7µA
(at VIN = 4.2V) current source will pull the RUN pin up to
VIN, which enables the controller. The RUN pin can be
driven directly from logic as showed in Figure 4.
1200
1000
800
600
400
200
0
Once the controller is enabled, the start-up of VOUT is
controlled by the internal soft-start, which slowly ramps
the positive reference to the error amplifier from 0V to
0.6V, allowing VOUT to rise smoothly from 0V to its final
value. The default internal soft-start time is around 1ms.
0.2
0.7
1.2
1.7
2.2
PLLLPF PIN VOLTAGE (V)
3809 F05
Figure 5. Relationship Between Oscillator Frequency
and Voltage at the PLLLPF Pin When Synchronizing to
an External Clock
3.3V OR 5V
LTC3809
RUN
LTC3809
RUN
2.4V
R
LP
3809 F04
C
LP
PLLLPF
SYNC/
MODE
Figure 4. RUN Pin Interfacing
DIGITAL
PHASE/
FREQUENCY
DETECTOR
EXTERNAL
OSCILLATOR
OSCILLATOR
Phase-Locked Loop and Frequency Synchronization
TheLTC3809hasaphase-lockedloop(PLL)comprisedof
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. This allows the turn-on of the external P-channel
MOSFETtobelockedtotherisingedgeofanexternalclock
signal applied to the SYNC/MODE pin. The phase detector
3809 F06
Figure 6. Phase-Locked Loop Block Diagram
3809f
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If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
PLLLPFpin. Iftheexternalandinternalfrequenciesarethe
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the internal and external
oscillators are identical. At the stable operating point, the
phase detector output is high impedance and the filter
capacitor CLP holds the voltage.
the VIN/VOUT ratio is close to unity, the synchronous
MOSFET may not be on for a sufficient amount of time to
transfer power from the output capacitor to the auxiliary
load. Forced continuous operation will support an auxil-
iary winding as long as there is a sufficient synchronous
MOSFET duty factor. The SYNC/MODE input pin removes
the requirement that power must be drawn from the
transformer primary side in order to extract power from
the auxiliary winding. With the loop in continuous mode,
the auxiliary output may nominally be loaded without
regard to the primary output load.
The auxiliary output voltage VAUX is normally set, as
shown in Figure 7, by the turns ratio N of the transformer:
The loop filter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01µF.
V
AUX = (N + 1) • VOUT
However, if the controller goes into pulse skipping opera-
tionandhaltsswitchingduetoalightprimaryloadcurrent,
then VAUX will droop. An external resistor divider from
VAUXtotheSYNC/MODEsetsaminimumvoltageVAUX(MIN)
:
Typically, the external clock (on SYNC/MODE pin) input
high level is 1.6V, while the input low level is 1.2V.
R6
R5
⎛
⎝
⎞
⎟
⎠
VAUX(MIN) = 0.4V • 1+
⎜
Table 1 summarizes the different states in which the
PLLLPF pin can be used.
If VAUX drops below this value, the SYNC/MODE voltage
forces temporary continuous switching operation until
VAUX is again above its minimum.
Table 1. The States of the PLLLPF Pin
PLLLPF PIN
0V
SYNC/MODE PIN
DC Voltage (<1.2V or V )
FREQUENCY
300kHz
IN
Floating
DC Voltage (<1.2V or V )
550kHz
IN
V
AUX
V
IN
V
IN
DC Voltage (<1.2V or V )
750kHz
IN
+
LTC3809
TG
SYNC/MODE
SW
L1
1:N
1µF
RC Loop Filter Clock Signal
Phase-Locked
to External Clock
R6
R5
V
OUT
Filter Caps DC Voltage (>1.35V and <V – 0.5V)
Spread Spectrum
460kHz to 635kHz
IN
+
C
OUT
BG
3809 F07
Auxiliary Winding Control Using SYNC/MODE Pin
Figure 7. Auxiliary Output Loop Connection
The SYNC/MODE pin can be used as an auxiliary feedback
to provide a means of regulating a flyback winding output.
When this pin drops below its ground-referenced 0.4V
threshold, continuous mode operation is forced.
Spread Spectrum Modulation with SYNC/MODE and
PLLLPF Pins
During continuous mode, current flows continuously in
the transformer primary side. The auxiliary winding draws
current only when the bottom synchronous N-channel
MOSFET is on. When primary load currents are low and/or
Switching regulators, which operate at fixed frequency,
conductelectromagneticinterference(EMI)totheirdown-
stream load(s) with high spectral power density at this
fundamental and harmonic frequencies. The peak energy
3809f
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Table 2 summarizes the different states in which the
SYNC/MODE Pin can be used.
can be lowered and distributed to other frequencies and
their harmonics by modulating the PWM frequency. The
LTC3809’s switching noise (at 550kHz) is spread between
460kHz and 635kHz in spread spectrum modulation op-
eration. Figure 8 shows the spectral plots of the output
(VOUT) noise with/without spread spectrum modulation.
Note the significant reduction in peak output noise
(>20dBm).
Table 2. The States of the SYNC/MODE Pin
SYNC/MODE PIN
CONDITION
GND (0V to 0.35V)
Forced Continuous Mode
Current Reversal Allowed
V
(0.45V to 1.2V)
Pulse Skipping Mode
No Current Reversal Allowed
FB
Resistor to V
Spread Spectrum Modulation
Pulse Skipping at Light Loads
No Current Reversal Allowed
IN
ThespreadspectrummodulationoperationoftheLTC3809
is enabled by setting SYNC/MODE pin to a DC voltage
between1.35VandseveralhundredmVbelowVIN bytying
a resistor between SYNC/MODE and VIN.
(1.35V to V – 0.5V)
IN
V
Burst Mode Operation
No Current Reversal Allowed
IN
Feedback Resistors
External Clock Signal
Regulate an Auxiliary Winding
VOUT Spectrum without Spread Spectrum Modulation
Enable Phase-Locked Loop
(Synchronize to External Clock)
Pulse Skipping at Light Load
No Current Reversal Allowed
Fault Condition: Short-Circuit and Current Limit
NOISE (dBm)
–10dBm/DIV
IftheLTC3809’sloadcurrentexceedstheshort-circuitcur-
rentlimit(ISC),whichissetbytheshort-circuitsensethresh-
old (∆VSC) and the on resistance (RDS(ON)) of bottom
N-channel MOSFET, the top P-channel MOSFET is turned
off and will not be turned on at the next clock cycle unless
the load current decreases below ISC. In this case, the
controller’s switching frequency is decreased and
the output is regulated by short-circuit (current limit)
protection.
3809 F08a
START FREQ: 400kHz
RBW: 100Hz
STOP FREQ: 700kHz
VOUT Spectrum with Spread Spectrum Modulation
(CSSM = 2200pF)
In a hard short (VOUT = 0V), the top P-channel MOSFET is
turned off and kept off until the short-circuit condition is
cleared. In this case, there is no current path from input
supply (VIN) to either VOUT or GND, which prevents
excessive MOSFET and inductor heating.
NOISE (dBm)
–10dBm/DIV
Low Input Supply Voltage
Although the LTC3809 can function down to below 2.4V,
the maximum allowable output current is reduced as VIN
decreasesbelow3V.Figure9showstheamountofchange
as the supply is reduced down to 2.4V. Also shown is the
3809 F08b
START FREQ: 400kHz
RBW: 100Hz
effect on VREF
.
STOP FREQ: 700kHz
Figure 8. Spectral Response of Spread Spectrum Modulation
3809f
18
LTC3809
W U U
U
APPLICATIO S I FOR ATIO
105
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
V
REF
100
Efficiency = 100% – (L1 + L2 + L3 + …)
95
90
MAXIMUM
SENSE VOLTAGE
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
85
80
75
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3809 circuits: 1) LTC3809 DC bias current,
2) MOSFET gate charge current, 3) I2R losses and
4) transition losses.
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
3809 F09
1) The VIN (pin) current is the DC supply current, given in
the Electrical Characteristics, which excludes MOSFET
driver currents. VIN current results in a small loss that
increases with VIN.
Figure 9. Line Regulation of VREF and Maximum Sense Voltage
Minimum On-Time Considerations
2) MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFET. Each time a
MOSFET gate is switched from low to high to low again, a
packet of charge dQ moves from VIN to ground. The
resulting dQ/dt is a current out of VIN, which is typically
much larger than the DC supply current. In continuous
mode, IGATECHG = f • QP.
Minimum on-time, tON(MIN) is the smallest amount of time
that the LTC3809 is capable of turning the top P-channel
MOSFET on. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle and high frequency applications may approach
the minimum on-time limit and care should be taken to
ensure that:
3) I2R losses are calculated from the DC resistances of the
MOSFETs, inductor and/or sense resistor. In continuous
mode, the average output current flows through L but is
“chopped” between the top P-channel MOSFET and the
bottom N-channel MOSFET. The MOSFET RDS(ON) multi-
plied by duty cycle can be summed with the resistance of
L to obtain I2R losses.
VOUT
OSC • V
tON(MIN)
<
f
IN
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC3809 will begin to skip
cycles (unless forced continuous mode is selected). The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase. The minimum on-
time for the LTC3809 is typically about 210ns. However,
as the peak sense voltage (IL(PEAK) • RDS(ON)) decreases,
the minimum on-time gradually increases up to about
260ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If forced
continuousmodeisselectedandthedutycyclefallsbelow
the minimum on time requirement, the output will be
regulated by overvoltage protection.
4) Transition losses apply to the external MOSFET and
increase with higher operating frequencies and input
voltages. Transition losses can be estimated from:
Transition Loss = 2 • VIN2 • IO(MAX) • CRSS • f
Other losses, including CIN and COUT ESR dissipative
lossesandinductorcorelosses,generallyaccountforless
than 2% total additional loss.
Checking Transient Response
Efficiency Considerations
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
3809f
19
LTC3809
W U U
U
APPLICATIO S I FOR ATIO
equalto(∆ILOAD)•(ESR), whereESRistheeffectiveseries
resistance of COUT. ∆ILOAD also begins to charge or
dischargeCOUT generatingafeedbackerrorsignalusedby
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. OPTI-LOOP compensation allows the transient re-
sponse to be optimized over a wide range of output
capacitance and ESR values.
Design Example
As a design example, assume VIN will be operating from a
maximum of 4.2V down to a minimum of 2.75V (powered
by a single lithium-ion battery). Load current requirement
is a maximum of 2A, but most of the time it will be in a
standby mode requiring only 2mA. Efficiency at both low
andhighloadcurrentsisimportant. BurstModeoperation
at light loads is desired. Output voltage is 1.8V. The IPRG
pin will be left floating, so the maximum current sense
threshold ∆VSENSE(MAX) is approximately 125mV.
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation.
VOUT
MaximumDuty Cycle =
= 65.5%
The ITH external components showed in the figure on the
firstpageofthisdatasheetwillprovideadequatecompen-
sation for most applications. The values can be modified
slightly (from 0.2 to 5 times their suggested values) to
optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitor needs to be
decided upon because the various types and values deter-
mine the loop feedback factor gain and phase. An output
current pulse of 20% to 100% of full load current having
a rise time of 1µs to 10µs will produce output voltage and
ITH pin waveforms that will give a sense of the overall loop
stability. The gain of the loop will be increased by increas-
ing RC and the bandwidth of the loop will be increased by
decreasing CC. The output voltage settling behavior is
related to the stability of the closed-loop system and will
demonstrate the actual overall supply performance. For a
detailedexplanationofoptimizingthecompensationcom-
ponents, including a review of control loop theory, refer to
Application Note 76.
V
IN(MIN)
From Figure 1, SF = 82%.
5
∆VSENSE(MAX)
IOUT(MAX) • ρT
RDS(ON)MAX
=
• 0.9 • SF •
= 0.032Ω
6
A 0.032Ω P-channel MOSFET in Si7540DP is close to this
value.
TheN-channelMOSFETinSi7540DPhas0.017ΩRDS(ON)
The short circuit current is:
.
90mV
0.017Ω
ISC
=
= 5.3A
So the inductor current rating should be higher than 5.3A.
The PLLLPF pin will be left floating, so the LTC3809 will
operate at its default frequency of 550kHz. For continuous
Burst Mode operation with 600mA IRIPPLE, the required
minimum inductor value is:
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
theloadrisetimeislimitedtoapproximately(25)•(CLOAD).
Thus a 10µF capacitor would be require a 250µs rise time,
limiting the charging current to about 200mA.
1.8V
550kHz • 600mA
1.8V
2.75V
⎛
⎝
⎞
⎟
⎠
LMIN
=
• 1−
= 1.88µH
⎜
A 6A 2.2µH inductor works well for this application.
CIN will require an RMS current rating of at least 1A at
temperature. A COUT with 0.1Ω ESR will cause approxi-
mately 60mV output ripple.
3809f
20
LTC3809
W U U
APPLICATIO S I FOR ATIO
U
PC Board Layout Checklist
• The current sense traces should be Kelvin connections
right at the P-channel MOSFET source and drain.
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the LTC3809.
• Keeping the switch node (SW) and the gate driver nodes
(TG,BG)awayfromthesmall-signalcomponents,espe-
cially the feedback resistors, and ITH compensation
components.
• The power loop (input capacitor, MOSFET, inductor,
output capacitor) should be as small as possible and
isolated as much as possible from LTC3809.
• Put the feedback resistors close to the VFB pins. The ITH
compensation components should also be very close to
the LTC3809.
V
IN
2.75V TO 8V
10µF
×2
2
SYNC/MODE
1
6
9
8
PLLLPF
V
IN
MP
L
C
IPRG
TG
ITH
Si7540DP
1.5µH
R
ITH
220pF
LTC3809EDD
V
OUT
15k
4
10
7
2.5V
I
TH
SW
BG
(5A AT 5V
)
IN
MN
Si7540DP
187k
+
3
5
C
OUT
V
RUN
FB
GND
11
150µF
59k
100pF
3809 F10
L: VISHAY IHLP-2525CZ-01
C
: SANYO 4TPB150MC
OUT
Figure 10. 550kHz, Synchronous DC/DC Converter with Internal Soft-Start
V
IN
2.75V TO 8V
10µF
×2
2
SYNC/MODE
10nF
10k
1
6
9
8
PLLLPF
IPRG
V
IN
MP
Si7540DP
L
TG
1.5µH
V
OUT
1.8V
(5A AT 5V
470pF
LTC3809EDD
15k
4
10
7
)
IN
I
SW
BG
TH
100pF
MN
Si7540DP
C
22µF
×2
OUT
118k
3
5
V
RUN
FB
GND
11
D
59k
OPT
100pF
3809 F11
L: VISHAY IHLP-2525CZ-01
D: ON SEMI MBRM120L (OPTIONAL)
Figure 11. Synchronizable DC/DC Converter with Ceramic Output Capacitors
3809f
21
LTC3809
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
6
0.38 ± 0.10
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD10) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3809f
22
LTC3809
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 ± 0.102
(.081 ± .004)
1.83 ± 0.102
(.072 ± .004)
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
1
5.23
(.206)
MIN
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
10
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
1
2
3
4 5
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MSE) 0603
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3809f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC3809
TYPICAL APPLICATIO S
U
Synchronous DC/DC Converter with Spread Spectrum Modulation
V
IN
3.3V
C
300k
IN
22µF
2
1
9
SYNCH/MODE
LTC3809EDD
PLLLPF
V
IN
1000pF
8
MP
L
TG
Si3447BDV
1.5µH
100pF
2200pF
15k
187k
V
2.5V
2A
OUT
6
4
3
IPRG
10
SW
7
5
I
MN
Si3460DV
TH
BG
470pF
V
RUN
C
FB
GND
11
OUT
22µF
59k
3809 TA04
L: VISHAY IHLP-2525CZ-01
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PART NUMBER
DESCRIPTION
COMMENTS
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≤ V , 4mm × 4mm QFN
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Step-Down DC/DC Controller
2.75V ≤ V ≤ 9.8V, 3mm × 2mm DFN or 8-Lead SOT-23,
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LTC3776
Dual, 2-Phase, No R
DDR/QDR Memory Termination
Synchronous Controller for
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an V with One IC, 2.75V ≤ V ≤ 9.8V,
DDQ TT IN
SENSE
Adjustable Constant Frequency with PLL Up to 850kHz,
Spread Spectrum Operation, 4mm × 4mm QFN and
24-Lead SSOP Packages
LTC3808
Low EMI, Synchronous Controller with Output Tracking
2.75V ≤ V ≤ 9.8V, 4mm × 3mm DFN, Spread Spectrum for
IN
20dB Lower Peak Noise
PolyPhase is a trademark of Linear Technology Corporation
.
3809f
LT/TP 0405 500 • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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