LTC3723-2_15 [Linear]
Synchronous Push-Pull PWM Controllers;
| 型号： | LTC3723-2_15 |
| 厂家： | 
Linear |
| 描述： | Synchronous Push-Pull PWM Controllers |
| 文件： | 总20页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3723-1/LTC3723-2
Synchronous Push-Pull
PWM Controllers
U
DESCRIPTIO
FEATURES
TheLTC®3723-1/LTC3723-2synchronouspush-pullPWM
controllers provide all of the control and protection func-
tions necessary for compact and highly efficient, isolated
power converters. High integration minimizes external
component count, while preserving design flexibility.
■
High Efficiency Synchronous Push-Pull PWM
■
1.5A Sink, 1A Source Output Drivers
■
Supports Push-Pull, Full-Bridge, Half-Bridge, and
Forward Topologies
■
Adjustable Push-Pull Dead-Time and Synchronous
Timing
The robust push-pull output stages switch at half the
oscillator frequency. Dead-time is independently pro-
grammed with an external resistor. Synchronous rectifier
timing is adjustable to optimize efficiency. A UVLO pro-
gram input provides precise system turn-on and turn off
voltages. The LTC3723-1 features peak current mode
controlwithprogrammableslopecompensationandlead-
ing edge blanking, while the LTC3723-2 employs voltage
mode control with voltage feedforward capability.
■
Adjustable System Undervoltage Lockout and
Hysteresis
■
Adjustable Leading Edge Blanking
■
Low Start-Up and Quiescent Currents
■
Current Mode (LTC3723-1) or Voltage Mode
(LTC3723-2) Operation
■
Single Resistor Slope Compensation
■
VCC UVLO and 25mA Shunt Regulator
■
Programmable Fixed Frequency Operation to 1MHz
■
50mA Synchronous Output Drivers
The LTC3723-1/LTC3723-2 feature extremely low operat-
ing and start-up currents. Both devices provide reliable
short-circuit and overtemperature protection. The
LTC3723-1/LTC3723-2 are offered in a 16-pin SSOP
package.
■
Soft-Start, Cycle-by-Cycle Current Limiting and
Hiccup Mode Short-Circuit Protection
■
5V, 15mA Low Dropout Regulator
■
Available in 16-Pin SSOP Package
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIO S
■
Telecommunications, Infrastructure Power Systems
Distributed Power Architectures
■
U
TYPICAL APPLICATIO
Isolated Push-Pull Converter
V
OUT
V
IN
ME
UVLO
SPRG
DRVA
SYNC
FROM
AUXILIARY
WINDING
•
•
LTC3901
DRVB
CS
V
CC
MF
V
REF
DPRG
C
SDRA
SDRB
T
V
V
REF
OUT
R
LEB
V
REF
+
V
LTC3723-1
COMP
FB GND
COLL
R
REF
V
OUT
LT1431
SS
GND-F GND-S
372312 TA01
372312f
1
LTC3723-1/LTC3723-2
W W
U W
ABSOLUTE AXI U RATI GS
(Note 1)
VCC to GND (Low Impedance Source) .......–0.3V to 10V
(Chip Self-Regulates at 10.3V)
VREF Output Current ............................... Self-Regulated
Operating Temperature (Notes 5,6)
LTC3723E........................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
Lead Temperature (Soldering, 10sec)................... 300°C
UVLO to GND............................................. –0.3V to VCC
All Other Pins to GND
(Low Impedance Source) .........................–0.3V to 5.5V
V
CC (Current Fed) ................................................. 40mA
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
V
1
2
3
4
5
6
7
8
16 SPRG
15 UVLO
14 SS
V
1
2
3
4
5
6
7
8
16 SPRG
15 UVLO
14 SS
REF
REF
SDRB
SDRA
DRVB
SDRB
SDRA
DRVB
13 FB
13 FB
V
12
R
LEB
V
CC
12 DPRG
11 COMP
10 CS
CC
DRVA
GND
11 COMP
10 CS
DRVA
GND
C
T
9
DPRG
C
T
9
RAMP
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
GN PART MARKING
37231
ORDER PART NUMBER
LTC3723EGN-2
GN PART MARKING
37232
ORDER PART NUMBER
LTC3723EGN-1
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 9.5V unless otherwise noted.
A
CC
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply
V
V
V
V
Undervoltage Lockout
UVLO Hysteresis
Measured on V
Measured on V
10.25
4.2
145
3
10.7
V
V
CCUV
CCHY
CCST
CCRN
CC
CC
CC
3.8
CC
I
I
Start-Up Current
V
= V
– 0.3V
UVLO
●
230
8
µA
mA
V
CC
Operating Current
No Load on Outputs
Current into V = 10mA
V
Shunt Regulator Voltage
Shunt Resistance
10.3
1.4
5.0
10
10.8
3.5
5.2
11.5
SHUNT
CC
R
Current into V = 10mA to 17mA
Ω
SHUNT
CC
SUVLO
SHYST
System UVLO Threshold
System UVLO Hysteresis Current
Measured on UVLO Pin, 10mA into V
4.8
8.5
V
CC
Current Flows Out of UVLO Pin, 10mA into V
µA
CC
Pulse Width Modulator
ROS Ramp Offset Voltage
Ramp Discharge Current
Measured on COMP, RAMP = 0V
0.65
50
V
mA
I
RAMP = 1V, COMP = 0V, C = 4V, 3723-1 Only
T
RMP
372312f
2
LTC3723-1/LTC3723-2
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 9.5V unless otherwise noted.
A
CC
CONDITIONS
Measured on CS, C = 1V, 3723-1 Only
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
I
Slope Compensation Current
30
68
µA
µA
SLP
T
C = 2.25V
T
DCMAX
DCMIN
DTADJ
Oscillator
OSCI
Maximum Duty Cycle
Minimum Duty Cycle
Dead-Time
COMP = 4.5V
COMP = 0V
●
●
47
48.2
0
50
%
%
ns
130
Initial Accuracy
T = 25°C, C = 270pF
220
–3
250
2.35
1.2
280
3
kHz
%
A
T
OSCT
V
Variation
V
= 6.5V to 9.5V, Overtemperature
CC
●
CC
OSCV
C Ramp Amplitude
T
Measured on C
V
T
Error Amplifier
V
FB Input Voltage
FB Input Range
Open-Loop Gain
Input Bias Current
Output High
COMP = 2.5V, (Note 3)
Measured on FB, (Note 4)
COMP = 1V to 3V, (Note 3)
COMP = 2.5V, (Note 3)
Load on COMP = –100µA
Load on COMP = 100µA
COMP = 2.5V
1.172
–0.3
70
1.22
2.5
V
V
FB
FB
I
AVOL
90
5
dB
nA
V
I
50
IB
V
V
4.7
4.92
0.27
700
5
OH
Output Low
0.5
V
OL
I
I
Output Source Current
Output Sink Current
400
2
µA
mA
SOURCE
SINK
COMP = 2.5V
Reference
V
Initial Accuracy
Load Regulation
Line Regulation
Total Variation
T = 25°C, Measured on V
REF
4.925
5.00
2
5.075
15
V
mV
mV
V
REF
A
REFLD
REFLN
REFTV
REFSC
Load on V = 100µA to 5mA
REF
V
= 6.5V to 9.5V
1
10
CC
Line, Load and Temperature
●
4.900
18
5.000
30
5.100
45
Short-Circuit Current
V
Shorted to GND
mA
REF
Push-Pull Outputs
DRVH(x)
DRVL(x)
RDH(x)
RDL(x)
TDR(x)
TDF(x)
Output High Voltage
I
I
I
I
= –100mA
9.0
9.0
9.2
0.17
2.9
1.7
10
V
V
OUT(x)
OUT(x)
OUT(x)
OUT(x)
Output Low Voltage
Pull-Up Resistance
Pull-Down Resistance
Rise-Time
= 100mA
0.6
4
= –10mA to –100mA
= –10mA to –100mA
= 1nF
Ω
Ω
ns
ns
2.5
C
C
OUT(x)
OUT(x)
Fall-Time
= 1nF
10
Synchronous Outputs
OUTH(x)
OUTL(x)
RHI(x)
RLO(x)
TR(x)
Output High Voltage
I
I
I
I
= –30mA
9.2
0.44
11
V
V
OUT(x)
OUT(x)
OUT(x)
OUT(x)
Output Low Voltage
Pull-Up Resistance
Pull-Down Resistance
Rise-Time
= 30mA
0.6
15
20
= –10mA to -30mA
= –10mA to -30mA
= 50pF
Ω
Ω
ns
ns
15
C
C
10
OUT(x)
OUT(x)
TF(x)
Fall-Time
= 50pF
10
Current Limit and Shutdown
CLPP
CLSD
CLDEL
Pulse by Pulse Current Limit Threshold
Measured on CS
280
475
300
600
80
320
725
mV
mV
ns
Shutdown Current Limit Threshold
Current Limit Delay to Output
Measured on CS
100mV Overdrive on CS, (Note 2)
372312f
3
LTC3723-1/LTC3723-2
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 9.5V unless otherwise noted.
A
CC
SYMBOL
SSI
PARAMETER
CONDITIONS
MIN
10
TYP
13
MAX
16
UNITS
Soft-Start Current
SS = 2.5V
µA
V
SSR
Soft-Start Reset Threshold
Fault Reset Threshold
Measured on SS
Measured on SS
0.7
4.5
0.4
4.2
0.1
3.5
FLT
V
Note 1: Absolute Maximum Ratings are those values beyond which the life
performance specifications from 0°C to 70°C. Specifications over the
–40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls.
Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
of a device may be impaired.
Note 2: Includes leading edge blanking delay, R = 20k, not tested in
LEB
production.
Note 3: FB is driven by a servo loop amplifier to control V
for these
COMP
tests.
Note 4: Set FB to –0.3V, 2.5V and insure that COMP does not phase invert.
Note 5: The LTC3723E–1/LTC3723E-2 are guaranteed to meet
U W
(T = 25°C unless otherwise noted)
A
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency vs
Temperature
Start-Up I vs V
V
vs I
CC
CC
CC
SHUNT
10.50
10.25
10.00
9.75
200
150
100
50
260
250
240
230
220
C
= 270pF
T
9.50
0
0
10
20
30
40
50
0
2
4
6
8
10
–60 –40 –20
0
20 40 60 80 100
I
(mA)
V
(V)
TEMPERATURE (°C)
SHUNT
CC
372312 G02
372312 G01
372312 G03
Leading Edge Blanking Time
vs R
V
REF
vs Temperature
V
REF
vs I
REF
LEB
5.01
5.00
4.99
4.98
4.97
350
300
250
200
150
100
50
5.05
5.00
4.95
4.90
4.85
4.80
T = 25°C
J
T = 85°C
J
T = –40°C
J
0
–60 –40 –20
0
20 40 60 80 100
20
(mA)
5
10 15
25 30 35 40
0
0
10 20 30 40 50
70
90 100
80
60
TEMPERATURE (°C)
R
(kΩ)
I
LEB
REF
372312 G06
372312 G05
372312 G04
372312f
4
LTC3723-1/LTC3723-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS (T = 25°C unless otherwise noted)
A
LTC3723 Deadtime vs R
DPRG
With and Without 200k Prebias
Compensation
Error Amplifier Gain/Phase
Start-Up I vs Temperature
CC
275
250
225
200
175
150
125
100
75
190
180
170
160
150
140
130
120
110
100
100
80
60
40
20
0
200k PREBIAS
NO 200k PREBIAS
–180
–270
–360
50
10
100
1k
10k
100k 1M
10M
0
100 150 200 250 300 350 400 450 500
50
–55
–25
5
35
65
95
125
FREQUENCY (Hz)
R
(kΩ)
TEMPERATURE (°C)
DPRG
372312 G07
372312 G09
372312 G08
V
Shunt Voltage vs
Synchronous Driver Turn-Off Delay
CC
Slope Current vs Temperature
Temperature
vs R
Referenced to CT Peak
SPRG
10.5
10.4
10.3
10.2
10.1
10.0
9.9
900
800
700
600
500
400
300
200
100
0
90
80
70
60
50
40
30
20
10
0
I
= 10mA
CC
C
= 2.25V
T
C
= 1V
T
9.8
–55
–25
5
35
65
95
125
0
150
(kΩ)
200
50
100
250
300
–55
–25
5
35
65
95
125
TEMPERATURE (°C)
R
TEMPERATURE (°C)
SPRG
372312 G11
372312 G12
372312 G10
Synchronous Driver Turn-Off
Delay vs R Referenced to
SPRG
FB Input Voltage vs Temperature
Push-Pull Driver Outputs
1.205
1.204
1.203
1.202
1.201
1.200
1.199
1.198
1.197
350
300
250
200
150
100
50
R
= 150k
DPRG
0
–50
0
50
100
150
(kΩ)
200
250
300
–55
–25
5
35
65
95
125
TEMPERATURE (°C)
R
SPRG
372312 G13
372312 G14
372312f
5
LTC3723-1/LTC3723-2
U
U
PI DESCRIPTIO S
(LTC3723-1/LTC3723-2)
VREF (Pin 1/Pin 1): Output of the 5.0V Reference. VREF is
capableofsupplyingupto18mAtoexternalcircuitry.VREF
should be decoupled to GND with a 0.47µF ceramic
capacitor.
mended. VIN and VREF bypass capacitors must be termi-
natedwithastarconfigurationasclosetoGNDaspractical
for best performance.
CT (Pin 8/Pin 8): Timing Capacitor for the Oscillator. Use
a ±5% or better low ESR ceramic capacitor for best
results. CT ramp amplitude is 2.35V peak-to-peak
(typical).
SDRB (Pin 2/Pin 2): 50mA Driver for Synchronous Recti-
fier associated with DRVB.
SDRA (Pin 3/Pin 3): 50mA Driver for Synchronous Recti-
fier associated with DRVA.
DPRG (Pin 9/Pin 12): Programming Input for Push-Pull
Dead-Time. Connect a resistor between DPRG and VREF
to program the dead-time. The nominal voltage on DPRG
is 2V.
DRVB (Pin 4/Pin 4): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is op-
tional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
RAMP (N/A/Pin 9): Input to PWM Comparator for
LTC3723-2 Only (Voltage Mode Controller). The voltage
on RAMP is internally level shifted by 650mV.
CS (Pin 10/Pin 10): Input to Pulse-by-Pulse and Overload
Current Limit Comparators, Output of Slope Compensa-
tionCircuitry. Thepulse-by-pulsecomparatorhasanomi-
nal 300mV threshold, while the overload comparator has
anominal600mVthreshold.Aninternalswitchdischarges
CS to GND after every timing period. Slope compensation
current flows out of CS during the PWM period.
An external resistor connected from CS to the external
current sense resistor programs the amount of slope
compensation.
V
CC (Pin 5/Pin 5):Supply Voltage Input to the LTC3723-1/
LTC3723-2 and 10.25V Shunt Regulator. The chip is
enabled after VCC has risen high enough to allow the VCC
shunt regulator to conduct current and the UVLO com-
parator threshold is exceeded. Once the VCC shunt regu-
lator has turned on, VCC can drop to as low as 6V (typical)
and maintain operation. Bypass VCC to GND with a high
quality 1µF or larger ceramic capacitor to supply the
transientcurrentscausedbythehighspeedswitchingand
capacitive loads presented by the on chip totem pole
drivers.
COMP (Pin 11/Pin 11): Error Amplifier Output, Inverting
Input to Phase Modulator.
RLEB (Pin 12/N/A): Timing Resistor for Leading Edge
Blanking. Use a 10k to 100k resistor connected between
RLEB and GND to program from 40ns to 310ns of leading
edge blanking of the current sense signal on CS for the
LTC3723-1. A ±1% tolerance resistor is recommended.
TheLTC3723-2hasafixedblankingtimeofapproximately
80ns. The nominal voltage on RLEB is 2V. If leading edge
blanking is not required, tie RLEB to VREF to disable.
DRVA (Pin 6/Pin 6): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is op-
tional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
FB (Pin 13/Pin 13): Error Amplifier Inverting Input. This is
the voltage feedback input for the LTC3723. The nominal
regulation voltage at FB is 1.2V.
GND (Pin 7/Pin 7): All circuits in the LTC3723 are refer-
enced to GND. Use of a ground plane is highly recom-
372312f
6
LTC3723-1/LTC3723-2
U
U
PI DESCRIPTIO S
(LTC3723-1/LTC3723-2)
SS (Pin 14/Pin 14): Soft-Start/Restart Delay Circuitry
Timing Capacitor. A capacitor from SS to GND provides a
controlled ramp of the current command (LTC3723-1) or
dutycycle(LTC3723-2).Duringoverloadconditions,SSis
discharged to ground initiating a soft-start cycle. SS
chargingcurrentisapproximately13µA. SSwillchargeup
to approximately 5V in normal operation. During a con-
stant overload current fault, SS will oscillate at a low
frequency between approximately 0.5V and 4V.
threshold is exceeded, the LTC3723-1/LTC3723-2 com-
mences a soft-start cycle and a 10µA (nominal) current is
fed out of UVLO to program the desired amount of system
hysteresis. The hysteresis level can be adjusted by chang-
ing the resistance of the divider. UVLO can also be used to
terminate all switching by pulling UVLO down to less than
4V. An open drain or collector switch can perform this
function without changing the system turn on or turn off
voltages.
UVLO (Pin 15/Pin 15): Input to Program System Turn-On
andTurn-OffVoltages.ThenominalthresholdoftheUVLO
comparator is 5.0V. UVLO is connected to the main DC
system feed through a resistor divider. When the UVLO
SPRG (Pin 16/Pin 16): A resistor is connected between
SPRG and GND to set the turn off delay for the synchro-
nous rectifier driver outputs. The nominal voltage on
SPRG is 2V.
W U
TI I G DIAGRA
W
PROGRAMMABLE
SYNCHRONOUS
TURN-OFF DELAY
PROGRAMMABLE
DEAD-TIME
DRVA
DRVB
SDRA
SDRB
CURRENT
SENSE
OR C RAMP
T
PWM
COMPARATOR
(–)
372312 TD01
372312f
7
LTC3723-1/LTC3723-2
W
BLOCK DIAGRA S
LTC3723-1 Block Diagram
V
UVLO
15
V
REF
1
C
T
DPRG
9
SPRG
16
CC
5
8
V
UVLO
REF, LDO
1.2V
5V
CC
10µA
10.25V “ON”
6V “OFF”
V
CC
REF GOOD
ERROR
AMPLIFIER
SYSTEM
UVLO
V
CC
GOOD
FB 13
–
+
+
–
3
2
SDRA
SDRB
1.2V
5V
SYNC
RECTIFIER
DRIVE
PULSE WIDTH
MODULATOR
LOGIC
50k
COMP 11
–
+
14.9k
+
–
OSCILLATOR
650mV
1A SOURCE
Q
R
S
6
DRVA
Q
Q
T
1.5A SINK
+
–
R
Q
S
V
REF
1A SOURCE
1.5A SINK
13µA
SS 14
4
DRVB
SHUTDOWN
CURRENT
LIMIT
FAULT
LOGIC
+
–
600mV
SLOPE
COMPENSATOR
PULSE-BY-PULSE
CURRENT LIMIT
CS 10
12
BLANK
+
–
R
7
LEB
300mV
372312 BD01
GND
372312f
8
LTC3723-1/LTC3723-2
W
BLOCK DIAGRA S
LTC3723-2 Block Diagram
V
UVLO
15
V
C
T
SPRG
16
CC
REF
1
5
8
V
UVLO
REF, LDO
1.2V
5V
CC
10µA
10.25V “ON”
6V “OFF”
V
CC
REF GOOD
ERROR
AMPLIFIER
SYSTEM
UVLO
V
CC
GOOD
FB 13
–
+
+
–
3
2
SDRA
SDRB
1.2V
5V
SYNC
RECTIFIER
DRIVE
PULSE WIDTH
MODULATOR
LOGIC
50k
COMP 11
–
+
+
–
OSCILLATOR
650mV
RAMP
9
1A SOURCE
Q
R
S
6
4
DRVA
DRVB
Q
Q
T
1.5A SINK
1A SOURCE
1.5A SINK
R
Q
+
–
OUTPUT
DRIVE
LOGIC
S
V
REF
13µA
SS 14
SHUTDOWN
CURRENT
LIMIT
FAULT
LOGIC
+
–
600mV
PULSE-BY-PULSE
CURRENT LIMIT
CS 10
BLANK
+
–
7
9
300mV
372312 BD02
GND
DPRG
372312f
9
LTC3723-1/LTC3723-2
U
OPERATIO
PleaserefertothedetailedBlockDiagramsforthisdiscus- Programming Driver Dead-Time
sion. The LTC3723-1 and LTC3723-2 are synchronous
The LTC3723-1/LTC3723-2 controllers include a feature
PWMpush-pullcontrollers. TheLTC3723-1operateswith
peak pulse-by-pulse current mode control while the
LTC3723-2 offers voltage mode control operation. They
are best suited for moderate to high power isolated power
systems where small size and high efficiency are required.
The push-pull topology delivers excellent transformer
utilization and requires only two low side power MOSFET
switches. Both controllers generate 180° out of phase
0% to <50% duty cycle drive signals on DRVA and DRVB.
The external MOSFETs are driven directly by these power-
ful on-chip drivers. The external MOSFETs typically con-
trol opposite primary windings of a centertapped power
transformer. The centertap primary winding is connected
totheinputDCfeed. Thesecondaryofthetransformercan
beconfiguredindifferentsynchronousornonsynchronous
configurations depending on the application needs.
to program the minimum time between the output signals
on DRVA and DRVB commonly referred to as the driver
dead-time. This function will come into play if the control-
leriscommandedformaximumdutycycle. Thedead-time
is set with an external resistor connected between DPRG
and VREF (see Figure 1). The nominal regulated voltage on
DPRG is 2V. The external resistor programs a current
which flows into DPRG. The dead-time can be adjusted
from 90ns to 300ns with this resistor. The dead-time can
also be modulated based on an external current source
that feeds current into DPRG. Care must be taken to limit
the current fed into DPRG to 350µA or less. An internal
10µA current source sets a maximum deadtime if DPRG is
floated.Theinternalcurrentsourcecausestheprogrammed
deadtime to vary non-linearly with increasing values of
RDPRG (see typical performance characteristics). An ex-
The duty ratio is controlled by the voltage on COMP. A ternal 200k resistor connected from DPRG to GND will
switching cycle commences with the falling edge of the compensate for the internal 10µA current source and
internal oscillator clock pulse. The LTC3723-1 attenuates linearize the deadtime delay vs RDPRG characteristic.
the voltage on COMP and compares it to the current sense
Powering the LTC3723-1/LTC3723-2
signal to terminate the switching cycle. The LTC3723-2
compares the voltage on COMP to a timing ramp to
terminate the cycle. The LTC3723-2’s CT waveform can be
used for this purpose or separate R-C components can be
connected to RAMP to generate the timing ramp. If the
voltage on CS exceeds 300mV, the present cycle is termi-
nated. If the voltage on CS exceeds 600mV, all switching
stops and a soft-start sequence is initiated.
TheLTC3723-1/LTC3723-2utilizeanintegratedVCC shunt
regulatortoservethedualpurposesoflimitingthevoltage
applied to VCC as well as signaling that the chip’s bias
voltage is sufficient to begin switching operation (under
voltage lockout). With its typical 10.2V turn-on voltage
and 4.2V UVLO hysteresis, the LTC3723-1/LTC3723-2 is
tolerant of loosely regulated input sources such as an
auxiliary transformer winding. The VCC shunt is capable of
sinking up to 40mA of externally applied current. The
UVLO turn-on and turn-off thresholds are derived from an
internally trimmed reference making them extremely ac-
curate. In addition, the LTC3723-1/LTC3723-2 exhibits
The LTC3723-1 / LTC3723-2 also provide drive signals for
secondarysidesynchronousrectifierMOSFETs.Synchro-
nous rectification improves converter efficiency, espe-
cially as the output voltages drop. Independent turn-off
control of the synchronous rectifiers is provided via SPRG
in order to optimize the benefit of the synchronous recti-
fiers. A resistor from SPRG to GND sets the desired turn
off delay.
V
REF
R
DPRG
10µA
DPRG
+
–
A host of other features including an error amplifier,
systemUVLOprogramming,adjustableleadingedgeblank-
ing, slope compensation and programmable dead-time
provide flexibility for a variety of applications.
+
V
–
TURN-ON
OUTPUT
OPTIONAL 200k
2V
2.5V
372312 F01
Figure 1. Delay Timeout Circuitry
372312f
10
LTC3723-1/LTC3723-2
U
OPERATIO
very low (145µA typ) start-up current that allows the use
UVLO. The amount of DC feed hysteresis provided by this
current is: 10µA • RTOP, (Figure 3). The system UVLO
threshold is: 5V • {(RTOP + RBOTTOM)/RBOTTOM}. If the
voltage applied to UVLO is present and greater than 5V
prior to the VCC UVLO circuitry activation, then the internal
UVLO logic will prevent output switching until the follow-
ing three conditions are met: (1) VCC UVLO is enabled, (2)
of 1/8W to 1/4W trickle charge start-up resistors.
The trickle charge resistor should be selected as follows:
RSTART(MAX) = VIN(MIN) – 10.7V/250µA
Adding a small safety margin and choosing standard
values yields:
V
REF is in regulation and (3) UVLO pin is greater than 5V.
APPLICATION
DC/DC
V
RANGE
R
START
IN
36V to 72V
85V to 270V
100k
430k
1.4M
UVLO can also be used to enable and disable the power
converter. An open drain transistor connected to UVLO as
shown in Figure 3 provides this capability.
Off-Line
RMS
PFC Preregulator
390V
DC
VCC should be bypassed with a 0.1µF to 1µF multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the VCC supply before the
bootstrap winding, or an auxiliary regulator circuit takes
over.
R
TOP
UVLO
ON OFF
R
BOTTOM
372312 F03
CHOLDUP = (ICC + IDRIVE) • tDELAY/3.8V
(minimum UVLO hysteresis)
Figure 3. System UVLO Setup
Regulated bias supplies as low as 7V can be utilized to
provide bias to the LTC3723-1/LTC3723-2. Refer to
Figure 2 for various bias supply configurations.
Off-Line Bias Supply Generation
If a regulated bias supply is not available to provide VCC
voltage to the LTC3723-1/LTC3723-2 and supporting
circuitry, onemustbegenerated. Sincethepowerrequire-
ment is small, approximately 1W, and the regulation is not
critical, a simple open-loop method is usually the easiest
and lowest cost approach. One method that works well is
to add a winding to the main power transformer, and post
regulate the resultant square wave with an L-C filter (see
Figure 4a). The advantage of this approach is that it
maintains decent regulation as the supply voltage varies,
and it does not require full safety isolation from the input
winding of the transformer. Some manufacturers include
a primary winding for this purpose in their standard
V
IN
V
BIAS
< V
UVLO
12V ±10%
1.5k
1N5226
3V
1N914
R
START
+
1µF
1µF
C
HOLD
V
CC
V
CC
372312 F02
Figure 2. Bias Configurations
Programming Undervoltage Lockout
The LTC3723-1/LTC3723-2 provides undervoltage lock-
out (UVLO) control for the input DC voltage feed to the
power converter in addition to the VCC UVLO function
described in the preceding section. Input DC feed UVLO is
provided with the UVLO pin. A comparator on UVLO
compares a divided down input DC feed voltage to the 5V
precision reference. When the 5V level is exceeded on
UVLO, the SS pin is released and output switching com-
mences. At the same time a 10µA current is enabled which
flows out of UVLO into the voltage divider connected to
V
IN
V
CC
R
START
2k
+
15V*
1µF
C
HOLD
372312 F04a
*OPTIONAL
Figure 4a. Auxiliary Winding Bias Supply
372312f
11
LTC3723-1/LTC3723-2
U
OPERATIO
Figure 5, the leading edge of an external pulse is used to
terminate the natural clock cycle. If the external frequency
is higher than the oscillator frequency, the internal oscil-
lator will synchronize with the external input frequency.
product offerings as well. A different approach is to add a
winding to the output inductor and peak detect and filter
the square wave signal (see Figure 4b). The polarity of this
winding is designed so that the positive voltage square
wave is produced while the output inductor is freewheel-
ing. An advantage of this technique over the previous is
that it does not require a separate filter inductor and since
the voltage is derived from the well-regulated output
voltage, it is also well controlled. One disadvantage is that
this winding will require the same safety isolation that is
required for the main transformer. Another disadvantage
is that a much larger VCC filter capacitor is needed, since
it does not generate a voltage as the output is first starting
up, or during short-circuit conditions.
LTC3723
f < f
OSC EXT
< 1.25 • f
OSC
C
T
C
T
EXTERNAL
FREQUENCY
SOURCE
68pF
390Ω
BAT54
210µA
2.56V • C
f
= f /2
SW OSC
f
≅
OSC
T
372312 F05
Figure 5. Synchronization from External Source
V
IN
V
OUT
Single-Ended Operation
L
OUT
R
+
START
ISO BARRIER
In addition to push-pull and full-bridge topologies, single-
ended topologies such as the forward and flyback con-
verter can benefit from the many advanced features of the
LTC3723. In Figure 6, the LTC3723 is used with the
LTC4440, 100V high side driver to implement a two-
transistor forward converter. DRVB is used which limits
the converter’s maximum duty cycle to 50% (less pro-
grammable driver dead time).
1µF
C
HOLD
372312 F04b
V
CC
Figure 4b. Output Inductor Bias Supply
Programming the LTC3723-1/LTC3723-2 Oscillator
V
IN
TG
TS
The high accuracy LTC3723-1/LTC3723-2 oscillator cir-
cuit provides flexibility to program the switching fre-
quency and slope compensation required for current
mode control (LTC3723-1). The oscillator circuit pro-
duces a 2.35V peak-to-peak amplitude ramp waveform on
CT.Typicalmaximumdutycyclesof49%arepossible.The
oscillator is capable of operation up to 1MHz by the
following equation:
LTC4440
GND
IN
–V
IN
DRVB
TO SYNCHRONOUS
SECONDARY MOSFET
SDRB
GND
LTC3723
CT = 1/(14.8k • FOSC
)
210µA
2 • 2.56V • C
f
≅
C
T
SW
T
Note that this is the frequency seen on CT. The output
drivers switch at 1/2 of this frequency. Also note that
higher switching frequency and added driver dead-time
via DPRG will reduce the maximum duty cycle.
C
T
372312 F06
Figure 6. Two-Transistor Forward Converter (Duty Cycle < 50%)
The LTC3723-1/LTC3723-2 can be synchronized to an
external frequency source such as another PWM chip. In
372312f
12
LTC3723-1/LTC3723-2
U
OPERATIO
The 50% duty-cycle limit is overcome with the circuit
shown in Figure 7. Operation is similar to external syn-
chronization, except DRVA output is used to terminate its
ownclockcycleearly. Switchingperiodisnowequaltothe
oscillator period plus programmable driver dead time.
Maximum on time is equal to oscillator period minus
driver dead time.
Voltage Mode with LTC3723-2
Figure 9 shows how basic connections differ between
current mode LTC3723-1 and voltage mode LTC3723-2.
Oscillator may be used as the ramp input or the LTC3723-
2 includes an internal 10mA ramp discharge useful when
implementing voltage feedforward. Open loop control in
which the duty cycle varies inversely proportional to input
voltage is shown in Figure 10.
Although near 100% duty cycle operation may be of
benefit with non-isolated converters, it is often desirable
to limit the duty cycle of single-ended isolated converters.
Instead of immediately ending the unused clock’s output,
Figure 8 uses a transistor to switch in additional timing
capacitor charge current. This allows one to preset the
maximum duty.
LTC3723-1
C
DPRG
9
V
RLEB
12
T
REF
1
8
R
R
T
C
LEB
DPRG
TO INPUT
VOLTAGE
DRVA DRVB
LTC3723-1
1
fSW
≅
C
T
⎛
⎞
2.56V •CT
+ T
LTC3723-2
LTC3723-2
⎜
⎝
DPRG
⎟
⎠
210µA
C
T
C
RAMP
V
DPRG
RAMP
9
C
V
DPRG
12
T
REF
1
T
REF
1
⎛
⎞
2.56V •CT
210µA
8
9
12
8
DMAX ≅ fSW
– T
DPRG
⎜
⎝
⎟
⎠
68pF
390Ω
BAT54
R
R
DPRG
DPRG
C
C
T
T
372312 F09
372312 F07
Figure 9. LTC3723-1 Current Mode and LTC3723-2 Voltage
Mode Connections
Figure 7. LTC3723-1 > 50% Duty Cycle
V
TO INPUT
VOLTAGE
IN
LTC3723-2
13
FB
–V
IN
C
RAMP COMP
11
T
8
9
DRVB
TO SYNCHRONOUS
SECONDARY MOSFET
DRVA
SDRB
C
T
LTC3723-1
50k
V
1
REF
R
C
T
fSW
≅
372312 F10
⎛
⎞
1
1
2.56V •CT
+
⎜
⎟
MMBT2369
210µA 210µA + 3 /R
(
)
⎝
⎠
Figure 10. LTC3723-2 Open Loop Control (Duty Cycle is
Inversely Proportional to Input Voltage)
C
⎛
⎝
⎞
T
2.56V •CT
210µA
DMAX ≅ fSW
– T
DPRG
⎜
⎟
⎠
372312 F08
Figure 8. LTC3723-1 One-Switch Forward or Flyback Converter
(Maximum Duty Cycle 50% to 100%)
372312f
13
LTC3723-1/LTC3723-2
U
OPERATIO
The LTC3723-1 derives a compensating slope current
from the oscillator ramp waveform and sources this
current out of CS. This function is disabled in the
LTC3723-2. The desired level of slope compensation is
selected with an external resistor connected between CS
and the external current sense resistor, (Figure 11).
The pulse-by-pulse comparator has a 300mV nominal
threshold. If the 300mV threshold is exceeded, the PWM
cycle is terminated. The overcurrent comparator is set
approximately 2x higher than the pulse-by-pulse level. If
the current signal exceeds this level, the PWM cycle is
terminated, the soft-start capacitor is quickly discharged
and a soft-start cycle is initiated. If the overcurrent condi-
tion persists, the LTC3723-1/LTC3723-2 halts PWM op-
eration and waits for the soft-start capacitor to charge up
to approximately 4V before a retry is allowed. The soft-
start capacitor is charged by an internal 13µA current
source. If the fault condition has not cleared when soft-
start reaches 4V, the soft-start pin is again discharged and
a new cycle is initiated. This is referred to as hiccup mode
operation. In normal operation and under most abnormal
conditions, the pulse-by-pulse comparator is fast enough
to prevent hiccup mode operation. In severe cases, how-
ever, with high input voltage, very low RDS(ON) MOSFETs
and a shorted output, or with saturating magnetics, the
overcurrent comparator provides a means of protecting
the power converter.
Current Sensing and Overcurrent Protection
Current sensing provides feedback for the current mode
control loop and protection from overload conditions. The
LTC3723-1/LTC3723-2 are compatible with either resis-
tive sensing or current transformer methods. Internally
connected to the LTC3723-1/LTC3723-2 CS pin are two
comparators that provide pulse-by-pulse and overcurrent
shutdown functions respectively, (Figure 12).
LTC3723
SWITCH
CURRENT
V(C )
T
I =
R
SLOPE
C
33k
T
CS
ADDED
SLOPE
R
CS
33k
CURRENT SENSE
WAVEFORM
372312 F11
Leading Edge Blanking
Figure 11. Slope Compensation Circuitry
TheLTC3723-1/LTC3723-2providesprogrammablelead-
ing edge blanking to prevent nuisance tripping of the
currentsensecircuitry. Leadingedgeblankingrelievesthe
filteringrequirementsfortheCSpin,greatlyimprovingthe
response to real overcurrent conditions. It also allows the
use of a ground referenced current sense resistor or
transformer(s), further simplifying the design. With a
single 10k to 100k resistor from RLEB to GND, blanking
times of approximately 40ns to 320ns are programmed. If
not required, connecting RLEB to VREF can disable leading
edge blanking. Keep in mind that the use of leading edge
blankingwillslightlyreducethelinearcontrolrangeforthe
pulse width modulator.
H = SHUTDOWN
OUTPUTS
PWM
UVLO
ENABLE
LATCH
PULSE BY PULSE
CURRENT LIMIT
PWM
LOGIC
Q
Q
PWM
S
R
Q
+
–
S
CS
300mV
OVERLOAD
CURRENT LIMIT
R
CS
+
–
13µA
SS
4.1V
0.4V
S
R
Q
–
+
600mV
UVLO
ENABLE
+
–
C
SS
Q
372312 F12
Figure 12. Current Sense/Fault Circuitry Detail
372312f
14
LTC3723-1/LTC3723-2
U
OPERATIO
High Current Drivers
new primary side power delivery pulse. This feature pro-
vides optimized timing for the synchronous MOSFETs
which improves efficiency. At higher load currents it
becomes more advantageous to delay the turn-off of the
synchronous rectifiers until the beginning of the new
power pulse. This allows for secondary freewheeling
currenttoflowthroughthesynchronousMOSFETchannel
instead of its body diode.
The LTC3723-1/LTC3723-2 high current, high speed driv-
ers provide direct drive of external power N-channel
MOSFET switches. The drivers swing from rail to rail. Due
to the high pulsed current nature of these drivers (1.5A
sink, 1A source), care must be taken with the board layout
to obtain advertised performance. Bypass VCC with a 1µF
minimum, low ESR, ESL ceramic capacitor. Connect this
capacitor with minimal length PCB leads to both VCC and
GND. A ground plane is highly recommended. The driver
output pins (DRVA, DRVB) connect to the gates of the
external MOSFET switches. The PCB traces making these
connections should also be as short as possible to mini-
mize overshoot and undershoot of the drive signal.
The turn-off delay is programmed with a resistor from
SPRG to GND, (Figure 13). The nominal regulated voltage
on SPRG is 2V. The external resistor programs a current
which flows out of SPRG. The delay can be adjusted from
approximately 20ns to 200ns, with resistor values of 10k
to 200k. Do not leave SPRG floating. The amount of delay
can also be modulated based on an external current
source that sinks current out of SPRG. Care must be taken
to limit the current out of SPRG to 350µA or less.
Synchronous Rectification
The LTC3723-1/LTC3723-2 produces the precise timing
signals necessary to control secondary side synchronous
rectifier MOSFETs on SDRA and SDRB. Synchronous
rectifiers are used in place of Schottky or silicon diodes on
the secondary side to improve converter efficiency. As
MOSFET RDS(ON) levels continue to drop, significant effi-
ciency improvements can be realized with synchronous
rectification, provided that the MOSFET switch timing is
optimized. Synchronous rectification also provides bipo-
lar output current capability, that is, the ability to sink as
well as source current.
SPRG
+
+
V
–
TURN-OFF
SYNC OUT
R
SPRG
2V
–
372312 F13
Figure 13. Synchronous Delay Circuitry
Programming the Synchronous Rectifier
Turn-Off Delay
The LTC3723-1/LTC3723-2 controllers include a feature
to program the turn-off edge of the secondary side syn-
chronous rectifier MOSFETs relative to the beginning of a
372312f
15
LTC3723-1/LTC3723-2
U
TYPICAL APPLICATIO S
•
•
•
•
•
372312f
16
LTC3723-1/LTC3723-2
U
TYPICAL APPLICATIO S
•
•
•
•
•
•
E F F I C I E N C Y ( % )
372312f
17
LTC3723-1/LTC3723-2
U
TYPICAL APPLICATIO S
•
•
•
•
•
•
•
•
E F F I C I E N C Y ( % )
372312f
18
LTC3723-1/LTC3723-2
U
TYPICAL APPLICATIO S
LTC3723-1 300W 42V to 56V to 12V/25A Isolated Bus Converter
IN
IN
+V
OUT
ES1B
L1
V
V
IN
F
0.56µH
1.2k
0.5W
1nF
V
IN
100V
1µF
100V
1µF
100V
×3
12V
1
12V
1
10Ω
1W
0.33µF
BAS21
6
BAS21
6
ES1B
100V
T1
29.46mm × 25.4mm × 10.2mm PLANAR
–V
IN
V
E
V
E
–V
OUT
V
CC
V
CC
2
11
9
+V
OUT
3
3
B
INP BOOST
LTC4440ES6
TG
A
INP BOOST
LTC4440ES6
TG
+V
OUT
4.7Ω
4.7Ω
5
V
F
L2
5
4
3
7
0.44µH
GND TS
GND TS
HAT2169
×2
HAT2169
Si7370DP
Si7370DP
2
4
2
4
22µF
25V
×3
0.1µF
0.1µF
×2
2.2nF
250V
5
4.7µF
25V
2x
Si7370DP
Si7370DP
A
5.1Ω
1/4W
–V
OUT
B
–V
OUT
V
F
V
E
+V
1µF, 100V TDK C3225X7R2A105M
OUT
L3
12V 1mH
100Ω
4.7µF, 25V TDK C4532X7R1E475M
22µF, 25V TDK C4532X7R1E226M
D1: MMBZ5240B
4.53k
4.53k
BAS21
I
SNS
2.67k
1.27k
2.67k
1.27k
R1
1
6
1k
0.015Ω
1.5W
+
D2: MMBZ5242B
L1: COILCRAFT DO1813P-561HC
L2: PULSE PA0513.441
L3: COILCRAFT DO1608C-105
T1: PULSE PA0901.004 (4:4:4:4CT)
T2: PULSE PA0785 (1:0.5T)
68µF
20V
BAS21
MMBT3904
11
+
12
–
14 15
6
5
–
2
3
16
33.2k
+
CSF
CSF MF MF2 CSE
CSE ME ME2
V
CC
T2
1
1
8
4
5
9
LTC3901EGN
PGND GND2
SYNC
PV
CC
PGND2 TIMER
D1
10V
22Ω
GND
8
0.1µF
100Ω
220pF
1µF
4
10
13
7
4.7µF
470pF
V
IN
12V
MMBT3904
–V
OUT
30k
97
13
12
11
10
9
A
B
1/4W
I
48V
IN
SNS
2
6
4
3
53V
48V
IN
96
95
94
93
92
91
DRVA DRVB
SDRB SDRA
CS
COMP
100Ω
1/4W
42V
IN
5
10
11
IN
V
LTC3723EGN-1
464k
CC
53V
IN
15
UVLO
FB GND C
SPRG RLEB SS DPRG
V
42V
T
REF
1
IN
13
7
8
16
12 14
9
100pF
150k
66.5k
33k
24.9k
330pF
1µF
270pF
10k
D2
12V
8
68nF
0.47µF
7
5
10
15
LOAD CURRENT (A)
20
25
5
10
15
LOAD CURRENT (A)
20
25
372312 TA05
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.009
.015 ± .004
(0.38 ± 0.10)
(0.229)
REF
.045 ±.005
16 15 14 13 12 11 10 9
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
0° – 8°
.007 – .0098
(0.178 – 0.249)
TYP
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
.254 MIN
.150 – .165
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
3. DRAWING NOT TO SCALE
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
1
2
3
4
5
6
7
8
.0165 ± .0015
.0250 BSC
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RECOMMENDED SOLDER PAD LAYOUT
GN16 (SSOP) 0204
372312f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC3723-1/LTC3723-2
U
TYPICAL APPLICATIO
LTC3723-1 100W, 36V to 72V to 3.3V/30A Isolated Forward Converter
IN
IN
L1
0.33µH
L2
0.85µH
V
V
T1
23.4mm × 20.1mm × 9.4mm PLANAR
OUT
IN
V
V
OUT
IN
2
4
7
8
1µF
1µF
100V
100V
×2
2.2nF
V
X
100µF
–V
IN
3
5
10
11
6.3V
Si7336ADP
Si7336ADP
×2
+
Si7450DP
×2
×2
5.1Ω
1/2W
470µF
6.3V
94
93
92
91
90
89
88
87
86
2.2nF
48V
IN
2.2nF
630V
5.1Ω
1/2W
–V
OUT
0.03Ω
–V
OUT
1W
L3
1mH
10V
BAS21
845Ω
B0540W
B0540W
15Ω
1/4W
1
6
V
V
X
+
1.00k
68µF
20V
BAS21
820Ω
562Ω
V
B
REF
5
10
15
20
25
30
5
1
+
2
–
3
4
LOAD CURRENT (A)
120K
26.1k
FG
CS
CS
CG
V
CC
T2
D1
10V
7
1
8
4
5
8
SYNC
TIMER
V
LTC3900ES8
IN
10V
A
30k
120pF
220pF
0.47µF
25V
GND
6
1nF
560Ω
10
CS
6
4
150Ω
2
DRVA
DRVB
1/4W
SDRB
COMP
5
–V
OUT
V
CC
383k
LTC3723EGN-1
15
10nF
UVLO
11
GND SS
C
SPRG RLEB FB DPRG
16 12 13
V
T
REF
4.7nF
330Ω
330Ω
7
14
8
9
150k
1
100pF
C
T
V
V
OUT
REF
820Ω
V
REF
4.7nF
10k
1
1µF
68nF
MOC207
66.5k
33k
V
B
220pF
0.47µF
1k
6
1
27.4k
5
6
V
IN
1µF, 100V TDK C3225X7R2A105M (1210)
100µF, 6.3V TDK C3225X5R0J107M (1210)
2.2nF, 630V TDK C3216JB2J222K
470µF, 6.3V SANYO 6TPD470M
D1: MMBZ5240B
L1: COILCRAFT DO1813P-331HC
L2: PULSE PA1292.910
470pF
COMP
OPTO
4
5
2
V
REF
LT4430ES6
FB
OC
A
50k
GND
2
MMBT2369
8.66k
2.2nF
250V
6.04k
3
47nF
L3: COILCRAFT DO1608C-105
T1: PULSE PA810.007 (7:6:6:1:1:1T)
T2: PULSE PA0184 (1:1T)
V
IN
C
T
V
OUT
372312 TA06
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PART NUMBER
DESCRIPTION
COMMENTS
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Drives N-Channel Synchronous MOSFETs, Programmable Timeout,
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Overshoot Control on Start-Up and Short-Circuit Recovery,
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PolyPhase is a registered trademark of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.
372312f
LT 1105 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003
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