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LTC2424 [Linear]

4-/8-Channel 20-Bit uPower No Latency ADCs; 4- / 8通道的20位微功耗无延迟的ADC
LTC2424
型号： LTC2424
厂家： Linear    Linear
描述：

4-/8-Channel 20-Bit uPower No Latency ADCs
4- / 8通道的20位微功耗无延迟的ADC
文件： 总28页 (文件大小：320K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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Final Electrical Specifications  
LTC2424/LTC2428  
4-/8-Channel 20-Bit µPower  
No Latency ∆ΣTM ADCs  
March 2000  
U
FEATURES  
DESCRIPTIO  
The LTC®2424/LTC2428 are 4-/8-channel 2.7V to 5.5V  
micropower 20-bit A/D converters with an integrated  
oscillator, 8ppm INL and 1.2ppm RMS noise. They use  
delta-sigma technology and provide single cycle digital  
filter settling time (no latency delay) for multiplexed  
applications. The first conversion after the channel is  
changedisalwaysvalid.ThroughasinglepintheLTC2424/  
LTC2428 can be configured for better than 110dB rejec-  
tion at 50Hz or 60Hz ±2%, or can be driven by an external  
oscillator for a user defined rejection frequency in the  
range 1Hz to 800Hz. The internal oscillator requires no  
external frequency setting components.  
■
Pin Compatible 4-/8-Channel 20-Bit ADCs  
■
8ppm INL, No Missing Codes at 20 Bits  
■
4ppm Full-Scale Error and 0.5ppm Offset  
■
1.2ppm Noise  
■
Digital Filter Settles in a Single Cycle. Each  
Conversion is Accurate, Even After Changing  
Channels  
■
Fast Mode: 16-Bit Noise, 12-Bit TUE at 100sps  
■
Internal Oscillator—No External Components  
Required  
■
110dB Min, 50Hz/60Hz Notch Filter  
■
Reference Input Voltage: 0.1V to VCC  
■
Live Zero—Extended Input Range Accommodates  
The converters accept any external reference voltage from  
0.1VtoVCC. Withtheirextendedinputconversionrangeof  
–12.5% VREF to 112.5% VREF (VREF = FSSET – ZSSET) the  
LTC2424/LTC2428 smoothly resolve the offset and  
overrange problems of preceding sensors or signal con-  
ditioning circuits.  
12.5% Overrange and Underrange  
Single Supply 2.7V to 5.5V Operation  
■
■
Low Supply Current (200µA) and Auto Shutdown  
Can Be Interchanged with 24-Bit LTC2404/LTC2408  
■
if ZSSET Pin is Grounded  
U
APPLICATIO S  
The LTC2424/LTC2428 communicate through a flexible  
4-wire digital interface which is compatible with SPI and  
MICROWIRETM protocols.  
■
Weight Scales  
■
Direct Temperature Measurement  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
■
Gas Analyzers  
Strain-Gage Transducers  
Instrumentation  
Data Acquisition  
Industrial Process Control  
4-Digit DVMs  
No Latency ∆Σ is a trademark of Linear Technology Corporation.  
MICROWIRE is a trademark of National Semiconductor Corporation.  
■
■
■
■
■
U
TYPICAL APPLICATIO  
Total Unadjusted Error vs Output Code  
10  
0.1V TO V  
CC  
2.7V TO 5.5V  
8
6
7
4
3
2, 8  
1µF  
MUXOUT  
ADCIN  
FS  
SET CC  
V
SERIAL DATA LINK  
MICROWIRE AND  
SPI COMPATABLE  
9
CH0  
4
23  
20  
25  
19  
21  
24  
10 CH1  
11 CH2  
12 CH3  
13 CH4*  
14 CH5*  
15 CH6*  
17 CH7*  
CSADC  
2
CSMUX  
SCK  
0
ANALOG  
INPUTS  
20-BIT  
∆∑ ADC  
4-/8-CHANNEL  
MUX  
–2  
–4  
–6  
–8  
–10  
+
MPU  
CLK  
–0.12V  
TO  
REF  
1.12V  
D
IN  
REF  
–
SDO  
V
CC  
LTC2424/LTC2428  
= INTERNAL OSC/50Hz REJECTION  
= EXTERNAL CLOCK SOURCE  
= INTERNAL OSC/60Hz REJECTION  
5
ZS  
SET  
26  
F
O
GND  
0
8,338,608  
OUTPUT CODE (DECIMAL)  
16,777,215  
24248 TA01  
1, 6, 16, 18, 22, 27, 28  
*THESE PINS ARE NO CONNECTS ON THE LTC2404  
24248 TA02  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-  
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.  
1
LTC2424/LTC2428  
W W U W  
ABSOLUTE MAXIMUM RATINGS  
(Notes 1, 2)  
Operating Temperature Range  
Supply Voltage (VCC) to GND.......................–0.3V to 7V  
Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V)  
Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)  
Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)  
Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)  
LTC2424C/LTC2428C .............................. 0°C to 70°C  
LTC2424I/LTC2428I ........................... –40°C to 85°C  
Storage Temperature Range ................. –65°C to 150°C  
Lead Temperature (Soldering, 10 sec).................. 300°C  
U
W U  
PACKAGE/ORDER INFORMATION  
ORDER  
TOP VIEW  
ORDER  
TOP VIEW  
PART NUMBER  
PART NUMBER  
1
2
GND  
GND  
1
2
GND  
GND  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
GND  
GND  
V
V
CC  
CC  
LTC2424CG  
LTC2424IG  
LTC2428CG  
LTC2428IG  
3
F
3
F
FS  
FS  
SET  
O
O
SET  
4
SCK  
4
SCK  
ADCIN  
ZS  
ADCIN  
ZS  
5
SDO  
5
SDO  
SET  
SET  
6
CSADC  
GND  
6
CSADC  
GND  
GND  
GND  
7
7
MUXOUT  
MUXOUT  
8
D
8
D
V
V
IN  
IN  
CC  
CC  
9
CSMUX  
CLK  
9
CSMUX  
CLK  
CH0  
CH1  
CH2  
CH3  
NC  
CH0  
CH1  
CH2  
CH3  
CH4  
CH5  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
GND  
NC  
GND  
CH7  
GND  
NC  
GND  
CH6  
NC  
G PACKAGE  
28-LEAD PLASTIC SSOP  
G PACKAGE  
28-LEAD PLASTIC SSOP  
TJMAX = 125°C, θJA = 130°C/W  
TJMAX = 125°C, θJA = 130°C/W  
Consult factory for Military grade parts.  
U
CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)  
PARAMETER  
CONDITIONS  
0.1V ≤ V ≤ V , (Note 5)  
MIN  
TYP  
MAX  
UNITS  
Resolution (No Missing Codes)  
Integral Nonlinearity  
●
20  
Bits  
REF  
CC  
V
REF  
V
REF  
= 2.5V (Note 6)  
= 5V (Note 6)  
●
●
4
8
10  
20  
ppm of V  
REF  
REF  
ppm of V  
ppm of V  
ppm of V  
ppm of V  
Integral Nonlinearity (Fast Mode)  
Offset Error  
2.5V < V < V , 100 Samples/Second, f = 2.048MHz  
●
●
40  
0.5  
3
250  
10  
REF  
CC  
O
REF  
REF  
REF  
2.5V ≤ V ≤ V  
REF  
CC  
Offset Error (Fast Mode)  
Offset Error Drift  
2.5V < V < 5V, 100 Samples/Second, f = 2.048MHz  
REF O  
2.5V ≤ V ≤ V  
0.04  
4
ppm of V /°C  
REF  
REF  
CC  
CC  
Full-Scale Error  
2.5V ≤ V ≤ V  
●
15  
ppm of V  
ppm of V  
REF  
REF  
REF  
Full-Scale Error (Fast Mode)  
Full-Scale Error Drift  
2.5V < V < 5V, 100 Samples/Second, f = 2.048MHz  
10  
REF  
O
2.5V ≤ V ≤ V  
0.04  
ppm of V /°C  
REF  
REF  
CC  
2
LTC2424/LTC2428  
CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating  
U
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Total Unadjusted Error  
V
REF  
V
REF  
= 2.5V  
= 5V  
8
16  
ppm of V  
ppm of V  
REF  
REF  
Output Noise  
V
V
= 0V, V  
= 5V (Note 13)  
6
µV  
µV  
IN  
REF  
RMS  
Output Noise (Fast Mode)  
= 5V, 100 Samples/Second, f = 2.048MHz  
20  
REF  
O
RMS  
Normal Mode Rejection 60Hz ±2%  
Normal Mode Rejection 50Hz ±2%  
Power Supply Rejection, DC  
Power Supply Rejection, 60Hz ±2%  
Power Supply Rejection, 50Hz ±2%  
(Note 7)  
(Note 8)  
●
●
110  
110  
130  
130  
100  
110  
110  
dB  
dB  
dB  
dB  
dB  
V
REF  
V
REF  
V
REF  
= 2.5V, V = 0V  
IN  
= 2.5V, V = 0V, (Notes 7, 16)  
IN  
= 2.5V, V = 0V, (Notes 8, 16)  
IN  
U
U
U
U
A ALOG I PUT A D REFERE CE  
The ● denotes specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. (Note 3)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
–0.125 • V  
0.1  
TYP  
MAX  
UNITS  
V
V
V
C
C
Input Voltage Range  
(Note 14)  
●
●
1.125 • V  
REF  
IN  
REF  
Reference Voltage Range  
Input Sampling Capacitance  
Reference Sampling Capacitance  
Input Leakage Current  
Reference Leakage Current  
On Channel Leakage Current  
MUX On-Resistance  
V
CC  
V
REF  
1
1.5  
1
pF  
S(IN)  
pF  
S(REF)  
IN(LEAK)  
REF(LEAK)  
IN(MUX)  
I
I
I
CS = V  
●
●
●
–100  
–100  
100  
100  
±20  
nA  
nA  
nA  
CC  
V
REF  
= 2.5V, CS = V  
1
CC  
V = 2.5V (Note 15)  
S
R
ON  
I
I
= 1mA, V = 2.7V  
= 1mA, V = 5V  
●
●
250  
120  
300  
250  
Ω
Ω
OUT  
OUT  
CC  
CC  
MUX ∆R vs Temperature  
0.5  
20  
%/°C  
%
ON  
∆R vs V (Note 15)  
ON  
S
I
I
t
t
t
MUX Off Input Leakage  
MUX Off Output Leakage  
MUX Break-Before-Make Interval  
Enable Turn-On Time  
Channel Off, V = 2.5V  
●
●
±20  
±20  
nA  
nA  
ns  
S(OFF)  
D(OFF)  
OPEN  
ON  
S
Channel Off, V = 2.5V  
D
290  
490  
190  
70  
V = 1.5V, R = 3.4k, C = 15pF  
ns  
S
L
L
Enable Turn-Off Time  
V = 1.5V, R = 3.4k, C = 15pF  
ns  
OFF  
S
L
L
QIRR  
QINJ  
MUX Off Isolation  
V
IN  
= 2V , R = 1k, f = 100kHz  
dB  
pC  
pF  
P-P  
L
Charge Injection  
R = 0Ω, C = 1000pF, V = 1V  
±1  
10  
S
L
S
C
C
Input Off Capacitance (MUX)  
Output Off Capacitance (MUX)  
S(OFF)  
D(OFF)  
10  
pF  
3
LTC2424/LTC2428  
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS  
The ● denotes specifications which apply over the full  
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)  
SYMBOL  
PARAMETER  
CONDITIONS  
2.7V ≤ V ≤ 5.5V  
MIN  
TYP  
MAX  
UNITS  
V
V
V
V
High Level Input Voltage  
●
●
●
●
●
●
2.5  
2.0  
V
V
IH  
IL  
IH  
IL  
CC  
CS, F  
2.7V ≤ V ≤ 3.3V  
O
CC  
Low Level Input Voltage  
CS, F  
4.5V ≤ V ≤ 5.5V  
0.8  
0.6  
V
V
CC  
2.7V ≤ V ≤ 5.5V  
O
CC  
High Level Input Voltage  
SCK  
2.7V ≤ V ≤ 5.5V (Note 9)  
2.5  
2.0  
V
V
CC  
2.7V ≤ V ≤ 3.3V (Note 9)  
CC  
Low Level Input Voltage  
SCK  
4.5V ≤ V ≤ 5.5V (Note 9)  
0.8  
0.6  
V
V
CC  
2.7V ≤ V ≤ 5.5V (Note 9)  
CC  
I
I
Digital Input Current  
0V ≤ V ≤ V  
CC  
–10  
–10  
10  
µA  
µA  
pF  
pF  
V
IN  
IN  
CS, F  
O
Digital Input Current  
SCK  
0V ≤ V ≤ V (Note 9)  
10  
IN  
IN  
CC  
C
C
V
V
V
V
Digital Input Capacitance  
10  
10  
IN  
CS, F  
O
Digital Input Capacitance  
SCK  
(Note 9)  
IN  
High Level Output Voltage  
SDO  
I = –800µA  
O
●
●
●
●
●
V
V
– 0.5V  
– 0.5V  
OH  
OL  
OH  
OL  
CC  
CC  
Low Level Output Voltage  
SDO  
I = 1.6mA  
O
0.4V  
V
High Level Output Voltage  
SCK  
I = –800µA (Note 10)  
O
V
Low Level Output Voltage  
SCK  
I = 1.6mA (Note 10)  
O
0.4V  
10  
V
I
High-Z Output Leakage  
SDO  
–10  
2
µA  
OZ  
+
V
V
H
MUX High Level Input Voltage  
MUX Low Level Input Voltage  
V = 3V  
●
●
V
V
IN MUX  
+
L
V = 2.4V  
0.8  
IN MUX  
W U  
POWER REQUIRE E TS  
The ● denotes specifications which apply over the full operating temperature range,  
otherwise specifications are at TA = 25°C. (Note 3)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
V
CC  
Supply Voltage  
●
2.7  
5.5  
V
I
I
Supply Current (Pin 2)  
Conversion Mode  
Sleep Mode  
CC  
CS = 0V (Note 12)  
●
●
200  
20  
300  
30  
µA  
µA  
CS = V (Note 12)  
CC  
Multiplexer Supply Current (Pin 8)  
All Logic Inputs Tied Together  
●
15  
40  
µA  
CC(MUX)  
V
IN  
= 0V or 5V  
4
LTC2424/LTC2428  
W U  
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range,  
otherwise specifications are at TA = 25°C. (Note 3)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
f
External Oscillator Frequency Range  
20-Bit Effective Resolution  
12-Bit Effective Resolution  
●
●
2.56  
2.56k  
307.2  
2.048M  
kHz  
Hz  
EOSC  
t
t
t
External Oscillator High Period  
External Oscillator Low Period  
Conversion Time  
●
●
0.5  
0.5  
390  
390  
µs  
µs  
HEO  
LEO  
F = 0V  
●
●
●
130.66  
156.80  
133.33  
160  
136  
163.20  
(in kHz)  
ms  
ms  
ms  
CONV  
O
F = V  
O
CC  
External Oscillator (Note 11)  
20480/f  
EOSC  
f
Internal SCK Frequency  
Internal Oscillator (Note 10)  
External Oscillator (Notes 10, 11)  
19.2  
kHz  
kHz  
ISCK  
f
/8  
EOSC  
D
Internal SCK Duty Cycle  
(Note 10)  
(Note 9)  
(Note 9)  
(Note 9)  
45  
55  
%
kHz  
ns  
ISCK  
f
t
t
t
External SCK Frequency Range  
External SCK Low Period  
●
●
●
2000  
ESCK  
250  
250  
1.23  
LESCK  
External SCK High Period  
ns  
HESCK  
DOUT_ISCK  
Internal SCK 24-Bit Data Output Time  
Internal Oscillator (Notes 10, 12)  
External Oscillator (Notes 10, 11)  
●
●
1.25  
1.28  
ms  
ms  
192/f  
(in kHz)  
EOSC  
t
t
t
t
t
t
t
External SCK 24-Bit Data Output Time  
CS ↓ to SDO Low Z  
CS ↑ to SDO High Z  
CS ↓ to SCK ↓  
(Note 9)  
●
●
●
●
●
●
●
●
●
24/f  
(in kHz)  
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DOUT_ESCK  
ESCK  
0
0
150  
150  
150  
1
2
(Note 10)  
(Note 9)  
0
3
CS ↓ to SCK ↑  
50  
4
SCK ↓ to SDO Valid  
SDO Hold After SCK ↓  
SCK Set-Up Before CS ↓  
SCK Hold After CS ↓  
200  
KQMAX  
KQMIN  
(Note 5)  
15  
50  
t
t
5
6
50  
Note 1: Absolute Maximum Ratings are those values beyond which the  
life of the device may be impaired.  
Note 2: All voltage values are with respect to GND.  
Note 10: The converter is in internal SCK mode of operation such that  
the SCK pin is used as digital output. In this mode of operation the  
SCK pin has a total equivalent load capacitance CLOAD = 20pF.  
Note 11: The external oscillator is connected to the FO pin. The external  
oscillator frequency, fEOSC, is expressed in kHz.  
Note 3: VCC = 2.7 to 5.5V unless otherwise specified, source input  
is 0Ω. CSADC = CSMUX = CS. VREF = FSSET – ZSSET  
.
Note 12: The converter uses the internal oscillator.  
Note 4: Internal Conversion Clock source with the FO pin tied  
to GND or to VCC or to external conversion clock source with  
FO = 0V or FO = VCC  
.
f
EOSC = 153600Hz unless otherwise specified.  
Note 13: The output noise includes the contribution of the internal  
calibration operations.  
Note 5: Guaranteed by design, not subject to test.  
Note 14: For reference voltage values VREF > 2.5V the extended input  
of –0.125 • VREF to 1.125 • VREF is limited by the absolute maximum  
Note 6: Integral nonlinearity is defined as the deviation of a code from  
a straight line passing through the actual endpoints of the transfer  
curve. The deviation is measured from the center of the quantization  
band.  
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%  
(external oscillator).  
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%  
(external oscillator).  
Note 9: The converter is in external SCK mode of operation such that  
the SCK pin is used as digital input. The frequency of the clock signal  
driving SCK during the data output is fESCK and is expressed in kHz.  
rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF  
0.267V + 0.89 • VCC the input voltage range is –0.3V to 1.125 • VREF  
≤
.
For 0.267V + 0.89 • VCC < VREF ≤ VCC the input voltage range is –0.3V  
to VCC + 0.3V.  
Note 15: VS is the voltage applied to a channel input. VD is the voltage  
applied to the MUX output.  
Note 16: VCC(DC) = 4.1V, VCC(AC) = 2.8VP-P  
.
5
LTC2424/LTC2428  
U
U
U
PIN FUNCTIONS  
GND (Pins 1, 6, 16, 18, 22, 27, 28): Ground. Should be  
connected directly to a ground plane through a minimum  
length trace or it should be the single-point-ground in a  
single-point grounding system.  
CSMUX (Pin 20): MUX Chip Select Input. A logic high on  
this input allows the MUX to receive a channel address. A  
logic low enables the selected MUX channel and connects  
it to the MUXOUT pin for A/D conversion. For normal  
operation, drive this pin in parallel with CSADC.  
VCC (Pins 2, 8): Positive Supply Voltage. 2.7V ≤ VCC  
≤
5.5V. Bypass to GND with a 10µF tantalum capacitor in  
parallel with 0.1µF ceramic capacitor as close to the part  
as possible.  
DIN (Pin 21): Digital Data Input. The multiplexer address  
is shifted into this input on the last four rising CLK edges  
before CSMUX goes low.  
FSSET (Pin 3): Full-Scale Set Input. This pin defines the  
full-scale input value. When VIN = FSSET, the ADC outputs  
full scale (FFFFFH). The total reference voltage (VREF) is  
CSADC (Pin 23): ADC Chip Select Input. A low on this pin  
enables the SDO digital output and following each conver-  
sion, the ADC automatically enters the Sleep mode and  
remains in this low power state as long as CSADC is high.  
A high on this pin also disables the SDO digital output. A  
low-to-high transition on CSADC during the Data Output  
state aborts the data transfer and starts a new conversion.  
Fornormaloperation,drivethispininparallelwithCSMUX.  
FSSET – ZSSET  
.
ADCIN (Pin 4): Analog Input. The input voltage range is  
–0.125 • VREF to 1.125 • VREF. For VREF > 2.5V the input  
voltage range may be limited by the pin absolute maxi-  
mum rating of –0.3V to VCC + 0.3V.  
SDO (Pin 24): Three-State Digital Output. During the data  
output period this pin is used for serial data output. When  
the chip select CSADC is high (CSADC = VCC), the SDO pin  
is in a high impedance state. During the Conversion and  
Sleep periods, this pin can be used as a conversion status  
output. The conversion status can be observed by pulling  
CSADC low.  
ZSSET (Pin 5): Zero-Scale Set Input. This pin defines the  
zero-scaleinputvalue. WhenVIN =ZSSET, theADCoutputs  
zeroscale(00000H).ForpincompatibilitywiththeLTC2404/  
LTC2408 this pin must be grounded.  
MUXOUT(Pin7):MUXOutput.Thispinistheoutputofthe  
multiplexer. Tie to ADCIN for normal operation.  
CH0 (Pin 9): Analog Multiplexer Input.  
CH1 (Pin 10): Analog Multiplexer Input.  
CH2 (Pin 11): Analog Multiplexer Input.  
CH3 (Pin 12): Analog Multiplexer Input.  
SCK(Pin25):ShiftClockforDataOut. Thisclocksynchro-  
nizes the serial data transfer of the ADC data output. Data  
isshiftedoutofSDOonthefallingedgeofSCK. Fornormal  
operation, drive this pin in parallel with CLK.  
FO (Pin 26): Digital input which controls the ADC’s notch  
frequencies and conversion time. When the FO pin is  
connectedtoVCC (FO =VCC), theconverterusesitsinternal  
oscillator and the digital filter first null is located at 50Hz.  
When the FO pin is connected to GND (FO = OV), the  
converter uses its internal oscillator and the digital filter  
first null is located at 60Hz. When FO is driven by an  
external clock signal with a frequency fEOSC, the converter  
uses this signal as its clock and the digital filter first null is  
located at a frequency fEOSC/2560. The resulting output  
word rate is fEOSC/20480.  
CH4(Pin13):AnalogMultiplexerInput. Noconnectonthe  
LTC2424.  
CH5(Pin14):AnalogMultiplexerInput. Noconnectonthe  
LTC2424.  
CH6(Pin15):AnalogMultiplexerInput. Noconnectonthe  
LTC2424.  
CH7(Pin17):AnalogMultiplexerInput. Noconnectonthe  
LTC2424.  
CLK (Pin 19): Shift Clock for Data In. This clock synchro-  
nizes the serial data transfer into the MUX. For normal  
operation, drive this pin in parallel with SCK.  
6
LTC2424/LTC2428  
U
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FU CTIO AL BLOCK DIAGRA  
INTERNAL  
OSCILLATOR  
V
CC  
GND  
AUTOCALIBRATION  
AND CONTROL  
F
O
CH0  
CH1  
CH2  
CH3  
CH4  
CH5  
CH6  
CH7  
(INT/EXT)  
∫
∫
∫
SDO  
SERIAL  
INTERFACE  
∑
ADC  
SCK  
ZS  
SET  
CSADC  
FS  
SET  
DECIMATING FIR  
CSMUX  
CHANNEL  
SELECT  
DAC  
D
IN  
CLK  
24248 BD  
TEST CIRCUITS  
V
CC  
3.4k  
SDO  
SDO  
3.4k  
C
LOAD  
= 20pF  
C
= 20pF  
LOAD  
Hi-Z TO V  
OH  
OH  
V
OL  
V
OH  
TO V  
Hi-Z TO V  
TO Hi-Z  
24248 TC01  
OL  
OL  
V
V
TO V  
OH  
OL  
TO Hi-Z  
24248 TC02  
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APPLICATIONS INFORMATION  
Converter Operation Cycle  
(DIN). By tying SCK to CLK and CSADC to CSMUX, the  
interface requires only four wires.  
TheLTC2424/LTC2428arelowpower,4-/8-channeldelta-  
sigma analog-to-digital converters with easy-to-use  
4-wire interfaces. Their operation is simple and made up  
of four states. The converter operation begins with the  
conversion, followed by a low power sleep state and  
concluded with the data output (see Figure 1). Channel  
selectionmaybeperformedwhilethedeviceisinthesleep  
state or at the conclusion of the data output state. The  
interface consists of serial data output (SDO), serial clock  
(CLK/SCK), chip select (CSADC/CSMUX) and data input  
Initially, the LTC2424 or LTC2428 performs a conversion.  
Once the conversion is complete, the device enters the  
sleep state. While in the sleep state, power consumption  
is reduced by an order of magnitude. The part remains in  
the sleep state as long as CSADC is logic HIGH. The  
conversion result is held indefinitely in a static shift  
register while the converter is in the sleep state.  
Channel selection for the next conversion cycle is per-  
formed while the device is in the sleep state or at the end  
7
LTC2424/LTC2428  
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APPLICATIONS INFORMATION  
or external SCK. These modes do not require program-  
ming configuration registers; moreover, they do not dis-  
turbthecyclicoperationdescribedabove. Thesemodesof  
operation are described in detail in the Serial Interface  
Timing Modes section.  
CONVERT  
CHANNEL SELECT  
(SLEEP)  
SLEEP  
Conversion Clock  
A major advantage delta-sigma converters offer over  
conventional type converters is an on-chip digital filter  
(commonly known as Sinc or Comb filter). For high  
resolution, low frequency applications, this filter is typi-  
cally designed to reject line frequencies of 50 or 60Hz plus  
their harmonics. In order to reject these frequencies in  
excess of 110dB, a highly accurate conversion clock is  
required. The LTC2424/LTC2428 incorporate an on-chip  
highly accurate oscillator. This eliminates the need for  
externalfrequencysettingcomponentssuchascrystalsor  
oscillators.Clockedbytheon-chiposcillator,theLTC2424/  
LTC2428 reject line frequencies (50 or 60Hz ±2%) a  
minimum of 110dB.  
CSADC  
AND  
1
SCK  
0
DATA OUTPUT  
(CHANNEL SELECT)  
24248 F01  
Figure 1. LTC2428 State Transition Diagram  
of the data output state. A specific channel is selected by  
applyinga4-bitserialwordtotheDIN pinontherisingedge  
ofCLKwhileCSMUXisHIGH,seeFigure4andTable3.The  
channel is selected based on the last four bits clocked into  
the DIN pin before CSMUX goes low. If DIN is all 0’s, the  
previous channel remains selected.  
Ease of Use  
The LTC2424/LTC2428 data output has no latency, filter  
settlingorredundantdataassociatedwiththeconversion  
cycle.Thereisaone-to-onecorrespondencebetweenthe  
conversion and the output data. Therefore, multiplexing  
an analog input voltage is easy.  
In the example, Figure 4, the MUX channel is selected  
during the sleep state, just before the data output state  
begins. Once the channel selection is complete, the device  
remains in the sleep state as long as CSADC remains  
HIGH.  
The LTC2424/LTC2428 perform offset and full-scale cali-  
brations every conversion cycle. This calibration is trans-  
parent to the user and has no effect on the cyclic operation  
described above. The advantage of continuous calibration  
is extreme stability of offset and full-scale readings with  
respect to time, supply voltage change and temperature  
drift.  
Once CSADC is pulled low, the device begins outputting  
theconversionresult.Thereisnolatencyintheconversion  
result. Since there is no latency, the first conversion  
following a change in input channel is valid and corre-  
sponds to that channel. The data output corresponds to  
theconversionjustperformed. Thisresultisshiftedouton  
the serial data output pin (SDO) under the control of the  
serial clock (SCK). Data is updated on the falling edge of  
SCK allowing the user to reliably latch data on the rising  
edge of SCK, see Figure 4. The data output state is  
concluded once 24 bits are read out of the ADC or when  
CSADCisbroughtHIGH.Thedeviceautomaticallyinitiates  
a new conversion and the cycle repeats.  
Power-Up Sequence  
The LTC2424/LTC2428 automatically enter an internal  
reset state when the power supply voltage VCC drops  
below approximately 2.2V. When the VCC voltage rises  
above this critical threshold, the converter creates an  
internal power-on-reset (POR) signal with duration of  
approximately 0.5ms. The POR signal clears all internal  
registers within the ADC and initiates a conversion. At  
Through timing control of the CSADC and SCK pins, the  
LTC2424/LTC2428 offer two modes of operation: internal  
8
LTC2424/LTC2428  
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APPLICATIONS INFORMATION  
power-up,themultiplexerchannelisdisabledandshould  
be programmed once the device enters the sleep state.  
TheresultsofthefirstconversionfollowingaPORarenot  
valid since a multiplexer channel was disabled.  
any channel input pin (CH0 to CH7) without affecting the  
performance of the device. In the physical layout, it is im-  
portanttomaintaintheparasiticcapacitanceoftheconnec-  
tion between this series resistance and the channel input  
pin as low as possible; therefore, the resistor should be  
located as close as practical to the channel input pin. The  
effectoftheseriesresistanceontheconverteraccuracycan  
be evaluated from the curves presented in the Analog In-  
put/Reference Current section. In addition, a series resis-  
torwillintroduceatemperaturedependentoffseterrordue  
to the input leakage current. A 1nA input leakage current  
Reference Voltage Range  
The LTC2424/LTC2428 can accept a reference voltage  
from 0V to VCC. The converter output noise is determined  
by the thermal noise of the front-end circuits, and as such,  
its value in microvolts is nearly constant with reference  
voltage. A decrease in reference voltage will not signifi-  
cantly improve the converter’s effective resolution. On the  
other hand, a reduced reference voltage will improve the  
overall converter INL performance. The recommended  
range for the LTC2424/LTC2428 voltage reference is  
100mV to VCC.  
will develop a 1ppm offset error on a 5k resistor if VREF  
=
5V. This error has a very strong temperature dependency.  
Output Data Format  
TheLTC2424/LTC2428serialoutputdatastreamis24bits  
long. The first 4 bits represent status information indicat-  
ing the sign, input range and conversion state. The next 20  
bits are the conversion result, MSB first.  
Input Voltage Range  
Theconverterisabletoaccommodatesystemleveloffset  
and gain errors as well as system level overrange  
situations due to its extended input range, see Figure 2.  
The LTC2424/LTC2428 converts input signals within the  
extended input range of –0.125 • VREF to 1.125 • VREF  
(VREF = FSSET – ZSSET).  
The LTC2424/LTC2428 can be interchanged with the  
LTC2404/LTC2408. Thetwodevicesaredesignedtoallow  
the user to incorporate either device in the same design as  
long as ZSSET of the LTC2424/LTC2428 is tied to ground.  
While the LTC2424/LTC2428 output word lengths are 24  
bits (as opposed to the 32-bit output of the LTC2404/  
LTC2408), their output clock timing can be identical to the  
LTC2404/LTC2408. As shown in Figure 3, the LTC2424/  
LTC2408dataoutputisconcludedonthefallingedgeofthe  
24th serial clock (SCK). In order to maintain drop-in com-  
patibilitywiththeLTC2404/LTC2408,itispossibletoclock  
the LTC2424/LTC2428 with an additional 8 serial clock  
pulses. This results in 8 additional output bits which are  
always logic HIGH.  
For large values of VREF this range is limited to a voltage  
rangeof–0.3Vto(VCC +0.3V).Beyondthisrangetheinput  
ESDprotectiondevicesbegintoturnonandtheerrorsdue  
to the input leakage current increase rapidly.  
Input signals applied to VIN may extend below ground by  
–300mVandaboveVCCby300mV.Inordertolimitanyfault  
current, a resistor of up to 5k may be added in series with  
V
CC  
+ 0.3V  
Bit 23 (first output bit) is the end of conversion (EOC)  
indicator. This bit is available at the SDO pin during the  
conversion and sleep states whenever the CS pin is LOW.  
This bit is HIGH during the conversion and goes LOW  
when the conversion is complete.  
9/8V  
REF  
V
REF  
ABSOLUTE  
MAXIMUM  
INPUT  
NORMAL  
INPUT  
RANGE  
EXTENDED  
INPUT  
RANGE  
1/2V  
REF  
RANGE  
Bit 22 (second output bit) is a dummy bit (DMY) and is  
always LOW.  
0
–1/8V  
REF  
Bit 21 (third output bit) is the conversion result sign indi-  
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this  
bitisLOW.Thesignbitchangesstateduringthezerocode.  
–0.3V  
24248 F02  
Figure 2. LTC2424/LTC2428 Input Range  
9
LTC2424/LTC2428  
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CSADC  
8
8
8
8 (OPTIONAL)  
SCK  
SDO  
EOC = 1  
EOC = 0  
SLEEP  
EOC = 1  
DATA OUT  
4 STATUS BITS 20 DATA BITS  
LAST 8 BITS ALWAYS 1  
DATA OUTPUT  
CONVERSION  
CONVERSION  
24248 F03  
Figure 3. LTC2424/LTC2428 Compatible Timing with the LTC2404/LTC2408  
Bit 20 (forth output bit) is the extended input range (EXR)  
indicator. If the input is within the normal input range  
0 ≤ VIN ≤ VREF, this bit is LOW. If the input is outside the  
normal input range, VIN > VREF or VIN < 0, this bit is HIGH.  
indicating a new conversion cycle has been initiated. This  
bit serves as EOC (Bit 23) for the next conversion cycle.  
Table 2 summarizes the output data format.  
As long as the voltage on the VIN pin is maintained within  
the –0.3V to (VCC + 0.3V) absolute maximum operating  
range, a conversion result is generated for any input value  
from –0.125 • VREF to 1.125 • VREF. For input voltages  
greaterthan1.125•VREF,theconversionresultisclamped  
to the value corresponding to 1.125 • VREF. For input  
voltages below –0.125 • VREF, the conversion result is  
The function of these bits is summarized in Table 1.  
Table 1. LTC2424/LTC2428 Status Bits  
Bit 23  
EOC  
Bit 22  
DMY  
Bit 21  
SIG  
Bit 20  
EXR  
Input Range  
> V  
V
0
0
0
0
0
0
0
0
1
1
1
0
0
1
IN  
REF  
0 < V ≤ V  
IN  
REF  
clamped to the value corresponding to –0.125 • VREF  
.
+
–
V
V
= 0 /0  
1/0  
0
IN  
IN  
< 0  
Channel Selection  
Bit 19 (fifth output bit) is the most significant bit (MSB).  
Bits 19-0 are the 20-bit conversion result MSB first.  
Bit 0 is the least significant bit (LSB).  
Typically, CSADC and CSMUX are tied together or CSADC  
is inverted and drives CSMUX. SCK and CLK are tied  
together and driven with a common clock signal. During  
channel selection, CSMUX is HIGH. Data is shifted into the  
DIN pin on the rising edge of CLK, see Figure 4. Table 3  
shows the bit combinations forchannel selection. Inorder  
to enable the multiplexer output, CSMUX must be pulled  
LOW. The multiplexer should be programmed after the  
previousconversioniscomplete.Inordertoguaranteethe  
conversioniscomplete,themultiplexeraddressingshould  
be delayed a minimum tCONV (approximately 133ms for a  
60Hz notch) after the data out is read.  
DataisshiftedoutoftheSDOpinundercontroloftheserial  
clock (SCK), see Figure 4. Whenever CSADC is HIGH, SDO  
remains high impedance and any SCK clock pulses are  
ignored by the internal data out shift register.  
In order to shift the conversion result out of the device,  
CSADC must first be driven LOW. EOC is seen at the SDO  
pinofthedeviceonceCSADCispulledLOW. EOCchanges  
real time from HIGH to LOW at the completion of a  
conversion. This signal may be used as an interrupt for an  
external microcontroller. Bit 23 (EOC) can be captured on  
the first rising edge of SCK. Bit 22 is shifted out of the  
deviceonthefirstfallingedgeofSCK. Thefinaldatabit(Bit  
0) is shifted out on the falling edge of the 23rd SCK and  
may be latched on the rising edge of the 24th SCK pulse.  
On the falling edge of the 24th SCK pulse, SDO goes HIGH  
While the multiplexer is being programmed, the ADC is in  
a low power sleep state. Once the MUX addressing is  
complete, the data from the preceding conversion can be  
read. A new conversion cycle is initiated following the data  
read cycle with the analog input tied to the newly selected  
channel.  
10  
LTC2424/LTC2428  
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APPLICATIONS INFORMATION  
t
CONV  
CSMUX/CSADC  
SDO  
Hi-Z  
Hi-Z  
EOC  
“0”  
SIG  
EXT  
MSB  
LSB  
BIT 23 BIT 22  
BIT 0  
SCK/CLK  
D
IN  
EN  
D2  
D1  
D0  
DON’T CARE  
24248 F04  
Figure 4. Typical Data Input/Output Timing  
Table 2. LTC2424/LTC2428 Output Data Format  
Bit 23  
EOC  
Bit 22  
DMY  
Bit 21  
SIG  
Bit 20  
EXR  
Bit 19  
MSB  
Bit 18  
Bit 17  
Bit 16  
Bit 15  
…
Bit 0  
LSB  
Input Voltage  
> 9/8 • V  
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
1
1
0
1
0
1
0
1
0
1
0
1
0
0
IN  
REF  
9/8 • V  
REF  
V
V
+ 1LSB  
1
REF  
REF  
1
3/4V + 1LSB  
1
REF  
3/4V  
1
REF  
1/2V + 1LSB  
1
REF  
1/2V  
1
REF  
1/4V + 1LSB  
1
REF  
1/4V  
1
REF  
+
–
0 /0  
1/0*  
0
–1LSB  
–1/8 • V  
0
REF  
V
< –1/8 • V  
0
IN  
REF  
*The sign bit changes state during the 0 code.  
Table 3. Logic Table for Channel Selection  
Frequency Rejection Selection (FO Pin Connection)  
CHANNEL STATUS  
EN  
0
D2  
X
0
D1  
X
0
D0  
X
0
The LTC2424/LTC2428 internal oscillator provides better  
than 110dB normal mode rejection at the line frequency  
and all its harmonics for 50Hz ±2% or 60Hz ±2%. For  
60Hz rejection, FO (Pin 26) should be connected to GND  
(Pin 1) while for 50Hz rejection the FO pin should be  
connected to VCC (Pin 2).  
All Off  
CH0  
1
CH1  
1
0
0
1
CH2  
1
0
1
0
CH3  
1
0
1
1
CH4*  
1
1
0
0
The selection of 50Hz or 60Hz rejection can also be made  
by driving FO to an appropriate logic level. A selection  
change during the sleep or data output states will not  
disturb the converter operation. If the selection is made  
CH5*  
1
1
0
1
CH6*  
CH7*  
1
1
1
0
1
1
1
1
*Not used for the LTC2424.  
11  
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during the conversion state, the result of the conversion in  
progress may be outside specifications but the following  
conversions will not be affected.  
converter uses an external serial clock. If the change  
occurs during the conversion state, the result of the  
conversion in progress may be outside specifications but  
the following conversions will not be affected. If the  
change occurs during the data output state and the  
converterisintheInternalSCKmode,theserialclockduty  
cycle may be affected but the serial data stream will  
remain valid.  
When a fundamental rejection frequency different from  
50Hz or 60Hz is required or when the converter must be  
synchronized with an outside source, the LTC2424/  
LTC2428 can operate with an external conversion clock.  
The converter automatically detects the presence of an  
external clock signal at the FO pin and turns off the internal  
oscillator. The frequency fEOSC of the external signal must  
be at least 2560Hz (1Hz notch frequency) to be detected.  
The external clock signal duty cycle is not significant as  
long as the minimum and maximum specifications for the  
high and low periods tHEO and tLEO are observed.  
Table 4 summarizes the duration of each state as a  
function of FO.  
–60  
–70  
–80  
While operating with an external conversion clock of a  
frequency fEOSC, the LTC2424/LTC2428 provide better  
than 110dB normal mode rejection in a frequency range  
fEOSC/2560 ±4% and its harmonics. The normal mode  
rejection as a function of the input frequency deviation  
from fEOSC/2560 is shown in Figure 5.  
–90  
–100  
–110  
–120  
–130  
–140  
Whenever an external clock is not present at the F pin the  
O
–12  
–8  
–4  
0
4
8
12  
converter automatically activates its internal oscillator  
and enters the Internal Conversion Clock mode. The  
LTC2424/LTC2428 operation will not be disturbed if the  
change of conversion clock source occurs during the  
sleep state or during the data output state while the  
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)  
24248 F05  
Figure 5. LTC2424/LTC2428 Normal Mode Rejection When  
Using an External Oscillator of Frequency fEOSC  
Table 4. LTC2424/LTC2428 State Duration  
State  
Operating Mode  
Duration  
133ms  
160ms  
CONVERT  
Internal Oscillator  
F = LOW (60Hz Rejection)  
O
F = HIGH (50Hz Rejection)  
O
External Oscillator  
F = External Oscillator  
20480/f  
(In Seconds)  
EOSC  
O
with Frequency f  
kHz  
EOSC  
(f  
EOSC  
/2560 Rejection)  
SLEEP  
As Long As CSADC = HIGH Until CSADC = 0 and SCK  
DATA OUTPUT  
Internal Serial Clock  
External Serial Clock with  
F = LOW/HIGH  
(Internal Oscillator)  
As Long As CSADC = LOW But Not Longer Than 1.67ms  
(32 SCK cycles)  
O
F = External Oscillator with  
As Long As CSADC = LOW But Not Longer Than 256/f  
ms  
EOSC  
O
Frequency f  
kHz  
(32 SCK cycles)  
EOSC  
As Long As CSADC = LOW But Not Longer Than 32/f ms  
SCK  
Frequency f  
kHz  
(32 SCK cycles)  
SCK  
1
MAXIMUM OUTPUT  
WORD RATE (OWR)  
OWR =  
inHz  
t
CONVERT + tDATAOUTPUT  
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Operation at Higher Data Output Rates  
dataratewitha5Vreference. Therelationshipbetweenthe  
output data rate (ODR) and the frequency applied to the FO  
pin (FO) is:  
The LTC2424/LTC2428 typically operate with an internal  
oscillator of 153.6kHz. This corresponds to a notch fre-  
quency of 60Hz and an output rate of 7.5 samples/second.  
The internal oscillator is enabled if the FO pin is logic LOW  
(logic HIGH for a 50Hz notch). It is possible to drive the FO  
pin with an external oscillator for higher data output rates.  
As shown in Figure 6, an external clock of 2.048MHz  
applied to the FO pin results in a notch frequency of 800Hz  
with a data output rate of 100 samples/second.  
ODR = FO/20480  
For output data rates up to 50 samples/second, the total  
unadjusted error (TUE) is better than 16 bits, and better  
than 12 bits at 100 samples/second. As shown in Figure 8,  
for output data rates of 100 samples/second, the TUE is  
better than 15 bits for VREF below 2.5V. Figure 9 shows an  
unaveraged total unadjusted error for the LTC2424 or  
LTC2428 operating at 100 samples/second with VREF =  
2.5V.Figure10showsthesamedeviceoperatingwitha5V  
reference and an output data rate of 7.5 samples/second.  
Figure 7 shows the total unadjusted error (Offset Error +  
Full-Scale Error + INL + DNL) as a function of the output  
LTC2424  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
GND  
GND  
GND  
256  
R9 1k  
10k  
R8 1k  
R7 5k  
12 BITS  
13 BITS  
OUTPUT RATE = 100sps  
V
CC  
224  
192  
160  
128  
96  
3
F
FS  
O
R6 47k  
SET  
10 TVEN POT  
SWITCH  
4
SCK  
SDO  
ADCIN  
C8 5pF  
5
ZS  
SET  
6
C9  
+
CSADC  
GND  
C6  
270pF  
0.1µF  
5V  
7
HCO4  
6
GND  
MUXOUT  
HCO4  
8
5
13  
11  
9
3
2
1
D
V
CC  
IN  
14 BITS  
15 BITS  
9
4
64  
7
CSMUX  
CLK  
CH0  
CH1  
CH2  
CH3  
NC  
10  
11  
12  
13  
14  
C7  
10pF  
12  
10  
8
32  
GND  
NC  
0
3.0 3.5  
1.0 1.5 2.0 2.5  
4.0 4.5 5.0  
REFERENCE VOLTAGE (V)  
GND  
NC  
24248 F08  
24248 F06  
NC  
Figure 8. Total Error vs VREF (Output Rate = 100sps)  
Figure 6. Selectable 100 Sample/Second Turbo Mode  
10  
V
V
= 5V  
REF  
CC  
5
= 2.5V  
256  
V
= 5V  
12 BITS  
REF  
0
–5  
224  
192  
160  
–10  
–15  
–20  
13 BITS  
128  
96  
–25  
–30  
–35  
–40  
14 BITS  
16 BITS  
64  
32  
0
0
2.5  
INPUT VOLTAGE (V)  
50  
100  
0
150  
24248 F09  
OUTPUT RATE (SAMPLES/SEC)  
24248 F07  
Figure 9. Total Unadjusted Error at  
100 Samples/Second (No Averaging)  
Figure 7. Total Error vs Output Rate (VREF = 5V)  
13  
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6
300mVP-P input signal at 2Hz). The exceptional DC  
performance of the LTC2424/LTC2428 enables signals to  
be digitized independent of a large DC offset. Figures 12a  
and 12b show the dynamic performance with a 15Hz  
signal superimposed on a 2V DC level. The same signal  
with no DC level is shown in Figures 12c and 12d.  
4
2
0
–2  
–4  
–6  
–8  
–10  
SERIAL INTERFACE  
The LTC2424/LTC2428 transmit the conversion results,  
program the channel selection, and receive the start of  
conversion command through a synchronous 4-wire in-  
terface(SCK=CLK,CSADC=CSMUX).Duringtheconver-  
sion and sleep states, this interface can be used to assess  
the converter status. While in the sleep state this interface  
may be used to program an input channel. During the data  
output state, it is used to read the conversion result.  
0
5
INPUT VOLTAGE (V)  
24248 F10  
Figure 10. Total Unadjusted Error at  
7.5 Samples/Second (No Averaging)  
At 100 samples/second, the LTC2424/LTC2428 can be  
used to capture transient data. This is useful for monitor-  
ingsettlingorautogainranginginasystem.TheLTC2424/  
LTC2428 can monitor signals at an output rate of 100  
samples/second.Afteracquiring100samples/seconddata,  
the FO pin may be driven LOW enabling 60Hz rejection to  
110dB and the highest possible DC accuracy. The no  
latency architecture of the LTC2424/LTC2428 allows con-  
secutive readings (one at 100 samples/second the next at  
7.5 samples/second) without interaction between the two  
readings.  
ADC Serial Clock Input/Output (SCK)  
The serial clock signal present on SCK (Pin 25) is used to  
synchronizethedatatransfer.Eachbitofdataisshiftedout  
of the SDO pin on the falling edge of the serial clock.  
In the Internal SCK mode of operation, the SCK pin is an  
output and the LTC2424/LTC2428 creates its own serial  
clock by dividing the internal conversion clock by 8. In the  
External SCK mode of operation, the SCK pin is used as  
input. The internal or external SCK mode is selected on  
power-up and then reselected every time a HIGH-to-LOW  
transition is detected at the CSADC pin. If SCK is HIGH or  
As shown in Figure 11, the LTC2424/LTC2428 can cap-  
ture transient data with 90dB of dynamic range (with a  
0
0.20  
2Hz  
100sps  
0.15  
0.10  
–20  
–40  
0V OFFSET  
0.05  
–60  
0
–0.05  
–0.10  
–0.15  
–0.20  
–80  
–100  
–120  
0
25  
50  
0.5  
1
1.5  
2
2.5  
FREQUENCY (Hz)  
TIME (SEC)  
24248 F11a  
24248 F11b  
Figure 11a. Digitized Waveform  
Figure 11. Transient Signal Acquisition  
Figure 11b. Output FFT  
14  
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0
–20  
2.20  
2.15  
2.10  
2.05  
2.00  
1.95  
1.90  
1.85  
1.80  
–40  
–60  
–80  
–100  
–120  
0
25  
50  
0.5  
1
1.5  
2
2.5  
TIME (SEC)  
FREQUENCY (Hz)  
24248 F12b  
24248 F12a  
Figure 12a. Digitized Waveform with 2V DC Offset  
Figure 12b. FFT Waveform with 2V DC Offset  
0
0.20  
0.15  
0.10  
–20  
–40  
0.05  
–60  
0.00  
–0.05  
–0.10  
–0.15  
–0.20  
–80  
–100  
–120  
0
25  
50  
0.5  
1
1.5  
2
2.5  
FREQUENCY (Hz)  
TIME (SEC)  
24248 F12c  
24248 F12d  
Figure 12c. Digitized Waveform with No Offset  
Figure 12d. FFT Waveform with No Offset  
Figure 12. Using the LTC2424/LTC2428’s High Accuracy Wide Dynamic Range  
to Digitize a 300mVP-P 15Hz Waveform with a Large DC Offset (VCC = 5V, VREF = 5V)  
floatingatpower-uporduringthistransition,theconverter  
is used as an end of conversion indicator during the  
enters the internal SCK mode. If SCK is LOW at power-up  
or during this transition, the converter enters the external  
SCK mode.  
conversion and sleep states.  
When CSADC (Pin 23) is HIGH, the SDO driver is switched  
to a high impedance state. This allows sharing the serial  
interface with other devices. If CSADC is LOW during the  
convert or sleep state, SDO will output EOC. If CSADC is  
LOW during the conversion phase, the EOC bit appears  
HIGH on the SDO pin. Once the conversion is complete,  
EOC goes LOW. The device remains in the sleep state until  
the first rising edge of SCK occurs while CSADC = 0.  
Multiplexer Serial Input Clock (CLK)  
Generally, this pin is externally tied to SCK for 4-wire op-  
eration.OntherisingedgeofCLK(Pin19)withCSMUXheld  
HIGH,dataisseriallyshiftedintothemultiplexer.IfCSMUX  
is LOW the CLK input will be disabled and the channel  
selection unchanged.  
ADC Chip Select Input (CSADC)  
Serial Data Output (SDO)  
TheactiveLOWchipselect,CSADC(Pin23),isusedtotest  
the conversion status and to enable the data output  
transfer as described in the previous sections.  
The serial data output pin, SDO (Pin 24), drives the serial  
data during the data output state. In addition, the SDO pin  
15  
LTC2424/LTC2428  
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In addition, the CSADC signal can be used to trigger a new  
conversion cycle before the entire serial data transfer has  
been completed. The LTC2424/LTC2428 will abort any  
serial data transfer in progress and start a new conversion  
cycle anytime a LOW-to-HIGH transition is detected at the  
CSADC pin after the converter has entered the data output  
state (i.e., after the first rising edge of SCK occurs with  
CSADC = 0).  
External Serial Clock (SPI/MICROWIRE Compatible)  
This timing mode uses an external serial clock (SCK) to  
shift out the conversion result, see Figure 13. This same  
external clock signal drives the CLK pin in order to pro-  
gram the multiplexer. A single CS signal drives both the  
multiplexer CSMUX and converter CSADC inputs. This  
common signal is used to monitor and control the state of  
the conversion as well as enable the channel selection.  
Multiplexer Chip Select (CSMUX)  
The serial clock mode is selected on the falling edge of  
CSADC. To select the external serial clock mode, the serial  
clock pin (SCK) must be LOW during each CSADC falling  
edge.  
For 4-wire operation, this pin is tied directly to CSADC or  
the output of an inverter tied to CSADC. CSMUX (Pin 20)  
is driven HIGH during selection of a multiplexer channel.  
On the falling edge of CSMUX, the selected channel is  
enabled and drives MUXOUT.  
The serial data output pin (SDO) is HI-Z as long as CSADC  
is HIGH. At any time during the conversion cycle, CSADC  
may be pulled LOW in order to monitor the state of the  
converter. While CSADC is LOW, EOC is output to the SDO  
pin. EOC = 1 while a conversion is in progress and EOC =  
0 if the device is in the sleep state. Independent of CSADC,  
the device automatically enters the low power sleep state  
once the conversion is complete.  
Data Input (DIN)  
The data input to the multiplexer, DIN (Pin 21), is used to  
program the multiplexer. The input channel is selected by  
serially shifting a 4-bit input word into the DIN pin under  
the control of the multiplexer clock, CLK. Data is shifted  
into the multiplexer on the rising edge of CLK. Table 3  
shows the logic table for channel selection. In order to  
select or change a previously programmed channel, an  
enable bit (DIN = 1) must proceed the 3-bit channel select  
serialdata. TheusermaysetDIN =0tocontinuallyconvert  
on the previously selected channel.  
While the device is in the sleep state, prior to entering the  
data output state, the user may program the multiplexer.  
As shown in Figure 13, the multiplexer channel is selected  
by serial shifting a 4-bit word into the DIN pin on the rising  
edge of CLK (CLK is tied to SCK). The first bit is an enable  
bit that must be HIGH in order to program a channel. The  
next three bits determine which channel is selected, see  
Table 3. On the falling edge of CSMUX, the new channel is  
selectedandwillbevalidforthefirstconversionperformed  
followingthedataoutputstate.Clocksignalsappliedtothe  
CLK pin while CSMUX is LOW (during the data output  
state) will have no effect on the channel selection. Further-  
more, if DIN is held LOW or CLK is held LOW during the  
sleep state, the channel selection is unchanged.  
SERIAL INTERFACE TIMING MODES  
The LTC2424/LTC2428’s 4-wire interface is SPI and  
MICROWIRE compatible. This interface offers two modes  
of operation. These include an internal or external serial  
clock. The following sections describe both of these serial  
interface timing modes in detail. For both cases the  
converter can use the internal oscillator (FO = LOW or FO  
= HIGH) or an external oscillator connected to the FO pin.  
Refer to Table 5 for a summary.  
When the device is in the sleep state (EOC = 0), its  
conversion result is held in an internal static shift register.  
Table 5. LTC2424/LTC2428 Interface Timing Modes  
SCK  
Conversion  
Cycle  
Data  
Connection  
and  
Output  
Control  
Configuration  
External SCK  
Internal SCK  
Source  
External  
Internal  
Control  
Waveforms  
CSADC and SCK  
CSADC and SCK  
Figures 7, 8, 9  
Figures 10, 11  
CSADC ↓  
CSADC ↓  
16  
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2.7V TO 5.5V  
V
CC  
= 50Hz REJECTION  
= EXTERNAL OSCILLATOR  
= 60Hz REJECTION  
V
F
O
CC  
LTC2424/LTC2428  
0.1V  
CC  
FS  
CSMUX  
CSADC  
SCK  
CS  
SET  
TO V  
–0.12V  
TO 1.12V  
CH0  
REF  
REF  
TO CH7  
MUXOUT  
ADCIN  
SCK  
CLK  
D
IN  
ZS  
SDO  
SET  
GND  
CSADC/  
CSMUX  
SCK/CLK  
SDO  
TEST EOC  
TEST EOC  
BIT23  
BIT22 BIT21 BIT20 BIT19 BIT18  
SIG EXR MSB  
BIT4  
BIT0  
LSB  
TEST EOC  
Hi-Z  
Hi-Z  
Hi-Z  
D1  
D
IN  
DON’T CARE  
EN  
D2  
D0  
DON’T CARE  
24248 F13  
Figure 13. External Serial Clock Timing Diagram  
The device remains in the sleep state until the first rising  
edge of SCK is seen while CSADC is LOW. Data is shifted  
out the SDO pin on each falling edge of SCK. This enables  
external circuitry to latch the output on the rising edge of  
SCK. EOC can be latched on the first rising edge of SCK  
and the last bit of the conversion result can be latched on  
the 24th rising edge of SCK. On the 24th falling edge of  
SCK, thedevicebeginsanewconversion. SDOgoesHIGH  
(EOC = 1) indicating a conversion is in progress.  
While the device is performing the internal calibration, it is  
sensitive to ground current disturbances. Error currents  
flowing in the ground pin may lead to offset errors. If the  
SCK pin is toggling during the calibration, these ground  
disturbances will occur. The solution is to either drive the  
multiplexer clock input (CLK) separately from the ADC  
clock input (SCK), or program the multiplexer in the first  
1ms following the data output cycle. The remaining 65ms  
may be used to allow the input signal to settle.  
At the conclusion of the data cycle, CSADC may remain  
LOW and EOC monitored as an end-of-conversion inter-  
rupt. Alternatively, CSADC may be driven HIGH setting  
SDO to HI-Z. As described above, CSADC may be pulled  
LOWatanytimeinordertomonitortheconversionstatus.  
For each of these operations, CSMUX may be tied to  
CSADC without affecting the selected channel.  
Typically, CSADC remains LOW during the data output  
state. However, the data output state may be aborted by  
pulling CSADC HIGH anytime between the first rising edge  
and the 24th falling edge of SCK, see Figure 15. On the  
rising edge of CSADC, the device aborts the data output  
state and immediately initiates a new conversion. This is  
useful for systems not requiring all 24 bits of output data,  
aborting an invalid conversion cycle or synchronizing the  
start of a conversion.  
At the conclusion of the data output cycle, the converter  
enters a user transparent calibration cycle prior to actually  
performing a conversion on the selected input channel.  
Thisenablesa66ms(for60Hznotchfrequency)lookahead  
time for the multiplexer input. Following the data output  
cycle, the multiplexer input channel may be selected any  
time in this 66ms window by pulling CSADC HIGH and  
serial shifting data into the DIN pin, see Figure 14.  
Internal Serial Clock  
This timing mode uses an internal serial clock to shift out  
the conversion result and program the multiplexer, see  
Figure 16. A CS signal directly drives the CSADC input,  
while the inverse of CS drives the CSMUX input. The CS  
17  
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CSADC/  
CSMUX  
SCK/CLK  
TEST EOC  
TEST EOC  
BIT23 BIT22 BIT21 BIT20BIT19BIT18  
SIG EXR MSB  
BIT4  
BIT0  
LSB  
SDO  
Hi-Z  
D
DON’T CARE  
EN D2  
D1  
D0 DON’T CARE  
IN  
CONVERTER  
STATE  
CONV  
SLEEP  
DATA OUTPUT  
INTERNAL CALIBRATION  
66ms LOOK AHEAD  
CONVERSION ON SELECTED CHANNEL  
66ms CONVERT  
133ms CONVERSION CYCLE (OUTPUT RATE = 7.5Hz)  
24248 F14  
Figure 14. Use of Look Ahead to Program Multiplexer After Data Output  
2.7V TO 5.5V  
V
CC  
= 50Hz REJECTION  
= EXTERNAL OSCILLATOR  
= 60Hz REJECTION  
V
F
O
CC  
LTC2424/LTC2428  
0.1V  
CC  
FS  
CSMUX  
CSADC  
SCK  
CS  
SET  
TO V  
–0.12V  
TO 1.12V  
CH0  
REF  
REF  
TO CH7  
MUXOUT  
ADCIN  
SCK  
CLK  
D
IN  
ZS  
SDO  
SET  
GND  
CSADC/  
CSMUX  
SCK/CLK  
SDO  
TEST EOC  
TEST EOC  
BIT23  
BIT22 BIT21 BIT20 BIT19 BIT18  
SIG EXR MSB  
BIT9 BIT8  
Hi-Z  
Hi-Z  
D1  
D
DON’T CARE  
EN  
D2  
D0  
DON’T CARE  
IN  
24248 F15  
Figure 15. External Serial Clock with Reduced Data Output Length Timing Diagram  
signal is used to monitor and control the state of the  
conversion cycles as well as enable the channel selection.  
The multiplexer is programmed during the data output  
state. Theinternalserialclock(SCK)generatedbytheADC  
is applied to the multiplexer clock input (CLK).  
resistor is active on the SCK pin during the falling edge of  
CSADC; therefore, the internal serial clock timing mode is  
automatically selected if SCK is not externally driven.  
The serial data output pin (SDO) is HI-Z as long as CSADC  
is HIGH. At any time during the conversion cycle, CSADC  
may be pulled LOW in order to monitor the state of the  
converter. Once CSADC is pulled LOW, SCK goes LOW  
and EOC is output to the SDO pin. EOC = 1 while a  
conversion is in progress and EOC = 0 if the device is in the  
sleep state.  
In order to select the internal serial clock timing mode, the  
serial clock pin (SCK) must be floating (HI-Z) or pulled  
HIGHpriortothefallingedgeofCSADC.Thedevicewillnot  
enter the internal serial clock mode if SCK is driven LOW  
on the falling edge of CSADC. An internal weak pull-up  
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2.7V TO 5.5V  
V
CC  
= 50Hz REJECTION  
= EXTERNAL OSCILLATOR  
= 60Hz REJECTION  
V
F
O
CC  
LTC2424/LTC2428  
0.1V  
CC  
FS  
CSMUX  
CS  
SET  
TO V  
10k  
–0.12V  
TO 1.12V  
CH0  
CSADC  
SCK  
REF  
REF  
TO CH7  
MUXOUT  
ADCIN  
CLK  
D
IN  
ZS  
SDO  
SET  
GND  
CSMUX  
CSADC  
SCKCLK  
SDO  
t
EOCtest  
TEST EOC  
TEST EOC  
BIT23 BIT22 BIT21 BIT20 BIT19 BIT18  
SIG EXR MSB  
BIT4 BIT3 BIT2 BIT1 BIT0  
LSB  
TEST EOC  
Hi-Z  
Hi-Z  
Hi-Z  
D
IN  
DON’T CARE  
EN D2  
D1  
D0  
DON’T CARE  
24248 F16  
Figure 16. Internal Serial Clock Timing Diagram  
WhentestingEOC,iftheconversioniscomplete(EOC=0),  
thedevicewillexitthesleepstateandenterthedataoutput  
state if CSADC remains LOW. In order to prevent the  
device from exiting the low power sleep state, CSADC  
must be pulled HIGH before the first rising edge of SCK. In  
the internal SCK timing mode, SCK goes HIGH and the  
device begins outputting data at time tEOCtest after the  
falling edge of CSADC (if EOC = 0) or tEOCtest after EOC  
goes LOW (if CSADC is LOW during the falling edge of  
EOC). The value of tEOCtest is 23µs if the device is using its  
internal oscillator (F0 = logic LOW or HIGH). If FO is driven  
by an external oscillator of frequency fEOSC, then tEOCtest is  
3.6/fEOSC. IfCSADCispulledHIGHbeforetimetEOCtest, the  
device remains in the sleep state. The conversion result is  
held in the internal static shift register.  
edgeofSCK.Theinternallygeneratedserialclockisoutput  
to the SCK pin. This signal may be used to shift the  
conversion result into external circuitry. EOC can be  
latchedonthefirstrisingedgeofSCKandthelastbitofthe  
conversion result on the 24th rising edge of SCK. After the  
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays  
HIGH, and a new conversion starts.  
While operating in the internal serial clock mode, the SCK  
output of the ADC may be used as the multiplexer clock  
(CLK). DIN is latched into the multiplexer on the rising  
edge of CLK. As shown in Figure 16, the multiplexer  
channel is selected by serial shifting a 4-bit word into the  
DIN pin on the rising edge of CLK. The first bit is an enable  
bitwhichmustbeHIGHinordertoprogramachannel.The  
next three bits determine which channel is selected, see  
Table 3. On the rising edge of CSADC (falling edge of  
CSMUX), the new channel is selected and will be valid for  
the next conversion. If DIN is held LOW during the data  
outputstate,thepreviouschannelselectionremainsvalid.  
If CSADC remains LOW longer than tEOCtest, the first rising  
edge of SCK will occur and the conversion result is serially  
shiftedoutoftheSDOpin. Thedataoutputcyclebeginson  
this first rising edge of SCK and concludes after the 24th  
rising edge. Data is shifted out the SDO pin on each falling  
19  
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Typically, CSADC remains LOW during the data output  
state. However, the data output state may be aborted by  
pulling CSADC HIGH anytime between the first and 24th  
rising edge of SCK, see Figure 17. On the rising edge of  
CSADC, the device aborts the data output state and  
immediately initiates a new conversion. This is useful for  
systems not requiring all 24 bits of output data, aborting  
an invalid conversion cycle, or synchronizing the start of  
a conversion. If CSADC is pulled HIGH while the con-  
verter is driving SCK LOW, the internal pull-up is not  
available to restore SCK to a logic HIGH state. This will  
cause the device to exit the internal serial clock mode on  
the next falling edge of CSADC. This can be avoided by  
adding an external 10k pull-up resistor to the SCK pin or  
by never pulling CSADC HIGH when SCK is LOW.  
mode.However,certainapplicationsmayrequireanexter-  
nal driver on SCK. If this driver goes HI-Z after outputting  
a LOW signal, the LTC2424/LTC2428’s internal pull-up  
remains disabled. Hence, SCK remains LOW. On the next  
falling edge of CSADC, the device is switched to the  
external SCK timing mode. By adding an external 10k pull-  
up resistor to SCK, this pin goes HIGH once the external  
driver goes HI-Z. On the next CSADC falling edge, the  
device will remain in the internal SCK timing mode.  
Asimilarsituationmayoccurduringthesleepstatewhen  
CSADC is pulsed HIGH-LOW-HIGH in order to test the  
conversion status. If the device is in the sleep state  
(EOC = 0), SCK will go LOW. Once CSADC goes HIGH  
(within the time period defined above as tEOCtest), the  
internal pull-up is activated. For a heavy capacitive load  
on the SCK pin, the internal pull-up may not be adequate  
to return SCK to a HIGH level before CSADC goes LOW  
again. This is not a concern under normal conditions  
Whenever SCK is LOW, the LTC2424/LTC2428’s internal  
pull-up at pin SCK is disabled. Normally, SCK is not  
externally driven if the device is in the internal SCK timing  
2.7V TO 5.5V  
V
CC  
= 50Hz REJECTION  
= EXTERNAL OSCILLATOR  
= 60Hz REJECTION  
V
F
O
CC  
LTC2424/LTC2428  
0.1V  
CC  
FS  
CS  
CSMUX  
SET  
TO V  
10k  
CH0  
–0.12V  
TO 1.12V  
CSADC  
SCK  
REF  
REF  
TO CH7  
MUXOUT  
ADCIN  
CLK  
D
IN  
ZS  
SDO  
SET  
GND  
CSMUX  
CSADC  
SCKCLK  
SDO  
t
EOCtest  
TEST EOC  
TEST EOC  
BIT23 BIT22 BIT21 BIT20 BIT19 BIT18  
SIG EXR MSB  
BIT12 BIT11 BIT10 BIT9 BIT8  
TEST EOC  
Hi-Z  
Hi-Z  
Hi-Z  
D
DON’T CARE  
EN D2  
D1  
D0  
DON’T CARE  
IN  
24248 F17  
Figure 17. Internal Serial Clock with Reduced Data Output Length Timing Diagram  
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where CSADC remains LOW after detecting EOC = 0. This  
situation is easily avoided by adding an external 10k pull-  
up resistor to the SCK pin.  
For reference, on a regular FR-4 board, signal propaga-  
tion velocity is approximately 183ps/inch for internal  
traces and 170ps/inch for surface traces. Thus, a driver  
generating a control signal with a minimum transition  
time of 1ns must be connected to the converter pin  
through a trace shorter than 2.5 inches. This problem  
becomes particularly difficult when shared control lines  
areusedandmultiplereflectionsmayoccur.Thesolution  
is to carefully terminate all transmission lines close to  
their characteristic impedance.  
DIGITAL SIGNAL LEVELS  
The LTC2424/LTC2428’s digital interface is easy to use.  
Its digital inputs (FO, CSADC, CSMUX, CLK, DIN and SCK  
in External SCK mode of operation) accept standard TTL/  
CMOS logic levels and can tolerate edge rates as slow as  
100µs.However,someconsiderationsarerequiredtotake  
advantageofexceptionalaccuracyandlowsupplycurrent.  
Parallel termination near the LTC2424/LTC2428 input  
pins will eliminate this problem but will increase the driver  
powerdissipation.Aseriesresistorbetween27Ωand56Ω  
placed near the driver or near the LTC2424/LTC2428 pin  
will also eliminate this problem without additional power  
dissipation. The actual resistor value depends upon the  
trace impedance and connection topology.  
The digital output signals (SDO and SCK in Internal SCK  
mode of operation) are less of a concern because they are  
not generally active during the conversion state.  
InordertopreservetheaccuracyoftheLTC2424/LTC2428,  
it is very important to minimize the ground path imped-  
ance which may appear in series with the input and/or  
reference signal and to reduce the current which may flow  
through this path. The ZSSET pin (Pin 6) should be con-  
nected directly to the signal ground.  
Driving the Input and Reference  
The analog input and reference of the typical delta-sigma  
analog-to-digital converter are applied to a switched ca-  
pacitornetwork.Thisnetworkconsistsofcapacitorsswitch-  
ing between the analog input (ADCIN), ZSSET (Pin 6) and  
the reference (FSSET). The result is small current spikes  
seenatbothADCINandVREF. Asimplifiedinputequivalent  
circuit is shown in Figure 18.  
The power supply current during the conversion state  
should be kept to a minimum. This is achieved by restrict-  
ing the number of digital signal transitions occurring  
during this period.  
While a digital input signal is in the 0.5V to (VCC – 0.5V)  
range, the CMOS input receiver draws additional current  
from the power supply. It should be noted that, when any  
one of the digital input signals (FO, CSADC, CSMUX, DIN,  
CLK and SCK in External SCK mode of operation) is within  
this range, the LTC2424/LTC2428 power supply current  
mayincreaseevenifthesignalinquestionisatavalidlogic  
level. For micropower operation and in order to minimize  
the potential errors due to additional ground pin current,  
it is recommended to drive all digital input signals to full  
CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)].  
The key to understanding the effects of this dynamic input  
current is based on a simple first order RC time constant  
model. Using the internal oscillator, the internal switched  
capacitor network of the LTC2424/LTC2428 is clocked at  
153,600Hz corresponding to a 6.5µs sampling period.  
Fourteentimeconstantsarerequiredeachtimeacapacitor  
is switched in order to achieve 1ppm settling accuracy.  
Therefore, the equivalent time constant at VIN and VREF  
should be less than 6.5µs/14 = 460ns in order to achieve  
1ppm accuracy.  
Severe ground pin current disturbances can also occur  
due to the undershoot of fast digital input signals. Under-  
shoot and overshoot can occur because of the imped-  
ance mismatch at the converter pin when the transition  
time of an external control signal is less than twice the  
propagation delay from the driver to LTC2424/LTC2428.  
Input Current (VIN)  
If complete settling occurs on the input, conversion re-  
sultswillbeunaffectedbythedynamicinputcurrent. Ifthe  
settling is incomplete, it does not degrade the linearity  
performance of the device. It simply results in an offset/  
21  
LTC2424/LTC2428  
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APPLICATIONS INFORMATION  
ADCV  
CC  
(PIN 2)  
R
SW  
I
I
REF  
REF  
5k  
FS  
SET  
MUXV  
ADCV  
CC  
(PIN 2)  
CC  
(PIN 8)  
SELECTED  
CHANNEL  
±I  
AVERAGE INPUT CURRENT:  
= 0.25(V – 0.5 • V ) • f • C  
EQ  
DC  
R
SW  
75Ω  
R
SW  
5k  
I
I
I
I
DC  
IN(MUX)  
IN(LEAK)  
IN(LEAK)  
IN  
REF  
CHX  
MUXOUT  
ADCIN  
C
EQ  
I
IN(MUX)  
1pF (TYP)  
R
SW  
5k  
24248 F18  
ZS  
SET  
f
f
= 50Hz, INTERNAL OSCILLATOR: f = 128kHz  
= 60Hz, INTERNAL OSCILLATOR: f = 153.6kHz  
OUT  
OUT  
EXTERNAL OSCILLATOR: 2.56kHz ≤ f ≤ 307.2kHz  
Figure 18. LTC2424/LTC2428 Equivalent Analog Input Circuit  
full-scale shift, see Figure 19. To simplify the analysis of  
ANTIALIASING  
input dynamic current, two separate cases are assumed:  
large capacitance at VIN (CIN > 0.01µF) and small capaci-  
tance at VIN (CIN < 0.01µF).  
One of the advantages delta-sigma ADCs offer over con-  
ventional ADCs is on-chip digital filtering. Combined with  
a large oversampling ratio, the LTC2424/LTC2428 signifi-  
cantly simplify antialiasing filter requirements.  
If the total capacitance at VIN (see Figure 20) is small  
(<0.01µF), relativelylargeexternalsourceresistances(up  
to 20k for 20pF parasitic capacitance) can be tolerated  
without any offset/full-scale error.  
The digital filter provides very high rejection except at  
integer multiples of the modulator sampling frequency  
(fS), see Figure 21. The modulator sampling frequency is  
256 • FO, where FO is the notch frequency (typically 50Hz  
or 60Hz). The bandwidth of signals not rejected by the  
digitalfilterisnarrow(≈0.2%)comparedtothebandwidth  
of the frequencies rejected.  
TUE  
0
–20  
–40  
–60  
–80  
0
V
/2  
V
REF  
REF  
V
24248 F19  
IN  
–100  
–120  
–140  
Figure 19. Offset/Full-Scale Shift  
R
SOURCE  
f /2  
S
f
0
CH0 TO  
CH7  
S
INTPUT  
SIGNAL  
SOURCE  
INPUT FREQUENCY  
C
PAR  
20pF  
C
IN  
24248 F21  
LTC2424/  
LTC2428  
Figure 21. Sync4 Filter Rejection  
24248 F20  
Figure 20. An RC Network at CH0 to CH7  
22  
LTC2424/LTC2428  
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APPLICATIONS INFORMATION  
canbeconfiguredintoaresistiveladder,usingtheLTC2428  
to sense each node. This approach allows a single excita-  
tion current passed through the entire ladder, reducing  
total supply current consumption. In addition, this ap-  
proach requires only one high precision resistor, thereby  
reducingcost. Agroupofuptoseventemperaturescanbe  
measured as a group by a single LTC2428 in a loop-pow-  
ered remote acquisition unit. In the example shown in  
Figure 22, the excitation current is 240µA at 0°C. The  
LTC2428 requires 300µA, leaving nearly 3.5mA for the  
remainder of the remote transmitter.  
As a result of the oversampling ratio (256) and the digital  
filter, minimal (if any) antialias filtering is required in front  
of the LTC2424/LTC2428. If passive RC components are  
placed in front of the LTC2424/LTC2428, the input dy-  
namic current should be considered. In cases where large  
effective RC time constants are used, an external buffer  
amplifier may be required to minimize the effects of input  
dynamic current.  
The modulator contained within the LTC2424/LTC2428  
can handle large-signal level perturbations without satu-  
rating. Signal levels up to 40% of VREF do not saturate the  
analog modulator. These signals are limited by the input  
ESDprotectionto300mVbelowgroundand300mVabove  
VCC.  
The resistance of any of the RTDs (PT1 to PT7) is deter-  
mined from the voltage across it, as compared to the  
voltage drop across the reference resistor (R1). This is a  
ratiometricimplementationwherethevoltagedropacross  
R1 is given by VREF – VCH1. Channel 7 is used to measure  
the voltage on a representative length of wire. If the same  
type and length of wire is used for all connections, then  
errors associated with the voltage drops across all wiring  
can be removed in software. The contribution of wiring  
drop can be scaled if wire lengths are not equal.  
The LTC2428’s Resolution and Accuracy Allows You  
to Measure Points in a Ladder of Sensors  
In many industrial processes, for example, cracking tow-  
ers in petroleum refineries, a group of temperature mea-  
surements must be related to one another. A series of  
platinum RTDs that sense slow changing temperatures  
5V  
300µA  
R2  
6
+
0.1µF  
47µF  
OPTIONAL  
GAIN  
5V  
LTC1634-2.5  
3
2
BLOCK  
7
+
4
5
6
LTC1050  
R1  
20.1k  
0.1%  
–
4
R3  
R2  
UP TO SEVERAL  
HUNDRED FEET.  
ALL SAME  
5V  
WIRE TYPE  
OPTIONAL  
PROTECTION  
RESISTORS  
5k MAX  
7
4
3
FS  
2, 8  
1µF  
PT1  
100Ω  
V
MUXOUT  
ADCIN  
SET CC  
9
CH0  
PLATINUM  
RTD  
23  
20  
25  
19  
21  
24  
10 CH1  
11 CH2  
12 CH3  
13 CH4  
14 CH5  
15 CH6  
17 CH7  
CSADC  
CSMUX  
SCK  
20-BIT  
PT2  
PT7  
8-CHANNEL  
MUX  
+
∆∑ ADC  
CLK  
D
IN  
SDO  
TO PT3-PT6  
V
CC  
LTC2428  
GND  
5
ZS  
SET  
26  
F
O
24248 F22  
1, 6, 16, 18, 22, 27, 28  
Figure 22. Measuring Up to Seven RTD Temperatures with One Reference Resistor and One Reference Current  
23  
LTC2424/LTC2428  
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APPLICATIONS INFORMATION  
Gain can be added to this circuit as the total voltage drop  
across all the RTDs is small compared to ADC full-scale  
range. The maximum recommended gain is 50, as limited  
by both amplifier noise contribution, as well as the maxi-  
mum voltage developed at CH0 when all sensors are at the  
maximum temperature specified for platinum RTDs.  
flows through the switch. The LTC1050 was chosen for  
its low input current and offset voltage, as well as its  
ability to drive the input of a ∆Σ ADC.  
Insert Gain or Buffering After the Multiplexer  
SeparateMUXOUTandADCINterminalspermitinsertion  
of a gain stage between the MUX and the ADC. If passive  
filtering is used at the input to the ADC, a buffer amplifier  
is strongly recommended to avoid errors resulting from  
thedynamicADCinputcurrent. Ifantialiasingisrequired,  
it should be placed at the input to the MUX. If bandwidth  
limitingisrequiredtoimprovenoiseperformance, afilter  
with a –3dB point at 1500Hz will reduce the effective total  
noisebandwidthofthesystemto15Hz.Aroll-offat1500Hz  
eliminates all higher order images of the base bandwidth  
of 6Hz. In the example shown, the optional bandwidth-  
limitingfilterhasa–3dBpointat1450Hz. Thisfiltercanbe  
inserted after the multiplexer provided that higher source  
impedance prior to the multiplexer does not reduce the  
–3dB frequency, extending settling time, and resulting in  
charge sharing between samples. The settling time of this  
filter to 20+ bits of accuracy is less than 2ms. In the pres-  
ence of external wideband noise, this filter reduces the  
apparent noise by a factor of 5. Note that the noise band-  
width for noise developed in the amplifier is 150Hz. In the  
example shown, the gain of the amplifier is set to 40, the  
pointatwhichamplifiernoisegaindominatestheLTC2428  
noise. Input voltage range as shown is then 0V to 125mV  
DC. The recommended capacitor at C2 for a gain of 40  
would be 560pF.  
Adding gain requires that one of the resistors (PT1 to PT7)  
be a precision resistor in order to eliminate the error asso-  
ciated with the gain setting resistors R2 and R3. Note, that  
if a precision (100Ω to 400Ω) resistor is used in place of  
one of the RTDs (PT7 recommended), R1 does not need  
to be a high precision resistor. Although the substitution  
of a precision reference resistor for an RTD to determine  
gain may suggest that R2 and R3 (and R1) need not be  
precise, temperature fluctuations due to airflow may ap-  
pear as noise that cannot be removed in firmware. Conse-  
quently, these resistors should be low temperature coef-  
ficient devices. The use of higher resistance RTDs is not  
recommended in this topology, although the inclusion of  
one 1000Ω RTD at the top on the ladder will have minimal  
impact on the lower elements. The same caveat applies to  
fast changing temperatures. Any fast changing sensors  
should be at the top of the ladder.  
The LTC2428’s Uncommitted Multiplexer Finds Use in  
a Programmable Gain Scheme  
If the multiplexer in the LTC2428 is not committed to  
channel selection, it can be used to select various signal-  
processing options such as different gains, filters or at-  
tenuator characteristics. In Figure 23, the multiplexer is  
shown selecting different taps on an R/2R ladder in the  
feedback loop of an amplifier. This example allows selec-  
tion of gain from 1 to 128 in binary steps. Other feedback  
networks could be used to provide gains tailored for  
specific purposes. (For example, 1x, 1.1x, 1.41x, 2x,  
2.028x,5x,10x,40x,etc.)Alternatively,differentbandpass  
characteristicsorsignalinversion/noninversioncouldbe  
selected. The R/2R ladder can be purchased as a network  
to ensure tight temperature tracking. Alternatively, resis-  
tors in a ladder or as separate dividers can be assembled  
from discrete resistors. In the configuration shown, the  
channel resistance of the multiplexer does not contribute  
much to the error budget, as only input op amp current  
An 8-Channel DC-to-Daylight Digitizer  
ThecircuitinFigure25showsanexampleoftheLTC2428’s  
flexibility in digitizing a number of real-world physical  
phenomena—from DC voltages to ultraviolet light. All of  
the examples implement single-ended signal condition-  
ing. Although differential signal conditioning is a pre-  
ferred approach in applications where the sensor is a  
bridge-type, is located some distance from the ADC or  
operates in a high ambient noise environment, the  
LTC2428’slowpowerdissipationallowscircuitoperation  
in close proximity to the sensor. As a result, conditioning  
the sensor output can be greatly simplified through the  
24  
LTC2424/LTC2428  
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APPLICATIONS INFORMATION  
5V  
3
AV = 1, 2, 4...128  
6
V
+
IN  
LTC1050  
2
–
5V  
0.1V TO V  
3
CC  
7
4
2, 8  
1µF  
10k  
10k  
10k  
10k  
10k  
10k  
10k  
10k  
2
FS  
V
MUXOUT  
ADCIN  
SET CC  
9
CH0  
20k  
20k  
20k  
20k  
20k  
20k  
20k  
23  
20  
25  
19  
21  
24  
10 CH1  
11 CH2  
12 CH3  
13 CH4  
14 CH5  
15 CH6  
17 CH7  
4
CSADC  
CSMUX  
SCK  
8
20-BIT  
∆∑ ADC  
8-CHANNEL  
MUX  
+
CLK  
16  
32  
64  
128  
D
IN  
SDO  
V
CC  
LTC2428  
GND  
5
ZS  
SET  
26  
F
O
24248 F23  
1, 6, 16, 18, 22, 27, 28  
Figure 23. Using the Multiplexer to Produce Programmable Gains of 1 to 128  
5V  
OPTIONAL  
BANDWIDTH  
3
2
7
LIMIT  
+
6
LTC1050  
MAY BE REQUIRED BY OTHER  
AMPLIFIERS (IS REQUIRED BY  
BIPOLAR AMPLIFIERS)  
C1  
0.022µF  
–
R4  
5K  
4
R3  
200k  
R1  
5.1k  
R2  
5.1K  
C2  
OPTIONAL GAIN  
AND ROLL-OFF  
5V  
7
4
3
FS  
2, 8  
10µF  
V
MUXOUT  
ADCIN  
SET CC  
9
CH0  
23  
20  
25  
19  
21  
24  
10 CH1  
11 CH2  
12 CH3  
13 CH4  
14 CH5  
15 CH6  
17 CH7  
CSADC  
CSMUX  
SCK  
20-BIT  
8-CHANNEL  
MUX  
ANALOG  
INPUTS  
+
∆∑ ADC  
CLK  
D
IN  
SDO  
V
CC  
LTC2428  
GND  
5
ZS  
SET  
26  
F
O
24248 F24  
1, 6, 16, 18, 22, 27, 28  
Figure 24. Inserting Gain Between the Multiplexer and the ADC Input  
25  
LTC2424/LTC2428  
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APPLICATIONS INFORMATION  
use of single-ended arrangements. In those applications  
where differential signal conditioning is required, chopper  
amplifier-based or self-contained instrumentation ampli-  
fiers (also available from LTC) can be used with the  
LTC2428.  
tolerance and 5ppm/°C temperature coefficient would  
also be adequate for most applications.  
Two channels (CH3 and CH4) of the LTC2428 are used to  
accommodate a 3-wire 100Ω, Pt RTD in a unique circuit  
that allows true RMS/RF signal power measurement from  
audio to gigahertz (GHz) frequencies. The unique feature  
ofthiscircuitisthatthesignalpowerdissipatedinthe50Ω  
termination in the form of heat is measured by the 100Ω  
RTD. Two readings are required to compensate for the  
RTD’s lead-wire resistance. The reading on CH4 is multi-  
plied by 2 and subtracted from the reading on CH3 to  
determine the exact value of the RTD.  
With the resistor network connected to CH0, the LTC2428  
isabletomeasureDCvoltagesfrom1mVto1kVinasingle  
range without the need for autoranging. The 990k resistor  
should be a 1W resistor rated for high voltage operation.  
Alternatively, the 990k resistor can be replaced with a  
seriesconnectionofseverallowercost,lowerpowermetal  
film resistors.  
The circuit connected to CH1 shows an LT1793 FET input  
operational amplifier used as an electrometer for high  
impedance, low frequency applications such as measur-  
ing pH. The circuit has been configured for a gain of 21;  
thus, the input signal range is –15mV ≤ VIN ≤ 250mV. An  
amplifier circuit is necessary in these applications be-  
cause high output impedance sensors cannot drive  
switched-capacitor ADCs directly. The LT1793 was cho-  
sen for its low input bias current (10pA, max) and low  
noise (8nV/√Hz) performance. As shown, the use of a  
driven guard (and TeflonTM standoffs) is recommended in  
high impedance sensor applications; otherwise, PC board  
surface leakage current effects can degrade results.  
While the LTC2428 is capable of measuring signals over a  
range of five decades, the implementation (mechanical,  
electrical and thermal) of this technique ultimately deter-  
mines the performance of the circuit. The thermal resis-  
tanceoftheassembly(the50Ω/RTDmasstoitsenclosure)  
will determine the sensitivity of the circuit. The dynamic  
range of the circuit will be determined by the maximum  
temperature the assembly is rated to withstand, approxi-  
mately 850°C. Details of the implementation are quite  
involved and are beyond the scope of this document.  
Please contact LTC directly for a more comprehensive  
treatment of this implementation.  
In the circuit connected to the LTC2428’s CH5 input, a  
thermistor is configured in a half-bridge arrangement that  
could be used to measure the case temperature of the  
RTD-basedthermalpowermeasurementschemedescribed  
previously. In general, thermistors yield very good resolu-  
tion over a limited temperature range. For the half-bridge  
arrangement shown, the LTC2428 can measure tempera-  
ture changes over nearly 5 orders of magnitude.  
The circuit connected to CH2 illustrates a precision half-  
wave rectifier that uses the LTC2428’s internal ∆Σ ADC as  
an integrator. This circuit can be used to measure 60Hz,  
120Hz or from 400Hz to 1kHz with good results. The  
LTC2428’s internal sinc4 filter effectively eliminates any  
frequency in this range. Above 1kHz, limited amplifier  
gain-bandwidthproductandtransientovershootbehavior  
can combine to degrade performance. The circuit’s dy-  
namicrangeislimitedbyoperationalamplifierinputoffset  
voltage and the system’s overall noise floor. Using an  
LTC1050 chopper-stabilized operational amplifier with a  
Connected to the LTC2428’s CH6 input, an infrared ther-  
mocouple (Omega Engineering OS36-1) can be used in  
limited range, noncontact temperature measurement ap-  
plications or applications where high levels of infrared  
light must be measured. Given the LTC2428’s 1.2ppmRMS  
noise performance, measurement resolution using infra-  
red thermocouples is approximately 0.25°C—equivalent  
to the resolution of a conventional Type J thermocouple.  
V
OS of 5µV, the dynamic range of this application covers  
approximately 5 orders of magnitude. The circuit configu-  
ration is best implemented with a precision, 3-terminal,  
2-resistor 10kΩ network (for example, an IRC PFC-D  
network) for R6 and R7 to maintain gain and temperature  
stability. Alternatively, discrete resistors with 0.1% initial  
Teflon is a trademark of Dupont Company.  
26  
LTC2424/LTC2428  
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These infrared thermocouples are self-contained: 1) they  
do not require external cold junction compensation; 2)  
they cannot use conventional open thermocouple detec-  
tion schemes; and 3) their output impedances are high,  
approximately 3kΩ. Alternatively, conventional thermo-  
couples can be connected directly to the LTC2428 (not  
shown) and cold junction compensation can be provided  
byanexternaltemperaturesensorconnectedtoadifferent  
channel(seethethermistorcircuitonCH5)orbyusingthe  
LT1025, a monolithic cold-junction compensator IC.  
The photodiode chosen (Hammatsu S1336-5BK) pro-  
duces an output of 500mA per watt of optical illumination.  
The output of the photodiode is dependent on two factors:  
active detector area (2.4mm • 2.4mm) and illumination  
intensity. With the 5k resistor, optical intensities up to  
368W/m2 at 960nM (direct sunlight is approximately  
1000W/m2) can be measured by the LTC2428. With a  
resolution of 1nA, the optical dynamic range covers 5  
orders of magnitude.  
The application circuits shown connected to the LTC2428  
demonstrate the mix-and-match capabilities of this multi-  
plexed-input, high resolution ∆Σ ADC. Very low level  
signals and high level signals can be accommodated with  
a minimum of additional circuitry.  
The components connected to CH7 are used to sense  
daylightorphotodiodecurrentwitharesolutionof300pA.  
In the figure, the photodiode is biased in photoconduc-  
tive mode; however, the LTC2428 can accommodate  
either photovoltaic or photoconductive configurations.  
U
PACKAGE DESCRIPTIO  
Dimensions in millimeters (inches) unless otherwise noted.  
G Package  
28-Lead Plastic SSOP (0.209)  
(LTC DWG # 05-08-1640)  
10.07 – 10.33*  
(0.397 – 0.407)  
28 27 26 25 24 23 22 21 20 19 18  
16 15  
17  
7.65 – 7.90  
(0.301 – 0.311)  
5
7
8
1
2
3
4
6
9 10 11 12 13 14  
5.20 – 5.38**  
(0.205 – 0.212)  
1.73 – 1.99  
(0.068 – 0.078)  
0° – 8°  
0.65  
(0.0256)  
BSC  
0.13 – 0.22  
0.55 – 0.95  
(0.005 – 0.009)  
(0.022 – 0.037)  
0.05 – 0.21  
(0.002 – 0.008)  
0.25 – 0.38  
(0.010 – 0.015)  
NOTE: DIMENSIONS ARE IN MILLIMETERS  
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH  
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE  
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD  
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE  
G28 SSOP 1098  
27  
LTC2424/LTC2428  
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TYPICAL APPLICATION  
DC  
VOLTMETER  
INPUT  
R1  
GUARD RING  
900k  
5V  
0.1%, 1W, 1000 WVDC  
7
ELECTROMETER  
INPUT  
1mV TO 1000V  
3
2
R5  
5k, 1%  
+
R2  
4.7k  
6
(pH, PIEZO)  
LT1793  
0.1%  
0V TO 5V  
–
4
–60mV TO 4V  
–5V  
R3, 10k  
LT1236CS8-5  
R4  
1k  
6
2
5V  
OUT IN  
8V  
REF  
C1, 0.1µF  
+
+
5V  
MAX  
GND  
4
10µF  
100µF  
3-WIRE R-PACK  
60Hz  
R6  
R7  
5V  
10k, 0.1%  
10k, 0.1%  
AC  
INPUT  
5V  
7
4
3
FS  
2, 8  
V
1µF  
SERIAL DATA LINK  
1µF  
R9  
1k  
1%  
R10  
7
MUXOUT  
ADCIN  
SET CC  
5k  
IN914  
6
IN914  
2
3
–
1%  
9
CH0  
RT  
MICROWIRE AND  
SPI COMPATABLE  
10 CH1  
11 CH2  
12 CH3  
13 CH4  
14 CH5  
15 CH6  
17 CH7  
LTC1050  
23  
20  
CSADC  
R8  
100Ω, 5%  
+
CSMUX  
CLK  
4
19, 25  
21  
20-BIT  
8-CHANNEL  
MUX  
20mV TO 80mV  
+
∆∑ ADC  
MPU  
–5V  
D
IN  
R11  
24  
SDO  
–
24.9k, 0.1%  
V
REF  
5V  
LTC2428  
GND  
INTERNAL OSC  
60Hz–RF  
5
ZS  
SET  
26  
F
SELECTED FOR  
RF POWER  
O
60Hz REJECTION  
<1mV  
J1  
J2  
100Ω  
24248 F25  
1, 6, 16, 18, 22, 27, 28  
Pt RTD  
50Ω  
(3-WIRE)  
FORCE SENSE  
2.7V AT 0°C  
0.9V AT 40°C  
–2.2mV to 16mV  
0V to 4V  
R12  
24.9k, 0.1%  
J3  
V
REF  
5V  
50Ω LOAD  
BONDED TO  
RTD ON  
INSULATED  
MOUNTING  
LOCAL  
TEMP  
THERMISTOR  
10kΩ NTC  
5V  
DAYLIGHT  
HAMAMATSU  
PHOTODIODE  
S1336-5BK  
OMEGA  
0S36-01  
INFRARED  
R13  
5k  
0.1%  
INFRARED  
THERMOCOUPLE  
Fiugre 25. Measure DC to Daylight Using the LTC2428  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
COMMENTS  
LTC1050  
Precision Chopper Stabilized Op Amp  
Precision Bandgap Reference  
No External Components, 5µV Offset, 1.6µV  
0.05% Max Initial Accuracy, 5ppm/°C Drift  
50µA, 0.04%, 3ppm/°C Drift  
P–P  
LT1236  
LT1461-2.5  
LT1793  
Precision, Low Power, Low Drift Reference  
Low Noise JFET Input Op Amp  
10pA Max Input Bias Current, Low Voltage Noise: 8nV  
<4ppm INL, No Missing Codes, 4ppm Full Scale  
LTC2400  
24-Bit Micropower ∆Σ ADC in SO-8  
4/8 Channel, 24-Bit ∆Σ ADCs  
LTC2404/LTC2408  
<4ppm INL, No Missing Codes, Interchangeable with the  
LTC2424/LTC2428 if ZS is grounded  
SET  
24248f LT/TP 0300 4K • PRINTED IN USA  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
28  
●
●
LINEAR TECHNOLOGY CORPORATION 2000  
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com  

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