LTC1867CGN#TRPBF [Linear]
LTC1867 - 16-Bit, 8-Channel 200ksps ADCs; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C;型号: | LTC1867CGN#TRPBF |
厂家: | Linear |
描述: | LTC1867 - 16-Bit, 8-Channel 200ksps ADCs; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
文件: | 总18页 (文件大小:311K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1863/LTC1867
12-/16-Bit, 8-Channel
200ksps ADCs
Features
Description
The LTC®1863/LTC1867 are pin-compatible, 8-channel
12-/16-bit A/D converters with serial I/O, and an internal
reference. The ADCs typically draw only 1.3mA from a
single 5V supply.
n
Sample Rate: 200ksps
n
16-Bit No Missing Codes and 2ꢀSB Maꢁ ꢂNꢀ
n
8-Channel Multipleꢁer with:
Single Ended or Differential ꢂnputs and
Unipolar or Bipolar Conversion Modes
The 8-channel input multiplexer can be configured for
either single-ended or differential inputs and unipolar
or bipolar conversions (or combinations thereof). The
automatic nap and sleep modes benefit power sensitive
applications.
n
SPꢂ/MꢂCROWꢂRE™ Serial ꢂ/O
n
Signal-to-Noise Ratio: 89dB
n
Single 5V Operation
n
On-Chip or Eꢁternal Reference
n
Low Power: 1.3mA at 200ksps, 0.76mA at 100ksps
n
n
n
The LTC1867’s DC performance is outstanding with a
2LSB INL specification and no missing codes over tem-
perature. The signal-to-noise ratio (SNR) for the LTC1867
is typically 89dB, with the internal reference.
Sleep Mode
Automatic Nap Mode Between Conversions
16-Pin Narrow SSOP Package
Housed in a compact, narrow 16-pin SSOP package, the
LTC1863/LTC1867 can be used in space-sensitive as well
as low-power applications.
applications
n
Industrial Process Control
n
High Speed Data Acquisition
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
Battery Operated Systems
Multiplexed Data Acquisition Systems
n
n
Imaging Systems
Block Diagram
ꢂntegral Nonlinearity vs Output Code
(ꢀTC1867)
2.0
1.5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
LTC1863/LTC1867
CH0
CH1
CH2
CH3
CH4
V
DD
GND
SDI
SDO
SCK
CS/CONV
1.0
12-/16-BIT
200ksps
ADC
ANALOG
INPUT
MUX
+
–
SERIAL
PORT
0.5
0
CH5
CH6
V
REF
INTERNAL
2.5V REF
–0.5
–1.0
–1.5
–2.0
CH7/COM
9
REFCOMP
18637 BD
0
16384
32768
49152
65536
OUTPUT CODE
18637 GO1
18637fb
1
For more information www.linear.com/LTC1863
LTC1863/LTC1867
aBsolute maximum ratings
pin conFiguration
(Note 1, 2)
Supply Voltage (V )................................... –0.3V to 6V
DD
TOP VIEW
Analog Input Voltage
CH0
CH1
1
2
3
4
5
6
7
8
16
V
DD
CH0-CH7/COM (Note 3) ...........–0.3V to (V + 0.3V)
DD
DD
15 GND
V
, REFCOMP (Note 4) ......... –0.3V to (V + 0.3V)
REF
CH2
14
13
12
11
10
9
SDI
Digital Input Voltage (SDI, SCK, CS/CONV)
CH3
SDO
(Note 4) ................................................. –0.3V to 10V
CH4
SCK
Digital Output Voltage (SDO) ....... –0.3V to (V + 0.3V)
DD
CH5
CS/CONV
Power Dissipation.............................................. 500mW
Operating Temperature Range
CH6
V
REF
CH7/COM
REFCOMP
LTC1863C/LTC1867C/LTC1867AC............ 0°C to 70°C
LTC1863I/LTC1867I/LTC1867AI ...........–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
T
JMAX
= 110°C, θ = 95°C/W
JA
orDer inFormation
ꢀEAD FREE FꢂNꢂSH
LTC1863CGN#PBF
LTC1863IGN#PBF
LTC1867CGN#PBF
LTC1867IGN#PBF
LTC1867ACGN#PBF
LTC1867AIGN #PBF
TAPE AND REEꢀ
PART MARKꢂNG*
1863
PACKAGE DESCRꢂPTꢂON
TEMPERATURE RANGE
0°C to 70°C
LTC1863CGN#TRPBF
LTC1863IGN#TRPBF
LTC1867CGN#TRPBF
LTC1867IGN#TRPBF
LTC1867ACGN#TRPBF
LTC1867AIGN#TRPBF
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
1863
–40°C to 85°C
0°C to 70°C
1867
1867
–40°C to 85°C
0°C to 70°C
1867
1867
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
converter characteristics
temperature range, otherwise specifications are at TA = 25°C. With eꢁternal reference (Notes 5, 6)
ꢀTC1863
TYP
ꢀTC1867
TYP
ꢀTC1867A
TYP
PARAMETER
CONDꢂTꢂONS
MꢂN
12
MAX
MꢂN
16
MAX
MꢂN
16
MAX
UNꢂTS
Bits
l
l
Resolution
No Missing Codes
Integral Linearity Error
12
15
16
Bits
l
l
Unipolar (Note 7)
Bipolar
1
1
4
4
2
2.5
LSB
LSB
l
Differential Linearity Error
Transition Noise
1
–2
3
–1
1.75
LSB
0.1
0.74
0.74
LSB
RMS
l
l
Offset Error
Unipolar (Note 8)
Bipolar
3
4
32
64
32
64
LSB
LSB
Offset Error Match
Unipolar
Bipolar
1
1
2
2
2
2
LSB
LSB
18637fb
2
For more information www.linear.com/LTC1863
LTC1863/LTC1867
The l denotes the specifications which apply over the full operating
converter characteristics
temperature range, otherwise specifications are at TA = 25°C. With eꢁternal reference (Notes 5, 6)
ꢀTC1863
TYP
ꢀTC1867
TYP
ꢀTC1867A
TYP
PARAMETER
Offset Error Drift
Gain Error
CONDꢂTꢂONS
MꢂN
MAX
MꢂN
MAX
MꢂN
MAX
UNꢂTS
0.5
0.5
0.5
ppm/°C
Unipolar
Bipolar
6
6
96
96
64
64
LSB
LSB
Gain Error Match
Gain Error Tempco
1
4
2
LSB
Internal Reference
External Reference
15
2.7
15
2.7
15
2.7
ppm/°C
ppm/°C
Power Supply Sensitivity
V
= 4.75V – 5.25V
1
5
5
LSB
DD
(Note 5)
Dynamic accuracy
ꢀTC1863
TYP
ꢀTC1867/ꢀTC1867A
SYMBOꢀ PARAMETER
CONDꢂTꢂONS
MꢂN
MAX
MꢂN
TYP
89
MAX
UNꢂTS
dB
SNR
Signal-to-Noise Ratio
1kHz Input Signal
73.6
S/(N+D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal
73.5
88
dB
THD
Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Channel-to-Channel Isolation
Full Power Bandwidth
1kHz Input Signal, Up to 5th Harmonic
1kHz Input Signal
–94.5
–94.5
–100
1.25
–95
–95
–117
1.25
dB
dB
100kHz Input Signal
–3dB Point
dB
MHz
The l denotes the specifications which apply over the full operating temperature range, otherwise
analog input
specifications are at TA = 25°C. (Note 5)
ꢀTC1863/ꢀTC1867/ꢀTC1867A
SYMBOꢀ
PARAMETER
CONDꢂTꢂONS
MꢂN
TYP
MAX
UNꢂTS
l
l
Analog Input Range
Unipolar Mode (Note 9)
Bipolar Mode
0-4.096
2.048
V
V
C
Analog Input Capacitance for CH0 to
CH7/COM
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
32
4
pF
pF
IN
l
l
t
Sample-and-Hold Acquisition Time
Input Leakage Current
1.5
1.1
µs
ACQ
On Channels, CHX = 0V or V
1
µA
DD
(Note 5)
internal reFerence characteristics
ꢀTC1863/ꢀTC1867/ꢀTC1867A
PARAMETER
CONDꢂTꢂONS
MꢂN
TYP
2.5
MAX
UNꢂTS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
I
= 0
= 0
2.48
2.52
REF
REF
REF
REF
OUT
OUT
15
ppm/°C
mV/V
kΩ
4.75V ≤ V ≤ 5.25V
0.43
6
DD
I
≤0.1mA
OUT
REFCOMP Output Voltage
I
= 0
4.096
V
OUT
18637fb
3
For more information www.linear.com/LTC1863
LTC1863/LTC1867
The l denotes the specifications which apply over the
Digital inputs anD Digital outputs
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
ꢀTC1863/ꢀTC1867/ꢀTC1867A
SYMBOꢀ
PARAMETER
CONDꢂTꢂONS
MꢂN
TYP
MAX
UNꢂTS
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.75V
= 0V to V
2.4
V
V
IH
IL
DD
DD
IN
0.8
10
I
µA
pF
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage (SDO)
2
IN
V
DD
V
DD
= 4.75V, I = –10µA
= 4.75V, I = –200µA
4.75
4.74
V
V
OH
O
O
l
l
4
V
Low Level Output Voltage (SDO)
V
DD
V
DD
= 4.75V, I = 160µA
= 4.75V, I = 1.6mA
0.05
0.1
V
V
OL
O
O
0.4
I
I
Output Source Current
Output Sink Current
SDO = 0V
SDO = V
–32
19
mA
mA
SOURCE
SINK
DD
µA
pF
l
l
Hi-Z Output Leakage
Hi-Z Output Capacitance
CS/CONV = High, SDO = 0V or V
CS/CONV = High (Note 10)
10
15
DD
Data Format
Unipolar
Bipolar
Straight Binary
Two’s Complement
The l denotes the specifications which apply over the full operating temperature
power requirements
range, otherwise specifications are at TA = 25°C. (Note 5)
ꢀTC1863/ꢀTC1867/ꢀTC1867A
SYMBOꢀ
PARAMETER
CONDꢂTꢂONS
MꢂN
TYP
MAX
5.25
1.8
UNꢂTS
V
Supply Voltage
Supply Current
(Note 9)
4.75
V
DD
l
I
f
= 200ksps
1.3
150
0.2
mA
µA
µA
DD
SAMPLE
NAP Mode
l
l
SLEEP Mode
3
9
P
Power Dissipation
6.5
mW
DISS
18637fb
4
For more information www.linear.com/LTC1863
LTC1863/LTC1867
timing characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
ꢀTC1863/ꢀTC1867/ꢀTC1867A
SYMBOꢀ
PARAMETER
CONDꢂTꢂONS
MꢂN
TYP
MAX
3.5
40
UNꢂTS
kHz
µs
l
l
l
f
t
t
f
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
200
SAMPLE
3
CONV
Acquisition Time
1.5
40
5
1.1
µs
ACQ
SCK
1
SCK Frequency
MHz
ns
l
l
l
l
l
l
CS/CONV High Time
Short CS/CONV Pulse Mode
100
13
11
10
–6
4
SDO Valid After SCK↓
C = 25pF (Note 11)
L
22
ns
2
SDO Valid Hold Time After SCK↓
SDO Valid After CS/CONV↓
SDI Setup Time Before SCK↑
SDI Hold Time After SCK↑
SLEEP Mode Wake-Up Time
Bus Relinquish Time After CS/CONV↑
C = 25pF
L
ns
3
C = 25pF
L
30
ns
4
15
10
ns
5
ns
6
C
= 10µF, C = 2.2µF
VREF
60
20
ms
ns
7
REFCOMP
l
C = 25pF
L
40
8
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Unipolar offset is the offset voltage measured from +1/2LSB
when the output code flickers between 0000 0000 0000 0000 and
0000 0000 0000 0001 for LTC1867 and between 0000 0000 0000 and
0000 0000 0001 for LTC1863. Bipolar offset is the offset voltage measured
from –1/2LSB when output code flickers between 0000 0000 0000 0000
and 1111 1111 1111 1111 for LTC1867, and between
Note 2: All voltage values are with respect to GND (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V , they
DD
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND without latchup. These pins are not
0000 0000 0000 and 1111 1111 1111 for LTC1863.
Note 9: Recommended operating conditions. The input range of 2.048V
for bipolar mode is measured with respect to V – = 2.5V.
clamped to V
.
DD
IN
Note 10: Guaranteed by design, not subject to test.
Note 5: V = 5V, f
= 200ksps at 25°C, t = t = 5ns and
r f
DD
SAMPLE
V – = 2.5V for bipolar mode unless otherwise specified.
IN
Note 11: t of 25ns maximum allows f
up to 20MHz for rising capture
2
SCK
with 50% duty cycle and f
setup time for the receiving logic).
up to 40MHz for falling capture (with 3ns
Note 6: Linearity, offset and gain error specifications apply for both
unipolar and bipolar modes. The INL and DNL are tested in bipolar mode.
SCK
18637fb
5
For more information www.linear.com/LTC1863
LTC1863/LTC1867
typical perFormance characteristics
(ꢀTC1867)
ꢂntegral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
Histogram for 4096 Conversions
2.0
1.5
2500
2000
1500
1000
500
2.0
1.5
2152
1.0
1.0
0.5
0.5
0
0
935
–0.5
–1.0
–1.5
–2.0
– 0.5
– 1.0
– 1.5
– 2.0
579
276
122
26
1
–4 –3 –2
5
3
0
4
0
0
16384
32768
49152
65536
–1
0
1
2
0
16384
32768
49152
65536
OUTPUT CODE
CODE
OUTPUT CODE
18637 GO2
18637 GO3
18637 GO1
4096 Points FFT Plot (fꢂN = 1kHz,
REFCOMP = Eꢁternal 5V)
4096 Points FFT Plot (fꢂN = 1kHz)
Crosstalk vs ꢂnput Frequency
0
–20
0
–80
–90
SNR = 88.8dB
SINAD = 87.9dB
THD = 95dB
SNR = 90dB
SINAD = 88.5dB
THD = 94dB
–20
–40
f
= 200ksps
f
= 200ksps
SAMPLE
SAMPLE
–40
INTERNAL REFERENCE
V
= 0V
REF
–100
–110
–120
–130
–140
REFCOMP = EXT 5V
–60
–60
ADJACENT PAIR
–80
–80
–100
–120
–140
–100
–120
–140
NONADJACENT PAIR
25
50
75
100
25
50
75
100
0
0
1
10
100
1000
ACTIVE CHANNEL INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
18637 G04
18637 G05
18637 G06
Signal-to-Noise Ratio vs
Frequency
Signal-to-(Noise + Distortion) vs
ꢂnput Frequency
Total Harmonic Distortion vs
ꢂnput Frequency
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
10
INPUT FREQUENCY (kHz)
100
1
10
100
1
10
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
18637 G07
18637 G08
18637 G09
18637fb
6
For more information www.linear.com/LTC1863
LTC1863/LTC1867
typical perFormance characteristics
(ꢀTC1863/ꢀTC1867)
Supply Current vs fSAMPꢀE
Supply Current vs Supply Voltage
Supply Current vs Temperature
2.0
1.5
1.0
0.5
0
1.5
1.5
1.4
1.3
1.2
1.1
1.0
V
= 5V
V
f
= 5V
SAMPLE
V
f
= 5V
SAMPLE
DD
DD
DD
= 200ksps
= 200ksps
1.4
1.3
1.2
1.1
1.0
1
10
100
(ksps)
1000
–50
0
25
50
75
100
–25
4.75
5.0
5.25
4.5
5.5
f
TEMPERATURE (°C)
SAMPLE
SUPPLY VOLTAGE (V)
18637 G10
18637 G12
18637 G11
ꢂntegral Nonlinearity vs Output
Code (ꢀTC1863)
Differential Nonlinearity vs
Output Code (ꢀTC1863)
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2048
3072 3584
4096
2560
512 1024 1536
0
2048
3072 3584
4096
2560
512 1024 1536
OUTPUT CODE
OUTPUT CODE
18637 G14
18637 G13
18637fb
7
For more information www.linear.com/LTC1863
LTC1863/LTC1867
pin Functions
CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog
inputs must be free of noise with respect to GND. CH7/
COM can be either a separate channel or the common
minus input for the other channels.
SCK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer.
SDO (Pin 13): Digital Data Output. The A/D conversion
result is shifted out of this output. Straight binary format
for unipolar mode and two’s complement format for
bipolar mode.
REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass
to GND with 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor (4.096V Nominal). To overdrive
SDꢂ (Pin 14): Digital Data Input Pin. The A/D configuration
word is shifted into this input.
REFCOMP, tie V to GND.
REF
V
(Pin 10): 2.5V Reference Output. This pin can also
REF
GND (Pin 15): Analog and Digital GND.
be used as an external reference buffer input for improved
accuracy and drift. Bypass to GND with 2.2µF tantalum
capacitor in parallel with 0.1µF ceramic capacitor.
V
(Pin 16): Analog and Digital Power Supply. Bypass to
DD
GND with 10µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor.
CS/CONV (Pin 11): This input provides the dual function
of initiating conversions on the ADC and also frames the
serial data transfer.
typical connection Diagram
+
5V
CH0
CH1
CH2
CH3
CH4
CH5
CH6
V
DD
2.048Vꢀ
DIFFERENTIAL
INPUTS
GND
SDI
–
LTC1863/
LTC1867
SDO
SCK
DIGITAL
I/O
4.096Vꢀ
SINGLE-ENDED
INPUT
+
CS/CONV
2.5V
V
REF
2.2µF
CH7/COM REFCOMP
4.096V
10µF
18637ꢀTCD
test circuits
ꢀoad Circuits for Access Timing
ꢀoad Circuits for Output Float Delay
5V
5V
3k
3k
DN
DN
DN
DN
3k
C
C
L
3k
C
C
L
L
L
(A) V TO Hi-Z
OH
(B) V TO Hi-Z
OL
(A) Hi-Z TO V AND V TO V
OH OL
(B) Hi-Z TO V AND V TO V
OL OH
OH
OL
18637 TC02
18637 TC01
18637fb
8
For more information www.linear.com/LTC1863
LTC1863/LTC1867
timing Diagrams
t
(For Short Pulse Mode)
t (SDO Valid Before SCK↑),
2
1
t (SDO Valid Hold Time After SCK↓)
3
t
1
t
2
50%
50%
CS/CONV
SCK
SDO
0.4V
t
3
2.4V
0.4V
t (SDI Setup Time Before SCK↑),
5
t (SDO Valid After CONV↓)
4
t (SDI Hold Time After SCK↑)
6
t
4
t
6
t
5
2.4V
CS/CONV
SCK
SDI
0.4V
Hi-Z
2.4V
0.4V
2.4V
0.4V
2.4V
0.4V
SDO
t (SLEEP Mode Wake-Up Time)
7
t (BUS Relinquish Time)
8
t
7
t
8
2.4V
SCK
50%
CS/CONV
SLEEP BIT (SLP = 0)
READ-IN
90%
10%
Hi-Z
CS/CONV
50%
SDO
1867 TD
applications inFormation
Overview
The LTC1863/LTC1867 are complete, low power multi-
plexedADCs.Theyconsistofa12-/16-bit,200kspscapaci-
tive successive approximation A/D converter, a precision
internal reference, a configurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from
the most significant bit (MSB) to the least significant bit
(LSB). The input is successively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low-power, differential
comparator. At the end of a conversion, the DAC output
balances the analog input. The SAR contents (a 12-/16-bit
data word) that represent the analog input are loaded into
the 12-/16-bit output latches.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted.Betweenconversions,theADCsreceiveaninput
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
thenextconversion.Intheacquirephase,aminimumtime
of1.5µswillprovideenoughtimeforthesample-and-hold
capacitors to acquire the analog signal.
18637fb
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LTC1863/LTC1867
applications inFormation
Analog ꢂnput Multipleꢁer
Changing the MUX Assignment “On the Fly”
1st Conversion
2nd Conversion
The analog input multiplexer is controlled by a 7-bit input
data word. The input data word is defined as follows:
+
–
+
–
CH2
CH3
–
+
CH2
CH3
{
{
{
{
SD OS S1 S0 COM UNI SLP
SD = SINGLE/DIFFERENTIAL BIT
OS = ODD/SIGN BIT
CH4
CH5
+
+
CH4
CH5
CH7/COM
(UNUSED)
CH7/COM (
)
–
S1 = ADDRESS SELECT BIT 1
S0 = ADDRESS SELECT BIT 0
COM = CH7/COM CONFIGURATION BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
18637 AI02
Tables 1 and 2 show the configurations when COM = 0,
and COM = 1.
Table 1. Channel Configuration (When COM = 0, CH7/COM Pin
ꢂs Used as CH7)
Channel Configuration
SD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OS
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
COM
0
“+”
CH0
CH2
CH4
CH6
CH1
CH3
CH5
CH7
CH0
CH2
CH4
CH6
CH1
CH3
CH5
CH7
“–”
CH1
CH3
CH5
CH7
CH0
CH2
CH4
CH6
GND
GND
GND
GND
GND
GND
GND
GND
Eꢁamples of Multipleꢁer Options
0
4 Differential
8 Single-Ended
0
CH0
CH1
+
–
+
–
(
(
)
)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
+
+
+
+
+
+
+
+
–
0
{
{
{
{
+
0
(
(
)
)
CH2
CH3
–
0
+
0
+
–
+
–
(
(
)
)
CH4
CH5
–
+
0
0
CH6
CH7/COM
(
(
)
)
–
+
GND (
)
–
0
0
7 Single-Ended
to CH7/COM
0
Combinations of Differential
and Single-Ended
0
CH0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
+
+
+
+
+
+
+
+
0
{
CH1
–
0
CH2
CH3
–
{
0
+
+
+
+
+
CH4
CH5
CH6
CH7/COM
Table 2. Channel Configuration (When COM = 1, CH7/COM Pin
ꢂs Used as COMMON)
Channel Configuration
CH7/COM (
)
–
GND ( )
–
18637 AI01
SD
1
OS
0
S1
0
S0
0
COM
“+”
CH0
CH2
CH4
CH6
CH1
CH3
CH5
“–”
1
1
1
1
1
1
1
CH7/COM
CH7/COM
CH7/COM
CH7/COM
CH7/COM
CH7/COM
CH7/COM
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
18637fb
10
For more information www.linear.com/LTC1863
LTC1863/LTC1867
applications inFormation
Driving the Analog ꢂnputs
LT1360-37MHzvoltagefeedbackamplifier.3.8mAsupply
current. 5V to 15V supplies. Good AC/DC specs.
The analog inputs of the LTC1863/LTC1867 are easy to
drive. Each of the analog inputs can be used as a single-
ended input relative to the GND pin (CH0-GND, CH1-GND,
etc)orinpairs(CH0andCH1, CH2andCH3, CH4andCH5,
CH6 and CH7) for differential inputs. In addition, CH7 can
act as a COM pin for both single-ended and differential
modes if the COM bit in the input word is high. Regard-
less of the MUX configuration, the “+” and “–” inputs are
sampled at the same instant. Any unwanted signal that is
common mode to both inputs will be reduced by the com-
mon mode rejection of the sample-and-hold circuit. The
inputs draw only one small current spike while charging
the sample-and-hold capacitors during the acquire mode.
In conversion mode, the analog inputs draw only a small
leakage current. If the source impedance of the driving
circuit is low then the LTC1863/LTC1867 inputs can be
driven directly. More acquisition time should be allowed
for a higher impedance source.
LT1363-50MHzvoltagefeedbackamplifier.6.3mAsupply
current. Good AC/DC specs.
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
amplifiers. 6.3mA supply current per amplifier. Good
AC/DC specs.
LT1468 - 90MHz, 22V/µs 16-bit accurate amplifier
LT1469 - Dual LT1468
ꢂnput Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1863/LTC1867 noise and distortion. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For instance, Figure 1 shows a 50Ω
source resistor and a 2000pF capacitor to ground on the
input will limit the input bandwidth to 1.6MHz. The source
impedance has to be kept low to avoid gain error and
degradation in the AC performance. The capacitor also
acts as a charge reservoir for the input sample-and-hold
and isolates the ADC input from sampling glitch sensitive
circuitry. High quality capacitors and resistors should be
used since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity.Carbonsurfacemountresistorscanalsogenerate
distortion from self heating and from damage that may
occurduringsoldering.Metalfilmsurfacemountresistors
are much less susceptible to both problems.
The following list is a summary of the op amps that are
suitable for driving the LTC1863/LTC1867. More detailed
informationisavailableintheLinearTechnologydatabooks
or Linear Technology website.
LT1007 - Low noise precision amplifier. 2.7mA supply
current 5V to 15V supplies. Gain bandwidth product
8MHz. DC applications.
LT1097 - Low cost, low power precision amplifier. 300µA
supply current. 5V to 15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227-140MHzvideocurrentfeedbackamplifier. 10mA
supply current. 5V to 15V supplies. Low noise and low
distortion.
18637fb
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For more information www.linear.com/LTC1863
LTC1863/LTC1867
applications inFormation
50Ω
Dynamic Performance
ANALOG
INPUT
CH0
LTC1863/
2000pF
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
LTC1867
GND
REFCOMP
10µF
1867 F01a
Figure 1a. Optional RC ꢂnput Filtering for Single-Ended ꢂnput
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 3 shows a typical SINAD of 87.9dB
with a 200kHz sampling rate and a 1kHz input. When an
1000pF
50Ω
CH0
DIFFERENTIAL
LTC1863/
ANALOG
INPUTS
1000pF
1000pF
LTC1867
50Ω
CH1
REFCOMP
10µF
external 5V is applied to REFCOMP (tie V
to GND), a
REF
1867 F01b
signal-to-noise ratio of 90dB can be achieved.
Figure 1b. Optional RC ꢂnput Filtering for Differential ꢂnputs
0
SNR = 88.8dB
SINAD = 87.9dB
–20
THD = 95dB
DC Performance
f
= 200ksps
SAMPLE
–40
–60
INTERNAL REFERENCE
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where
a DC signal is applied to the input of the ADC and the
resulting output codes are collected over a large number
of conversions. For example, in Figure 2 the distribution
of output codes is shown for a DC input that had been
digitized 4096 times. The distribution is Gaussian and the
RMS code transition noise is about 0.74LSB.
–80
–100
–120
–140
25
50
75
100
0
FREQUENCY (kHz)
18637 G04
2500
2152
2000
Figure 3. ꢀTC1867 Nonaveraged 4096 Point FFT Plot
Total Harmonic Distortion
1500
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
935
1000
500
0
579
1
276
122
2
26
–4 –3 –2
5
3
1
0
4
–1
0
2
2
2
2
CODE
V2 + V3 + V4 ...+ VN
THD = 20log
18637 GO3
V1
Figure 2. ꢀTC1867 Histogram for 4096 Conversions
18637fb
12
For more information www.linear.com/LTC1863
LTC1863/LTC1867
applications inFormation
Digital ꢂnterface
where V is the RMS amplitude of the fundamental fre-
1
quencyandV throughV aretheamplitudesofthesecond
2
N
TheLTC1863/LTC1867haveaverysimpledigitalinterface
thatisenabledbythecontrolinput,CS/CONV.Alogicrising
edgeappliedtotheCS/CONVinputwillinitiateaconversion.
After the conversion, taking CS/CONV low will enable the
serial port and the ADC will present digital data in two’s
complement format in bipolar mode or straight binary
formatinunipolarmode,throughtheSCK/SDOserialport.
through Nth harmonics.
ꢂnternal Reference
The LTC1863/LTC1867 has an on-chip, temperature
compensated, curvature corrected, bandgap reference
that is factory trimmed to 2.5V. It is internally connected
to a reference amplifier and is available at V (Pin 10).
REF
ꢂnternal Clock
A 6k resistor is in series with the output so that it can be
easily overdriven by an external reference if better drift
and/or accuracy are required as shown in Figure 4. The
The internal clock is factory trimmed to achieve a typical
conversion time of 3µs and a maximum conversion time,
3.5µs, over the full operating temperature range. The typi-
cal acquisition time is 1.1µs, and a throughput sampling
rate of 200ksps is tested and guaranteed.
reference amplifier gains the V
voltage by 1.638V/V
REF
to 4.096V at REFCOMP (Pin 9). This reference amplifier
compensation pin, REFCOMP, must be bypassed with a
10µF ceramic or tantalum in parallel with a 0.1µF ceramic
for best noise performance.
Automatic Nap Mode
TheLTC1863/LTC1867gointoautomaticnapmode when
CS/CONV is held high after the conversion is complete
(see Figure 6). With a typical operating current of 1.3mA
andautomatic150µAnapmodebetweenconversions, the
power dissipation drops with reduced sample rate. The
R1
6k
V
10
2.2µF
9
REF
BANDGAP
REFERENCE
2.5V
REFCOMP
REFERENCE
AMP
4.096V
ADC only keeps the V
and REFCOMP voltages active
REF
whenthepartisintheautomaticnapmode. Theslowerthe
sample rate allows the power dissipation to be lower (see
Figure 5).
10µF
15
R2
R3
GND
LTC1863/LTC1867
1867 F04a
2.0
V
DD
= 5V
Figure 4a. ꢀTC1867 Reference Circuit
5V
1.5
1.0
0.5
0
V
IN
LT1019A-2.5
V
10
2.2µF
9
V
OUT
REF
LTC1863/
LTC1867
REFCOMP
+
10µF
0.1µF
15
GND
1
10
100
(ksps)
1000
f
SAMPLE
1867 F04b
18637 G10
Figure 4b. Using the ꢀT1019-2.5 as an Eꢁternal Reference
Figure 5. Supply Current vs fSAMPꢀE
18637fb
13
For more information www.linear.com/LTC1863
LTC1863/LTC1867
applications inFormation
If the CS/CONV returns low during a bit decision, it can
create a small error. For best performance ensure that
the CS/CONV returns low either within 100ns after the
conversion starts (i.e. before the first bit decision) or
after the conversion ends. If CS/CONV is low when the
conversion ends, the MSB bit will appear on SDO at the
end of the conversion and the ADC will remain powered
up (see Figure 7).
of the common return for these bypass capacitors is es-
sential to the low noise operation of the ADC. The width
for these tracks should be as wide as possible.
Timing and Control
Conversion start is controlled by the CS/CONV digital in-
put. The rising edge transition of the CS/CONV will start a
conversion. Once initiated, it cannot be restarted until the
conversion is complete. Figures 6 and 7 show the timing
diagrams for two types of CS/CONV pulses.
Sleep Mode
If the SLP = 1 is selected in the input word, the ADC
will enter SLEEP mode and draw only leakage current
Example1(Figure6)showstheLTC1863/LTC1867operat-
ing in automatic nap mode with CS/CONV signal staying
HIGH after the conversion. Automatic nap mode provides
powerreductionatreducedsamplerate.TheADCscanalso
operate with the CS/CONV signal returning LOW before
the conversion ends. In this mode (Example 2, Figure 7),
the ADCs remain powered up.
(provided that all the digital inputs stay at GND or V ).
DD
After release from the SLEEP mode, the ADC need 60ms
to wake up (2.2µF/10µF bypass capacitors on V
REFCOMP pins).
/
REF
Board ꢀayout and Bypassing
Forbestperformance,itisrecommendedtokeepSCK,SDI,
and SDO at a constant logic high or low during acquisition
andconversion,eventhoughthesesignalsmaybeignored
by the serial interface (DON’T CARE). Communication
with other devices on the bus should not coincide with
To obtain the best performance, a printed circuit board
with a ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside
an analog signal.
the conversion period (t
).
CONV
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar mode.
All analog inputs should be screened by GND. V
,
REF
REFCOMP and V should be bypassed to this ground
DD
plane as close to the pin as possible; the low impedance
t
ACQ
1/f
SCK
CS/CONV
t
NAP MODE
CONV
NOT NEEDED FOR LTC1863
13 14 15 16
SCK
SDI
1
2
3
4
5
6
7
8
9
10
11
12
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
SD 0S
MSB
S1 S0 COM UNI SLP
Hi-Z
Hi-Z
SDO
(LTC1863)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
(LTC1867)
1867 F06
Figure 6. Eꢁample 1, CS/CONV Starts a Conversion and Remains HꢂGH Until Neꢁt Data Transfer. With CS/CONV Remaining HꢂGH After
the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate.
18637fb
14
For more information www.linear.com/LTC1863
LTC1863/LTC1867
applications inFormation
t
CS/CONV
ACQ
NOT NEEDED FOR LTC1863
SCK
DON'T CARE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
SD 0S
S1 S0 COM UNI SLP
DON'T CARE
CONV
DON'T CARE
t
SDO
MSB = D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LTC1863)
Hi-Z
Hi-Z
t
CONV
SDO
(LTC1867)
MSB = D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1867 F07
Figure 7. Eꢁample 2, CS/CONV Starts a Conversion With Short Active HꢂGH Pulse.
With CS/CONV Returning ꢀOW Before the Conversion, the ADC Remains Powered Up.
111...111
011...111
011...110
111...110
BIPOLAR
ZERO
100...001
100...000
011...111
011...110
000...001
000...000
111...111
111...110
UNIPOLAR
ZERO
FS = 4.096
FS = 4.096
n
000...001
000...000
n
1LSB = FS/2
100...001
100...000
1LSB = FS/2
1LSB = (LTC1863) = 1mV
1LSB = (LTC1867) = 62.5µV
1LSB = (LTC1863) = 1mV
1LSB = (LTC1867) = 62.5µV
–1 0V
LSB
INPUT VOLTAGE (V)
1
–FS/2
FS/2 – 1LSB
0V
FS – 1LSB
LSB
INPUT VOLTAGE (V)
1867 F09
1867 F08
Figure 8. ꢀTC1863/ꢀTC1867 Bipolar Transfer
Characteristics (Two’s Complement)
Figure 9. ꢀTC1863/ꢀTC1867 Unipolar Transfer
Characteristics (Straight Binary)
18637fb
15
For more information www.linear.com/LTC1863
LTC1863/LTC1867
package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-ꢀead Plastic SSOP (Narrow .150 ꢂnch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
.045 .005
(4.801 – 4.978)
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 REV B 0212
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
18637fb
16
For more information www.linear.com/LTC1863
LTC1863/LTC1867
revision history (Revision history begins at Rev B)
REV
DATE
DESCRꢂPTꢂON
PAGE NUMBER
B
6/14
Fixed the Order Information.
2
18637fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC1863/LTC1867
relateD parts
PART NUMBER
DESCRꢂPTꢂON
COMMENTS
LTC1417
14-Bit, 400ksps Serial ADC
20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
Bandgap, 130µA Supply Current, 10ppm/°C, SOT-23 Package
Low Input Offset: 75µV/125µV
LT1460
Micropower Precision Series Reference
Single/Dual 90MHz, 22V/µs, 16-Bit Accurate Op Amps
16-Bit, 200ksps Serial ADC
LT1468/LT1469
LTC1609
65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
60µA Supply Current, 10ppm/°C, SOT-23 Package
LT1790
Micropower Low Dropout Reference
10-Bit/12-Bit, 8-Channel, 1.25Msps ADC
10-Bit/12-Bit, 8-Channel, 400ksps ADC
12-Bit, 1-/2-Channel 250ksps ADC in MSOP
LTC1850/LTC1851
LTC1852/LTC1853
LTC1860/LTC1861
Parallel Output, Programmable MUX and Sequencer, 5V Supply
Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
LTC1860L/LTC1861L 3V, 12-Bit, 1-/2-Channel 150ksps ADC
LTC1864/LTC1865 16-Bit, 1-/2-Channel 250ksps ADC in MSOP
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADC in MSOP
18637fb
LT 0614 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
18
●
●
LINEAR TECHNOLOGY CORPORATION 2008
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC1863
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