LTC1709EG-85#TRPBF_技术文档

LTC1709-85

2-Phase, 5-Bit VID,

Current Mode, High Efficiency,

Synchronous Step-Down Switching Regulator

U

DESCRIPTIO

FEATURES

The LTC^®1709-85 is a 2-phase, VID programmable, syn-

chronous step-down switching regulator controller that

drivestwoallN-channelexternalpowerMOSFETstagesin

a fixed frequency architecture. The 2-phase controller

drives its two output stages out of phase at frequencies up

to 300kHz to minimize the RMS ripple currents in both

input and output capacitors. The 2-phase technique effec-

tively multiplies the fundamental frequency by two, im-

proving transient response while operating each channel

at an optimum frequency for efficiency. Thermal design is

also simplified.

■

Output Stages Operate Antiphase Reducing Input

Capacitance Requirements and Power Supply

Induced Noise

Dual Input Supply Capability for Load Sharing

5-Bit VID Code (VRM 8.5): V_OUT= 1.05V to 1.825V

True Remote Sensing Differential Amplifier

Power Good Output Indicator

■

±1% Output Voltage Accuracy

Active Voltage Positioning Capable

Current Mode Control Ensures Current Sharing

OPTI-LOOP^®Compensation Minimizes C_OUT

Three Operational Modes: PWM, Burst and Cycle Skip

Programmable Fixed Frequency: 150kHz to 300kHz

Wide V_INRange: 4V to 36V Operation

An operating mode select pin (FCB) can be used to select

among three modes including Burst Mode^®operation for

highestefficiency.Aninternaldifferentialamplifierprovides

true remote sensing of the regulated supply’s positive and

negative output terminals as required in high current ap-

plications.

Adjustable Soft-Start Current Ramping

Internal Current Foldback and Short-Circuit Shutdown

Overvoltage Soft Latch Eliminates Nuisance Trips

Available in 36-Lead Narrow SSOP Package

The RUN/SS pin provides soft-start and optional timed,

short-circuit shutdown. Current foldback limits MOSFET

dissipation during short-circuit conditions when the

overcurrentlatchoffisdisabled.OPTI-LOOPcompensation

allows the transient response to be optimized for a wide

range of output capacitors and ESR values.

U

APPLICATIO S

■

Server/Desktop Computers

■

Internet Servers

■

Large Memory Arrays

DC Power Distribution Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

OPTI-LOOP and Burst Mode are registered trademarks of Linear Technology Corporation.

U

TYPICAL APPLICATIO

V

IN

5V TO 28V

+

10µF

35V

×4

0.1µF

V

IN

FCB

TG1

S

0.002Ω

RUN/SS

BOOST1

SW1

0.47µF

220pF

3.3k

1µH

S

LTC1709-85

I

TH

BG1

SGND

PGND

+

SENSE1

PGOOD

–

5 VID BITS VID0–VID4

TG2

BOOST2

SW2

V

OUT

EAIN

0.47µF

1.05V TO 1.825V

40A

1µH

ATTENOUT

ATTENIN

BG2

V

INTV

DIFFOUT

CC

+

10µF

C

OUT

+

–

SENSE2

OS

1000µF

4V

+

–

OS

×2

170985 F01

Figure 1. High Current Dual Phase Step-Down Converter

170985f

1

LTC1709-85

W W U W

U

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

PACKAGE/ORDER I FOR ATIO

TOP VIEW

ORDER PART

Input Supply Voltage (V_IN).........................36V to –0.3V

Topside Driver Voltages (BOOST1,2).........42V to –0.3V

Switch Voltage (SW1, 2) .............................36V to –5 V

SENSE1⁺, SENSE2⁺, SENSE1^–,

NUMBER

1

2

NC

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

RUNN/SS

+

TG1

SENSE1

–

LTC1709EG-85

3

SW1

BOOST1

SENSE1

4

EAIN

PLLFLTR

PLLIN

SENSE2^–Voltages ................... (1.1)INTV_CCto –0.3V

EAIN, V_OS⁺, V_OS^–, EXTV_CC, INTV_CC, RUN/SS,

V_BIAS, ATTENIN, ATTENOUT, PGOOD,

5

V

IN

6

BG1

7

EXTV

CC

FCB

VID25mV–VID3 Voltages ........................7V to –0.3V

Boosted Driver Voltage (BOOST-SW) ..........7V to –0.3V

8

INTV

CC

I

TH

9

PGND

BG2

SGND

PLLFLTR, PLLIN, V_DIFFOUT

,

10

11

12

13

14

15

16

17

18

V

DIFFOUT

–

FCB Voltages ................................... INTV_CCto –0.3V

I_THVoltage................................................2.7V to –0.3V

Peak Output Current <1µs(TGL1,2, BG1,2)................ 3A

INTV_CCRMS Output Current................................ 50mA

Operating Ambient Temperature Range

BOOST2

SW2

V

OS

+

–

+

TG2

SENSE2

PGOOD

V

ATTENOUT

ATTENIN

VID25mV

VID0

BIAS

VID3

VID2

VID1

(Note 2) .............................................. –40°C to 85°C

Junction Temperature (Note 3)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

G PACKAGE

36-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 85°C/W

Consult LTC Marketing for parts specified with wider operating temperature

ranges.

ELECTRICAL CHARACTERISTICS ^The● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_BIAS= 3.3V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

V

Regulated Feedback Voltage

Maximum Current Sense Threshold

Feedback Current

I

Voltage = 1.2V (Note 4)

TH

●

0.792

62

0.800

75

0.808

88

V

mV

nA

EAIN

SENSEMAX

INEAIN

I

(Note 4)

–5

–50

V

Output Voltage Load Regulation

LOADREG

Measured in Servo Loop, ∆I Voltage: 1.2V to 0.7V

●

0.1

–0.1

0.5

–0.5

%

TH

Measured in Servo Loop, ∆I Voltage: 1.2V to 2V

TH

V

Reference Voltage Line Regulation

Forced Continuous Threshold

Forced Continuous Current

V

= 3.6V to 30V (Note 4)

IN

0.002

0.8

0.02

0.84

–1

%/V

V

REFLNREG

FCB

●

0.76

I

– 0.17

4.3

µA

V

FCB

V

Burst Inhibit (Constant Frequency)

Threshold

Measured at FCB pin

Measured at V

4.8

BINHIBIT

V

Output Overvoltage Threshold

Undervoltage Lockout

●

0.84

3

0.86

3.5

3

0.88

4

V

OVL

EAIN

UVLO

V

Ramping Down

IN

TH

g

Transconductance Amplifier g

I

= 1.2V, Sink/Source 5µA (Note 4)

mmho

V/mV

m

Transconductance Amplifier Gain

= 1.2V, (g • Z ; No Ext Load) (Note 4)

1.5

mOL

m

L

170985f

2

LTC1709-85

The ● denotes the specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_BIAS= 3.3V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Input DC Supply Current

Normal Mode

(Note 5)

Q

EXTV Tied to V , V

= 5V

470

20

µA

CC

RUN/SS

OUT OUT

Shutdown

V

= 0V

40

I

Soft-Start Charge Current

RUN/SS Pin ON Arming

= 1.9V

–0.5

1.0

–1.2

1.5

4.1

2

µA

V

RUN/SS

V

Rising

1.9

4.5

4

RUN/SS

RUN/SSLO

SCL

RUN/SS Pin Latchoff Arming

RUN/SS Discharge Current

Shutdown Latch Disable Current

Total Sense Pins Source Current

Maximum Duty Factor

Rising from 3V

V

I

Soft Short Condition V

= 0.5V, V

= 4.5V

RUN/SS

0.5

µA

%

EAIN

V

= 0.5V

EAIN

1.6

–60

99.5

5

SDLHO

SENSE

Each Channel: V

In Dropout

(Note 6)

–

– = V

+ + = 0V

–85

98

SENSE1 , 2

DF

MAX

Top Gate Transition Time:

Rise Time

Fall Time

TG1, 2 t

C

= 3300pF

30

40

90

ns

r

f

LOAD

Bottom Gate Transition Time:

Rise Time

Fall Time

(Note 6)

LOAD

BG1, 2 t

C

= 3300pF

30

20

90

ns

r

f

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

C

= 3300pF Each Driver (Note 6)

90

ns

1D

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

C

= 3300pF Each Driver (Note 6)

90

2D

t

Minimum On-Time

Tested with a Square Wave (Note 7)

180

ON(MIN)

Internal V Regulator

CC

V

Internal V Voltage

6V < V < 30V, V = 4V

EXTVCC

4.8

4.5

5.0

0.2

80

5.2

1.0

160

V

%

INTVCC

CC

IN

INT

INTV Load Regulation

I

= 0 to 20mA, V

= 4V

EXTVCC

LDO

CC

EXT

EXTV Voltage Drop

= 20mA, V

= 5V

mV

V

CC

EXTVCC

EXTV Switchover Voltage

= 20mA, EXTV Ramping Positive

●

4.7

0.2

EXTVCC

LDOHYS

CC

EXTV Switchover Hysteresis

= 20mA, EXTV Ramping Negative

V

CC

VID Parameters

V

Operating Supply Voltage Range

2.7

5.5

V

BIAS

R

Resistance Between ATTENIN

and ATTENOUT Pins

10

40

kΩ

ATTEN

Resistive Divider Error

V

= 3.3V

BIAS

–0.25

0.25

0.8

1

%

kΩ

V

ERR

R

VID25mV to VID3 Pull-Up Resistance

VID25mV to VID3 Logic Threshold Low

VID25mV to VID3 Logic Threshold High

VID25mV to VID3 Leakage

(Note 8)

PULLUP

VID

V

= 3.3V

THLOW

THHIGH

LEAK

BIAS

= 3.3V

2

V

< VID25mV–VID3 < 7V

µA

Oscillator and Phase-Locked Loop

f

Nominal Frequency

Lowest Frequency

Highest Frequency

PLLIN Input Resistance

V

= 1.2V

= 0V

190

120

280

220

140

310

50

250

160

360

kHz

kΩ

NOM

LOW

HIGH

PLLFLTR

≥ 2.4V

R

PLLIN

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

PLLFLTR

f

< f

> f

–15

15

µA

PLLIN

OSC

R

Controller 2-Controller 1 Phase

180

Deg

RELPHS

170985f

3

LTC1709-85

The ● denotes the specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_BIAS= 3.3V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PGOOD Output

V

PGOOD Voltage Low

I

= 2mA

= 5V

0.1

0.3

V

PGL

PGOOD

I

PGOOD Leakage Current

PGOOD Trip Level, Either Controller

V

±1

µA

PGOOD

V

with Respect to Set Output Voltage

PG

EAIN

V

Ramping Negative

Ramping Positive

–6

6

–7.5

7.5

–9.5

9.5

%

EAIN

Differential Amplifier/Op Amp Gain Block

A

Gain

0.995

46

1

1.005

V/V

dB

DA

CMRR

Common Mode Rejection Ratio

Input Resistance

0V < V < 5V

55

80

DA

CM

R

Measured at V + Input

kΩ

IN

OS

Note 1: Absolute Maximum Ratings are those values beyond which the

life of a device may be impaired.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 2: The LTC1709EG-85 is guaranteed to meet performance

specifications from 0°C to 70°C. Specifications over the –40°C to 85°C

operating temperature range are assured by design, characterization and

correlation with statistical process controls.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: The minimum on-time condition corresponds to the on inductor

peak-to-peak ripple current ≥40% I

(see Minimum On-Time

MAX

Note 3: T is calculated from the ambient temperature T and power

Considerations in the Applications Information section).

J

A

dissipation P according to the following formula:

D

Note 8: Each built-in pull-up resistor attached to the VID inputs also has a

LTC1709EG-85: T = T + (P • 85°C/W)

Note 4: The LTC1709-85 is tested in a feedback loop that servos V to a

series diode to allow input voltages higher than the VIDV supply without

damage or clamping (see the Applications Information section).

J

A

D

CC

ITH

specified voltage and measures the resultant V

.

EAIN

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Load Current

(3 Operating Modes)

Efficiency vs Input Voltage

Efficiency vs Output Current

100

80

60

40

20

0

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

I

= 20A

OUT

Burst Mode

OPERATION

V

= 1.825V

V

= 5V

IN

FORCED

= 8V

CONTINUOUS

= 12V

= 20V

MODE

CONSTANT

FREQUENCY

(BURST DISABLE)

V

= 1.825V

EXTVCC

OUT

= 0V

V

IN

V

OUT

= 5V

FREQ = 200kHz

V

= 1.6V

= 0V

FCB

FREQ = 200kHz

0.1

1

10

100

0.01

0.1

1

10 100

5

10

15

INPUT VOLTAGE (V)

20

OUTPUT CURRENT (A)

LOAD CURRENT (A)

170985 G02

170985 G01

170985 G03

170985f

4

LTC1709-85

U W

TYPICAL PERFOR A CE CHARACTERISTICS

INTV_CCand EXTV_CCSwitch

Voltage vs Temperature

Supply Current vs Input Voltage

and Mode

EXTV_CCVoltage Drop

1000

800

600

400

200

0

5.05

5.00

4.95

4.90

4.85

4.80

4.75

4.70

250

200

150

100

50

INTV VOLTAGE

CC

ON

EXTV SWITCHOVER THRESHOLD

CC

SHUTDOWN

0

50

TEMPERATURE (°C)

100 125

0

5

10

15

20

25

30

35

0

10

20

30

40

50

–50 –25

0

25

75

INPUT VOLTAGE (V)

CURRENT (mA)

170985 G04

170985 G05

170985 G06

Maximum Current Sense Threshold

vs Percent of Nominal Output

Voltage (Foldback)

Maximum Current Sense Threshold

vs Duty Factor

Internal 5V LDO Line Reg

75

50

25

0

5.1

5.0

80

70

60

50

40

30

20

10

0

I

= 1mA

LOAD

4.9

4.8

4.7

4.6

4.5

4.4

0

20

40

60

80

100

20

INPUT VOLTAGE (V)

30

35

0

5

10

15

25

50

0

25

75

100

DUTY FACTOR (%)

PERCENT OF NOMINAL OUTPUT VOLTAGE (%)

170985 G08

170985 G07

170985 G09

Current Sense Threshold

vs I_THVoltage

Maximum Current Sense Threshold

vs V_RUN/SS(Soft-Start)

Maximum Current Sense Threshold

vs Sense Common Mode Voltage

90

80

60

40

20

80

76

72

68

64

60

V

= 1.6V

SENSE(CM)

70

60

50

40

30

20

10

0

–10

–20

–30

0

1

2

3

4

5

6

0

0.5

1

1.5

2

0

0.5

1

1.5

(V)

2

2.5

V

(V)

RUN/SS

COMMON MODE VOLTAGE (V)

V

ITH

170985 G10

170985 G11

170985 G12

170985f

5

LTC1709-85

TYPICAL PERFOR A CE CHARACTERISTICS

U W

SENSE Pins Total Source Current

Load Regulation

V_ITHvs V_RUN/SS

0.0

–0.1

–0.2

–0.3

–0.4

2.5

2.0

1.5

1.0

100

50

FCB = 0V

= 15V

V

= 0.7V

OSENSE

V

IN

FIGURE 1

0

–50

–100

0.5

0

1

2

3

4

5

0

2

3

4

5

6

0

0.5

1

1.5

2

1

V

(V)

LOAD CURRENT (A)

V

SENSE

COMMON MODE VOLTAGE (V)

RUN/SS

170985 G13

170985 G14

170985 G15

Maximum Current Sense

Threshold vs Temperature

RUN/SS Current vs Temperature

Soft-Start Up

80

78

76

74

72

70

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

V_ITH

1V/DIV

V_OUT

2V/DIV

V_RUN/SS

2V/DIV

100ms/DIV

170985 G18

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

170985 G16

170985 G17

Load Step

Burst Mode Operation

Constant Frequency Mode

V_IN= 15V, V_OUT= 1.6V, I_L= 400mA_RMS

V_IN= 15V, V_OUT= 1.6V

V_IN= 15V, V_OUT= 1.6V, I_L= 200mA_RMS

V_OUT(AC)

20mV/DIV

V_OUT(AC)

20mV/DIV

V_OUT

50mV/DIV

I_L1

1A/DIV

I_L1

1A/DIV

I_OUT

0/20A

I_L2

1A/DIV

I_L2

1A/DIV

FCB = 0V

FCB = OPEN

FCB = INTV_CC

20µs/DIV

170985 G19

10µs/DIV

170985 G25

2µs/DIV

170985 G26

170985f

6

LTC1709-85

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Oscillator Frequency

vs Temperature

Current Sense Pin Input Current

vs Temperature

EXTV_CCSwitch Resistance

vs Temperature

–13

–12

–11

–10

–9

10

8

350

300

V

OUT

= 1.6V

V

= 2.4V

PLLFLTR

250

200

150

100

50

6

V

= 0V

PLLFLTR

4

2

0

–8

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75

125

–50 –25

0

25

50

75

100 125

100

TEMPERATURE (°C)

170985 G20

170985 G21

170985 G22

Undervoltage Lockout

vs Temperature

V_RUN/SSShutdown Latch

Thresholds vs Temperature

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

3.50

3.45

3.40

3.35

LATCH ARMING

LATCHOFF

THRESHOLD

3.30

3.25

3.20

0

50

100 125

–50 –25

0

25

75

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

170985 G23

170985 G24

U

PI FU CTIO S

RUN/SS (Pin 1): Combination of Soft-Start, Run Control SENSE1^–, SENSE2^–(Pins 3, 13): The (–) Input to the

Input and Short-Circuit Detection Timer. A capacitor to Differential Current Comparators.

groundatthispinsetstheramptimetofullcurrentoutput.

EAIN(Pin4):Inputtotheerroramplifierthatcomparesthe

Forcing this pin below 0.8V causes the IC to shut down all

feedback voltage to the internal 0.8V reference voltage.

internal circuitry. All functions are disabled in shutdown.

This pin is normally connected to a resistive divider from

SENSE1⁺, SENSE2⁺(Pins 2,14): The (+) Input to Each the output of the differential amplifier (DIFFOUT).

Differential Current Comparator. The I_THpin voltage and

built-in offsets between SENSE^–and SENSE⁺pins in

conjunction with R_SENSEset the current trip threshold.

170985f

7

LTC1709-85

U

PI FU CTIO S

PLLFLTR (Pin 5): The phase-locked loop’s lowpass filter

is tied to this pin. Alternatively, this pin can be driven with

an AC or DC voltage source to vary the frequency of the

internal oscillator.

pulled to ground when the voltage on the EAIN pin is not

within ±7.5% of its set point.

TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top

N-Channel MOSFETS. These are the outputs of floating

drivers with a voltage swing equal to INTV_CCsuperim-

posed on the switch node voltage SW.

PLLIN (Pin 6): External Synchronization Input to Phase

Detector. This pin is internally terminated to SGND with

50kΩ. The phase-locked loop will force the rising top gate

signal of controller 1 to be synchronized with the rising

edge of the PLLIN signal.

SW2, SW1 (Pins 25, 34): Switch Node Connections to

Inductors. Voltage swing at these pins is from a Schottky

diode (external) voltage drop below ground to V_IN.

FCB(Pin7):ForcedContinuousControl Input. Thisinput

acts on both output stages . Pulling this pin below 0.8V

will force continuous synchronous operation. Do not

leave this pin floating without a decoupling capacitor.

BOOST2, BOOST1 (Pins 26, 33): Bootstrapped Supplies

to the Topside Floating Drivers. External capacitors are

connectedbetweentheBOOSTandSWpins,andSchottky

diodes are connected between the BOOST and INTV_CC

pins.

I_TH(Pin 8): Error Amplifier Output and Switching Regula-

torCompensationPoint.Bothcurrentcomparator’sthresh-

oldsincreasewiththiscontrolvoltage. Thenormalvoltage

range of this pin is from 0V to 2.4V

BG2, BG1 (Pins 27, 31): High Current Gate Drives for

Bottom N-Channel MOSFETS. Voltage swing at these pins

is from ground to INTV_CC.

SGND (Pin 9): Signal Ground. This pin is common to both

controllers. Route separately to the PGND pin.

PGND(Pin28):DriverPowerGround.Connecttosources

of bottom N-channel MOSFETS and the (–) terminals of

C_IN.

V_DIFFOUT(Pin 10): Output of a Differential Amplifier. This

pin provides true remote output voltage sensing. V_DIFFOUT

normally drives an external resistive divider that sets the

output voltage.

INTV_CC(Pin 29): Output of the Internal 5V Linear Low

Dropout Regulator and the EXTV_CCSwitch. The driver and

control circuits are powered from this voltage source.

Decouple to power ground with a 1µF ceramic capacitor

placed directly adjacent to the IC and minimum of 4.7µF

additional tantalum or other low ESR capacitor.

V_OS^–, V_OS⁺(Pins 11, 12): Inputs to an Operational Ampli-

fier. Internal precision resistors configure it as a differen-

tial amplifier whose output is V_DIFFOUT

.

ATTENOUT (Pin 15): Voltage Feedback Signal Resistively

EXTV_CC(Pin 30): External Power Input to an Internal

Switch. This switch closes and supplies INTV_CC,bypass-

ing the internallow dropout regulator whenever EXTV_CCis

higher than 4.7V. See EXTV_CCConnection in the Applica-

tions Information section. Do not exceed 7V on this pin

Divided According to the VID Programming Code.

ATTENIN (Pin 16): The Input to the VID Controlled Resis-

tive Divider.

VID25mV–VID3 (Pins 17,18, 19, 20, 21): VID Control

Logic Input Pins.

and ensure V_EXTVCC≤ V_INTVCC

.

V_IN(Pin32):MainSupplyPin.Shouldbecloselydecoupled

to the IC’s signal ground pin.

V

_BIAS(Pin 22): Supply Pin for the VID Control Circuit.

PGOOD (Pin 23): Open-Drain Logic Output. PGOOD is

NC (Pin 36): Do Not Connect.

170985f

8

LTC1709-85

U

U W

FU CTIO AL DIAGRA

PLLIN

PHASE DET

f

IN

50k

PLLFLTR

R

LP

C

LP

CLK1

OSCILLATOR

CLK2

TO SECOND

CHANNEL

INTV

CC

V

IN

D

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

B

BOOST

TG

C

B

DROP

OUT

DET

+

TOP

BOT

C

IN

PGOOD

D1

–

+

0.86V

BOT FCB

TOP ON

SW

S

Q

EAIN

–

+

SWITCH

LOGIC

INTV

CC

R

0.74V

BG

–

B

C

OUT

+

–

V

OS

PGND

0.55V

V

OUT

A1

–

+

SHDN

–

R

SENSE

+

V

OS

INTV

CC

I

2

1

–

+

–

+

DIFFOUT

+

SENSE

30k

0.86V

4(V

)

–

FB

3V

–

+

4.5V

0.18µA

FCB

SLOPE

COMP

45k

2.4V

+

–

FCB

EAIN

V

FB

V

0.80V

REF

V

IN

–

+

EA

V

IN

0.80V

0.86V

+

–

4.8V

OV

5V

LDO

REG

+

–

EXTV

CC

C

I

TH

1.2µA

INTV

CC

5V

+

SHDN

RST

RUN

SOFT

START

C

R

C

C2

6V

4(V

)

FB

INTERNAL

SUPPLY

SGND

RUN/SS

C

SS

ATTENIN

10k

5-BIT VID DECODER

ATTENOUT

TYPICAL ALL

VID PINS

40k

R1

VID25mV VID0 VID1 VID2 VID3

V

BIAS

170985 FBD

170985f

9

LTC1709-85

U

(Refer to Functional Diagram)

OPERATIO

Main Control Loop

tion. In this mode, the top and bottom MOSFETs are

alternately turned on to maintain the output voltage

independent of direction of inductor current. When the

FCBpinisbelowV_INTVCC– 2Vbutgreaterthan0.80V, the

controller enters Burst Mode operation. Burst Mode

operation sets a minimum output current level before

inhibiting the top switch and turns off the synchronous

MOSFET(s) when the inductor current goes negative.

This combination of requirements will, at low currents,

force the I_THpin below a voltage threshold that will

temporarily inhibit turn-on of both output MOSFETs until

the output voltage drops. There is 60mV of hysteresis in

the burst comparator B tied to the I_THpin. This hysteresis

produces output signals to the MOSFETs that turn them

on for several cycles, followed by a variable “sleep”

interval depending upon the load current. The resultant

output voltage ripple is held to a very small value by

having the hysteretic comparator after the error amplifier

gain block.

TheLTC1709-85usesaconstantfrequency,currentmode

step-down architecture with the two output stages oper-

ating 180 degrees out of phase. During normal operation,

each top MOSFET is turned on when the clock for that

channel sets the RS latch, and turned off when the main

current comparator, I₁, resets the RS latch. The peak

inductor current at which I₁resets the RS latch is con-

trolled by the voltage on the I_THpin, which is the output of

error amplifier EA. The EAIN pin receives the voltage

feedback signal, which is compared to the internal refer-

ence voltage by the EA. When the load current increases,

it causes a slight decrease in V_EAINrelative to the 0.8V

reference, which in turn causes the I_THvoltage to increase

until the average inductor current matches the new load

current. After the top MOSFET has turned off, the bottom

MOSFET is turned on until either the inductor current

starts to reverse, as indicated by current comparator I₂, or

the beginning of the next cycle.

The top MOSFET drivers are biased from floating boot-

strap capacitor C_B, which normally is recharged during

each off cycle through an external diode when the top

MOSFET turns off. As V_INdecreases to a voltage close to

V_OUT, the loop may enter dropout and attempt to turn on

the top MOSFET continuously. The dropout detector de-

tects this and forces the top MOSFET off for about 500ns

every tenth cycle to allow C_Bto recharge.

Constant Frequency Operation

When the FCB pin is tied to INTV_CC, Burst Mode operation

is disabled and a forced minimum peak output current

requirementisremoved.Thisprovidesconstantfrequency,

discontinuous (preventing reverse inductor current) cur-

rent operation over the widest possible output current

range.Thisconstantfrequencyoperationisnotasefficient

as Burst Mode operation, but does provide a lower noise,

constant frequency operating mode down to approxi-

mately 1% of designed maximum output current.

The main control loop is shut down by pulling the RUN/

SS pin low. Releasing RUN/SS allows an internal 1.2µA

current source to charge soft-start capacitor C_SS. When

C_SSreaches 1.5V, the main control loop is enabled with

the I_THvoltage clamped at approximately 30% of its

maximum value. As C_SScontinues to charge, the I_THpin

voltageisgraduallyreleasedallowingnormal,full-current

operation.

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous current

operation. This is the least efficient operating mode, but

may be desirable in certain applications. The output can

source or sink current in this mode. When sinking current

while in forced continuous operation, current will be

forced back into the main power supply potentially boost-

ing the input supply to dangerous voltage levels—

BEWARE!

Low Current Operation

The FCB pin selects between two modes of low current

operation. When the FCB pin voltage is below 0.80V, the

controller forces continuous PWM current mode opera-

170985f

10

LTC1709-85

U

(Refer to Functional Diagram)

OPERATIO

Frequency Synchronization

Output Overvoltage Protection

The phase-locked loop allows the internal oscillator to be

synchronized to an external source via the PLLIN pin. The

output of the phase detector at the PLLFLTR pin is also the

DC frequency control input of the oscillator that operates

over a 140kHz to 310kHz range corresponding to a DC

voltageinputfrom0Vto2.4V.Whenlocked,thePLLaligns

the turn on of the top MOSFET to the rising edge of the

synchronizingsignal.WhenPLLINisleftopen,thePLLFLTR

pingoeslow,forcingtheoscillatortominimumfrequency.

An overvoltage comparator, OV, guards against transient

overshoots (>7.5%) as well as other more serious condi-

tions that may overvoltage the output. In this case, the top

MOSFETisturnedoffandthebottomMOSFETisturnedon

until the overvoltage condition is cleared.

Power Good (PGOOD)

The PGOOD pin is connected to the drain of an internal

MOSFET. The MOSFET turns on when the output voltage

is not within ±7.5% of its nominal output level as deter-

mined by the feedback divider. When the output is within

±7.5% of its nominal value, the MOSFET is turned off

within 10µs and the PGOOD pin should be pulled up by an

external resistor to a source of up to 7V.

InputcapacitanceESRrequirementsandefficiencylosses

are substantially reduced because the peak current drawn

from the input capacitor is effectively divided by two and

power loss is proportional to the RMS current squared. A

two stage, single output voltage implementation can

reduce input path power loss by 75% and radically reduce

the required RMS current rating of the input capacitor(s).

Short-Circuit Detection

The RUN/SS capacitor is used initially to limit the inrush

current from the input power source. Once the control-

lershavebeengiventime, asdeterminedbythecapacitor

on the RUN/SS pin, to charge up the output capacitors

and provide full-load current, the RUN/SS capacitor is

then used as a short-circuit timeout circuit. If the output

voltage falls to less than 70% of its nominal output

voltage the RUN/SS capacitor begins discharging as-

suming that the output is in a severe overcurrent and/or

short-circuit condition. If the condition lasts for a long

enough period as determined by the size of the RUN/SS

capacitor, the controller will be shut down until the

RUN/SS pin voltage is recycled. This built-in latchoff can

be overidden by providing a current >5µA at a compli-

ance of 5V to the RUN/SS pin. This current shortens the

soft-start period but also prevents net discharge of the

RUN/SS capacitor during a severe overcurrent and/or

short-circuit condition. Foldback current limiting is acti-

vated when the output voltage falls below 70% of its

nominal level whether or not the short-circuit latchoff

circuit is enabled.

INTV_CC/EXTV_CCPower

Power for the top and bottom MOSFET drivers and most

of the IC circuitry is derived from INTV_CC. When the

EXTV_CCpin is left open, an internal 5V low dropout

regulator supplies INTV_CCpower. If the EXTV_CCpin is

taken above 4.7V, the 5V regulator is turned off and an

internalswitchisturnedonconnectingEXTV_CCtoINTV_CC.

This allows the INTV_CCpower to be derived from a high

efficiency external source such as the output of the regu-

lator itself or a secondary winding, as described in the

Applications Information section. An external Schottky

diode can be used to minimize the voltage drop from

EXTV_CCto INTV_CCin applications requiring greater than

the specified INTV_CCcurrent. Voltages up to 7V can be

applied to EXTV_CCfor additional gate drive capability.

Differential Amplifier

This amplifier provides true differential output voltage

sensing. Sensing both V_OUT⁺and V_OUT^–benefits regula-

tion in high current applications and/or applications

having electrical interconnection losses. The amplifier is

not capable of sinking current and therefore must be

resistively loaded to do so.

170985f

11

LTC1709-85

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APPLICATIO S I FOR ATIO

The basic LTC1709-85 application circuit is shown in

Figure 1 on the first page. External component selection

begins with the selection of the inductor(s) based on

ripple current requirements and continues with the

R_{SENSE1, 2}resistor selection using the calculated peak

inductor current and/or maximum current limit. Next, the

power MOSFETs and D1 and D2 are selected. The oper-

atingfrequencyandtheinductorarechosenbasedmainly

on the amount of ripple current. Finally, C_INis selected for

its ability to handle the input ripple current (that

PolyPhase^TMoperation minimizes) and C_OUTis chosen

with low enough ESR to meet the output ripple voltage

and load step specifications (also minimized with

PolyPhase). Currentmodearchitectureprovidesinherent

currentsharingbetweenoutputstages. Thecircuitshown

in Figure 1 can be configured for operation up to an input

voltageof28V(limitedbytheexternalMOSFETs).Current

mode control allows the ability to connect the two output

stages to two different input power supply rails. A heavy

output load can take some power from each input supply

according to the selection of the R_SENSEresistors.

A graph for the voltage applied to the PLLFLTR pin vs

frequency is given in Figure 2. As the operating frequency

isincreasedthegatechargelosseswillbehigher,reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 310kHz.

2.5

2.0

1.5

1.0

0.5

0

120

170

220

270

320

OPERATING FREQUENCY (kHz)

170985 F02

Figure 2. Operating Frequency vs V_PLLFLTR

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because

MOSFET gate charge and transition losses increase di-

rectly with frequency. In addition to this basic tradeoff, the

effect of inductor value on ripple current and low current

operation must also be considered. The PolyPhase ap-

proach reduces both input and output ripple currents

while optimizing individual output stages to run at a lower

fundamental frequency, enhancing efficiency.

R_SENSESelection For Output Current

R_{SENSE1, 2}are chosen based on the required peak output

current. The LTC1709-85 current comparator has a maxi-

mum threshold of 75mV/R_SENSEand an input common

mode range of SGND to 1.1(INTV_CC). The current com-

parator threshold sets the peak inductor current, yielding

a maximum average output current I_MAXequal to the peak

value less half the peak-to-peak ripple current, ∆I_L.

Assuming a common input power source for each output

stage and allowing a margin for variations in the

LTC1709-85 and external component values yields:

R_SENSE= 2(50mV/I_MAX

)

The inductor value has a direct effect on ripple current.

The inductor ripple current ∆I_Lper individual section, N,

decreases with higher inductance or frequency and

Operating Frequency

increases with higher V_INor V_OUT

:

The LTC1709-85 uses a constant frequency, phase-

lockable architecture with the frequency determined by

an internal capacitor. This capacitor is charged by a fixed

current plus an additional current which is proportional

tothevoltageappliedtothePLLFLTRpin.RefertoPhase-

Locked Loop and Frequency Synchronization for addi-

tional information.

V_OUT

fL

V_OUT

V

IN

∆I_L=

1−

where f is the individual output stage operating frequency.

PolyPhase is a registered trademark of Linear Technology Corporation.

170985f

12

LTC1709-85

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APPLICATIO S I FOR ATIO

In a 2-phase converter, the net ripple current seen by the

output capacitor is much smaller than the individual

inductor ripple currents due to ripple cancellation. The

details on how to calculate the net output ripple current

can be found in Application Note 77.

ferrite, molypermalloy, or Kool Mµ^®cores. Actual core

loss is independent of core size for a fixed inductor value,

but it is very dependent on inductance selected. As induc-

tance increases, core losses go down. Unfortunately,

increased inductance requires more turns of wire and

therefore copper losses will increase.

Figure 3 shows the net ripple current seen by the output

capacitors for the 1- and 2-phase configurations. The

outputripplecurrentisplottedforafixedoutputvoltageas

the duty factor is varied between 10% and 90% on the

x-axis. The output ripple current is normalized against the

inductor ripple current at zero duty factor. The graph can

be used in place of tedious calculations, simplifying the

design process.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Accepting larger values of ∆I_Lallows the use of low

inductances, butcanresultinhigheroutputvoltageripple.

A reasonable starting point for setting ripple current is

∆I_L= 0.4(I_OUT)/2, where I_OUTis the total load current.

Remember, the maximum ∆I_Loccurs at the maximum

input voltage. The individual inductor ripple currents are

determined by the inductor, input and output voltages.

Molypermalloy (from Magnetics, Inc.) is a very good, low

loss core material for toroids, but it is more expensive

than ferrite. A reasonable compromise from the same

manufacturer is Kool Mµ. Toroids are very space effi-

cient, especially when you can use several layers of wire.

Because they lack a bobbin, mounting is more difficult.

However, designs for surface mount are available which

do not increase the height significantly.

1.0

1-PHASE

2-PHASE

0.9

0.8

Power MOSFET, D1 and D2 Selection

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Two external power MOSFETs must be selected for each

outputstagewiththeLTC1709-85:oneN-channelMOSFET

for the top (main) switch, and one N-channel MOSFET for

the bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTV_CC

voltage. This voltage is typically 5V during start-up

(see EXTV_CCPin Connection). Consequently, logic-level

threshold MOSFETs must be used in most applications.

The only exception is if low input voltage is expected

(V_IN< 5V); then, sublogic-level threshold MOSFETs

(V_GS(TH)< 1V) should be used. Pay close attention to the

BV_DSSspecification for the MOSFETs as well; most of the

logic-level MOSFETs are limited to 30V or less.

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

170985 F03

Figure 3. Normalized Output Ripple Current

vs Duty Factor [I_RMS≈ 0.3 (∆I_O(P–P))]

Inductor Core Selection

Once the values for L1 and L2 are known, the type of

inductor must be selected. High efficiency converters

generally cannot afford the core loss found in low cost

powdered iron cores, forcing the use of more expensive

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

resistance R_DS(ON), reverse transfer capacitance C_RSS

,

input voltage and maximum output current. When the

LTC1709-85 is operating in continuous mode the duty

Kool Mµ is a registered trademark of Magnetics, Inc.

170985f

13

LTC1709-85

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APPLICATIO S I FOR ATIO

factors for the top and bottom MOSFETs of each output

stage are given by:

conduct during the dead-time between the conduction of

the two large power MOSFETs. This helps prevent the

body diode of the bottom MOSFET from turning on,

storing charge during the dead-time, and requiring a

reverse recovery period which would reduce efficiency. A

1A to 3A Schottky (depending on output current) diode is

generally a good compromise for both regions of opera-

tion due to the relatively small average current. Larger

diodes result in additional transition losses due to their

larger junction capacitance.

V_OUT

V

IN

Main SwitchDuty Cycle =

V – V_OUT

IN

Synchronous SwitchDuty Cycle =

V

IN

The MOSFET power dissipations at maximum output

current are given by:

C_INand C_OUTSelection

2

In continuous mode, the source current of each top

V_OUTI_MAX

P_MAIN

=

1+ δ R

+

(

)

DS(ON)

N-channel MOSFET is a square wave of duty cycle V_OUT

/

V

2

I_MAX

2

IN

V_IN. A low ESR input capacitor sized for the maximum

RMS current must be used. The details of a closed form

equation can be found in Application Note 77. Figure 4

shows the input capacitor ripple current for a 2-phase

configuration with the output voltage fixed and input

voltage varied. The input ripple current is normalized

against the DC output current. The graph can be used in

place of tedious calculations. The minimum input ripple

currentcanbeachievedwhentheinputvoltageistwicethe

output voltage

2

k V

C

f

(

)

(

_RSS)( )

IN

2

V – V_OUTI_MAX

IN

P

SYNC

=

1+ δ R

DS(ON)

(

)

V

IN

2

where δ is the temperature dependency of R_DS(ON)and k

is a constant inversely related to the gate drive current.

Both MOSFETs have I²R losses but the topside N-channel

equation includes an additional term for transition losses,

which peak at the highest input voltage. For V_IN< 20V the

high current efficiency generally improves with larger

MOSFETs, while for V_IN> 20V the transition losses rapidly

increasetothepointthattheuseofahigherR_DS(ON)device

with lower C_RSSactual provides higher efficiency. The

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during a

short-circuit when the synchronous switch is on close to

100% of the period.

In the graph of Figure 4, the 2-phase local maximum input

RMS capacitor currents are reached when:

V_OUT2k − 1

=

V

IN

4

where k = 1, 2

These worst-case conditions are commonly used for

design because even significant deviations do not offer

much relief. Note that capacitor manufacturer’s ripple

currentratingsareoftenbasedononly2000hoursoflife.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to

meet size or height requirements in the design. Always

consult the capacitor manufacturer if there is any

question.

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized R_DS(ON)vs temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs. C_RSSis usually specified in the

MOSFET characteristics. The constant k = 1.7 can be

used to estimate the contributions of the two terms in the

main switch dissipation equation.

It is important to note that the efficiency loss is propor-

The Schottky diodes, D1 and D2 shown in Figure 1

170985f

14

LTC1709-85

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APPLICATIO S I FOR ATIO

0.6

surface mount packages makes very physically small

implementations possible. The ability to externally com-

pensate the switching regulator loop using the I_TH

pin(OPTI-LOOP compensation) allows a much wider se-

lection of output capacitor types. OPTI-LOOP compensa-

tion effectively removes constraints on output capacitor

ESR. The impedance characteristics of each capacitor

type are significantly different than an ideal capacitor and

therefore require accurate modeling or bench evaluation

during design.

0.5

0.4

1-PHASE

2-PHASE

0.3

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

Manufacturers such as Nichicon, United Chemicon and

Sanyo should be considered for high performance

through-hole capacitors. The OS-CON semiconductor

dielectriccapacitoravailablefromSanyoandthePanasonic

SP surface mount types have the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON type capacitors is recommended to reduce

the inductance effects.

170985 F04

Figure 4. Normalized RMS Input Ripple Current

vs Duty Factor for 1 and 2 Output Stages

tional to the input RMS current squared and therefore a

2-phase implementation results in 75% less power loss

when compared to a single phase design. Battery/input

protection fuse resistance (if used), PC board trace and

connector resistance losses are also reduced by the

reduction of the input ripple current in a 2-phase system.

The required amount of input capacitance is further

reduced by the factor, 2, due to the effective increase in

the frequency of the current pulses.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum elec-

trolytic and dry tantalum capacitors are both available in

surface mount configurations. New special polymer sur-

face mount capacitors offer very low ESR also but have

muchlowercapacitivedensityperunitvolume. Inthecase

oftantalum,itiscriticalthatthecapacitorsaresurgetested

for use in switching power supplies. Several excellent

choices are the AVX TPS, AVX TPSV or the KEMET T510

seriesofsurfacemounttantalums,availableincaseheights

ranging from 2mm to 4mm. Other capacitor types include

Sanyo OS-CON, Nichicon PL series and Sprague 595D

series. Consultthemanufacturerforotherspecificrecom-

mendations. A combination of capacitors will often result

in maximizing performance and minimizing overall cost

and size.

The selection of C_OUTis driven by the required effective

series resistance (ESR). Typically once the ESR require-

ment has been met, the RMS current rating generally far

exceeds the I_RIPPLE(P-P)requirements. The steady state

output ripple (∆V_OUT) is determined by:

1

∆V_OUT≈ ∆I_RIPPLEESR +

16fC_OUT

Where f = operating frequency of each stage, C_OUT

output capacitance and ∆I_RIPPLE= combined inductor

=

ripple currents.

The output ripple varies with input voltage since ∆I_Lis a

functionofinputvoltage.Theoutputripplewillbelessthan

50mV at max V_INwith ∆I_L= 0.4I_OUT(MAX)/2 assuming:

INTV_CCRegulator

An internal P-channel low dropout regulator produces 5V

at the INTV_CCpin from the V_INsupply pin. The INTV_CC

regulator powers the drivers and internal circuitry of the

LTC1709-85. The INTV_CCpin regulator can supply up to

50mA peak and must be bypassed to power ground with

C_OUTrequired ESR < 4(R_SENSE) and

C_OUT> 1/(16f)(R_SENSE

)

The emergence of very low ESR capacitors in small,

170985f

15

LTC1709-85

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APPLICATIO S I FOR ATIO

a minimum of 4.7µF tantalum or electrolytic capacitor. An

additional 1µF ceramic capacitor placed very close to the

IC is recommended due to the extremely high instanta-

neous currents required by the MOSFET gate drivers.

separate 5V supply during normal operation (4.7V <

_EXTVCC< 7V) and from the internal regulator when the

V

external 5V supply is not available. Do not apply greater

than 7V to the EXTV_CCpin and ensure that EXTV_CC< V_IN+

0.3V when using the application circuits shown. If an

external voltage source is applied to the EXTV_CCpin when

the V_INsupply is not present, a diode can be placed in

series with the LTC1709-85’s V_INpin and a Schottky diode

between the EXTV_CCand the V_INpin, to prevent current

from backfeeding V_IN.

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC1709-85 to

be exceeded. The supply current is dominated by the gate

charge supply current, in addition to the current drawn

from the differential amplifier output. The gate charge is

dependent on operating frequency as discussed in the

Efficiency Considerations section. The supply current can

either be supplied by the internal 5V regulator or via the

EXTV_CCpin. When the voltage applied to the EXTV_CCpin

is less than 4.7V, all of the INTV_CCload current is supplied

by the internal 5V linear regulator. Power dissipation for

the IC is higher in this case by (I_IN)(V_IN– INTV_CC) and

efficiency is lowered. The junction temperature can be

estimated by using the equations given in Note 1 of the

Electrical Characteristics. For example, the LTC1709-85

V_INcurrentislimitedtolessthan24mAfroma24Vsupply:

Topside MOSFET Driver Supply (C_B,D_B) (Refer to

Functional Diagram)

External bootstrap capacitors C_B1and C_B2connected to

the BOOST1 and BOOST2 pins supply the gate drive

voltages for the topside MOSFETs. Capacitor C_Bin the

Functional Diagram is charged though diode D_Bfrom

INTV_CCwhentheSWpinislow.WhenthetopsideMOSFET

turns on, the driver places the C_Bvoltage across the gate-

sourceofthedesiredMOSFET.ThisenhancestheMOSFET

and turns on the topside switch. The switch node voltage,

SW, rises to V_INand the BOOST pin rises to V_IN+ V_INTVCC

.

T_J= 70°C + (24mA)(24V)(85°C/W) = 119°C

The value of the boost capacitor C_Bneeds to be 30 to 100

times that of the total input capacitance of the topside

MOSFET(s). ThereversebreakdownofD_Bmustbegreater

than V_IN(MAX).

Use of the EXTV_CCpin reduces the junction temperature

to:

T_J= 70°C + (24mA)(5V)(85°C/W) = 80.2°C

The final arbiter when defining the best gate drive ampli-

tude level will be the input supply current. If a change is

made that decreases input current, the efficiency has

improved. If the input current does not change then the

efficiency has not changed either.

The input supply current should be measured while the

controller is operating in continuous mode at maximum

V_INand the power dissipation calculated in order to

prevent the maximum junction temperature from being

exceeded.

Output Voltage

EXTV_CCConnection

TheLTC1709-85hasatrueremotevoltagesensecapablity.

Thesensingconnectionsshouldbereturnedfromtheload

back to the differential amplifier’s inputs through a com-

mon, tightly coupled pair of PC traces. The differential

amplifier corrects for DC drops in both the power and

ground paths. The differential amplifier output signal is

divided down and compared with the internal precision

0.8V voltage reference by the error amplifier.

The LTC1709-85 contains an internal P-channel MOSFET

switch connected between the EXTV_CCand INTV_CCpins.

When the voltage applied to EXTV_CCrises above 4.7V, the

internal regulator is turned off and an internal switch

closes, connecting the EXTV_CCpin to the INTV_CCpin

therebysupplyinginternalandMOSFETgatedrivingpower

to the IC. The switch remains closed as long as the voltage

applied to EXTV_CCremains above 4.5V. This allows the

MOSFET driver and control power to be derived from a

170985f

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Output Voltage Programming

taking an additional 1.4s/µF to reach full current. The

outputcurrentthusrampsupslowly,reducingthestarting

surge current required from the input power supply. If

RUN/SS has been pulled all the way to ground there is a

delay before starting of approximately:

The output voltage is digitally programmed as defined in

Table 1 using the VID25mV to VID3 logic input pins. The

VID logic inputs program a precision, 0.25% internal

feedback resistive divider. The LTC1709-85 has an output

voltage range of 1.05V to 1.825V in 25mV steps.

1.5V

1.2µA

t_DELAY

=

C_SS= 1.25s/µF C

SS

(

)

Between the ATTENOUT pin and ground is a variable

resistor,R1,whosevalueiscontrolledbythefiveVIDinput

pins (VID25mV to VID3). Another resistor, R2, between

the ATTENIN and the ATTENOUT pins completes the

resistive divider. The output voltage is thus set by the ratio

of (R1 + R2) to R1.

Table 1. VID Output Voltage Programming

V

VID3

0

1

0

VID2

1

0

1

0

1

VID1

0

1

0

1

0

1

0

1

0

VID0

VID25mV

SENSE

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Each VID digital input is pulled up by a 40k resistor in

series with a diode from V_BIAS. Therefore, it must be

grounded to get a digital low input, and can be either

floatedorconnectedtoV_BIAStogetadigitalhighinput.The

series diode is used to prevent the digital inputs from

being damaged or clamped if they are driven higher than

V_BIAS. The digital inputs accept CMOS voltage levels.

V_BIASis the supply voltage for the VID section. It is

normally connected to INTV_CCbut can be driven from

other sources. If it is driven from another source, that

source must be in the range of 2.7V to 5.5V and must be

alive prior to enabling the LTC1709-85.

Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) Run/Shut-

down,2)soft-startand3)adefeatableshort-circuitlatchoff

timer. Soft-start reduces the input power sources’ surge

currents by gradually increasing the controller’s current

limit I_TH(MAX). The latchoff timer prevents very short,

extreme load transients from tripping the overcurrent

latch. A small pull-up current (>5µA) supplied to the RUN/

SS pin will prevent the overcurrent latch from operating.

The following explanation describes how the functions

operate.

An internal 1.2µA current source charges up the soft-start

capacitor, C_SS. When the voltage on RUN/SS reaches

1.5V, the controller is permitted to start operating. As the

voltage on RUN/SS increases from 1.5V to 3.0V, the

internal current limit is increased from 25mV/R_SENSEto

75mV/R_SENSE. The output current limit ramps up slowly,

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This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor, R_SS, to the RUN/SS pin as

showninFigure5. Thisresistanceshortensthesoft-start

period and prevents the discharge of the RUN/SS capaci-

tor during a severe overcurrent and/or short-circuit con-

dition. When deriving the 5µA current from V_INas in the

figure, current latchoff is always defeated. The diode

connecting this pull-up resistor to INTV_CC, as in Figure 5,

eliminates any extra supply current during shutdown

while eliminating the INTV_CCloading from preventing

controller start-up.

The time for the output current to ramp up is then:

3V − 1.5V

1.2µA

t

=

C_SS= 1.25s/µF C

SS

(

)

IRAMP

By pulling the RUN/SS pin below 0.8V the LTC1709-85 is

put into low current shutdown (I_Q< 40µA). The RUN/SS

pins can be driven directly from logic as shown in

Figure 5. Diode D1 in Figure 5 reduces the start delay but

allows C_SSto ramp up slowly providing the soft-start

function. The RUN/SS pin has an internal 6V zener clamp

(see Functional Diagram).

Why should you defeat current latchoff? During the

prototypingstageofadesign,theremaybeaproblemwith

noise pickup or poor layout causing the protection circuit

to latch off the controller. Defeating this feature allows

troubleshooting of the circuit and PC layout. The internal

short-circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure. A decision can be made after the design is com-

plete whether to rely solely on foldback current limiting or

to enable the latchoff feature by removing the pull-up

resistor.

V

INTV

IN

CC

R

3.3V OR 5V

RUN/SS

*

R

*

SS

D1

RUN/SS

D1*

C

SS

C

SS

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

170985 F06

Figure 5. RUN/SS Pin Interfacing

The value of the soft-start capacitor C_SSmay need to be

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin also provides the ability to latch off the

controllerswhenanovercurrentconditionisdetected.The

RUN/SS capacitor, C_SS, is used initially to limit the inrush

current of both controllers. After the controllers have been

started and been given adequate time to charge up the

output capacitors and provide full load current, the RUN/

SS capacitor is used for a short-circuit timer. If the output

C_SS> (C_OUT)(V_OUT)(10^-4)(R_SENSE

)

The minimum recommended soft-start capacitor of

C_SS= 0.1µF will be sufficient for most applications.

voltagefallstolessthan70%ofitsnominalvalueafterC_SSPhase-Locked Loop and Frequency Synchronization

reaches 4.1V, C_SSbegins discharging on the assumption

TheLTC1709-85hasaphase-lockedloopcomprisedofan

that the output is in an overcurrent condition. If the

internal voltage controlled oscillator and phase detector.

condition lasts for a long enough period as determined by

This allows the top MOSFET turn-on to be locked to the

thesizeoftheC_SS,thecontrollerwillbeshutdownuntilthe

rising edge of an external source. The frequency range of

RUN/SS pin voltage is recycled. If the overload occurs

during start-up, the time can be approximated by:

the voltage controlled oscillator is ±50% around the

center frequency f_O. A voltage applied to the PLLFLTR pin

of 1.2V corresponds to a frequency of approximately

220kHz. The nominal operating frequency range of the

LTC1709-85 is 140kHz to 310kHz.

t

_LO1≈ (C_SS• 0.6V)/(1.2µA) = 5 • 10⁵(C_SS)

Iftheoverloadoccursafterstart-up,thevoltageonC_SSwill

continue charging and will provide additional time before

latching off:

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the

170985f

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_LO2≈ (C_SS• 3V)/(1.2µA) = 2.5 • 10⁶(C_SS)

18

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external and internal oscillators. This type of phase detec-

tor will not lock up on input frequencies close to the

harmonics of the VCO center frequency. The PLL hold-in

range, ∆f_H, is equal to the capture range, ∆f_C:

Minimum On-Time Considerations

Minimum on-time, t_ON(MIN), is the smallest time duration

that the LTC1709-85 is capable of turning on the top

MOSFET. Itisdeterminedbyinternaltimingdelaysandthe

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

∆f_H= ∆f_C= ±0.5 f_O(150kHz-300kHz)

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter network on the PLLFLTR pin. A simplified block

diagram is shown in Figure 6.

V_OUT

V f

_IN( )

t_{ON MIN}

<

(

)

If the external frequency (f_PLLIN) is greater than the oscil-

lator frequency f_0SC, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency

is less than f_0SC, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-

quencies are the same but exhibit a phase difference, the

currentsourcesturnonforanamountoftimecorrespond-

ing to the phase difference. Thus the voltage on the

PLLFLTR pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

stable operating point the phase comparator output is

open and the filter capacitor C_LPholds the voltage. The

LTC1709-85 PLLIN pin must be driven from a low imped-

ance source such as a logic gate located close to the pin.

Ifthedutycyclefallsbelowwhatcanbeaccommodatedby

the minimum on-time, the LTC1709-85 will begin to skip

cycles resulting in variable frequency operation. The out-

put voltage will continue to be regulated, but the ripple

current and ripple voltage will increase.

The minimum on-time for the LTC1709-85 is generally

less than 200ns. However, as the peak sense voltage

decreases, the minimum on-time gradually increases.

This is of particular concern in forced continuous applica-

tions with low ripple current at light loads. If the duty cycle

drops below the minimum on-time limit in this situation,

a significant amount of cycle skipping can occur with

correspondingly larger ripple current and voltage ripple.

If an application can operate close to the minimum

on-time limit, an inductor must be chosen that has a low

enough inductance to provide sufficient ripple amplitude

to meet the minimum on-time requirement. As a general

rule, keep the inductor ripple current of each phase equal

The loop filter components (C_LP, R_LP) smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components C_LPand R_LPdetermine how fast the loop

acquires lock. Typically R_LP=10k and C_LPis 0.01µF to

0.1µF.

to or greater than 15% of I_OUT(MAX)at V_IN(MAX)

.

R

LP

2.4V

10k

C

PHASE

DETECTOR

LP

EXTERNAL

OSC

PLLFLTR

PLLIN

DIGITAL

OSC

PHASE/

FREQUENCY

DETECTOR

50k

170985 F07

Figure 6. Phase-Locked Loop Block Diagram

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FCB Pin Operation

Efficiency Considerations

The following table summarizes the possible states avail- The percent efficiency of a switching regulator is equal to

able on the FCB pin:

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

Table 2

FCB Pin

Condition

0V to 0.75V

Forced Continuous (Current Reversal

Allowed—Burst Inhibited)

0.85V < V < V

– 2V

Minimum Peak Current Induces

Burst Mode Operation

FCB

INTVCC

%Efficiency = 100% – (L1 + L2 + L3 + ...)

No Current Reversal Allowed

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

V

Burst Mode Operation Disabled

Constant Frequency Mode Enabled

No Current Reversal Allowed

INTVCC

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC1709-85 circuits: 1) I²R losses, 2) Topside

MOSFET transition losses, 3) INTV_CCregulator current

and 4) LTC1709-85 V_INcurrent (including loading on the

differential amplifier output).

No Minimum Peak Current

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak

outputvoltageexcursionunderworst-casetransientload-

ing conditions. The open-loop DC gain of the control loop

is reduced depending upon the maximum load step speci-

fications. Voltage positioning can easily be added to the

LTC1709-85 by loading the I_THpin with a resistive divider

having a Thevenin equivalent voltage source equal to the

midpoint operating voltage of the error amplifier, or 1.2V

(see Figure 7).

1) I²R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resistor,

and input and output capacitor ESR. In continuous mode

the average output current flows through L and R_SENSE

,

but is “chopped” between the topside MOSFET and the

synchronous MOSFET. If the two MOSFETs have approxi-

mately the same R_DS(ON), then the resistance of one

MOSFET can simply be summed with the resistances of L,

R_SENSEand ESR to obtain I²R losses. For example, if each

R_DS(ON)=10mΩ, R_L=10mΩ, andR_SENSE=5mΩ, thenthe

total resistance is 25mΩ. This results in losses ranging

from 2% to 8% as the output current increases from 3A to

15A per output stage for a 5V output, or a 3% to 12% loss

per output stage for a 3.3V output. Efficiency varies as the

inverse square of V_OUTfor the same external components

and output power level. The combined effects of increas-

ingly lower output voltages and higher currents required

by high performance digital systems is not doubling but

quadrupling the importance of loss terms in the switching

regulator system!

The resistive load reduces the DC loop gain while main-

taining the linear control range of the error amplifier. The

worst-case peak-to-peak output voltage deviation due to

transient loading can theoretically be reduced to half or

alternatively the amount of output capacitance can be

reduced for a particular application. A complete explana-

tion is included in Design Solutions 10 or the LTC1736

data sheet. (See www.linear.com)

INTV

CC

R

T2

I

TH

LTC1709-85

R

C

T1

2) Transition losses apply only to the topside MOSFET(s),

and are significant only when operating at high input

voltages (typically 12V or greater). Transition losses can

be estimated from:

C

170985 F08

2

Figure 7. Active Voltage Positioning Applied to the LTC1709-85

Transition Loss = (1.7) V_INI_O(MAX)C_RSS

f

170985f

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3) INTV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results from

switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high to

low again, a packet of charge dQ moves from INTV_CCto

ground. The resulting dQ/dt is a current out of INTV_CCthat

is typically much larger than the control circuit current. In

continuous mode, I_GATECHG= (Q_T+ Q_B), where Q_Tand Q_B

are the gate charges of the topside and bottom side

MOSFETs.

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in DC (resistive) load

current. When a load step occurs, V_OUTshifts by an

amount equal to ∆I_LOAD(ESR), where ESR is the effective

seriesresistanceofC_OUT(∆I_LOAD)alsobeginstochargeor

discharge C_OUTgenerating the feedback error signal that

forces the regulator to adapt to the current change and

return V_OUTto its steady-state value. During this recovery

time V_OUTcan be monitored for excessive overshoot or

ringing, which would indicate a stability problem. The

availability of the I_THpin not only allows optimization of

control loop behavior but also provides a DC coupled and

AC filtered closed loop response test point. The DC step,

rise time, and settling at this test point truly reflects the

closed loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining

the rise time at the pin. The I_THexternal components

shown in the Figure 1 circuit will provide an adequate

starting point for most applications.

SupplyingINTV_CCpowerthroughtheEXTV_CCswitchinput

from an output-derived source will scale the V_INcurrent

required for the driver and control circuits by the ratio

(Duty Factor)/(Efficiency). For example, in a 20V to 5V

application, 10mA of INTV_CCcurrent results in approxi-

mately 3mA of V_INcurrent. This reduces the mid-current

loss from 10% or more (if the driver was powered directly

from V_IN) to only a few percent.

4) The V_INcurrent has two components: the first is the

DC supply current given in the Electrical Characteristics

table, which excludes MOSFET driver and control cur-

rents; the second is the current drawn from the differential

amplifier output. V_INcurrent typically results in a small

(<0.1%) loss.

The I_THseries R_C-C_Cfilter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.2 to 5 times their suggested values) to optimize

transient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be decided

upon first because the various types and values determine

the loop gain and phase. An output current pulse of 20%

to 80% of full-load current having a rise time of <2µs will

produce output voltage and I_THpin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop. The initial output voltage step resulting

from the step change in output current may not be within

the bandwidth of the feedback loop, so this signal cannot

be used to determine phase margin. This is why it is

better to look at the I_THpin signal which is in the feedback

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10%efficiencydegradationinportablesystems.Itisvery

important to include these “system” level losses in the

design of a system. The internal battery and input fuse

resistance losses can be minimized by making sure that

C_INhas adequate charge storage and a very low ESR at

the switching frequency. A 50W supply will typically

require a minimum of 200µF to 300µF of output capaci-

tance having a maximum of 10mΩ to 20mΩ of ESR. The

LTC1709-85 2-phase architecture typically halves the

inputandoutputcapacitancerequirementsovercompet-

ing solutions. Other losses including Schottky conduc-

tion losses during dead-time and inductor core losses

generally account for less than 2% total additional loss.

170985f

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loop and is the filtered and compensated control loop

response. The gain of the loop will be increased by

increasing R_Cand the bandwidth of the loop will be

increased by decreasing C_C. If R_Cis increased by the

same factor that C_Cis decreased, the zero frequency will

be kept the same, thereby keeping the phase the same in

the most critical frequency range of the feedback loop.

The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

The power dissipation on the topside MOSFET can be

easily estimated. Using a Siliconix Si4420DY for example;

R_DS(ON)= 0.013Ω, C_RSS= 300pF. At maximum input

voltagewithT_J(estimated)=110°Catanelevatedambient

temperature:

1.8V

5.5V

P_MAIN

=

10 ²1+ 0.005 110°C − 25°C

( ) )(

(

)

]

[

2

0.013Ω + 1.7 5.5V 10A 300pF

(

) (

)(

)

300kHz = 0.65W

(

)

Design Example

The worst-case power disipated by the synchronous

MOSFET under normal operating conditions at elevated

ambient temperature and estimated 50°C junction tem-

perature rise is:

Asadesignexample,assumeV_IN=5V(nominal),V_IN= 5.5V

(max), V_OUT=1.8V, I_MAX=20A, T_A=70°Candf = 300kHz.

Theinductancevalueischosenfirstbasedona30%ripple

current assumption. The highest value of ripple current

occursatthemaximuminputvoltage. TiethePLLFLTRpin

to the INTV_CCpin for 300kHz operation. The minimum

inductance for 30% ripple current is:

5.5V − 1.8V

2

P

SYNC

=

10A 1.48 0.013Ω

(

) (

)(

)

5.5V

= 1.29W

Ashort-circuittogroundwillresultinafoldedbackcurrent

of about:

V_OUT

V

IN

L ≥

1−

f ∆L

(

)

200ns 5.5V

25mV

0.004Ω

1

2

(

)

1.8V

)( )(

1.8V

5.5V

I_SC

=

+

= 7A

≥

1−

1.5µH

300kHz 30% 10A

(

)

≥ 1.35µH

The worst-case power disipated by the synchronous

MOSFET under short-circuit conditions at elevated ambi-

ent temperature and estimated 50°C junction temperature

rise is:

A 1.5µH inductor will produce 27% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 11.5A. The minimum on-

time occurs at maximum V_IN:

5.5V − 1.8V

2

P

SYNC

=

7A 1.48 0.013Ω

( )

(

)(

)

5.5V

V_OUT

V f

IN

1.8V

= 630mW

t_{ON MIN}

=

= 1.1µs

(

)

5.5V 300kHz

(

)(

)

which is less than normal, full-load conditions. Inciden-

tally, since the load no longer dissipates power in the

shorted condition, total system power dissipation is de-

creased by over 99%.

The R_SENSEresistors value can be calculated by using the

maximum current sense voltage specification with some

accomodation for tolerances:

50mV

11.5A

R_SENSE

=

≈ 0.004Ω

170985f

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3)AretheSENSE^–andSENSE⁺leadsroutedtogetherwith

minimum PC trace spacing? The filter capacitors between

SENSE⁺and SENSE^–pin pairs should be as close as

possibletotheLTC1709-85.Ensureaccuratecurrentsens-

ing with Kelvin connections at the current sense resistor.

The duty factor for this application is:

V_O1.8V

DF =

=

= 0.36

V

IN

5V

Using Figure 4, the RMS ripple current will be:

I_INRMS= (20A)(0.23) = 4.6A_RMS

4) Does the (+) plate of C_INconnect to the drains of the

topside MOSFETs as closely as possible? This capacitor

provides the AC current to the MOSFETs. Keep the input

currentpathformedbytheinputcapacitor,topandbottom

MOSFETs, and the Schottky diode on the same side of the

PC board in a tight loop to minimize conducted and

radiated EMI.

An input capacitor(s) with a 4.6A_RMSripple current rating

is required.

The output capacitor ripple current is calculated by using

the inductor ripple already calculated for each inductor

and multiplying by the factor obtained from Figure 3

along with the calculated duty factor. The output ripple in

continuous mode will be highest at the maximum input

voltage since the duty factor is <50%. The maximum

output current ripple is:

5) Is the INTV_CC1µF ceramic decoupling capacitor con-

nectedcloselybetweenINTV_CCandthepowergroundpin?

This capacitor carries the MOSFET driver peak currents. A

small value is recommended to allow placement immedi-

ately adjacent to the IC.

V_OUT

fL

6) Keep the switching nodes, SW1 (SW2), away from

sensitive small-signal nodes. Ideally the switch nodes

should be placed at the furthest point from the

LTC1709-85.

∆I_COUT

=

0.3 at 33%D F

(

)

1.8V

∆I_COUTMAX

=

0.3

300kHz 1.5µH

)(

(

)

7)Usealowimpedancesourcesuchasalogicgatetodrive

the PLLIN pin and keep the lead as short as possible.

= 1.2A_RMS

V_OUTRIPPLE= 20mΩ 1.2A

= 24mV

RMS

(

)

RMS

The diagram in Figure 8 illustrates all branch currents in a

2-phase switching regulator. It becomes very clear after

studying the current waveforms why it is critical to keep

the high-switching-current paths to a small physical size.

High electric and magnetic fields will radiate from these

“loops” just as radio stations transmit signals. The output

capacitor ground should return to the negative terminal of

the input capacitor and not share a common ground path

with any switched current paths. The left half of the circuit

gives rise to the “noise” generated by a switching regula-

tor. The ground terminations of the sychronous MOSFETs

and Schottky diodes should return to the negative plate(s)

of the input capacitor(s) with a short isolated PC trace

since very high switched currents are present. A separate

isolated path from the negative plate(s) of the input

capacitor(s) should be used to tie in the IC power ground

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1709-85. Check the following in your layout:

1) Are the signal and power grounds segregated? The

LTC1709-85 signal ground pin should return to the (–)

plate of C_OUTseparately. The power ground returns to the

sources of the bottom N-channel MOSFETs, anodes of the

Schottky diodes, and (–) plates of C_IN, which should have

as short lead lengths as possible.

2) Does the LTC1709-85 V_OS⁺pin connect to the point of

load? Does the LTC1709-85 V_OS^–pin connect to the load

return?

170985f

23

LTC1709-85

APPLICATIO S I FOR ATIO

U

W

U U

pin (PGND) and the signal ground pin (SGND). This

technique keeps inherent signals generated by high cur-

rent pulses from taking alternate current paths that have

finite impedances during the total period of the switching

regulator.ExternalOPTI-LOOPcompensationallowsover-

compensation for PC layouts which are not optimized but

this is not the recommended design procedure.

The input current peaks drop in half and the frequency is

doubled for this 2-phase converter. The input capacity

requirement is thus reduced theoretically by a factor of

four! Ceramic input capacitors with their unbeatably low

ESR characteristics can be used.

Figure 4 illustrates the RMS input current drawn from the

input capacitance vs the duty cycle as determined by the

ratio of input and output voltage. The peak input RMS

currentlevelofthesinglephasesystemisreducedby50%

in a 2-phase solution due to the current splitting between

the two stages.

Simplified Visual Explanation of How a 2-Phase

Controller Reduces Both Input and Output RMS Ripple

Current

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output

capacitors.TheRMSinputripplecurrentisdividedby,and

the effective ripple frequency is multiplied up by the

number of phases used (assuming that the input voltage

isgreaterthanthenumberofphasesusedtimestheoutput

voltage). The output ripple amplitude is also reduced by,

and the effective ripple frequency is increased by the

numberofphasesused.Figure9graphicallyillustratesthe

principle.

An interesting result of the 2-phase solution is that the V_IN

which produces worst-case ripple current for the input

capacitor, V_OUT= V_IN/2, in the single phase design pro-

duces zero input current ripple in the 2-phase design.

The output ripple current is reduced significantly when

compared to the single phase solution using the same

inductance value because the V_OUT/L discharge current

term from the stage that has its bottom MOSFET on

subtractscurrentfromthe(V_IN–V_OUT)/Lchargingcurrent

resultingfromthestagewhichhasitstopMOSFETon. The

output ripple current is:

The worst-case RMS ripple current for a single stage

design peaks at an input voltage of twice the output

voltage.Theworst-caseRMSripplecurrentforatwostage

design results in peak outputs of 1/4 and 3/4 of input

voltage. When the RMS current is calculated, higher

effective duty factor results and the peak current levels are

divided as long as the currents in each stage are balanced.

Refer to Application Note 19 for a detailed description of

how to calculate RMS current for the single stage switch-

ing regulator. Figures 3 and 4 illustrate how the input and

output currents are reduced by using an additional phase.

1− 2D 1−D

1− 2D +1

2V_OUT

fL

(

)

∆I_RIPPLE

=

where D is duty factor.

The input and output ripple frequency is increased by the

number of stages used, reducing the output capacity

requirements.WhenV_INisapproximatelyequalto2(V_OUT

)

as illustrated in Figures 3 and 4, very low input and output

ripple currents result.

170985f

24

LTC1709-85

U

W U U

APPLICATIO S I FOR ATIO

SW1

L1

R

SENSE1

D1

V

OUT

IN

R

IN

C

OUT

+

C

IN

R

L

SW2

L2

R

SENSE2

D2

BOLD LINES INDICATE

HIGH, SWITCHING

CURRENT LINES.

KEEP LINES TO A

MINIMUM LENGTH.

170985 F09

Figure 8. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator

170985f

25

LTC1709-85

U

W

U U

APPLICATIO S I FOR ATIO

SINGLE PHASE

DUAL PHASE

SW1 V

SW2 V

SW V

I

CIN

I

L1

I

COUT

L2

I

CIN

I

COUT

RIPPLE

170985 F10

Figure 9. Single and 2-Phase Current Waveforms

170985f

26

LTC1709-85

U

PACKAGE DESCRIPTIO

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

12.50 – 13.10*

(.492 – .516)

1.25 ±0.12

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

7.8 – 8.2

5.3 – 5.7

7.40 – 8.20

(.291 – .323)

0.42 ±0.03

0.65 BSC

5

7

8

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18

5.00 – 5.60**

(.197 – .221)

2.0

(.079)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

(.0035 – .010)

0.55 – 0.95

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

(.002)

NOTE:

G36 SSOP 0802

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

170985f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LTC1709-85

U

TYPICAL APPLICATIO

LTC1709-85

RUN/SS

10Ω

1

2

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

NC

TG1

L1

+

0.1µF

SENSE1

1000pF

0.002Ω

M2

3

–

SENSE1

EAIN

SW1

2.7k

0.22µF

4

BOOST1

M1

10k

5

D1

INTV

PLLFLTR

PLLIN

FCB

V

CC

IN

MBRS140T3

6

26.8k

BG1

6.81k

7

10Ω

C

IN

INTV

EXTV

5V (OPT)

CC

6.98k

470pF

+

8

+

I

INTV

TH

CC

0.1µF

10µF

100pF

9

C

OUT

SGND

PGND

BG2

V

IN

10

11

12

13

14

15

16

17

18

5V TO 15V

V

DIFFOUT

D2

MBRS140T3

–

BOOST2

SW2

M3

M4

OS

0.22µF

+

OS

V

OUT

0.002Ω

–

+

SENSE2

TG2

1.05V TO 1.825V

30A MAX

1000pF

10Ω

100k

L2

PGOOD

SWITCHING FREQUENCY = 200kHz

10Ω

470pF

ATTENOUT

ATTENIN

VID25mV

VID0

V

BIAS

C

: 5A RIPPLE CURRENT RATING REQUIRED

OUT

IN

0.1µF

10Ω

: 5 × 270µF/2V PANASONIC SP

VID3

VID2

VID1

L1 TO L2: SUMIDA CEP125-1R0MC-H 1µH

M1, M3: IRF7811W OR Si7860DP

M2, M4: IRF7811W ×2 OR Si7856DP

PENTIUM IS A REGISTERED TRADEMARK OF

INTEL CORPORATION

VID INPUTS

170985 F11

Figure 10. 5V to 15V Input, 1.05V to 1.825V/30A Pentium^®III Processor Power Supply with Active Voltage Positioning

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are trademarks of Linear Technology Corporation.

SENSE

170985f

LT/TP 1202 2K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

LINEAR TECHNOLOGY CORPORATION 2001

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1709EG-85#TRPBF
厂家：	Linear
描述：	LTC1709-85 - 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件：	总28页 (文件大小：313K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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