LTC1603CG_技术文档

LTC1603

High Speed, 16-Bit, 250ksps

Sampling A/D Converter

with Shutdown

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FEATURES

DESCRIPTIO

The LTC^®1603 is a 250ksps, 16-bit sampling A/D con-

verter that draws only 220mW from ±5V supplies. This

high performance device includes a high dynamic range

sample-and-hold, a precision reference and a high speed

parallel output. Two digitally selectable power shutdown

modes provide power savings for low power systems.

■

A Complete, 250ksps 16-Bit ADC

■

90dB S/(N+D) and –100dB THD (Typ)

■

Power Dissipation: 220mW (Typ)

■

Nap (7mW) and Sleep (10µW) Shutdown Modes

■

No Pipeline Delay

No Missing Codes over Temperature

Operates with Internal 15ppm/°C Reference

or External Reference

The LTC1603’s full-scale input range is ±2.5V. Outstand-

ing AC performance includes 90dB S/(N+D) and –100dB

THD at a sample rate of 250ksps.

■

True Differential Inputs Reject Common Mode Noise

5MHz Full Power Bandwidth

Theuniquedifferentialinputsample-and-holdcanacquire

single-ended or differential input signals up to its 15MHz

bandwidth. The 68dB common mode rejection allows

users to eliminate ground loops and common mode noise

by measuring signals differentially from the source.

±2.5V Bipolar Input Range

Pin Compatible with LTC1604 and LTC1608

36-Pin SSOP Package

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APPLICATIO S

The ADC has µP compatible,16-bit parallel output port.

Thereisnopipelinedelayinconversionresults. Aseparate

convert start input and a data ready signal (BUSY) ease

connections to FlFOs, DSPs and microprocessors.

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Telecommunications

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

High Speed Data Acquisition

Spectrum Analysis

Imaging Systems

■

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TYPICAL APPLICATIO

5V 10µF

2.2µF

10µF

10Ω

+

3

36

10

35

9

V

AV

DD

DV

DD

DGND

REF

DD

SHDN

CS

33

32

31

30

27

CONTROL

LOGIC

µP

CONVST

RD

CONTROL

LINES

REFCOMP

7.5k

AND

4

2.5V

REF

1.75X

TIMING

+

4.375V

BUSY

47µF

OV

DD

29

28

5V OR

+

3V

10µF

+

OGND

1

2

A

IN

+

–

DIFFERENTIAL

ANALOG INPUT

±2.5V

16-BIT

SAMPLING

ADC

OUTPUT

BUFFERS

B15 TO B0

16-BIT

PARALLEL

BUS

–

A

IN

D15 TO D0

11 TO 26

1603 TA01

AGND AGND AGND AGND

V

SS

34

5

6

7

8

10µF

+

–5V

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LTC1603

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ABSOLUTE MAXIMUM RATINGS

AV_DD= DV_DD= OV_DD= V_DD(Notes 1, 2)

PACKAGE/ORDER INFORMATION

ORDER

PART NUMBER

TOP VIEW

+

Supply Voltage (V_DD)................................................ 6V

Negative Supply Voltage (V_SS) ............................... –6V

Total Supply Voltage (V_DDto V_SS) .......................... 12V

Analog Input Voltage

(Note 3) ......................... (V_SS– 0.3V) to (V_DD+ 0.3V)

V_REFVoltage (Note 4) ................. –0.3V to (V_DD+ 0.3V)

REFCOMP Voltage (Note 4) ......... –0.3V to (V_DD+ 0.3V)

Digital Input Voltage (Note 4) ....................–0.3V to 10V

Digital Output Voltage.................. –0.3V to (V_DD+ 0.3V)

Power Dissipation............................................. 500mW

Operating Temperature Range

A

1

2

3

4

5

6

7

8

9

36 AV

35 AV

IN

DD

–

DD

V

34

V

SS

REF

LTC1603CG

LTC1603IG

REFCOMP

AGND

33 SHDN

32 CS

AGND

31 CONV

30 RD

AGND

29 OV

DD

DV

DD

28 OGND

27 BUSY

26 D0

25 D1

24 D2

23 D3

22

DGND 10

D15 (MSB) 11

D14 12

D13 13

D12 14

D11

15

D4

D10 16

D9 17

21 D5

20 D6

19 D7

LTC1603C .............................................. 0°C to 70°C

LTC1603I............................................ –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

D8 18

G PACKAGE

36-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 95°C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

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The ● denotes the specifications which apply over the full operating

CO VERTER

CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. With Internal Reference (Notes 5, 6)

PARAMETER

CONDITIONS

MIN

TYP

16

MAX

UNITS

Bits

Resolution (No Missing Codes)

Integral Linearity Error

Transition Noise

Offset Error

●

16

(Note 7)

(Note 8)

(Note 9)

±1

±3

LSB

0.7

LSB

●

±0.05 ±0.125

%

Offset Tempco

0.5

ppm/°C

Full-Scale Error

Internal Reference

External Reference

±0.125 ±0.25

±0.25

%

Full-Scale Tempco

I

(Reference) = 0, Internal Reference

OUT

±15

ppm/°C

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The ● denotes the specifications which apply over the full operating temperature range, otherwise

A ALOG I PUT

specifications are at T_A= 25°C.

SYMBOL PARAMETER

CONDITIONS

4.75 ≤ V ≤ 5.25V, –5.25 ≤ V ≤ –4.75V,

MIN

TYP

MAX

UNITS

V

IN

Analog Input Range (Note 2)

±2.5

V

DD

SS

–

+

V

≤ (A , A ) ≤ AV

IN IN DD

SS

I

Analog Input Leakage Current

Analog Input Capacitance

CS = High

●

±1

µA

IN

C

Between Conversions

During Conversions

43

5

pF

IN

t

Sample-and-Hold Acquisition Time

380

–1.5

5

ns

ACQ

AP

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Time Jitter

Analog Input Common Mode Rejection Ratio

ps

jitter

RMS

–

+

CMRR

–2.5V < (A = A ) < 2.5V

68

dB

IN

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LTC1603

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The ● denotes the specifications which apply over the full operating temperature range,

DY A IC ACCURACY

otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

S/N

Signal-to-Noise Ratio

5kHz Input Signal

100kHz Input Signal

●

87

90

dB

S/(N + D) Signal-to-(Noise + Distortion) Ratio

5kHz Input Signal

100kHz Input Signal (Note 10)

90

89

dB

●

84

THD

Total Harmonic Distortion

Up to 5th Harmonic

5kHz Input Signal

100kHz Input Signal

–100

–94

dB

–88

SFDR

IMD

Spurious Free Dynamic Range

Intermodulation Distortion

100kHz Input Signal

96

–88

5

dB

f

= 29.37kHz, f = 32.446kHz

IN2

IN1

Full Power Bandwidth

MHz

kHz

Full Linear Bandwidth (S/(N + D) ≥ 84dB

350

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I TER AL REFERE CE CHARACTERISTICS

(Note 5)

PARAMETER

CONDITIONS

MIN

2.475

TYP

MAX

2.515

UNITS

V

Output Voltage

Output Tempco

Line Regulation

I

= 0

2.500

REF

OUT

±15

ppm/°C

4.75 ≤ V ≤ 5.25V

–5.25V ≤ V ≤ –4.75V

0.01

LSB/V

DD

SS

V

Output Resistance

0 ≤

I

≤ 1mA

OUT

7.5

kΩ

REF

REFCOMP Output Voltage

I

= 0

4.375

V

OUT

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The ● denotes the specifications which apply over the

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

Digital Input Capacitance

High Level Output Voltage

V

= 5.25V

= 4.75V

= 0V to V

●

2.4

V

IH

IL

DD

IN

0.8

I

±10

µA

pF

IN

DD

C

V

5

IN

V

= 4.75V, I

= –10µA

= –400µA

4.5

V

OH

DD

OUT

●

4.0

V

Low Level Output Voltage

V

= 4.75V, I

= 160µA

= 1.6mA

0.05

0.10

V

OL

DD

OUT

●

0.4

±10

15

I

Hi-Z Output Leakage D15 to D0

Hi-Z Output Capacitance D15 to D0

Output Source Current

V

= 0V to V , CS High

µA

pF

OZ

OUT

DD

C

CS High (Note 11)

OZ

I

V

= 0V

–10

10

mA

SOURCE

SINK

OUT

Output Sink Current

= V

DD

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POWER REQUIRE E TS ^The● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

(Notes 12, 13)

(Note 12)

MIN

4.75

TYP

MAX

5.25

UNITS

V

Positive Supply Voltage

Negative Supply Voltage

V

DD

SS

–4.75

–5.25

I

Positive Supply Current

Nap Mode

CS = RD = 0V

●

18

1.5

1

30

2.4

100

mA

µA

DD

CS = 0V, SHDN = 0V

CS = 5V, SHDN = 0V

Sleep Mode

I

Negative Supply Current

Nap Mode

CS = RD = 0V

26

1

40

100

mA

µA

SS

CS = 0V, SHDN = 0V

CS = 5V, SHDN = 0V

Sleep Mode

P

Power Dissipation

Nap Mode

CS = RD = 0V

220

7.5

0.01

350

12

1

mW

D

CS = 0V, SHDN = 0V

CS = 5V, SHDN = 0V

Sleep Mode

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TI I G CHARACTERISTICS ^The● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

250

2.2

TYP

MAX

UNITS

kHz

µs

f

t

Maximum Sampling Frequency

Conversion Time

●

SMPL(MAX)

3.3

3.8

480

4

CONV

Acquisition Time

(Note 11)

ns

ACQ

Throughput Time (Acquisition + Conversion)

CS to RD Setup Time

µs

ACQ+CONV

(Notes 11, 12)

CS = Low (Note 12)

(Note 12)

0

ns

1

2

3

4

5

6

CS↓ to CONVST↓ Setup Time

SHDN↓ to CS↑ Setup Time

SHDN↑ to CONVST↓ Wake-Up Time

CONVST Low Time

10

ns

400

ns

●

40

ns

CONVST to BUSY Delay

C = 25pF

L

36

60

ns

80

t

Data Ready Before BUSY↑

ns

7

●

32

200

–5

t

Delay Between Conversions

Wait Time RD↓ After BUSY↑

Data Access Time After RD↓

(Note 12)

ns

8

9

C = 25pF

L

40

45

50

60

ns

10

●

C = 100pF

L

60

75

ns

t

Bus Relinquish Time

60

70

75

ns

11

LTC1603C

LTC1603I

●

t

RD Low Time

(Note 12)

●

t

ns

12

13

14

10

CONVST High Time

40

Aperture Delay of Sample-and-Hold

2

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LTC1603

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(Note 5)

TI I G CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

Note 8: Typical RMS noise at the code transitions. See Figure 17 for

of a device may be impaired.

histogram.

Note 2: All voltage values are with respect to ground with DGND, OGND

and AGND wired together unless otherwise noted.

Note 9: Bipolar offset is the offset voltage measured from –0.5LSB when

the output code flickers between 0000 0000 0000 0000 and 1111 1111

1111 1111.

Note 3: When these pin voltages are taken below V or above V , they

SS

DD

will be clamped by internal diodes. This product can handle input currents

greater than 100mA below V or above V without latchup.

Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion

is measured at 100kHz. These results are used to calculate Signal-to-Nosie

Plus Distortion (SINAD).

SS

DD

Note 4: When these pin voltages are taken below V , they will be clamped

SS

by internal diodes. This product can handle input currents greater than

Note 11: Guaranteed by design, not subject to test.

Note 12: Recommended operating conditions.

100mA below V without latchup. These pins are not clamped to V

.

SS

DD

Note 5: V = 5V, V = –5V, f

otherwise specified.

= 250kHz, and t = t = 5ns unless

r f

Note 13: The falling CONVST edge starts a conversion. If CONVST returns

high at a critical point during the conversion it can create small errors. For

best performance ensure that CONVST returns high either within 250ns

after conversion start or after BUSY rises.

DD

SS

SMPL

Note 6: Linearity, offset and full-scale specification apply for a single-

+

–

ended A input with A grounded.

IN

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

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TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity vs

Output Code

Differential Nonlinearity vs

Output Code

2.0

1.5

1.0

0.8

0.6

1.0

0.4

0.5

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

–32768

–16384

0

16384

32767

–32768

–16384

0

16384

32767

CODE

1603 G11

1603 G10

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LTC1603

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PIN FUNCTIONS

A_IN⁺(Pin 1): Positive Analog Input. The ADC converts the

OGND (Pin 28): Digital Ground for Output Drivers.

difference voltage between A_IN⁺and A_IN^–with a differen-

OV_DD(Pin 29): Digital Power Supply for Output Drivers.

Bypass to OGND with 10µF tantalum in parallel with 0.1µF

ceramic.

+

tial range of ±2.5V. A_INhas a ±2.5V input range when

–

A_INis grounded.

A_IN^–(Pin2):NegativeAnalogInput. Canbegrounded, tied

RD (Pin 30): Read Input. A logic low enables the output

drivers when CS is low.

+

to a DC voltage or driven differentially with A_IN

.

V_REF(Pin3):2.5VReferenceOutput.BypasstoAGNDwith

2.2µF tantalum in parallel with 0.1µF ceramic.

CONVST (Pin 31): Conversion Start Signal. This active

low signal starts a conversion on its falling edge when CS

is low.

REFCOMP (Pin 4): 4.375V Reference Compensation Pin.

Bypass to AGND with 47µF tantalum in parallel with 0.1µF

ceramic.

CS (Pin 32): The Chip Select Input. Must be low for the

ADC to recognize CONVST and RD inputs.

AGND(Pins5to8): AnalogGrounds. Tietoanalogground

plane.

SHDN (Pin 33): Power Shutdown. Drive this pin low with

CS low for nap mode. Drive this pin low with CS high for

sleep mode.

DV_DD(Pin 9): 5V Digital Power Supply. Bypass to DGND

with 10µF tantalum in parallel with 0.1µF ceramic.

V

_SS(Pin 34): –5V Negative Supply. Bypass to AGND with

DGND (Pin 10): Digital Ground for Internal Logic. Tie to

analog ground plane.

10µF tantalum in parallel with 0.1µF ceramic.

AV_DD(Pin 35): 5V Analog Power Supply. Bypass to AGND

with 10µF tantalum in parallel with 0.1µF ceramic.

D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15

is the Most Significant Bit.

AV_DD(Pin 36): 5V Analog Power Supply. Bypass to AGND

with 10µF tantalum in parallel with 0.1µF ceramic and

connect this pin to Pin 35 with a 10Ω resistor.

BUSY (Pin 27): The BUSY output shows the converter

status. It is low when a conversion is in progress. Data is

valid on the rising edge of BUSY.

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LTC1603

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10µF

2.2µF

10µF

5V 10µF

5V

10Ω

+

3

10

36

DD

35

9

V

AV

DD

DV

DGND

REF

DD

SHDN

CS

33

32

31

30

27

CONTROL

LOGIC

µP

CONVST

RD

CONTROL

LINES

REFCOMP

7.5k

AND

4

2.5V

REF

1.75X

TIMING

+

4.375V

BUSY

47µF

OV

DD

29

28

5V OR

+

3V

10µF

+

OGND

1

2

A

IN

+

DIFFERENTIAL

ANALOG INPUT

±2.5V

16-BIT

SAMPLING

ADC

OUTPUT

BUFFERS

B15 TO B0

16-BIT

PARALLEL

BUS

–

A

IN

D15 TO D0

–

11 TO 26

1603 TA01

AGND AGND AGND AGND

V

SS

5

6

7

8

34

10µF

+

–5V

TEST CIRCUITS

Load Circuits for Access Timing

Load Circuits for Output Float Delay

5V

1k

DN

1k

C

L

C

L

1k

C

L

C

L

(A) Hi-Z TO V AND V TO V

OH OL

(B) Hi-Z TO V AND V TO V

OL OH

(A) V TO Hi-Z

OH

(B) V TO Hi-Z

OL

OH

OL

1603 TC01

1603 TC02

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LTC1603

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APPLICATIONS INFORMATION

CONVERSION DETAILS

summing junctions. This input charge is successively

compared with the binary-weighted charges supplied by

the differential capacitive DAC. Bit decisions are made by

the high speed comparator. At the end of a conversion, the

The LTC1603 uses a successive approximation algorithm

and internal sample-and-hold circuit to convert an analog

signaltoa16-bitparalleloutput. TheADCiscompletewith

a sample-and-hold, a precision reference and an internal

clock. The control logic provides easy interface to micro-

processors and DSPs. (Please refer to the Digital Interface

section for the data format.)

+

–

differential DAC output balances the A_INand A_INinput

charges. The SAR contents (a 16-bit data word) which

+

–

represent the difference of A_INand A_INare loaded into

the 16-bit output latches.

Conversion start is controlled by the CS and CONVST

inputs. At the start of the conversion the successive

approximation register (SAR) resets. Once a conversion

cycle has begun it cannot be restarted.

DIGITAL INTERFACE

The A/D converter is designed to interface with micropro-

cessors as a memory mapped device. The CS and RD

control inputs are common to all peripheral memory

interfacing. A separate CONVST is used to initiate a con-

version.

During the conversion, the internal differential 16-bit

capacitive DAC output is sequenced by the SAR from the

Most Significant Bit (MSB) to the Least Significant Bit

+

–

Internal Clock

(LSB). Referring to Figure 1, the A_INand A_INinputs are

acquired during the acquire phase and the comparator

offset is nulled by the zeroing switches. In this acquire

phase,adurationof480nswillprovideenoughtimeforthe

sample-and-hold capacitors to acquire the analog signal.

Duringtheconvertphasethecomparatorzeroingswitches

open, putting the comparator into compare mode. The

input switches connect the C_SMPLcapacitors to ground,

transferring the differential analog input charge onto the

The A/D converter has an internal clock that runs the A/D

conversion.Theinternalclockisfactorytrimmedtoachieve

atypicalconversiontimeof3.3µsandamaximumconver-

sion time of 3.8µs over the full temperature range. No

external adjustments are required. The guaranteed maxi-

mum acquisition time is 480ns. In addition, a throughput

time (acquisition + conversion) of 4µs and a minimum

sampling rate of 250ksps are guaranteed.

3V Input/Output Compatible

C

SMPL

SAMPLE

+

The LTC1603 operates on ±5V supplies, which makes the

device easy to interface to 5V digital systems. This device

can also talk to 3V digital systems: the digital input pins

(SHDN, CS, CONVST and RD) of the LTC1603 recognize

3V or 5V inputs. The LTC1603 has a dedicated output

supply pin (OV_DD) that controls the output swings of the

digital output pins (D0 to D15, BUSY) and allows the part

to talk to either 3V or 5V digital systems. The output is

two’s complement binary.

A

IN

HOLD

ZEROING SWITCHES

HOLD

C

SMPL

–

HOLD

+C

DAC

+

–C

COMP

–

+V

DAC

Power Shutdown

The LTC1603 provides two power shutdown modes, Nap

and Sleep, to save power during inactive periods. The Nap

mode reduces the power by 95% and leaves only the

digital logic and reference powered up. The wake-up time

from Nap to active is 200ns. In Sleep mode all bias

–V

DAC

16

D15

D0

•

OUTPUT

LATCHES

SAR

1603 F01

Figure 1. Simplified Block Diagram

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LTC1603

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APPLICATIONS INFORMATION

currents are shut down and only leakage current remains

(about 1µA). Wake-up time from Sleep mode is much

slower since the reference circuit must power up and

settle. Sleepmodewake-uptimeisdependentonthevalue

of the capacitor connected to the REFCOMP (Pin 4). The

wake-up time is 160ms with the recommended 47µF

capacitor.

SHDN

t

3

CS

1603 F02a

Figure 2a. Nap Mode to Sleep Mode Timing

Shutdown is controlled by Pin 33 (SHDN). The ADC is in

shutdown when SHDN is low. The shutdown mode is

selected with Pin 32 (CS). When SHDN is low, CS low

selects nap and CS high selects sleep.

SHDN

t

4

CONVST

1603 F02b

Timing and Control

Figure 2b. SHDN to CONVST Wake-Up Timing

Conversion start and data read operations are controlled

by three digital inputs: CONVST, CS and RD. A falling edge

applied to the CONVST pin will start a conversion after the

ADC has been selected (i.e., CS is low). Once initiated, it

cannot be restarted until the conversion is complete.

Converter status is indicated by the BUSY output. BUSY is

low during a conversion.

CS

t

2

CONVST

RD

t

1

We recommend using a narrow logic low or narrow logic

high CONVST pulse to start a conversion as shown in

Figures 5 and 6. A narrow low or high CONVST pulse

prevents the rising edge of the CONVST pulse from upset-

ting the critical bit decisions during the conversion time.

Figure 4 shows the change of the differential nonlinearity

error versus the low time of the CONVST pulse. As shown,

if CONVST returns high early in the conversion (e.g.,

CONVST low time <500ns), accuracy is unaffected. Simi-

larly, if CONVST returns high after the conversion is over

(e.g., CONVST low time >t_CONV), accuracy is unaffected.

For best results, keep t₅less than 500ns or greater than

1603 F03

Figure 3. CS to CONVST Setup Timing

4

3

2

1

0

t

ACQ

CONV

t_CONV

.

Figures 5 through 9 show several different modes of

operation. In modes 1a and 1b (Figures 5 and 6), CS and

RDarebothtiedlow.ThefallingedgeofCONVSTstartsthe

conversion. The data outputs are always enabled and data

can be latched with the BUSY rising edge. Mode 1a shows

operationwithanarrowlogiclowCONVSTpulse. Mode1b

shows a narrow logic high CONVST pulse.

1500

2000

0

500

1000

2500

3000 3500

4000

CONVST LOW TIME, t (ns)

5

1603 F04

Figure 4. Change in DNL vs CONVST Low Time. Be Sure the

CONVST Pulse Returns High Early in the Conversion or After

the End of Conversion

In mode 2 (Figure 7) CS is tied low. The falling edge of

CONVST signal starts the conversion. Data outputs are in

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LTC1603

APPLICATIONS INFORMATION

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t

CONV

CS = RD = 0

t

5

CONVST

t

8

6

BUSY

DATA

t

7

DATA (N – 1)

D15 TO D0

DATA N

D15 TO D0

DATA (N + 1)

D15 TO D0

1603 F05

Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled

(CONVST =

)

t

CS = RD = 0

CONVST

t

8

CONV

t

5

13

t

6

BUSY

DATA

t

7

DATA (N – 1)

D15 TO D0

DATA N

D15 TO D0

DATA (N + 1)

D15 TO D0

1603 F06

Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled

(CONVST =

)

t

13

t

8

CS = 0

CONV

5

CONVST

t

6

BUSY

RD

t

11

9

t

12

t

10

DATA N

D15 TO D0

DATA

1603 F07

Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD

1603f

10

LTC1603

U

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APPLICATIONS INFORMATION

t

8

CS = 0

CONV

RD = CONVST

t

11

6

BUSY

DATA

t

7

10

DATA (N – 1)

D5 TO D0

DATA N

D15 TO D0

DATA N

D15 TO D0

DATA (N + 1)

D15 TO D0

1603 F08

Figure 8. Mode 2. Slow Memory Mode Timing

t

8

CONV

CS = 0

RD = CONVST

t

11

6

BUSY

t

10

DATA (N – 1)

D15 TO D0

DATA N

D15 TO D0

DATA

1603 F09

Figure 9. ROM Mode Timing

three-stateuntilreadbytheMPUwiththeRDsignal. Mode

2 can be used for operation with a shared data bus.

DIFFERENTIAL ANALOG INPUTS

Driving the Analog Inputs

In slow memory and ROM modes (Figures 8 and 9) CS is

tied low and CONVST and RD are tied together. The MPU

starts the conversion and reads the output with the com-

bined CONVST-RD signal. Conversions are started by the

MPU or DSP (no external sample clock is needed).

The differential analog inputs of the LTC1603 are easy to

drive.Theinputsmaybedrivendifferentiallyorasasingle-

endedinput(i.e.,theA_IN^–inputisgrounded).TheA_IN⁺and

–

A_INinputs are sampled at the same instant. Any un-

wanted signal that is common mode to both inputs will be

reduced by the common mode rejection of the sample-

and-hold circuit. The inputs draw only one small current

spike while charging the sample-and-hold capacitors at

the end of conversion. During conversion the analog

inputs draw only a small leakage current. If the source

impedance of the driving circuit is low, then the LTC1603

inputs can be driven directly. As source impedance in-

creases so will acquisition time (see Figure 10). For

minimum acquisition time with high source impedance, a

buffer amplifier should be used. The only requirement is

that the amplifier driving the analog input(s) must settle

after the small current spike before the next conversion

1603f

In slow memory mode the processor applies a logic low to

RD (= CONVST), starting the conversion. BUSY goes low,

forcing the processor into a wait state. The previous

conversion result appears on the data outputs. When the

conversion is complete, the new conversion results

appear on the data outputs; BUSY goes high, releasing the

processor and the processor takes RD (=CONVST) back

high and reads the new conversion data.

In ROM mode, the processor takes RD (=CONVST) low,

startingaconversionandreadingthepreviousconversion

result. Aftertheconversioniscomplete, theprocessorcan

read the new result and initiate another conversion.

11

LTC1603

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APPLICATIONS INFORMATION

10

LT^®1007: Low Noise Precision Amplifier. 2.7mA supply

current, ±5V to ±15V supplies, gain bandwidth product

8MHz, DC applications.

1

0.1

LT1097:LowCost, LowPowerPrecisionAmplifier. 300µA

supply current, ±5V to ±15V supplies, gain bandwidth

product 0.7MHz, DC applications.

LT1227:140MHzVideoCurrentFeedbackAmplifier.10mA

supply current, ±5V to ±15V supplies, low noise and low

distortion.

0.01

1

10

100

1k

10k

SOURCE RESISTANCE (Ω)

LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA sup-

ply current, ±5V to ±15V supplies, good AC/DC specs.

1603 F10

Figure 10. t_ACQvs Source Resistance

LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA sup-

ply current, good AC/DC specs.

starts (settling time must be 200ns for full throughput

rate).

LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback

Amplifiers. 6.3mA supply current per amplifier, good AC/

DC specs.

Choosing an Input Amplifier

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a

lowoutputimpedance(<100Ω)attheclosed-loopband-

width frequency. For example, if an amplifier is used in a

gainof+1andhasaunity-gainbandwidthof50MHz,then

the output impedance at 50MHz should be less than

100Ω. The second requirement is that the closed-loop

bandwidth must be greater than 15MHz to ensure

adequate small-signal settling for full throughput rate. If

slower op amps are used, more settling time can be

provided by increasing the time between conversions.

Input Filtering

The noise and the distortion of the input amplifier and

other circuitry must be considered since they will add to

the LTC1603 noise and distortion. The small-signal band-

width of the sample-and-hold circuit is 15MHz. Any noise

ordistortionproductsthatarepresentattheanaloginputs

will be summed over this entire bandwidth. Noisy input

circuitry should be filtered prior to the analog inputs to

minimize noise. A simple 1-pole RC filter is sufficient for

manyapplications.Forexample,Figure11showsa3000pF

capacitor from A_IN⁺to ground and a 100Ω source resistor

to limit the input bandwidth to 530kHz. The 3000pF

capacitor also acts as a charge reservoir for the input

sample-and-hold and isolates the ADC input from sam-

pling glitch sensitive circuitry. High quality capacitors and

resistors should be used since these components can add

distortion. NPO and silver mica type dielectric capacitors

haveexcellentlinearity.Carbonsurfacemountresistorscan

also generate distortion from self heating and from damage

that may occur during soldering. Metal film surface mount

resistors are much less susceptible to both problems.

The best choice for an op amp to drive the LTC1603 will

dependontheapplication. Generallyapplicationsfallinto

two categories: AC applications where dynamic specifi-

cations are most critical and time domain applications

where DC accuracy and settling time are most critical.

The following list is a summary of the op amps that are

suitable for driving the LTC1603. More detailed informa-

tion is available in the Linear Technology databooks, the

LinearView^TMCD-ROM and on our web site at:

www.linear-tech. com.

LinearView is a trademark of Linear Technology Corporation.

1603f

12

LTC1603

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APPLICATIONS INFORMATION

100Ω

1

2

3

4

5

R1

7.5k

+

–

ANALOG INPUT

A

V

IN

V

3

4

REF

BANDGAP

REFERENCE

2.500V

3000pF

IN

LTC1603

REFCOMP

REFERENCE

AMP

REF

4.375V

REFCOMP

AGND

R2

12k

47µF

R3

16k

AGND

5

1603 F11

LTC1603

1603 F12a

Figure 11. RC Input Filter

Figure 12a. LTC1603 Reference Circuit

Input Range

5V

1

2

3

+

–

A

V

The ±2.5V input range of the LTC1603 is optimized for low

noise and low distortion. Most op amps also perform well

over this same range, allowing direct coupling to the

analog inputs and eliminating the need for special transla-

tion circuitry.

IN

ANALOG

INPUT

V

IN

LT1019A-2.5

V

OUT

REF

LTC1603

4

REFCOMP

Some applications may require other input ranges. The

LTC1603 differential inputs and reference circuitry can

accommodate other input ranges often with little or no

additional circuitry. The following sections describe the

reference and input circuitry and how they affect the input

range.

+

10µF

0.1µF

5

AGND

1603 F12b

Figure 12b. Using the LT1019-2.5 as an External Reference

Internal Reference

The V_REFpin can be driven with a DAC or other means

showninFigure13.Thisisusefulinapplicationswherethe

peak input signal amplitude may vary. The input span of

the ADC can then be adjusted to match the peak input

signal, maximizing the signal-to-noise ratio. The filtering

of the internal LTC1603 reference amplifier will limit

the bandwidth and settling time of this circuit. A settling

time of 20ms should be allowed for after a reference

adjustment.

TheLTC1603hasanon-chip,temperaturecompensated,

curvature corrected, bandgap reference that is factory

trimmed to 2.500V. It is connected internally to a refer-

ence amplifier and is available at V_REF(Pin 3) (see Figure

12a). A 7.5k resistor is in series with the output so that it

can be easily overdriven by an external reference or other

circuitry (see Figure 12b). The reference amplifier gains

the voltage at the V_REFpin by 1.75 to create the required

internal reference voltage. This provides buffering

between the V_REFpin and the high speed capacitive DAC.

The reference amplifier compensation pin (REFCOMP,

Pin 4) must be bypassed with a capacitor to ground. The

reference amplifier is stable with capacitors of 22µF or

greater. For the best noise performance a 47µF ceramic

or 47µF tantalum in parallel with a 0.1µF ceramic is

recommended.

Differential Inputs

The LTC1603 has a unique differential sample-and-hold

circuit that allows rail-to-rail inputs. The ADC will always

+

–

convert the difference of A_IN– A_INindependent of the

common mode voltage (see Figure 15a). The common

mode rejection holds up to extremely high frequencies

(see Figure 14a). The only requirement is that both inputs

1603f

13

LTC1603

APPLICATIONS INFORMATION

U

W U U

1

2

3

4

5

+

1

2

+

–

A

V

IN

ANALOG INPUT

A

IN

ANALOG INPUT

2V TO 2.7V

DIFFERENTIAL

–

0V TO

5V

3

IN

V

+

–

±2.5V

REF

LTC1603

2V TO 2.7V

LTC1603

LTC1450

REF

4

REFCOMP

AGND

REFCOMP

AGND

10µF

47µF

5

1603 F13

1603 F14b

Figure 13. Driving V_REFwith a DAC

Figure 14b. Selectable 0V to 5V or ±2.5V Input Range

80

Full-Scale and Offset Adjustment

70

60

50

40

30

20

10

0

Figure 15a shows the ideal input/output characteristics

for the LTC1603. The code transitions occur midway

between successive integer LSB values (i.e., –FS +

0.5LSB, –FS + 1.5LSB, –FS + 2.5LSB,... FS – 1.5LSB,

FS –0.5LSB). The output is two’s complement binary with

1LSB = FS – (–FS)/65536 = 5V/65536 = 76.3µV.

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset

error must be adjusted before full-scale error. Figure 15b

shows the extra components required for full-scale error

adjustment. Zero offset is achieved by adjusting the offset

1k

10k

100k

1M

INPUT FREQUENCY (Hz)

1603 G14a

Figure 14a. CMRR vs Input Frequency

–

applied to the A_INinput. For zero offset error apply

can not exceed the AV_DDor V_SSpower supply voltages.

Integral nonlinearity errors (INL) and differential nonlin-

earity errors (DNL) are independent of the common mode

voltage, however, the bipolar zero error (BZE) will vary.

The change in BZE is typically less than 0.1% of the

common mode voltage. Dynamic performance is also

affected by the common mode voltage. THD will degrade

astheinputsapproacheitherpowersupplyrail,from96dB

with a common mode of 0V to 86dB with a common mode

of 2.5V or –2.5V.

011...111

011...110

000...001

000...000

111...111

111...110

100...001

100...000

Differential inputs allow greater flexibility for accepting

different input ranges. Figure 14b shows a circuit that

converts a 0V to 5V analog input signal with only an

additional buffer that is not in the signal path.

–(FS – 1LSB)

INPUT VOLTAGE (A – A

FS – 1LSB

+

–

)

IN

1603 F15a

Figure 15a. LTC1603 Transfer Characteristics

1603f

14

LTC1603

U

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APPLICATIONS INFORMATION

–5V

ANALOG

INPUT

1

+

analog ground plane. No other digital grounds should be

connected to this analog ground plane. Low impedance

analog and digital power supply common returns are

essential to low noise operation of the ADC and the foil

width for these tracks should be as wide as possible. In

applications where the ADC data outputs and control

signals are connected to a continuously active micropro-

cessor bus, it is possible to get errors in the conversion

results. These errors are due to feedthrough from the

microprocessor to the successive approximation com-

parator. The problem can be eliminated by forcing the

microprocessor into a WAIT state during conversion or by

using three-state buffers to isolate the ADC data bus. The

traces connecting the pins and bypass capacitors must be

kept short and should be made as wide as possible.

A

IN

R3

24k

2

–

R8

50k

A

IN

R4

100Ω

LTC1603

3

R5 R7

47k 50k

V

REF

R6

24k

4

5

REFCOMP

AGND

+

0.1µF

47µF

1603 F15b

Figure 15b. Offset and Full-Scale Adjust Circuit

+

–38µV (i.e., –0.5LSB) at A_INand adjust the offset at the

–

A_INinput by varying R8 until the output code flickers

The LTC1603 has differential inputs to minimize noise

coupling. CommonmodenoiseontheA_IN⁺andA_IN^–leads

will be rejected by the input CMRR. The A_IN^–input can be

between0000000000000000and1111111111111111.

For full-scale adjustment, an input voltage of 2.499886V

(FS/2–1.5LSBs)isappliedtoA_IN⁺andR7isadjusteduntil

the output code flickers between 0111 1111 1111 1110

and 0111 1111 1111 1111.

+

used as a ground sense for the A_INinput; the LTC1603

+

will hold and convert the difference voltage between A_IN

and A_IN^–. The leads to A_IN⁺(Pin 1) and A_IN^–(Pin 2) should

be kept as short as possible. In applications where this is

BOARD LAYOUT AND GROUNDING

+

–

not possible, the A_INand A_INtraces should be run side

by side to equalize coupling.

Wire wrap boards are not recommended for high resolu-

tion or high speed A/D converters. To obtain the best

performance from the LTC1603, a printed circuit board

with ground plane is required. Layout should ensure that

digital and analog signal lines are separated as much as

possible. Particular care should be taken not to run any

digital track alongside an analog signal track or under-

neath the ADC.The analog input should be screened by

AGND.

SUPPLY BYPASSING

High quality, low series resistance ceramic, 10µF or 47µF

bypasscapacitorsshouldbeusedattheV_DDandREFCOMP

pins as shown in Figure 16 and in the Typical Application

on the first page of this data sheet. Surface mount ceramic

capacitors such as Murata GRM235Y5V106Z016 provide

excellent bypassing in a small board space. Alternatively,

10µF tantalum capacitors in parallel with 0.1µF ceramic

capacitors can be used. Bypass capacitors must be lo-

cated as close to the pins as possible. The traces connect-

ing the pins and the bypass capacitors must be kept short

and should be made as wide as possible.

An analog ground plane separate from the logic system

ground should be established under and around the ADC.

Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other

analog grounds should be connected to this single analog

ground point. The REFCOMP bypass capacitor and the

DV_DDbypass capacitor should also be connected to this

1603f

15

LTC1603

U

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APPLICATIONS INFORMATION

1

+

A

IN

DIGITAL

SYSTEM

LTC1603

AV AV

–

A

IN

V

DV

DGND OV

10

OGND

28

REFCOMP AGND

REF

3

SS

DD

9

DD

29

2

ANALOG

INPUT

CIRCUITRY

4

5 TO 8 34

36

35

+

–

2.2µF

10µF

47µF

10µF 10µF 10µF

10µF

1603 F16

Figure 16. Power Supply Grounding Practice

2500

DC PERFORMANCE

The noise of an ADC can be evaluated in two ways: signal-

to-noise raio (SNR) in frequency domain and histogram in

time domain. The LTC1603 excels in both. Figure 18a

demonstrates that the LTC1603 has an SNR of over 90dB

in frequency domain. The noise in the time domain histo-

gram is the transition noise associated with a high resolu-

tion ADC which can be measured with a fixed DC signal

applied to the input of the ADC. The resulting output codes

are collected over a large number of conversions. The

shape of the distribution of codes will give an indication of

the magnitude of the transition noise. In Figure 17 the

distribution of output codes is shown for a DC input that

hasbeendigitized4096times.ThedistributionisGaussian

and the RMS code transition noise is about 0.66LSB. This

correspondstoanoiselevelof90.9dBrelativetofullscale.

Adding to that the theoretical 98dB of quantization error

for 16-bit ADC, the resultant corresponds to an SNR level

of 90.1dB which correlates very well to the frequency

domain measurements in DYNAMIC PERFORMANCE

section.

2000

1500

1000

500

0

–4

–5

–3 –2 –1

0

1

2

3

4

5

CODE

1603 F17

Figure 17. Histogram for 4096 Conversions

0

f

= 250kHz

SAMPLE

IN

SINAD = 90.2dB

THD = –103.2dB

= 9.959kHz

–20

–40

–60

–80

–100

–120

DYNAMIC PERFORMANCE

The LTC1603 has excellent high speed sampling capabil-

ity. Fast fourier transform (FFT) test techniques are used

to test the ADC’s frequency response, distortions and

noise at the rated throughput. By applying a low distortion

sine wave and analyzing the digital output using an FFT

algorithm, the ADC’s spectral content can be examined for

frequenciesoutsidethefundamental. Figures18aand18b

show typical LTC1603 FFT plots.

–140

0

20

40

60

80

100 120

FREQUENCY (kHz)

1603 F18a

Figure 18a. This FFT of the LTC1603’s Conversion of a

Full-Scale 10kHz Sine Wave Shows Outstanding Response

with a Very Low Noise Floor When Sampling at 250ksps

1603f

16

LTC1603

U

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APPLICATIONS INFORMATION

Signal-to-Noise Ratio

0

f

= 250kHz

SAMPLE

IN

= 97.152kHz

–20

SINAD = 89dB

THD = –96dB

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency to the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 18a shows a typical spectral content

with a 250kHz sampling rate and a 5kHz input. The

dynamicperformanceisexcellentforinputfrequenciesup

to and beyond the Nyquist limit of 125kHz.

–40

–60

–80

–100

–120

–140

0

20

40

60

80

100 120

FREQUENCY (kHz)

1603 F18b

Effective Number of Bits

Figure 18b. Even with Inputs at 100kHz, the LTC1603’s

Dymanic Linearity Remains Robust

The effective number of bits (ENOBs) is a measurement of

the resolution of an ADC and is directly related to the

S/(N + D) by the equation:

98

92

86

80

74

68

62

56

50

16

15

14

13

12

11

10

9

N = [S/(N + D) – 1.76]/6.02

where N is the effective number of bits of resolution and

S/(N + D) is expressed in dB. At the maximum sampling

rate of 250kHz the LTC1603 maintains above 14 bits up to

theNyquistinputfrequencyof125kHz(refertoFigure19).

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sumofallharmonicsoftheinputsignaltothefundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD is

expressed as:

8

1k

10k

100k

1M

FREQUENCY (Hz)

1603 F19

Figure 19. Effective Bits and Signal/(Noise + Distortion)

vs Input Frequency

2

V2 + V3 + V4 +...Vn

0

–10

–20

–30

–40

–50

–60

–70

THD = 20Log

V1

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through Vn are the amplitudes of the

secondthroughnthharmonics.THDvsInputFrequencyis

shown in Figure 20. The LTC1603 has good distortion

performance up to the Nyquist frequency and beyond.

–80

–90

THD

3RD

–100

–110

2ND

10k

INPUT FREQUENCY (Hz)

1k

100k

1M

1603 F20

Figure 20. Distortion vs Input Frequency

1603f

17

LTC1603

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APPLICATIONS INFORMATION

Intermodulation Distortion

etc. For example, the 2nd order IMD terms include

(fa – fb). If the two input sine waves are equal in magni-

tude, thevalue(indecibels)ofthe2ndorderIMDproducts

can be expressed by the following formula:

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused by

the presence of another sinusoidal input at a different

frequency.

Amplitude at (fa ± fb)

IMD fa± fb = 20Log

(

)

Amplitude at fa

If two pure sine waves of frequencies fa and fb are applied

to the ADC input, nonlinearities in the ADC transfer func-

tion can create distortion products at the sum and differ-

ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spec-

tral component excluding the input signal and DC. This

value is expressed in decibels relative to the RMS value of

a full-scale input signal.

0

f

= 250kHz

SAMPLE

IN1

IN2

= 29.3kHz

–20

–40

Full-Power and Full-Linear Bandwidth

= 32.4kHz

The full-power bandwidth is that input frequency at which

the amplitude of the reconstructed fundamental is

reduced by 3dB for a full-scale input signal.

–60

–80

The full-linear bandwidth is the input frequency at which

the S/(N + D) has dropped to 84dB (13.66 effective bits).

The LTC1603 has been designed to optimize input band-

width, allowingtheADCtoundersampleinputsignalswith

frequenciesabovetheconverter’sNyquistFrequency. The

noise floor stays very low at high frequencies; S/(N + D)

becomes dominated by distortion at frequencies far

beyond Nyquist.

–100

–120

–140

0

20

40

60

120

80

100

FREQUENCY (kHz)

1603 F21

Figure 21. Intermodulation Distortion Plot

1603f

18

LTC1603

U

PACKAGE DESCRIPTION

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

12.50 – 13.10*

(.492 – .516)

1.25 ±0.12

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

7.8 – 8.2

5.3 – 5.7

7.40 – 8.20

(.291 – .323)

0.42 ±0.03

0.65 BSC

5

7

8

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18

5.00 – 5.60**

(.197 – .221)

2.0

(.079)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

(.0035 – .010)

0.55 – 0.95

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

(.002)

NOTE:

G36 SSOP 0802

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

1603f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC1603

TYPICAL APPLICATION

U

Using the LTC1603 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System

5V

2.2µF

10µF

5V 10µF

10Ω

36

+

LTC1391

3

35

10

9

1µF

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

+

DV

DD

V

AV

DD

DGND

REF

DD

CH0

V

SHDN 33

CS 32

CH1

CH2

CH3

CH4

CH5

CH6

CH7

D

–

–5V

1µF

CONTROL

LOGIC

AND

TIMING

V

µP

CONTROL

LINES

CONVST 31

RD 30

7.5k

REFCOMP

D

OUT

4

2.5V

REF

1.75X

+

4.375V

D

IN

BUSY 27

47µF

CS

OV

29

5V OR

3V

10µF

DD

CLK

+

–

A

1

2

IN

+

–

OGND 28

CH7

CH0

GND

+

–

3000pF

16-BIT

SAMPLING

ADC

OUTPUT

BUFFERS

B15 TO B0

16-BIT

PARALLEL

BUS

5V

D15 TO D0

A

IN

LTC1391

1µF

11 TO 26

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LTC1603

+

AGND AGND AGND AGND V

SS

34

V

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

1603 TA03

5

6

7

8

D

–

–5V

10µF

+

V

+

–5V

D

OUT

D

IN

µP

CONTROL

LINES

CS

CLK

–

GND

CH7

RELATED PARTS

SAMPLING ADCs

PART NUMBER

LTC1410

LTC1415

LTC1418

LTC1419

LTC1604

LTC1605

LTC1608

DESCRIPTION

COMMENTS

12-Bit, 1.25Msps, ±5V ADC

12-Bit, 1.25Msps, Single 5V ADC

14-Bit, 200ksps, Single 5V ADC

Low Power 14-Bit, 800ksps ADC

16-Bit, 333ksps, ±5V ADC

71.5dB SINAD at Nyquist, 150mW Dissipation

55mW Power Dissipation, 72dB SINAD

15mW, Serial/Para llel ±10V

True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation

Pin Compatible with LTC1603

16-Bit, 100ksps, Single 5V ADC

16-Bit, 500ksps, ±5V ADC

±10V Inputs, 55mW, Byte or Parallel I/O

Pin Compatible with LTC1603

DACs

PART NUMBER

DESCRIPTION

16-Bit Serial SoftSpan^TMDAC

COMMENTS

LTC1592

±1LSB Max INL/DNL, Software-Selectable Output Spans

±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade

LTC1595

16-Bit Serial Multiplying I

DAC in SO-8

DAC

OUT

LTC1596

±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade

±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors

Low Power, Low Gritch, 4-Quadrant Multiplication

LTC1597

16-Bit Parallel, Multiplying DAC

16-Bit Serial V DAC

LTC1650

OUT

SoftSpan is a trademark of Linear Technolology Corporation.

1603f

LT/TP 0503 1K • PRINTED IN USA

20 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2003


型号：	LTC1603CG
厂家：	Linear
描述：	High Speed, 16-Bit, 250ksps Sampling A/D Converter with Shutdown 高速， 16位， 250ksps的采样A / D转换器，带有关断转换器光电二极管
文件：	总20页 (文件大小：251K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1603CG [Linear]

相关型号：

LTC1603CG#PBF

LTC1603CG#TR

LTC1603CG#TRPBF

LTC1603IG

LTC1603IG#PBF

LTC1603IG#TR

LTC1603IG#TRPBF

LTC1604

LTC1604ACG

LTC1604ACG#TR

LTC1604ACG#TRPBF

LTC1604AIG