LTC1596CISW [Linear]
Serial 16-Bit Multiplying DACs; 串行16位乘法DAC
| 型号： | LTC1596CISW |
| 厂家： | 
Linear |
| 描述： | Serial 16-Bit Multiplying DACs |
| 文件： | 总12页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1595/LTC1596/LTC1596-1
Serial 16-Bit
Multiplying DACs
U
DESCRIPTION
FEATURES
■
SO-8 Package (LTC1595)
The LTC®1595/LTC1596/LTC1596-1 are serial input,
16-bit multiplying current output DACs. The LTC1595 is
pinandhardwarecompatiblewiththe12-bitDAC8043and
comesin8-pinPDIPandSOpackages.TheLTC1596ispin
andhardwarecompatiblewiththe12-bitDAC8143/AD7543
and comes in 16-pin PDIP and SO wide packages.
■
DNL and INL: 1LSB Max
■
Low Glitch Impulse: 1nV-s Typ
■
Fast Settling to 1LSB: 2µs (with LT1468)
■
Pin Compatible with Industry Standard
12-Bit DACs: DAC8043 and DAC8143/AD7543
4-Quadrant Multiplication
■
■
■
Both are specified over the industrial temperature range.
Sensitivity of INL to op amp VOS is reduced by five times
compared to the industry standard 12-bit DACs, so most
systems can be easily upgraded to true 16-bit resolution
and linearity without requiring more precise op amps.
Low Supply Current: 10µA Max
Power-On Reset
LTC1595/LTC1596: Resets to Zero Scale
LTC1596-1: Resets to Midscale
3-Wire SPI and MICROWIRETM Compatible
Serial Interface
Daisy-Chain Serial Output (LTC1596)
Asynchronous Clear Input
■
These DACs include an internal deglitching circuit that
reduces the glitch impulse by more than ten times to less
than 1nV-s typ.
■
■
LTC1596: Clears to Zero Scale
LTC1596-1: Clears to Midscale
The DACs have a clear input and a power-on reset. The
LTC1595andLTC1596resettozeroscale.TheLTC1596-1
is a version of the LTC1596 that resets to midscale.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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APPLICATIONS
■
Process Control and Industrial Automation
■
Software Controlled Gain Adjustment
■
Digitally Controlled Filter and Power Supplies
■
Automatic Test Equipment
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TYPICAL APPLICATION
SO-8 Multiplying 16-Bit DAC Has Easy 3-Wire Serial Interface
Integral Nonlinearity
1.0
0.8
0.6
0.4
V
IN
5V
8
1
2
R
FB
33pF
V
DD
V
REF
7
6
5
CLK
SRI
LD
CLOCK
DATA
LOAD
–
0.2
0
3
OUT1
LTC1595
LT®1468
+
V
OUT
–0.2
–0.4
–0.6
–0.8
–1.0
GND
4
1595/96 TA01
0
16384
32768
49152
65535
DIGITAL INPUT CODE
1595/96 TA02
1
LTC1595/LTC1596/LTC1596-1
W W U W
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VDD to AGND .............................................. –0.5V to 7V
VDD to DGND .............................................. –0.5V to 7V
AGND to DGND............................................ VDD + 0.5V
DGND to AGND............................................. VDD + 0.5V
VREF to AGND, DGND............................................. ±25V
VOUT1, VOUT2 to AGND ................. –0.5V to (VDD + 0.5V)
Maximum Junction Temperature .......................... 150°C
Operating Temperature Range
LTC1595C/LTC1596C/LTC1596-1C ........ 0°C to 70°C
LTC1595I/LTC1596I/LTC1596-1I ...... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
R
FB to AGND, DGND .............................................. ±25V
Digital Inputs to DGND ................–0.5V to (VDD + 0.5V)
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/O
PACKAGE RDER I FOR ATIO
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
R
V
16
15
14
13
12
11
10
9
1
2
3
4
V
OUT1
OUT2
AGND
STB1
LD1
8
7
6
5
V
FB
DD
REF
CLK
SRI
LD
R
REF
DD
FB
V
OUT1
GND
CLR
DGND
STB4
STB3
LD2
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
SRO
SRI
TJMAX = 150°C, θJA = 130°C/W (N)
TJMAX = 150°C, θJA = 190°C/W (S)
STB2
N PACKAGE
SW PACKAGE
ORDER PART NUMBER
16-LEAD PDIP 16-LEAD PLASTIC SO WIDE
TJMAX = 150°C, θJA = 100°C/W (N)
TJMAX = 150°C, θJA = 130°C/W (SW)
LTC1595ACN8 LTC1595AIN8
LTC1595ACS8 LTC1595AIS8
LTC1595BCN8 LTC1595BIN8
LTC1595BCS8 LTC1595BIS8
LTC1595CCN8 LTC1595CIN8
LTC1595CCS8 LTC1595CIS8
ORDER PART NUMBER
LTC1596ACN
LTC1596ACSW
LTC1596BCN
LTC1596BCSW
LTC1596CCN
LTC1596CCSW
LTC1596AIN
LTC1596-1ACN
LTC1596-1ACSW LTC1596-1AISW
LTC1596-1BCN LTC1596-1BIN
LTC1596-1BCSW LTC1596-1BISW
LTC1596-1CCN LTC1596-1CIN
LTC1596-1CCSW LTC1596-1CISW
LTC1596-1AIN
LTC1596AISW
LTC1596BIN
LTC1596BISW
LTC1596CIN
LTC1596CISW
S8 PART MARKING
1595A 1595AI
1595B 1595BI
1595C 1595CI
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
LTC1595C/96C/96-1C
LTC1595A/96A/96-1A LTC1595B/96B/96-1B
SYMBOL PARAMETER
Accuracy
CONDITIONS
MIN
TYP
MAX
MIN TYP
MAX
MIN
TYP
MAX
UNITS
Resolution
●
●
16
16
16
16
16
15
Bits
Bits
Monotonicity
INL
Integral Nonlinearity
(Note 2) T = 25°C
±0.25
±0.35
± 1
±1
±2
±2
±4
±4
LSB
LSB
A
T
to T
●
MIN
MAX
2
LTC1595/LTC1596/LTC1596-1
ELECTRICAL CHARACTERISTICS
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
LTC1595C/96C/96-1C
LTC1595A/96A/96-1A LTC1595B/96B/96-1B
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN TYP
MAX
MIN
TYP
MAX
UNITS
DNL
Differential
Nonlinearity
T = 25°C
±0.2
±0.2
± 1
±1
±1
±1
±2
±2
LSB
LSB
A
T
to T
●
●
MIN
MAX
GE
Gain Error
(Note 3) T = 25°C
2
3
±16
±16
±16
±32
±32
±32
LSB
LSB
A
T
to T
MIN
MAX
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gain Temperature Coefficient
OUT1 Leakage Current
(Note 4) ∆Gain/∆Temperature
●
●
1
2
ppm/°C
I
(Note 5) T = 25°C
±3
±15
nA
nA
LEAKAGE
A
T
to T
MIN
MAX
Zero-Scale Error
T = 25°C
±0.2
±1
LSB
LSB
A
T
to T
●
●
MIN
MAX
PSRR
Power Supply Rejection
V
DD
= 5V ±10%
±1
±2
LSB/V
Reference Input
R
V
Input Resistance
REF
(Note 6)
●
5
7
10
kΩ
REF
AC Performance
Output Current Settling Time
Mid-Scale Glitch Impulse
(Notes 7, 8)
1
1
2
µs
nV-s
nV-s
Using LT1122 Op Amp, C
= 33pF
= 33pF
FEEDBACK
Digital-to-Analog Glitch Impulse
Full-Scale Transition, V = 0V,
REF
Using LT1122 Op Amp, C
FEEDBACK
Multiplying Feedthrough Error
Total Harmonic Distortion
V
= ±10V, 10kHz Sine Wave
1
mV
P-P
REF
THD
(Note 9)
108
11
dB
Equivalent DAC Thermal Noise
Voltage Density
(Note 10) f = 1kHz
nV/√Hz
Analog Outputs (Note 4)
Output Capacitance (Note 4)
C
DAC Register Loaded to All 1s
OUT
C
●
●
115
70
130
80
pF
pF
OUT1
DAC Register Loaded to All 0s
C
OUT1
Digital Inputs
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
●
●
●
●
2.4
V
V
IH
IL
0.8
±1
8
I
0.001
µA
pF
IN
C
Digital Input Capacitance
(Note 4) V = 0V
IN
IN
Digital Outputs: SRO (LTC1596/LTC1596-1)
V
V
Digital Output High Voltage
Digital Output Low Voltage
I
I
= 200µA
●
●
4
V
V
OH
OL
OH
OL
= 1.6mA
0.4
VDD = 5V ±10%, VREF = 10V, VOUT1 = GND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics (LTC1595)
t
t
Serial Input to CLK Setup Time
Serial Input to CLK Hold Time
●
●
30
30
5
5
ns
ns
DS
DH
3
LTC1595/LTC1596/LTC1596-1
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
MIN
60
60
60
60
0
TYP
MAX
UNITS
ns
t
t
t
t
t
Serial Input Data Pulse Width
Clock Pulse Width High
Clock Pulse Width Low
Load Pulse Width
●
●
●
●
●
SRI
CH
ns
ns
CL
ns
LD
LSB Clocked into Input Register
to DAC Register Load Time
ns
ASB
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics (LTC1596/LTC1596-1)
t
t
t
t
t
t
t
t
t
Serial Input to Strobe Setup Time
STB1 Used as the Strobe
STB2 Used as the Strobe
STB3 Used as the Strobe
STB4 Used as the Strobe
STB1 Used as the Strobe
STB2 Used as the Strobe
STB3 Used as the Strobe
STB4 Used as the Strobe
●
●
●
●
●
●
●
●
●
●
30
20
25
20
30
40
35
40
60
60
5
–5
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS1
DS2
DS3
DS4
DH1
DH2
DH3
DH4
SRI
–5
5
Serial Input to Strobe Hold Time
15
10
15
Serial Input Data Pulse Width
Strobe Pulse Width
t
t
to
to
(Note 11)
(Note 12)
STB1
STB4
t
t
Strobe Pulse Width
LD Pulse Width
●
60
ns
STB1
STB4
t
t
t
●
●
60
0
ns
ns
LD1, LD2
LSB Strobed into Input Register
to Load DAC Register Time
ASB
t
t
t
Clear Pulse Width
●
●
●
100
30
ns
ns
ns
CLR
PD1
PD
STB1 to SRO Propagation Delay
C = 50pF
150
200
L
STB2, STB3, STB4 to SRO
Propagation Delay
C = 50pF
L
30
Power Supply
V
Supply Voltage
Supply Current
●
●
4.5
5
5.5
10
V
DD
I
Digital Inputs = 0V or V
1.5
µA
DD
DD
The
●
denotes specifications which apply over the full operating
Note 8: To 0.0015% for a full-scale change, measured from the falling
temperature range.
edge of LD1, LD2 or LD.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 9: V = 6V
op amp = LT1007.
at 1kHz. DAC register loaded with all 1s;
REF
RMS
Note 2: ±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale.
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 10: Calculation from e = √4kTRB where: k = Boltzmann constant
(J/°K); R = resistance (Ω); T = temperature (°K); B = bandwidth (Hz).
Note 11: Minimum high time for STB1, STB2, STB4. Minimum low time
for STB3.
Note 12: Minimum low time for STB1, STB2, STB4. Minimum high time
for STB3.
n
Note 5: I
with DAC register loaded with all 0s.
OUT1
Note 6: Typical temperature coefficient is 100ppm/C.
Note 7: OUT1 load = 100Ω in parallel with 13pF.
4
LTC1595/LTC1596/LTC1596-1
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Mid-Scale Glitch Inpulse
Integral Nonlinearity (INL)
Differential Nonlinearity (INL)
1.0
0.8
0.6
0.4
1.0
0.8
1nV-s TYP
USING LT1122 OP AMP
+10
0
C
V
= 33pF
FEEDBACK
REF
0.6
= 10V
0.4
0.2
0.2
0
0
LD FALLING EDGE
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–10
0
1
2
3
4
0
16384
32768
49152
65535
0
32768
49152
16384
65535
TIME (µs)
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1595/96 G01
1595/96 TA02
1595/96 G03
Integral Nonlinearity
vs Reference Voltage
Differential Nonlinearity
vs Reference Voltage
Full-Scale Settling Waveform
1.0
0.5
1.0
0.5
DAC
OUTPUT
5V/DIV
GATED
SETTLING
WAVEFORM
500µV/DIV
1595/96 G04
1µs/DIV
USING LT1122 OP AMP
CFEEDBACK = 33pF
0
0
–10 –8 –6 –4 –2
0
2
4
6
8
10
–10 –8 –6 –4 –2
0
2
4
6
8
10
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1595/96 G05
1595/96 G06
Multiplying Mode Frequency
Response vs Digital Code
Integral Nonlinearity
vs Supply Voltage
Differential Nonlinearity
vs Supply Voltage
2
1
0
1.0
0.5
0
0
–20
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
ALL
BITS
ON
–40
V
REF
= 10V
–60
D5
D4
D3
–80
D2
D1
D0
–100
ALL
BITS OFF
USING LT1122 OP AMP
FEEDBACK
V
= 2.5V
4
REF
C
= 33pF
–120
2
6
8
9
2
6
8
9
100
1k
10k
100k
1M
10M
3
5
7
10
3
4
5
7
10
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
1595/96 G07
1595/96 G08
1595/96 G09
5
LTC1595/LTC1596/LTC1596-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current
Logic Threshold
vs Supply Voltage
vs Logic Input Voltage
3.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
DD
= 5V
2.5
2.0
1.5
1.0
0.5
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
1595/96 G11
1595/96 G10
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PIN FUNCTIONS
LTC1595
STB1, STB2, STB3, STB4 (Pins 4, 8, 10, 11): Serial
Interface Clock Inputs. STB1, STB2 and STB4 are rising
edge triggered inputs. STB3 is a falling edge triggered
input (see Truth Tables).
VREF (Pin 1): Reference Input.
RFB (Pin2):FeedbackResistor.Normallytiedtotheoutput
of the current to voltage converter op amp.
LD1, LD2(Pins5, 9):SerialInterfaceLoadControlInputs.
When LD1 and LD2 are pulled low, data is loaded from the
shift register into the DAC register, updating the DAC
output (see Truth Tables).
OUT1 (Pin 3): Current Output Pin. Tie to inverting input of
current to voltage converter op amp.
GND (Pin 4): Ground Pin.
SRO (Pin 6): The Output of the Shift Register. Becomes
LD (Pin 5): The Serial Interface Load Control Input. When
LD is pulled low, data is loaded from the shift register into
the DAC register, updating the DAC output.
valid on the active edge of the serial clock.
SRI (Pin 7): The Serial Data Input. Data on the SRI pin is
latched into the shift register on the active edge of the
serial clock. Data is loaded MSB first.
SRI (Pin 6): The Serial Data Input. Data on the SRI pin is
latchedintotheshiftregisterontherisingedgeoftheserial
clock. Data is loaded MSB first.
DGND (Pin 12): Digital Ground Pin.
CLK (Pin 7): The Serial Interface Clock Input.
CLR(Pin13):TheClearPinfortheDAC.ClearsDACtozero
scalewhenpulledlowonLTC1596.ClearsDACtomidscale
when pulled low on LTC1596-1. This pin should be tied to
VDD for normal operation.
VDD (Pin 8):The Positive Supply Input. 4.5V ≤ VDD ≤ 5.5V.
Requires a bypass capacitor to ground.
LTC1596/LTC1596-1
OUT1 (Pin 1): True Current Output Pin. Tie to inverting
input of current to voltage converter op amp.
VDD (Pin 14): The Positive Supply Input. 4.5V ≤ VDD
≤
5.5V. Requires a bypass capacitor to ground.
VREF (Pin 15): Reference Input.
OUT2 (Pin 2): Complement Current Output Pin. Tie to
analog ground.
RFB (Pin 16): Feedback Resistor. Normally tied to the
output of the current to voltage converter op amp.
AGND (Pin 3): Analog Ground Pin.
6
LTC1595/LTC1596/LTC1596-1
TRUTH TABLES
Table 1. LTC1596/LTC1596-1 Input Register
Table 2. LTC1596/LTC1596-1 DAC Register
CONTROL INPUTS
CONTROL INPUTS
STB1 STB2 STB3 STB4 Input Register and SRO Operation
CLR LD1 LD2
DAC Register Operation
0
1
1
0
0
0
Serial Data Bit on SRI Loaded into Input
Register, MSB First
Data Bit or SRI Appears on SRO Pin
After 16 Clocked Bits
0
X
X
Reset DAC Register and Input Register to
All 0s (LTC1596) or to Midscale (LTC1596-1)
(Asynchronous Operation)
0
0
0
0
0
1
1
1
1
X
X
1
No DAC Register Operation
1
X
X
X
X
1
X
X
X
X
0
X
X
X
X
1
No Input Register Operation
No SRO Operation
1
0
0
Load DAC Register with the Contents of Input
Register
W
BLOCK DIAGRA
(LTC1595)
56k
56k
V
R
FB
1
2
REF
7k
56k
56k
56k
56k
56k
56k
56k
112k
112k
112k
112k
3
4
OUT1
GND
V
8
DD
DECODER
D15
(MSB)
D14
D13
D12
D11
• • •
D0
(LSB)
DAC REGISTER
LOAD
LD
5
7
CLK
INPUT 16-BIT SHIFT REGISTER
IN
SRI
CLK
6
1595 BD
W U
W
TI I G DIAGRA
(LTC1595)
t
DH
t
DS
t
t
CH
CL
CLK INPUT
t
SRI
D0
LSB
PREVIOUS
WORD
D15
MSB
D14
D1
SRI
LD
t
ASB
t
LD
1595 TD
7
LTC1595/LTC1596/LTC1596-1
W
BLOCK DIAGRA
(LTC1596/LTC1596-1)
56k
56k
V
REF
R
FB
15
16
7k
56k
56k
56k
56k
56k
56k
56k
112k
112k
112k
112k
1
2
3
OUT1
OUT2
AGND
V
14
DD
DECODER
D15
CLR 13
D14
D13
D12
D11
• • •
D0
(LSB)
CLR
LOAD
(MSB)
5
9
LD1
LD2
DAC REGISTER
CLR
CLK
OUT
4
8
STB1
STB2
IN
SRI
INPUT 16-BIT SHIFT REGISTER
7
1596 BD
STB3 10
STB4
11
SRO
6
12
DGND
W U
W
TI I G DIAGRA
(LTC1596/LTC1596-1)
t
t
t
t
t
DS1 DH1
t
DS2 DH2
t
DS3 DH3
t
t
t
t
STB1
STB2
STB3
t
DS4 DH4
STROBE INPUT
STB1, STB2, STB4
(INVERT FOR STB3)
t
t
t
t
STB4
STB1
STB2
STB3
STB4
D15
MSB
D0
LSB
SRI
D14
D13
D1
t
t
ASB
SRI
t
t
LD1
LD2
LD1, LD2
t
PD
t
PD1
D15 (MSB)
PREVIOUS WORD
D14
D13
D0 (LSB)
PREVIOUS WORD
D15 (MSB)
CURRENT WORD
SRO
PREVIOUS WORD PREVIOUS WORD
1596 TD
8
LTC1595/LTC1596/LTC1596-1
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APPLICATIONS INFORMATION
Description
The16-pinLTC1596canoperateinidenticalfashiontothe
LTC1595 but offers additional pins for flexibility. Four
clock pins are available STB1, STB2, STB3 and STB4.
STB1, STB2 and STB4 operate like the CLK pin of the
LTC1595, capturing data on their rising edges. STB3
captures data on its falling edge (see Truth Table 1).
TheLTC1595/LTC1596are16-bitmultiplyingDACswhich
haveserialinputsandcurrentoutputs.Theyuseprecision
R/2R technology to provide exceptional linearity and
stability. The devices operate from a single 5V supply and
provide ±10V reference input and voltage output ranges
when used with an external op amp. These devices have
a proprietary deglitcher that reduces glitch impulse to
1nV-s over a 0V to 10V output range.
The LTC1596 has two load pins, LD1 and LD2. To load
data, both pins must be taken low. If one of the pins is
grounded,theotherpinwilloperateidenticallytoLTC1595’s
LD pin. An asynchronous clear input (CLR) resets the
LTC1596 to zero scale (and the LTC1596-1 to midscale)
when pulled low (see Truth Table 2).
Serial I/O
The LTC1595/LTC1596 have SPI/MICROWIRE compat-
ible serial ports that accept 16-bit serial words. Data is
accepted MSB first and loaded with a load pin.
The LTC1596 also has a data output pin SRO that can be
connected to the SRI input of another DAC to daisy-chain
multiple DACs on one 3-wire interface (see LTC1596
Timing Diagram).
The 8-pin LTC1595 has a 3-wire interface. Data is shifted
into the SRI data input on the rising edge of the CLK pin.
At the end of the data transfer, data is loaded into the DAC
register by pulling the LD pin low (see LTC1595 Timing
Diagram).
Unipolar (2-Quadrant Multiplying) Mode
(VOUT = 0V to –VREF
)
The LTC1595/LTC1596 can be used with a single op amp
to provide 2-quadrant multiplying operation as shown in
Figure 1. With a fixed –10V reference, the circuits shown
give a precision unipolar 0V to 10V output swing.
V
REF
–10V TO 10V
5V
0.1µF
13
14
15
16
10
4
7
5
6
9
8
11
33pF
R
V
V
REF
CLR
STB3
STB1
SRI
LD1
SRO
LD2
DD
FB
–
1
µP
OUT1
V
OUT
LT1001
LTC1596
0V TO –V
REF
+
OUT2
2
STB2
STB4
DGND
12
AGND
3
1595/96 F01a
TO NEXT DAC
FOR DAISY-CHAINING
V
5V
REF
(a)
–10V TO 10V
0.1µF
Table 1. Unipolar Binary Code Table
DIGITAL INPUT
8
1
2
R
FB
33pF
V
V
DD
CLK
REF
7
6
5
ANALOG OUTPUT
BINARY NUMBER
IN DAC REGISTER
–
3
VOUT
OUT1
SRI
LD
µP
LTC1595
V
OUT
0V TO –V
LT1001
MSB
LSB
REF
+
GND
4
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
–VREF (65,535/65,536)
–VREF (32,768/65,536) = –VREF/2
–VREF (1/65,536)
1595/96 F01b
0V
(b)
Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to –VREF
9
LTC1595/LTC1596/LTC1596-1
U
W U U
APPLICATIONS INFORMATION
Bipolar (4-Quadrant Multiplying) Mode
INLdegradationand0.15LSBDNLdegradationwitha10V
full-scale range. The main effects of op amp offset will be
a degradation of zero-scale error equal to the op amp
offset, and a degradation of full-scale error equal to twice
the op amp offset. For example, the same 500µV op amp
offset will cause a 3.3LSB zero-scale error and a 6.5LSB
full-scale error with a 10V full-scale range.
(VOUT = –VREF to VREF
)
The LTC1595/LTC1596 can be used with a dual op amp
and three external resistors to provide 4-quadrant multi-
plying operation as shown in Figure 2 (last page). With a
fixed 10V reference, the circuits shown give a precision
bipolar –10V to 10V output swing. Using the LTC1596-1
willcausethepower-onresetandclearpintoresettheDAC
to midscale (bipolar zero).
Op amp input bias current (IBIAS) contributes only a zero-
scale error equal to IBIAS(RFB) = IBIAS(RREF) = IBIAS(7k).
Table 2 shows a selection of LTC op amps which are
suitable for use with the LTC1595/LTC1596. For a thor-
ough discussion of 16-bit DAC settling time and op amp
selection, refer to Application Note 74, “Component and
MeasurementAdvancesEnsure16-BitDACSettlingTime.”
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC1595/LTC1596, thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding should be used. IOUT2 (LTC1596) and GND
(LTC1595) must be tied to the star ground with as low a
resistance as possible.
Op amp offset will contribute mostly to output offset and
gain and will have minimal effect on INL and DNL. For
example, a 500µV op amp offset will cause about 0.55LSB
Table 2. 16-Bit Settling Time for Various Amplifiers Driven by the LT1595 DAC. LT1468 (Shaded) Offers Fastest Settling Time While
Maintaining Accuracy Over Temperature
CONSERVATIVE SETTLING TIME
AND COMPENSATION VALUE
AMPLIFIER
LT1001
LT1007
LT1013
LT1077
LT1097
LT1112
LT1178
LT1468
COMMENTS
120µs
19µs
100pF
100pF
150pF
100pF
75pF
Good Low Speed Choice
I Gives ≈1LSB Error at 25°C
B
75µs
≈1LSB Error Due to V over Temperature
OS
200µs
120µs
120µs
450µs
2.5µs
Good Low Speed Choice
100pF
100pF
30pF
Good Low Speed Choice Dual
Low Power Dual
Fastest Settling with 16-Bit Performance
10
LTC1595/LTC1596/LTC1596-1
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
8
1
7
6
5
0.065
(1.651)
TYP
0.255 ± 0.015*
(6.477 ± 0.381)
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
–0.015
2
4
3
0.325
N8 1197
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
+0.889
8.255
(
)
(0.457 ± 0.076)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
(0.254 – 0.508)
7
5
8
6
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
SO8 0996
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
0.300 – 0.325
0.130 ± 0.005
0.045 – 0.065
(7.620 – 8.255)
(3.302 ± 0.127)
(1.143 – 1.651)
14
12
10
9
15
13
11
16
0.020
(0.508)
MIN
0.255 ± 0.015*
(6.477 ± 0.381)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
2
1
3
4
6
8
5
7
0.325
–0.015
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
N16 1197
+0.889
8.255
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
SW Package 16-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620)
0.291 – 0.299**
(7.391 – 7.595)
0.398 – 0.413*
(10.109 – 10.490)
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
15 14
12
10
9
16
13
11
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
TYP
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.009 – 0.013
NOTE 1
(0.229 – 0.330)
0.014 – 0.019
0.004 – 0.012
(0.102 – 0.305)
0.016 – 0.050
(0.356 – 0.482)
TYP
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
S16 (WIDE) 0396
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
2
3
5
7
8
1
4
6
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC1595/LTC1596/LTC1596-1
U
TYPICAL APPLICATIONS
R2
20k
R3
20k
V
REF
–10V TO 10V
5V
0.1µF
13
14
15
16
10
4
7
5
6
9
8
11
33pF
R
V
V
REF
CLR
STB3
STB1
SRI
LD1
SRO
LD2
DD
FB
–
1
2
R1
10k
µP
OUT1
OUT2
–
1/2 LT1112
+
LTC1596-1
(20k ÷ 2)
V
OUT
–V
1/2 LT1112
+
TO V
REF
REF
STB2
STB4
DGND
12
AGND
3
RESISTORS: CADDOCK T914-20K-010-02
(OR EQUIVALENT) 20k, 0.01%, TC TRACK = 2ppm/°C
TO NEXT DAC
FOR DAISY-CHAINING
1595/96 F02a
(a)
R3
20k
R2
20k
V
REF
Table 3. Bipolar Offset Binary Code Table
–10V TO 10V
5V
DIGITAL INPUT
ANALOG OUTPUT
BINARY NUMBER
VOUT
0.1µF
8
1
2
R
FB
IN DAC REGISTER
33pF
V
V
DD
REF
MSB
LSB
7
CLK
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
V
V
0V
REF (32,767/32,768)
REF (1/32,768)
6
–
3
R1
SRI
LTC1595
OUT1
µP
10k
5
–
LD
1/2 LT1112
+
GND
4
(20k ÷ 2)
V
–VREF (1/32,768)
–VREF
OUT
REF
1/2 LT1112
+
–V
TO V
REF
1595/96 F02b
(b)
Figure 2. Bipolar Operation (4-Quadrant Multiplication) VOUT = –VREF to VREF
RELATED PARTS
PART NUMBER
DACs
DESCRIPTION
COMMENTS
LTC1590
LTC1597
LTC1650
LTC1658
LTC7543/LTC8143/LTC8043
ADCs
Dual Serial I/O Multiplying I
12-Bit DAC
16-Pin SO and PDIP, SPI Interface
Low Glitch, ±1LSB Maximum INL, DNL
Low Noise and Glitch Rail-to-Rail V
Low Power, 8-Lead MSOP Rail-to-Rail V
Clear Pin and Serial Data Output (LTC8143)
OUT
Parallel 16-Bit Current Output DAC
Serial 16-Bit Voltage Output DAC
Serial 14-Bit Voltage Output DAC
OUT
OUT
Serial I/O Multiplying I
12-Bit DACs
OUT
LTC1418
LTC1604
LTC1605
LTC2400
Op Amps
LT1001
14-Bit, 200ksps 5V Sampling ADC
16-Bit, 333ksps Sampling ADC
Single 5V, 16-Bit 100ksps ADC
24-Bit, ∆∑ ADC in SO-8
16mW Dissipation, Serial and Parallel Outputs
±2.5V Input, SINAD = 90dB, THD = 100dB
Low Power, ±10V Inputs
1ppm (4ppm) Offset (Full Scale), Internal 50Hz/60Hz Notches
Precision Operational Amplifier
Low Offset, Low Drift
LT1112
LT1468
Dual Low Power, Precision Picoamp Input Op Amp
90MHz, 22V/µs, 16-Bit Accurate Op Amp
Low Offset, Low Drift
Precise, 1µs Settling to 0.0015%
References
LT1236
LT1634
Precision Reference
Micropower Reference
Ultralow Drift, 5ppm/°C, High Accuracy 0.05%
Ultralow Drift, 10ppm/°C, High Accuracy 0.05%
159561fa LT/TP 0299 2K REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
LINEAR TECHNOLOGY CORPORATION 1997
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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