LTC1286CS8#TRPBF [Linear]
LTC1286 - Micropower Sampling 12-Bit A/D Converters In S0-8 Packages; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LTC1286CS8#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1286 - Micropower Sampling 12-Bit A/D Converters In S0-8 Packages; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 转换器 模数转换器 光电二极管 |
| 文件： | 总24页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1286/LTC1298
Micropower Sampling
12-Bit A/D Converters In
S0-8 Packages
U
DESCRIPTION
FEATURES
■
The LTC1286/LTC1298 are micropower, 12-bit, succes-
sive approximation sampling A/D converters. They typi-
cally draw only 250µA of supply current when converting
and automatically power down to a typical supply current
of 1nA whenever they are not performing conversions.
They are packaged in 8-pin SO packages and operate on
5V to 9V supplies. These 12-bit, switched-capacitor, suc-
cessive approximation ADCs include sample-and-holds.
The LTC1286 has a single differential analog input. The
LTC1298 offers a software selectable 2-channel MUX.
12-Bit Resolution
■
8-Pin SOIC Plastic Package
■
Low Cost
■
Low Supply Current: 250µA Typ.
■
Auto Shutdown to 1nA Typ.
■
Guaranteed ±3/4LSB Max DNL
■
Single Supply 5V to 9V Operation
■
On-Chip Sample-and-Hold
■
60µs Conversion Time
■
Sampling Rates:
12.5 ksps (LTC1286)
11.1 ksps (LTC1298)
On-chip serial ports allow efficient data transfer to a wide
rangeofmicroprocessorsandmicrocontrollersoverthree
wires.This,coupledwithmicropowerconsumption,makes
remote location possible and facilitates transmitting data
through isolation barriers.
■
I/O Compatible with SPI, Microwire, etc.
■
Differential Inputs (LTC1286)
2-Channel MUX (LTC1298)
■
■
3V Versions AvailabU le: LTC1285/LTC1288
These circuits can be used in ratiometric applications or
with an external reference. The high impedance analog
inputs and the ability to operate with reduced spans (to
1.5V full scale) allow direct connection to sensors and
transducersinmanyapplications, eliminatingtheneedfor
gain stages.
APPLICATIONS
■
Battery-Operated Systems
■
Remote Data Acquisition
■
Battery Monitoring
■
Handheld Terminal Interface
■
Temperature Measurement
Isolated Data Acquisition
■
U
TYPICAL APPLICATIONS N
25µW, S0-8 Package, 12-Bit ADC
Supply Current vs Sample Rate
1000
Samples at 200Hz and Runs Off a 5V Supply
T
= 25°C
A
V
= V
= 5V
= 200kHz
CC
REF
4.7µF
5V
f
CLK
100
10
1
MPU
(e.g., 8051)
1
2
3
4
8
CC
V
V
P1.4
P1.3
P1.2
REF
7
ANALOG INPUT
0V TO 5V RANGE
+IN
CLK
LTC1286
6
5
–IN
D
OUT
SERIAL DATA LINK
GND
CS/SHDN
LTC1286/98 • TA01
0.1k
1k
10k
100k
SAMPLE FREQUENCY (Hz)
LTC1286/98 • TA02
1
LTC1286/LTC1298
W W
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ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
Supply Voltage (VCC) to GND................................... 12V
Voltage
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1286C/LTC1298C............................. 0°C to 70°C
LTC1286I/LTC1298I........................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
Analog and Reference ................ –0.3V to VCC + 0.3V
Digital Inputs......................................... –0.3V to 12V
Digital Output ............................. –0.3V to VCC + 0.3V
W
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PACKAGE/ORDER INFORMATION
TOP VIEW
TOP VIEW
ORDER PART
ORDER PART
V
1
2
3
4
8
7
6
5
1
2
3
4
V
V
CC
V
8
7
6
5
NUMBER
NUMBER
CC
REF
REF
CLK
D
+IN
–IN
+IN
–IN
CLK
D
LTC1286CS8
LTC1286IS8
LTC1286CN8
LTC1286IN8
OUT
OUT
GND
CS/SHDN
CS/SHDN
GND
N8 PACKAGE
8-LEAD PLASTIC DIP
S8 PACKAGE
8-LEAD PLASTIC SOIC
PART MARKING
TJMAX = 150°C, θJA = 130°C/W
T
JMAX = 150°C, θJA = 175°C/W
1286C
1286I
TOP VIEW
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
CS/SHDN
CH0
1
2
3
4
8
7
6
5
V
(V
)
1
2
3
4
V
(V
)
CS/SHDN
CH0
8
7
6
5
CC REF
CC REF
CLK
D
CLK
D
LTC1298CS8
LTC1298IS8
LTC1298CN8
LTC1298IN8
CH1
CH1
OUT
OUT
D
GND
GND
D
IN
IN
PART MARKING
N8 PACKAGE
8-LEAD PLASTIC DIP
S8 PACKAGE
8-LEAD PLASTIC SOIC
1298C
1298I
TJMAX = 150°C, θJA = 175°C/W
TJMAX = 150°C, θJA = 130°C/W
Consult factory for military grade parts.
W W U
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RECOM ENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage (Note 3)
LTC1286
LTC1298
4.5
4.5
9.0
5.5
V
V
CC
f
t
Clock Frequency
Total Cycle Time
V
= 5V
CC
(Note 4)
200
kHz
CLK
CYC
LTC1286, f
LTC1298, f
= 200kHz
= 200kHz
80
90
µs
µs
CLK
CLK
t
t
Hold Time, D After CLK↑
V = 5V
CC
150
ns
hDI
IN
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
LTC1286, V = 5V
LTC1298, V = 5V
2
2
µs
µs
suCS
CC
CC
t
t
t
t
t
Setup Time, D Stable Before CLK↑
V
V
V
V
= 5V
= 5V
= 5V
= 5V
400
2
ns
µs
µs
µs
suDI
IN
CC
CC
CC
CC
CLK High Time
WHCLK
WLCLK
WHCS
WLCS
CLK Low Time
2
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
2
LTC1286, f
LTC1298, f
= 200kHz
= 200kHz
75
85
µs
µs
CLK
CLK
2
LTC1286/LTC1298
U
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CONVERTER AND MULTIPLEXER CHARACTERISTICS (Note 5)
LTC1286
LTC1298
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
V
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
●
●
●
12
12
(Note 6)
±3/4
±1/4
3/4
±2
±3/4
±3
±3/4
±1/4
3/4
±2
±3/4
±3
Gain Error
±2
±8
±2
±8
–0.05V to V + 0.05V
Analog Input Range
(Note 7 and 8)
CC
1.5V to V + 0.05V
REF Input Range (LTC1286)
(Notes 7, 8, and 9)
4.5 ≤ V ≤ 5.5V
V
V
CC
CC
1.5V to 5.55V
5.5V < V ≤ 9V
CC
Analog Input Leakage Current (Note 10)
●
±1
±1
µA
U
(Note 5)
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
●
●
●
●
2
IH
IL
CC
CC
IN
0.8
2.5
V
I
I
= V
µA
µA
IH
IL
CC
= 0V
–2.5
IN
V
V
V
= 4.75V, I = 10µA
= 4.75V, I = 360µA
●
●
4.0
2.4
4.64
4.62
V
V
OH
CC
CC
O
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
V
= 4.75V, I = 1.6mA
●
●
0.4
V
µA
OL
CC
O
I
I
I
CS = High
±3
OZ
V
V
= 0V
–25
45
mA
mA
SOURCE
SINK
OUT
OUT
= V
CC
R
Reference Input Resistance
(LTC1286)
CS = V
CS = GND
5000
55
MΩ
kΩ
REF
CC
I
I
Reference Current (LTC1286)
CS = V
●
●
●
0.001
90
90
2.5
140
140
µA
µA
µA
REF
CC
t
t
≥ 640µs, f
= 80µs, f
≤ 25kHz
CLK
CYC
CYC
= 200kHz
CLK
Supply Current
CS = V
●
0.001 ±3.0
µA
CC
CC
LTC1286, t
LTC1286, t
≥ 640µs, f
≤ 25kHz
= 200kHz
●
●
200
250
400
500
µA
µA
CYC
CYC
CLK
= 80µs, f
CLK
LTC1298, t
LTC1298, t
≥ 720µs, f
≤ 25kHz
= 200kHz
●
●
290
340
490
640
µA
µA
CYC
CYC
CLK
= 90µs, f
CLK
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DYNAMIC ACCURACY
fSMPL = 12.5kHz (LTC1286), fSMPL = 11.1kHz (LTC1298) (Note 5)
SYMBOL
S/(N +D)
THD
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
dB
Signal-to-Noise Plus Distortion Ratio
Total Harmonic Distortion (Up to 5th Harmonic)
Spurious-Free Dynamic Range
Peak Harmonic or Spurious Noise
1kHz/7kHz Input Signal
1kHz/7kHz Input Signal
1kHz/7kHz Input Signal
1kHz/7kHz Input Signal
71/68
–84/–80
90/86
dB
SFDR
dB
–90/–86
dB
3
LTC1286/LTC1298
(Note 5)
AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
f
Analog Input Sample Time
Maximum Sampling Frequency
See Operating Sequence
1.5
CLK Cycles
SMPL
LTC1286
LTC1298
●
●
12.5
11.1
kHz
kHz
SMPL(MAX)
t
t
t
t
t
t
t
Conversion Time
See Operating Sequence
See Test Circuits
12
250
135
75
CLK Cycles
CONV
dDO
dis
en
Delay Time, CLK↓ to D
Data Valid
●
●
●
600
300
200
ns
ns
ns
ns
ns
ns
OUT
Delay Time, CS↑ to D
Hi-Z
See Test Circuits
OUT
Delay Time, CLK↓ to D
Enable
See Test Circuits
OUT
Time Output Data Remains Valid After CLK↓
C
LOAD
= 100pF
230
20
hDO
f
D
D
Fall Time
See Test Circuits
See Test Circuits
●
●
75
75
OUT
OUT
Rise Time
20
r
C
IN
Input Capacitance
Analog Inputs, On Channel
Analog Inputs, Off Channel
Digital Input
20
5
5
pF
pF
pF
Note 7: Two on-chip diodes are tied to each reference and analog input
The
●
denotes specifications which apply over the full operating
which will conduct for reference or analog input voltages one diode drop
temperature range.
below GND or one diode drop above V . This spec allows 50mV forward
CC
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: These devices are specified at 5V. For 3V specified devices, see
LTC1285 and LTC1288.
Note 4: Increased leakage currents at elevated temperatures cause the S/H
to droop, therefore it is recommended that f
75kHz at 70° and f
bias of either diode for 4.5V ≤ V ≤ 5.5V. This means that as long as the
CC
reference or analog input does not exceed the supply voltage by more than
50mV the output code will be correct. To achieve an absolute 0V to 5V
input voltage range will therefore require a minimum supply voltage of
4.950V over initial tolerance, temperature variations and loading. For 5.5V
< V ≤ 9V, reference and analog input range cannot exceed 5.55V. If
CC
≥ 120kHz at 85°C, f
≥
CLK
CLK
reference and analog input range are greater than 5.55V, the output code
≥ 1kHz at 25°C.
CLK
will not be guaranteed to be correct.
Note 5: V = 5V, V = 5V and CLK = 200kHz unless otherwise specified.
Note 6: Linearity error is specified between the actual end points of the
A/D transfer curve.
CC
REF
Note 8: The supply voltage range for the LTC1286 is from 4.5V to 9V, but
the supply voltage range for the LTC1298 is only from 4.5V to 5.5V.
Note 9: Recommended operating conditions
Note 10: Channel leakage current is measured after the channel selection.
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TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Supply Current vs Clock
Rate with CS High and CS Low
Supply Current vs Sample Rate
Supply Current vs Temperature
1000
100
10
35
30
25
20
15
450
400
T
= 25°C
= V
T
= 25°C
= V
A
CC
A
CC
T
= 25°C
A
V
= 5V
REF
V
= 5V
REF
V
f
= V
= 5V
CC
REF
= 200kHz
f
= 200kHz
CLK
CLK
350
LTC1298
LTC1298 f
=11.1kHz
=12.5kHz
LTC1286
SMPL
CS = 0
(AFTER CONVERSION)
10
300
250
200
5
1
LTC1286 f
0.002
0
SMPL
65
CS = V
CC
1
0.1k
1k
10k
100k
–55 –35 –15
5
45
85 105 125
25
200
100 120 140 160 180
1
60
20 40
80
SAMPLE RATE (kHz)
TEMPERATURE (°C)
FREQUENCY (kHz)
LT1286/98 G03
LT1286/98 G04
LT1286/98 G01
4
LTC1286/LTC1298
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TYPICAL PERFORMANCE CHARACTERISTICS
Reference Current vs
Sample Rate (LTC1286)
Change in Offset vs
Reference Voltage
Reference Current vs Temperature
100
90
80
70
60
50
40
30
20
10
0
3
95
T
= 25°C
A
T
= 25°C
= 5V
= 200kHz
= 12.5kHz
V
f
= V
SMPL
= 5V
= 12.5kHz
A
CC
CC
REF
V
V
= 5V
CC
REF
CLK
V
f
94.5
2.5
2
= 5V
= 200kHz
f
= 200kHz
CLK
SMPL
CLK
= 25°C
f
f
T
A
94
93.5
93
1.5
1
92.5
92
0.5
0
0
4
6
8
10
12
14
–55 –35 –15
5
25 45 65 85 105 125
2
3.5
4
1
1.5
2
2.5
3
4.5
5
TEMPERATURE (°C)
FREQUENCY (kHz)
REFERENCE VOLTAGE (V)
LT1286/98 G07
LT1286/98 G06
LT1286/98 G08
Change In Linearity vs
Reference Voltage
Change In Gain vs
Reference Voltage
Change in Offset vs Temperature
–0.5
–0.45
–0.4
–0.35
–0.3
–.25
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
0
-0.5
-1
T
A
= 25°C
T
= 25°C
= 5V
A
CC
V
= 5V
V
f
CC
f
f
= 200kHz
= 12.5kHz
= 200kHz
CLK
SMPL
CLK
SMPL
f
= 12.5kHz
1.5
-2
–0.2
–0.15
–0.1
–0.05
0
V
= V
= 200kHz
= f
= 5V
CC
REF
-2.5
-3
f
f
CLK
SMPL SMPL (MAX)
3.5
4
1
1.5
2
2.5
3
4.5
5
3.5
4
1
1.5
2
2.5
3
4.5
5
45
TEMPERATURE (°C)
65
-55 -35 -15
5
25
85
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
LT1286/98 G10
LT1286/98 G11
LT1286/98 G09
Peak-to-Peak ADC Noise vs
Reference Voltage
Effective Bits and S/(N + D)
vs Input Frequency
Differential Nonlinearity vs Code
1.0
0.80
0.60
0.40
2
1.5
1
12
11
74
68
T
= 25°C
CC
A
V
= 5V
10
9
62
56
50
44
38
f
= 200kHz
CLK
8
0.20
0.00
7
6
5
–0.20
–0.40
–0.60
4
3
0.5
0
T
= 25°C
A
V
= 5V
CC
2
1
f
f
= 200kHz
= 12.5kHz
CLK
SMPL
–0.80
–1.0
0
0
2048
4096
3
4
1
5
2
1
10
100
1000
CODE
REFERENCE VOLTAGE (V)
INPUT FREQUENCY (kHz)
LTC 1286/98 G20
LT1286/98 G15
5
LTC1286/LTC1298
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TYPICAL PERFORMANCE CHARACTERISTICS
Spurious Free Dynamic Range
vs Frequency
Attenuation vs
Input Frequency
S/(N+D) vs Input Level
100
90
0
80
70
T
= 25°C
A
10
V
f
= V
= 5V
CC
REF
= 1kHz
20
30
80
IN
f
= 12.5kHz
60
50
SMPL
70
60
50
40
50
40
30
20
10
40
30
20
10
0
60
70
T
= 25°C
80
A
T
= 25°C
A
V
= V
= 5V
CC
REF
= 12.5kHz
V
= V
= 5V
CC
REF
= 12.5kHz
90
f
SMPL
f
SMPL
100
0
1k
10k
100k
1M
1
10k
100k
1M
10M
–40
–30
–20
–10
0
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT LEVEL (dB)
LTC 1286/98 G27
LTC 1286/98 G26
LT1286/98 G25
Power Supply Feedthrough
vs Ripple Frequency
4096 Point FFT Plot
Intermodulation Distortion
0
0
0
T
V
f
= 25°C
= V
T
= 25°C
= V
= 5kHz
= 6kHz
T
= 25°C
= 5V (V
A
CC
A
CC
A
CC
= 5V
REF
V
f
= 5V
REF
V
V
f
= 20mV)
RIPPLE
–20
–20
= 5kHz
= 5V
IN
1
2
REF
CLK
f
= 200kHz
= 12.5kHz
f
f
= 200kHz
CLK
–40
–60
f
–40
–60
= 12.5kHz
SMPL
SMPL
–50
–80
–80
–100
–120
–100
–120
–140
–100
–140
4
6
7
0
1
2
3
5
1
10
100
1000
10000
4
6
7
0
1
2
3
5
FREQUENCY (kHz)
RIPPLE FREQUENCY (kHz)
FREQUENCY (kHz)
LTC 1286/98 G22
LTC 1286/98 G21
LTC 1286/98 G24
Maximum Clock Frequency vs
Source Resistance
Sample and Hold Aquisition
Time vs Source Resistance
Maximum Clock Frequency vs
Supply Voltage
10000
1000
100
300
250
200
150
100
50
300
290
280
270
260
T
= 25°C
= V
T
= 25°C
= V
A
CC
A
CC
V
= 5V
REF
V
= 5V
REF
V
IN
+INPUT
–INPUT
+
–
R
SOURCE
R
SOURCE
V
IN
+INPUT
–INPUT
T
= 25°C
A
V
= V
= 5V
CC
REF
250
0
0.1
1
10
100
1000 10000
0.1
1
10
5
6
7
8
9
SOURCE RESISTANCE (Ω)
SOURCE RESISTANCE (kΩ)
SUPPLY VOLTAGE (V)
LT1286/98 G16
LT1286/98 G12
LT1286/98 G13
6
LTC1286/LTC1298
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TYPICAL PERFORMANCE CHARACTERISTICS
Digital Input Logic Threshold
vs Supply Voltage
Minimum Clock Frequency
for 0.1 LSB Error vs Temperature
Input Channel Leakage Current
vs Temperature
1000
100
10
200
150
100
50
3
2
1
T
= 25°C
V
CC
= V
= 5V
REF
A
V
V
= 5V
REF
CC
= 5V
ON CHANNEL
1
OFF CHANNEL
0.1
0.01
0
3
4
5
6
7
8
9
–15
5
0
120
140
–55
25
45
65 85
–60 –40 –20
20 40 60 80 100
–35
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
LTC 1286/98 G17
LT1286/98 • G14
1196/98 G19
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PIN FUNCTIONS
LTC1286
LTC1298
VREF (Pin 1): Reference Input. The reference input defines
the span of the A/D converter.
IN+ (Pin 2): Positive Analog Input.
IN– (Pin 3): Negative Analog Input.
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1298. A logic high on this input
disables and powers down the LTC1298.
CH0 (Pin 2): Analog Input.
CH1 (Pin 3): Analog Input.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CS/SHDN (Pin 5): Chip Select Input. A logic low on this
input enables the LTC1286. A logic high on this input
disables and powers down the LTC1286.
DIN (Pin 5): Digital Data Input. The multiplexer address is
shifted into this input.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK(Pin7):ShiftClock. Thisclocksynchronizestheserial
data transfer and determines conversion speed.
CLK (Pin 7): Shift Clock. This clock synchronizes the
serial data transfer and determines conversion speed.
VCC (Pin 8): Power Supply Voltage. This pin provides
power to the A/D converter. It must be kept free of noise
and ripple by bypassing directly to the analog ground
plane.
VCC/VREF (Pin 8): Power Supply and Reference Voltage.
This pin provides power and defines the span of the A/D
converter. It must be kept free of noise and ripple by
bypassing directly to the analog ground plane.
7
LTC1286/LTC1298
W
BLOCK DIAGRAM
CS/SHDN
CLK
(D
IN
)
V
(V /V )
CC CC REF
BIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
D
OUT
+
IN (CH0)
C
SAMPLE
–
+
SAR
–
IN (CH1)
MICROPOWER
COMPARATOR
CAPACITIVE DAC
V
REF
PIN NAMES IN PARENTHESES
REFER TO THE LTC1298
GND
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
1.4V
V
V
OH
OL
D
OUT
3k
D
OUT
TEST POINT
t
t
LTC1286/98 • TC02
r
100pF
f
LTC1286/98 • TC01
Voltage Waveforms for DOUT Delay Times, tdDO
Load Circuit for tdis and ten
TEST POINT
3k
CLK
V
IL
t
V
t
WAVEFORM 2, t
CC dis
en
dDO
D
OUT
V
OH
t
dis
WAVEFORM 1
100pF
D
OUT
V
OL
LTC1286/98 • TC04
LTC1286/98 • TC03
8
LTC1286/LTC1298
TEST CIRCUITS
Voltage Waveforms for tdis
Voltage Waveforms for ten
LTC1286
V
IH
CS
CS
D
OUT
90%
10%
WAVEFORM 1
(SEE NOTE 1)
1
2
CLK
t
dis
D
OUT
WAVEFORM 2
(SEE NOTE 2)
B11
D
OUT
V
OL
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
t
en
LTC1286/98 • TC06
LTC1286/98 • TC05
Voltage Waveforms for ten
LTC1298
CS
START
D
IN
1
2
3
4
CLK
B11
D
OUT
V
OL
t
en
LTC1286/98 • TC07
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OVERVIEW
whiletheLTC1298operatesfroma4.5Vto5.5Vsupply.
The LTC1286 and LTC1298 are micropower, 12-bit, suc-
cessive approximation sampling A/D converters. The
LTC1286 typically draws 250µA of supply current when
sampling at 12.5kHz while the LTC1298 nominally con-
sumes 350µA of supply current when sampling at
11.1 kHz. The extra 100µA of supply current on the
LTC1298 comes from the reference input which is inten-
tionally tied to the supply. Supply current drops linearly as
the sample rate is reduced (see Supply Current vs Sample
Rate). The ADCs automatically power down when not
performing conversions, drawing only leakage current.
They are packaged in 8-pin SO and DIP packages. The
LTC1286 operates on a single supply from 4.5V to 9V,
Both the LTC1286 and the LTC1298 contain a 12-bit,
switched-capacitor ADC, a sample-and-hold, and a
serial port (see Block Diagram). Although they share
the same basic design, the LTC1286 and LTC1298
differ in some respects. The LTC1286 has a differential
input and has an external reference input pin. It can
measure signals floating on a DC common-mode volt-
age and can operate with reduced spans to 1V. Reduc-
ing the spans allows it to achieve 244µV resolution. The
LTC1298 has a two-channel input multiplexer and can
convert either channel with respect to ground or the
difference between the two. The reference input is tied
to the supply pin.
9
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SERIAL INTERFACE
A/D conversion result is output on the DOUT line. Bringing
CS high resets the LTC1286 for the next data exchange.
The 2-channel LTC1298 communicates with micropro-
cessors and other external circuitry via a synchronous,
half duplex, 4-wire serial interface. The single channel
LTC1286 uses a 3-wire interface (see Operating Sequence
in Figures 1 and 2).
The LTC1298 first receives input data and then transmits
back the A/D conversion result (half duplex). Because of
the half duplex operation, DIN and DOUT may be tied
together allowing transmission over just 3 wires: CS, CLK
and DATA (DIN/DOUT).
Data Transfer
Datatransferisinitiatedbyafallingchipselect(CS)signal.
After CS falls the LTC1298 looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
DIN input which configures the LTC1298 and starts the
conversion. After one null bit, the result of the conversion
is output on the DOUT line. At the end of the data exchange
CS should be brought high. This resets the LTC1298 in
preparation for the next data exchange.
The CLK synchronizes the data transfer with each bit being
transmitted on the falling CLK edge and captured on the
risingCLKedgeinbothtransmittingandreceiving systems.
The LTC1286 does not require a configuration input word
and has no DIN pin. A falling CS initiates data transfer as
shown in the LTC1286 operating sequence. After CS falls
the second CLK pulse enables DOUT. After one null bit the
t
CYC
CS
POWER
DOWN
t
suCS
CLK
OUT
NULL
HI-Z
NULL
HI-Z
D
BIT
B11
B10 B9 B8
BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
(MSB)
t
SMPL
t
t
DATA
CONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY.
t
CYC
CS
t
POWER DOWN
suCS
CLK
NULL
BIT
HI-Z
HI-Z
D
OUT
B10
B9
B11*
B8
B3 B2 B1
B2 B3 B4 B5 B6 B7
B11 B10 B9 B8 B7 B6 B5 B4
(MSB)
B0 B1
t
SMPL
t
t
DATA
CONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY.
t
: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
DATA
LTC1286/98 • F01
BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
Figure 1. LTC1286 Operating Sequence
10
LTC1286/LTC1298
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CS
D
1
D
2
IN
IN
D
1
D
2
OUT
OUT
SHIFT MUX
ADDRESS IN
1 NULL BIT SHIFT A/D CONVERSION
RESULT OUT
LTC1096/98 • AI01
MSB-First Data (MSBF = 0)
t
CYC
CS
t
POWER DOWN
suCS
CLK
ODD/
SIGN
START
D
IN
DON'T CARE
MSBF
SGL/
DIFF
NULL
HI-Z
HI-Z
BIT
D
OUT
B10
B2 B3 B4 B5 B6 B7 B8 B9
B11*
B3 B2 B1 B0 B1
B11 B10 B9 B8 B7 B6 B5 B4
(MSB)
t
SMPL
t
t
DATA
CONV
MSB-First Data (MSBF = 1)
t
CYC
CS
POWER
DOWN
t
suCS
CLK
ODD/
SIGN
START
D
IN
DON'T CARE
MSBF
SGL/
DIFF
NULL
HI-Z
HI-Z
D
OUT
BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
(MSB)
t
t
CONV
SMPL
t
DATA
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY.
t
: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
DATA
BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
LTC1286/98 • F02
Figure 2. LTC1298 Operating Sequence Example: Differential Inputs (CH+, CH–)
11
LTC1286/LTC1298
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Input Data Word
MSBF bit is a logical zero, LSB first data will follow the
normal MSB first data on the D
Sequence)
line. (see Operating
OUT
The LTC1286 requires no DIN word. It is permanently
configured to have a single differential input. The conver-
sion result appears on the DOUT line. The data format is
MSB first followed by the LSB sequence. This provides
easy interface to MSB or LSB first serial ports. For MSB
first data the CS signal can be taken high after B0 (see
Figure 1). The LTC1298 clocks data into the DIN input on
the rising edge of the clock. The input data words are
defined as follows:
Transfer Curve
TheLTC1286/LTC1298arepermanentlyconfiguredfor
unipolar only. The input span and code assignment for
this conversion type are shown in the following figures.
Transfer Curve
SGL/ ODD/
DIFF
START
MSBF
SIGN
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
MUX MSB FIRST/
ADDRESS LSB FIRST
LTC1096/9 • AI02
•
•
•
Start Bit
The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1298 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputs on the DIN pin are then ignored until the next CS
cycle.
0 0 0 0 0 0 0 0 0 0 0 1
V
IN
0 0 0 0 0 0 0 0 0 0 0 0
V
4096
REF
1LSB =
LTC1286/98 • AI04
Output Code
INPUT VOLTAGE
(V = 5.000V)
Multiplexer (MUX) Address
OUTPUT CODE
INPUT VOLTAGE
REF
4.99878V
1 1 1 1 1 1 1 1 1 1 1 1 1 1
V
V
– 1LSB
REF
REF
The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the + and
– signs in the selected row of the following tables. In
single-ended mode, all input channels are measured with
respect to GND.
4.99756V
1 1 1 1 1 1 1 1 1 1 1 1 1 0
– 2LSB
•
•
•
•
•
•
•
•
•
0.00122V
0V
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
LTC1286/98 • AI05
Operation with DIN and DOUT Tied Together
The LTC1298 can be operated with DIN and DOUT tied
together. This eliminates one of the lines required to
communicatetothemicroprocessor(MPU).Dataistrans-
mitted in both directions on a single wire. The processor
pin connected to this data line should be configurable as
either an input or an output. The LTC1298 will take control
of the data line and drive it low on the 4th falling CLK edge
after the start bit is received (see Figure 3). Therefore the
processor port line must be switched to an input before
this happens to avoid a conflict.
LTC1298 Channel Selection
MUX ADDRESS
CHANNEL #
SGL/DIFF ODD/SIGN
0
1
GND
–
–
1
1
0
0
0
1
0
1
+
SINGLE-ENDED
MUX MODE
+
–
+
+
–
DIFFERENTIAL
MUX MODE
LTC1096/8 • AI03
MSB First/LSB First (MSBF)
The output data of the LTC1298 is programmed for
MSB first or LSB first sequence using the MSBF bit.
When the MSBF bit is a logical one, data will appear on
line in MSB first format. Logical zeros will be
filled in indefinitely following the last data bit. When the
In the Typical Applications section, there is an example of
interfacingtheLTC1298withDIN andDOUT tiedtogetherto
the Intel 8051 MPU.
the D
OUT
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LTC1286/LTC1298
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MSBF BIT LATCHED
BY LTC1298
CS
1
2
3
4
CLK
DATA (D /D
)
START
SGL/DIFF
ODD/SIGN
MSBF
B11
B10
IN OUT
• • •
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1298
LTC1298 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
PROCESSOR MUST RELEASE
DATA LINE AFTER 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
LTC1298 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
LTC1286/98 F03
Figure 3. LTC1298 Operation with DIN and DOUT Tied Together
ACHIEVING MICROPOWER PERFORMANCE
input becomes high impedance at the end of each conver-
sion leaving the CLK running to clock out the LSB first data
or zeroes(seeFigures1and2).IftheCSisnotrunningrail-
to-rail, theinputlogicbufferwilldrawcurrent. Thiscurrent
may be large compared to the typical supply current. To
obtain the lowest supply current, bring the CS pin to
groundwhenitislowandtosupplyvoltagewhenitishigh.
With typical operating currents of 250µA and automatic
shutdown between conversions, the LTC1286/LTC1298
achieves extremely low power consumption over a wide
range of sample rates (see Figure 4). The auto-shutdown
allows the supply curve to drop with reduced sample rate.
Several things must be taken into account to achieve such
a low power consumption.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the DIN and CLK input have no effect on supply
current during this time. There is no need to stop DIN and
CLK with CS = high; they can continue to run without
drawing current.
1000
T
= 25°C
A
V
f
= V
= 5V
CC
REF
= 200kHz
CLK
100
10
1
LTC1298
LTC1286
Minimize CS Low Time
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transferring data as quickly as
possible, and then bringing it back high will result in the
lowest current drain. This minimizes the amount of time
the device draws power. After a conversion the ADC
automatically shuts down even if CS is held low (see
Figures 1 and 2). If the clock is left running to clock out
LSB-data or zero, the logic will draw a small current.
Figure 5 shows that the typical supply current with CS =
ground varies from 1µA at 1kHz to 35µA at 200kHz. When
CS = VCC, the logic is gated off and no supply current is
drawn regardless of the clock frequency.
0.1k
1k
10k
100k
SAMPLE RATE (kHz)
LT1286/98 G03
Figure 4. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate.
Shutdown
TheLTC1286/LTC1298areequippedwithautomaticshut-
down features. They draw power when the CS pin is low
and shut down completely when that pin is high. The bias
circuit and comparator powers down and the reference
13
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35
Clock Frequency
T
= 25°C
= V
A
30
25
20
15
V
= 5V
CC
REF
The maximum recommended clock frequency is 200kHz
for the LTC1286/LTC1298 running off a 5V supply. With
the supply voltage changing, the maximum clock fre-
quency for the devices also changes (see the typical curve
of Maximum Clock Rate vs Supply Voltage). If the maxi-
mum clock frequency is used, care must be taken to
ensure that the device converts correctly.
CS = 0
(AFTER CONVERSION)
10
5
1
0.002
0
CS = V
CC
Mixed Supplies
1
60
100 120 140 160 180 200
20 40
80
FREQUENCY (kHz)
It is possible to have a microprocessor running off a 5V
supply and communicate with the LTC1286 operating on
a 9V supply. The requirement to achieve this is that the
outputsofCSandCLKfromtheMPUhavetobeabletotrip
the equivalent inputs of the LTC1286 and the output of
DOUT from the LTC1286 must be able to toggle the
equivalent input of the MPU (see typical curve of Digital
Input Logic Threshold vs Supply Voltage). With the
LTC1286operatingona9Vsupply,theoutputofDOUT may
go between 0V and 9V. The 9V output may damage the
MPU running off a 5V supply. The way to get around this
possibility is to have a resistor divider on DOUT (Figure 6)
and connect the center point to the MPU input. It should
be noted that to get full shutdown, the CS input of the
LTC1286 must be driven to the VCC voltage to keep the CS
input buffer from drawing current. An alternative is to
leave CS low after a conversion, clock data until DOUT
outputs zeros, and then stop the clock low.
LT1286/98 G01
Figure 5. Shutdown current with CS high is 1nA typically,
regardless of the clock. Shutdown current with CS = ground
varies from 1µA at 1kHz to 35µA at 200kHz.
DOUT Loading
Capacitive loading on the digital output can increase power
consumption. A 100pF capacitor on the DOUT pin can add
more than 50µA to the supply current at a 200kHz clock
frequency. An extra 50µA or so of current goes into
charging and discharging the load capacitor. The same
goesfordigitallinesdrivenatahighfrequencybyanylogic.
The C × V × f currents must be evaluated and the trouble-
some ones minimized.
OPERATING ON OTHER THAN 5V SUPPLIES (LTC1286)
The LTC1286 operates from 4.5V to 9V supplies and the
LTC1298operatesfroma5Vsupply.TooperatetheLTC1286
on other than 5V supplies a few things must be kept in
mind.
4.7µF
9V
MPU
(e.g. 8051)
5V
Input Logic Levels
5V
DIFFERENTIAL INPUTS
V
V
P1.4
REF
CC
The input logic levels of CS, CLK and DIN are made to meet
TTL on a 5V supply. When the supply voltage varies, the
input logic levels also change. For the LTC1286 to sample
and convert correctly, the digital inputs have to be in the
proper logical low and high levels relative to the operating
supply voltage (see typical curve of Digital Input Logic
Threshold vs Supply Voltage). If achieving micropower
consumptionisdesirable,thedigitalinputsmustgorail-to-
rail between supply voltage and ground (see ACHIEVING
MICROPOWER PERFORMANCE section).
+IN
–IN
GND
CLK
P1.3
P1.2
50k
COMMON-MODE RANGE
0V TO 5V
D
OUT
CS
50k
LTC1286
LTC1286/98 • F06
Figure 6. Interfacing a 9V Powered LTC1286 to a 5V System
14
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BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
SAMPLE-AND-HOLD
Both the LTC1286 and the LTC1298 provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1286 acquires input signals from “+” input
relative to “–” input during the tSMPL time (see Figure 1).
However, the S&H of the LTC1298 can sample input
signals in the single-ended mode or in the differential
inputs during the tSMPL time (see Figure 7).
The LTC1286/LTC1298 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The VCC pin should be bypassed to the ground plane with
a 10µF tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1286/LTC1298 can
Single-Ended Inputs
also operate with smaller 1µF or less surface mount or The sample-and-hold of the LTC1298 allows conversion
ceramic bypass capacitors. All analog inputs should be of rapidly varying signals. The input voltage is sampled
referenced directly to the single point ground. Digital during the tSMPL time as shown in Figure 7. The sampling
inputs and outputs should be shielded from and/or routed interval begins as the bit preceding the MSBF bit is shifted
away from the reference and analog circuitry.
in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.
SAMPLE
HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
CS
t
t
CONV
SMPL
CLK
D
START
SGL/DIFF
MSBF
DON'T CARE
IN
D
B11
OUT
1ST BIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
"+" INPUT
"–" INPUT
LTC1096/8 • F07
Figure 7. LTC1298 “+” and “–” Input Settling Windows
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Differential Inputs
sample time can be increased by using a slower CLK
frequency.
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt-
ageontheselected “–”inputmustremain constantand be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per-
formed accurately. The conversion time is 12 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
“–” Input Settling
At the end of the tSMPL, the input capacitor switches to the
“–” input and conversion starts (see Figures 1 and 7).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltagesettlescompletelyduringthefirstCLKcycleofthe
–
conversiontimeandbefreeofnoise.MinimizingRSOURCE
and C2 will improve settling time. If a large “–” input
source resistance must be used, the time allowed for
settlingcanbeextendedbyusingaslowerCLKfrequency.
VERROR (MAX) = VPEAK × 2 × π × f(“–”) × 12/fCLK
Input Op Amps
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fCLK is the frequency of the
CLK. In most cases VERROR will not be significant. For a
60Hz signal on the “–” input to generate a 1/4LSB error
(305µV) with the converter running at CLK = 200kHz, its
peak value would have to be 13.48mV.
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(seeFigure7). Again, the“+”and“–”inputsamplingtimes
can be extended as described above to accommodate
sloweropamps.Mostopamps,includingtheLT1006and
LT1413 single supply op amps, can be made to settle well
even with the minimum settling windows of 6µs (“+”
input) which occur at the maximum clock rate of 200kHz.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1286/
LTC1298 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used or
if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
Source Resistance
The analog inputs of the LTC1286/LTC1298 look like a
20pF capacitor (CIN) in series with a 500Ω resistor (RON)
as shown in Figure 8. CIN gets switched between the
selected “+” and “–” inputs once during each conversion
cycle. Large external source resistors and capacitances
“+” Input Settling
“+”
+
The input capacitor of the LTC1286 is switched onto “+”
input during the tSMPL time (see Figure 1) and samples the
input signal within that time. However, the input capacitor
of the LTC1298 is switched onto “+” input during the
sample phase (tSMPL, see Figure 7). The sample phase is
1 1/2 CLK cycles before conversion starts. The voltage on
the “+” input must settle completely within tSMPLE for the
LTC1286 and the LTC1298 respectively. Minimizing
RSOURCE+ and C1 will improve the input settling time. If a
large “+” input source resistance must be used, the
INPUT
R
SOURCE
LTC1286/98
V
+
–
IN
C1
“–”
R
= 500Ω
ON
C
= 20pF
IN
–
INPUT
R
SOURCE
V
IN
C2
LTC1286/98 • F08
Figure 8. Analog Input Equivalent Circuit
16
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will slow the settling of the inputs. It is important that the
overall RC time constants be short enough to allow the
analog inputs to completely settle within the allowed time.
converter, the reference input should be driven by a
referencewithlowROUT(ex.LT1004,LT1019andLT1021)
or a voltage source with low ROUT
.
+
RC Input Filtering
REF
1
LTC1286
It is possible to filter the inputs with an RC network as
shown in Figure 9. For large values of CF (e.g., 1µF), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately IDC = 20pF × VIN/tCYC and is roughly
proportional to VIN. When running at the minimum cycle
time of 64µs, the input current equals 1.56µA at VIN = 5V.
In this case, a filter resistor of 75Ω will cause 0.1LSB of
full-scale error. If a larger filter resistor must be used,
errors can be eliminated by increasing the cycle time.
R
OUT
V
REF
GND
4
LTC1286/98 • F10
Figure 10. Reference Input Equivalent Circuit
Reduced Reference Operation
The minimum reference voltage of the LTC1298 is limited
to 4.5V because the VCC supply and reference are inter-
nally tied together. However, the LTC1286 can operate
with reference voltages below 1V.
I
DC
R
FILTER
The effective resolution of the LTC1286 can be increased
by reducing the input span of the converter. The LTC1286
exhibits good linearity and gain over a wide range of
referencevoltages(seetypicalcurvesofChangeinLinear-
ity vs Reference Voltage and Change in Gain vs Reference
Voltage). However, care must be taken when operating at
low values of VREF because of the reduced LSB step size
and the resulting higher accuracy requirement placed on
the converter. The following factors must be considered
when operating at low VREF values:
“+”
LTC1286
“–”
V
IN
C
FILTER
LTC1286/98 • F09
Figure 9. RC Input Filtering
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum
input leakage specification of 1µA (at 125°C) flowing
through a source resistance of 240Ω will cause a voltage
drop of 240µV or 0.2LSB. This error will be much reduced
at lower temperatures because leakage drops rapidly (see
typical curve of Input Channel Leakage Current vs Tem-
perature).
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
Offset with Reduced VREF
The offset of the LTC1286 has a larger effect on the output
code. When the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Change in Offset vs
Reference Voltage shows how offset in LSBs is related to
reference voltage for a typical value of VOS. For example,
a VOS of 122µV which is 0.1LSB with a 5V reference
becomes 0.5LSB with a 1V reference and 2.5LSBs with a
REFERENCE INPUTS
The reference input of the LTC1286 is effectively a 50kΩ
resistor from the time CS goes low to the end of the
conversion.Thereferenceinputbecomesahighimpedence
node at any other time (see Figure 10). Since the voltage
on the reference input defines the voltage span of the A/D
17
LTC1286/LTC1298
U
W
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APPLICATION INFORMATION
0.2V reference. If this offset is unacceptable, it can be tortionandnoiseattheratedthroughput.Byapplyingalow
corrected digitally by the receiving system or by offsetting distortion sine wave and analyzing the digital output using
the “–” input of the LTC1286.
an FFT algorithm, the ADC’s spectral content can be
examined for frequencies outside the fundamental. Figure
11 shows a typical LTC1286 plot.
Noise with Reduced VREF
The total input referred noise of the LTC1286 can be
reduced to approximately 400µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
isinsignificantwitha5Vreferencebutwillbecomealarger
fraction of an LSB as the size of the LSB is reduced.
0
T
V
f
= 25°C
A
= V
= 5V
CC
IN
REF
–20
= 5kHz
f
f
= 200kHz
CLK
SMPL
–40
–60
= 12.5kHz
–80
For operation with a 5V reference, the 400µV noise is
only 0.33LSB peak-to-peak. In this case, the LTC1286
noise will contribute virtually no uncertainty to the
output code. However, for reduced references the noise
may become a significant fraction of an LSB and cause
undesirable jitter in the output code. For example, with
a 2.5V reference this same 400µV noise is 0.66LSB
peak-to-peak. This will reduce the range of input volt-
ages over which a stable output code can be achieved by
1LSB.Ifthereferenceisfurtherreducedto1V,the400µV
noisebecomesequalto1.65LSBsandastablecodemay
be difficult to achieve. In this case averaging multiple
readings may be necessary.
–100
–120
–140
4
6
7
0
1
2
3
5
FREQUENCY (kHz)
LTC 1286/98 G21
Figure 11. LTC1286 Non-Averaged, 4096 Point FFT Plot
Signal-to-Noise Ratio
T
he Signal-to-Noise plus Distortion Ratio (S/N + D) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
This noise data was taken in a very clean setup. Any setup quency components at the ADC’s output. The output is
induced noise (noise or ripple on VCC, VREF or VIN) will add
to the internal noise. The lower the reference voltage to be
usedthemorecriticalitbecomestohaveaclean, noisefree
setup.
band limited to frequencies above DC and below one half
the sampling frequency. Figure 12 shows a typical spec-
tral content with a 12.5kHz sampling rate.
Effective Number of Bits
Conversion Speed with Reduced VREF
TheEffectiveNumberofBits(ENOBs)isameasurementof
the resolution of an ADC and is directly related to S/(N+D)
by the equation:
With reduced reference voltages, the LSB step size is
reduced and the LTC1286 internal comparator over-
drive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values
ENOB = [S/(N + D) – 1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 12.5kHz with a 5V supply, the LTC1286
maintains above 11 ENOBs at 10kHz input frequency.
Above 10kHz the ENOBs gradually decline, as shown in
Figure 12, due to increasing second harmonic distortion.
The noise floor remains low.
of V are used.
REF
DYNAMIC PERFORMANCE
The LTC1286/LTC1298 have exceptional sampling capa-
bility. Fast Fourier Transform (FFT) test techniques are
used to characterize the ADC’s frequency response, dis-
18
LTC1286/LTC1298
U
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APPLICATION INFORMATION
12
11
74
68
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
wavesareequalinmagnitudes, thevalue(indB)ofthe2nd
order IMD products can be expressed by the following
formula:
10
9
62
56
50
44
38
8
7
6
5
4
3
T
= 25°C
A
V
= 5V
CC
2
1
f
f
= 200kHz
CLK
SMPL
= 12.5kHz
0
1
10
100
1000
INPUT FREQUENCY (kHz)
LTC 1286/98 G20
amplitude f ± f
(
)
b
a
IMD f ± f = 20log
(
)
a
b
Figure 12. Effective Bits and S/(N + D) vs Input Frequency
amplitude at fa
Total Harmonic Distortion
For input frequencies of 5kHz and 6kHz, the IMD of the
LTC1286/LTC1298 is 73dB with a 5V supply.
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half of the sampling frequency. THD
is defined as:
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
valueisexpressedindBsrelativetotheRMSvalueofafull-
scale input signal.
V2 + V32 + V42 +... + VN2
2
THD = 20log
V
1
Full-Power and Full-Linear Bandwidth
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
second through the Nth harmonics. The typical THD speci-
fication in the Dynamic Accuracy table includes the 2nd
through 5th harmonics. With a 7kHz input signal, the
LTC1286/LTC1298 have typical THD of 80dB with VCC = 5V.
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full-scale input.
The full-linear bandwidth is the input frequency at which
the effective bits rating of the ADC falls to 11 bits. Beyond
this frequency, distortion of the sampled input signal
increases. The LTC1286/LTC1298 have been designed to
optimize input bandwidth, allowing the ADCs to
undersample input signals with frequencies above the
converters’ Nyquist Frequency.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition
to THD. IMD is the change in one sinusoidal input
caused by the presence of another sinusoidal input at a
different frequency.
19
LTC1286/LTC1298
U
TYPICAL APPLICATIONS N
MICROPROCESSOR INTERFACES
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1286/LTC1298
The LTC1286/LTC1298 can interface directly without ex-
ternal hardware to most popular microprocessor (MPU)
synchronous serial formats (see Table 1). If an MPU
without a dedicated serial port is used, then 3 or 4 of the
MPU's parallel port lines can be programmed to form the
serial link to the LTC1286/LTC1298. Included here is one
serial interface example and one example showing a
parallel port programmed to form the serial interface.
PART NUMBER
Motorola
TYPE OF INTERFACE
MC6805S2,S3
MC68HC11
MC68HC05
SPI
SPI
SPI
RCA
CDP68HC05
SPI
Hitachi
Motorola SPI (MC68HC11)
HD6305
HD63705
HD6301
HD63701
HD6303
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
CSI/O
TheMC68HC11hasbeenchosenasanexampleofanMPU
with a dedicated serial port. This MPU transfers data MSB
-firstandin8-bitincrements.TheDIN wordsenttothedata
register starts with the SPI process. With three 8-bit
transfers, the A/D result is read into the MPU. The second
8-bittransferclocksB11throughB8oftheA/Dconversion
result into the processor. The third 8-bit transfer clocks
the remaining bits, B7 through B0, into the MPU. The data
is right justified into two memory locations. ANDing the
second byte with OFHEX clears the four most significant
bits. This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
National Semiconductor
COP400 Family
COP800 Family
NS8050U
MICROWIRE†
MICROWIRE/PLUS†
MICROWIRE/PLUS†
MICROWIRE/PLUS†
HPC16000 Family
Texas Instruments
TMS7002
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
MC68HC11 Code
Intel
8051
Bit Manipulation on Parallel Port
In this example the DIN word configures the input MUX for
a single-ended input to be applied to CHO. The conversion
result is output MSB-first.
* Requires external hardware
MICROWIRE and MICROWIRE/PLUS are trademarks of
National Semiconductor Corp.
†
20
LTC1286/LTC1298
U
TYPICAL APPLICATIONS N
Timing Diagram for Interface to the MC68HC11
CS
CLK
SGL/
DIFF
ODD/
SIGN
DON'T CARE
MSBF
D
IN
START
D
OUT
B11 B10
B9
X
B8
X
B7
B6
X
B5
X
B4
X
B3
X
B2
X
B1
X
B0
X
MPU
TRANSMIT
WORD
ODD/
SIGN
SGL/
0
?
0
?
0
?
0
0
?
0
?
0
?
1
?
MSBF
?
X
X
X
X
DIFF
BYTE 2
BYTE 1
BYTE 3 (DUMMY)
MPU
RECEIVED
WORD
?
?
?
0
B11 B10
B9
B8
B7
B6
B5
B3
BYTE 3
B2
B1
B4
B0
BYTE 2
BYTE 1
LTC1286/98 AI06
Hardware and Software Interface to the MC68HC11
D
FROM LTC1298 STORED IN MC68HC11 RAM
OUT
MSB
CH0
D0
CS
0
0
B11
B3
B9
B1
B8
B0
BYTE 1
BYTE 2
0
0
B10
B2
#62
#63
SCK
CLK
ANALOG
INPUTS
LTC1298
MC68HC11
LSB
B4
D
OUT
MISO
B7
B6
B5
D
MOSI
CH1
IN
LTC1286/98 AI07
LABEL MNEMONIC OPERAND
COMMENTS
LABEL MNEMONIC OPERAND
COMMENTS
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
#$50
$1028
#$1B
$1009
#$01
$50
#$A0
$51
#$00
CONFIGURATION DATA FOR SPCR
LOAD DATA INTO SPCR ($1028)
CONFIG. DATA FOR PORT D DDR
LOAD DATA INTO PORT D DDR
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $50
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $51
LOAD DUMMY DIN WORD INTO
ACC A
WAIT1 BPL
LDAA
STAA
WAIT2 LDAA
BPL
WAIT1
$51
CHECK IF TRANSFER IS DONE
LOAD DIN INTO ACC A FROM $51
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD LTC1291 MSBs INTO ACC A
STORE MSBs IN $62
LOAD DUMMY INTO ACC A
FROM $52
LOAD DUMMY DIN INTO SPI,
START SCK
$102A
$1029
WAIT2
$102A
$62
LDAA
STAA
LDAA
$52
STAA
$102A
STAA
LDX
$52
#$1000
LOAD DUMMY DIN DATA INTO $52
LOAD INDEX REGISTER X WITH
$1000
WAIT3 LDAA
BPL
$1029
WAIT3
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOOP BCLR
LDAA
$08,X,#$01 D0 GOES LOW (CS GOES LOW)
BSET
LDAA
STAA
JMP
$08,X#$01 DO GOES HIGH (CS GOES HIGH)
$50
LOAD DIN INTO ACC A FROM $50
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG
$102A
$63
LOAD LTC1291 LSBs IN ACC
STORE LSBs IN $63
STAA
LDAA
$102A
$1029
LOOP
START NEXT CONVERSION
21
LTC1286/LTC1298
U
TYPICAL APPLICATIONS N
Interfacing to the Parallel Port of the INTEL 8051
Family
LABEL
MNEMONIC
OPERAND
COMMENTS
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
RRC
DJNZ
MOV
SETB
A, #FFH
P1.4
D word for LTC1298
IN
Make sure CS is high
CS goes low
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1298 and parallel port micro-
processors. Normally the CS, CLK and DIN signals would
be generated on 3 port lines and the DOUT signal read on
a 4th port line. This works very well. However, we will
demonstratehereaninterfacewiththeDIN andDOUT ofthe
LTC1298 tiedtogetherasdescribedintheSERIALINTER-
FACE section. This saves one wire.
P1.4
R4, #04
A
Load counter
LOOP 1
Rotate D bit into Carry
IN
P1.3
P1.2, C
P1.3
SCLK goes low
Output D bit to LTC1298
IN
SCLK goes high
R4, LOOP 1 Next bit
P1, #04
P1.3
R4, #09
C, P1.2
A
P1.3
P1.3
Bit 2 becomes an input
SCLK goes low
Load counter
LOOP 2
Read data bit into Carry
Rotate data bit into Acc.
SCLK goes high
The 8051 first sends the start bit and MUX address to the
LTC1298 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 12-bit A/D result over the same data
line.
SCLK goes low
R4, LOOP 2 Next bit
R2, A
A
Store MSBs in R2
Clear Acc.
R4, #04
C, P1.2
A
P1.3
P1.3
Load counter
LOOP 3
LOOP 4
Read data bit into Carry
Rotate data bit into Acc.
SCLK goes high
SCLK goes low
CS
CLK
P1.4
P1.3
P1.2
ANALOG
INPUTS
LTC1298
8051
D
OUT
R4, LOOP 3 Next bit
D
IN
MUX ADDRESS
A/D RESULT
R4, #04
A
Load counter
Rotate right into Acc.
LTC1286/98 TA01
R4, LOOP 4 Next Rotate
R3, A
P1.4
Store LSBs in R3
CS goes high
DOUT FROM 1298 STORED IN 8501 RAM
MSB
R2 B11 B10 B9 B8 B7 B6 B5 B4
LSB
R3 B3 B2 B1 B0 0
0
0
0
MSBF BIT LATCHED
INTO LTC1298
CS
CLK
DATA
/D
SGL/
DIFF
MSBF
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
ODD/
SIGN
START
(
D
)
IN OUT
8051 P1.2 OUTPUTS DATA
TO LTC1298
LTC1298 SENDS A/D RESULT
BACK TO 8051 P1.2
8051 P1.2 RECONFIGURED
AS IN INPUT AFTER THE 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
LTC1298 TAKES CONTROL OF DATA
LINE ON 4TH FALLING CLK
LTC1286/98 TA02
22
LTC1286/LTC1298
U
TYPICAL APPLICATIONS N
A “Quick Look” Circuit for the LTC1286
Users can get a quick look at the function and timing of the
LT1286 by using the following simple circuit (Figure 13).
Micropower Battery Voltage Monitor
A common problem in battery systems is battery voltage
monitoring.Thiscircuitmonitorsthe10cellstackofNiCad
orNiMHbatteriesfoundinlaptopcomputers.Itdrawsonly
67µA from the 5V supply at fSMPL = 0.1kHz and 25µA to
55µA from the battery. The 12-bits of resolution of the
LTC1286 are positioned over the desired range of 8V to
16V. This is easily accomplished by using the ADC’s
differential inputs. Tying the –input to the reference gives
an ADC input span of VREF to 2VREF (2.5V to 5V). The
resistordividerthenscalestheinputvoltagefor8Vto16V.
V
REF is tied to VCC. VIN is applied to the +IN input and the
–IN input is tied to the ground. CS is driven at 1/16 the
clock rate by the 74C161 and DOUT outputs the data. The
output data from the DOUT pin can be viewed on an
oscilloscope that is set up to trigger on the falling edge of
CS (Figure 14). Note the LSB data is partially clocked out
before CS goes high.
5V
4.7µF
CLR
CLK
A
B
C
D
P
GND
V
5V
CC
RC
BATTERY MONITOR
INPUT 8V TO 16V
5V
V
V
REF
CC
QA
QB
QC
QD
T
V
IN
+IN
–IN
GND
CLK
0.1µF
74C161
200k
91k
39k
LTC1286
D
OUT
CS
V
CC
+IN
–IN
CS
CLK
D
LOAD
LTC1286
OUT
V
REF
GND
1µF
3Ω
CLOCK IN 250kHz
TO OSCILLOSCOPE
LT1004-2.5
LTC1286/98 F13
Figure 13. “Quick Look” Circuit for the LTC1286
LTC1286/98 F15
Figure 15. Micropower Battery Voltage Monitor
LSB
(B0)
NULL
BIT
MSB
(B11)
VERTICAL: 5V/DIV
HORIZONTAL: 10µs/DIV
LTC1286/98 F14
Figure 14. Scope Trace the LTC1286 “Quick Look” Circuit
Showing A/D Output 101010101010 (AAAHEX
)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
23
LTC1286/LTC1298
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead Plastic DIP
0.400
(10.160)
MAX
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.320
(7.620 – 8.128)
0.045 – 0.065
(1.143 – 1.651)
8
1
7
6
5
4
0.065
(1.651)
TYP
0.250 ± 0.010
(6.350 ± 0.254)
0.009 – 0.015
(0.229 – 0.381)
0.125
(3.175)
MIN
0.020
(0.508)
MIN
+0.025
–0.015
0.045 ± 0.015
(1.143 ± 0.381)
0.325
2
3
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
S8 Package
8-Lead Plastic SOIC
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
(0.254 – 0.508)
7
5
8
6
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.150 – 0.157*
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
1
3
4
2
SO8 0294
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
LT/GP 0394 10K • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
24
●
●
LINEAR TECHNOLOGY CORPORATION 1994
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
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