LTC1157 [Linear]
3.3V Dual Micropower High-Side/Low-Side MOSFET Driver; 3.3V双路微功耗高侧/低侧MOSFET驱动器
| 型号： | LTC1157 |
| 厂家： | 
Linear |
| 描述： | 3.3V Dual Micropower High-Side/Low-Side MOSFET Driver |
| 文件： | 总8页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1157
3.3V Dual Micropower
High-Side/Low-Side MOSFET Driver
U
DESCRIPTIO
EATURE
S
F
■
■
■
■
■
■
■
■
■
Allows Lowest Drop 3.3V Supply Switching
Operates on 3.3V or 5V Nominal Supplies
3 Microamps Standby Current
The LTC1157 dual 3.3V micropower MOSFET gate driver
makes it possible to switch either supply or ground
reference loads through a low RDS(ON) N-channel switch
(N-channel switches are required at 3.3V because P-
channel MOSFETs do not have guaranteed RDS(ON) with
80 Microamps ON Current
Drives Low Cost N-Channel Power MOSFETs
No External Charge Pump Components
Controlled Switching ON and OFF Times
Compatible with 3.3V and 5V Logic Families
Available in 8-Pin SOIC
V
GS ≤ 3.3V). The LTC1157 internal charge pump boosts
the gate drive voltage 5.4V above the positive rail (8.7V
above ground), fully enhancing a logic level N-channel
switch for 3.3V high-side applications and a standard N-
channel switch for 3.3V low-side applications. The gate
drive voltage at 5V is typically 8.8V above supply (13.8V
above ground), so standard N-channel MOSFET switches
can be used for both high-side and low-side applications.
O U
PPLICATI
S
A
■
■
■
■
■
■
■
Notebook Computer Power Management
Palmtop Computer Power Management
P-Channel Switch Replacement
Battery Charging and Management
Mixed 5V and 3.3V Supply Switching
Stepper Motor and DC Motor Control
Cellular Telephones and Beepers
Micropower operation, with 3µA standby current and
80µA operating current, makes the LTC1157 well suited
for battery-powered applications.
The LTC1157 is available in both 8-pin DIP and SOIC.
U
O
TYPICAL APPLICATI
Ultra Low Voltage Drop 3.3V Dual High-Side Switch
Gate Voltage Above Supply
12
3.3V
10
8
+
10µF
6
V
S
(8.7V)
(8.7V)
IN1
IN2
G1
G2
IRLR024
3.3V
LOGIC
LTC1157
GND
4
3.3V
LOAD
IRLR024
2
3.3V
LOAD
LTC1157 • TA01
0
5.0 5.5
2.0 2.5 3.0 3.5 4.0 4.5
SUPPLY VOLTAGE (V)
6.0
LTC1157 • TA02
1
LTC1157
W W W
U
ABSOLUTE AXI U RATI GS
Operating Temperature Range
Supply Voltage ........................................... –0.3V to 7V
Any Input Voltage ............. (VS + 0.3V) to (GND – 0.3V)
Any Output Voltage............. (VS + 12V) to (GND – 0.3V)
Current (Any Pin)................................................. 50mA
LTC1157C............................................... 0°C to 70°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
W
U
/O
PACKAGE RDER I FOR ATIO
ORDER PART
ORDER PART
TOP VIEW
TOP VIEW
NUMBER
NUMBER
NC
GATE 1
GND
1
2
3
4
8
7
6
5
NC
NC
GATE 1
GND
1
2
3
4
8
7
6
5
NC
GATE 2
GATE 2
LTC1157CS8
LTC1157CN8
V
S
V
S
IN1
IN2
IN1
IN2
S8 PART MARKING
1157
N8 PACKAGE
S8 PACKAGE
8-LEAD PLASTIC SO
8-LEAD PLASTIC DIP
TJMAX = 100°C, θJA = 130°C/ W
TJMAX = 100°C, θJA = 150°C/ W
ELECTRICAL CHARACTERISTICS VS = 2.7V to 5.5V, TA = 25°C, unless otherwise noted.
LTC1157C
TYP
SYMBOL
PARAMETER
CONDITIONS
V = 3.3V, V = V = 0V (Note 1)
MIN
MAX
UNITS
I
Quiescent Current OFF
Quiescent Current ON
3
80
180
10
160
400
µA
µA
µA
Q
S
IN1
IN2
V = 3.3V, V = 3.3V (Note 2)
S
IN
V = 5V, V = 5V (Note 2)
S
IN
V
V
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
Gate Voltage Above Supply
●
●
●
70% × V
V
V
µA
pF
V
V
V
INH
INL
S
15% × V
±1
S
I
0V ≤ V ≤ V
IN
IN
S
C
V
5
IN
– V
V = 3V
●
●
●
4.0
4.5
7.5
4.7
5.4
8.8
6.5
7.0
12.0
GATE
S
S
V = 3.3V
S
V = 5V
S
t
t
Turn-ON Time
Turn-OFF Time
V = 3.3V, C
Time for V
Time for V
= 1000pF
ON
S
GATE
GATE
GATE
> V + 1V
30
75
130
240
300
750
µs
µs
S
> V + 2V
S
V = 5V, C
S
= 1000pF
GATE
Time for V
Time for V
> V + 1V
30
75
85
230
300
750
µs
µs
GATE
GATE
S
> V + 2V
S
V = 3.3V, C
Time for V
= 1000pF
< 0.5V
OFF
S
GATE
GATE
10
10
36
31
60
60
µs
µs
V = 5V, C
S
= 1000pF
GATE
Time for V
< 0.5V
GATE
The
● denotes specifications which apply over the full operating
temperature range.
Note 1: Quiescent current OFF is for both channels in OFF condition.
Note 2: Quiescent current ON is per driver and is measured independently.
2
LTC1157
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Standby Supply Current
Supply Current per Driver ON
Gate Voltage Above Supply
12
10
8
600
500
400
300
200
100
0
12
10
8
V
A
= V = 0V
ONE INPUT = ON
IN1
IN2
T
= 25°C
OTHER INPUT = OFF
T
A
= 25°C
6
6
4
4
2
2
0
0
5.0 5.5
5.0 5.5
2.0 2.5 3.0 3.5 4.0 4.5
SUPPLY VOLTAGE (V)
2.0 2.5 3.0 3.5 4.0 4.5
6.0
6.0
5.0 5.5
2.0 2.5 3.0 3.5 4.0 4.5
SUPPLY VOLTAGE (V)
6.0
SUPPLY VOLTAGE (V)
LTC1157 • TPC01
LTC1157 • TPC02
LTC1157 • TPC03
Input Threshold Voltage
Turn-OFF Time
Turn-ON Time
3.0
2.5
2.0
1.5
1.0
0.5
0
1000
800
600
400
300
200
0
60
50
40
30
20
10
0
C
GATE
= 1000pF
C
= 1000pF
GATE
T
= 25°C
A
TIME FOR V
< 0.5V
GATE
V
= 2V
V
= 5V
GS
GS
V
= 1V
GS
5.0 5.5
5.0 5.5
2.0 2.5 3.0 3.5 4.0 4.5
SUPPLY VOLTAGE (V)
5.0 5.5
2.0 2.5 3.0 3.5 4.0 4.5
SUPPLY VOLTAGE (V)
2.0 2.5 3.0 3.5 4.0 4.5
6.0
6.0
6.0
SUPPLY VOLTAGE (V)
LTC1157 • TPC04
LTC1157 • TPC05
LTC1157 • TPC06
Supply Current per Driver ON
Standby Supply Current
Gate Drive Current
1000
100
10
12
10
8
300
250
200
150
T
A
= 25°C
V
V
= 5V
S
V
= 5V
S
6
V
V
= 5V
S
4
2
0
100
50
0
V
= 3.3V
= 3.3V
S
S
= 3.3V
1
S
0.1
40
TEMPERATURE (˚C)
60
70
0
10
20
30
50
40
TEMPERATURE (˚C)
60
70
0
10
20
30
50
0
2
4
6
8
10
GATE VOLTAGE ABOVE SUPPLY (V)
LTC1157 • TPC09
LTC1157 • TPC07
LTC1157 • TPC08
3
LTC1157
U
U
U
PI FU CTIO S
Input Pins: The LTC1157 input pins are active high and
activatethechargepumpcircuitry whenswitchedON. The
LTC1157 logic inputs are high impedance CMOS gates
with ESD protection diodes to ground and supply and
therefore should not be forced beyond the power supply
rails.
relatively high impedance when driven above the rail (the
equivalent of a few hundred kΩ). Care should be taken to
minimize any loading of this pin by parasitic resistance to
ground or supply.
Supply Pin: The supply pin of the LTC1157 should never
be forced below ground as this may result in permanent
damage to the device. A 300Ω resistor should be inserted
in series with the ground pin if negative supply voltage
transients are anticipated.
Gate Drive Pins: The gate drive pin is either driven to
ground when the switch is turned OFF or driven above the
supply rail when the switch is turned ON. This pin is a
U
OPERATIO
The LTC1157 is a dual micropower MOSFET driver de-
signed specifically for operation at 3.3V and 5V and
includes the following functional blocks:
Gate Charge Pump
Gate drive for the power MOSFET is produced by an
internal charge pump circuit which generates a gate volt-
age substantially higher than the power supply voltage.
The charge pump capacitors are included on-chip and
thereforenoexternalcomponentsarerequiredtogenerate
the gate drive.
3.3V Logic Compatible Inputs
The LTC1157 inputs have been designed to accommodate
a wide range of 3.3V and 5V logic families. Approximately
50mV of hysteresis is provided to ensure clean switching.
Controlled Gate Rise and Fall Times
An ultra low standby current voltage regulator provides
continuous bias for the logic-to-CMOS converter. The
logic-to-CMOS converter output enables the rest of the
circuitry. In this way the power consumption is kept to an
absolute minimum in the standby mode.
When the input is switched ON and OFF, the gate is
charged by the internal charge pump and discharged in a
controlled manner. The charge and discharge rates have
been set to minimize RFI and EMI emissions.
W
BLOCK DIAGRA
(One Channel)
V
S
HIGH
FREQUENCY
OSCILLATOR
LOW STANDBY
CURRENT
REGULATOR
CHARGE
PUMP
GATE
GATE
DISCHARGE
LOGIC
VOLTAGE
REGULATOR
LOGIC-TO-CMOS
CONVERTER
INPUT
LTC1157 • BD
GND
4
LTC1157
U U
W
U
APPLICATIO S I FOR ATIO
MOSFET Selection
Obviously, this is too much current for the regulator (or
output capacitor) to supply and the output will glitch by as
much as a few volts.
The LTC1157 is designed to operate with both standard
andlogiclevelN-channelMOSFETswitches. Thechoiceof
switch is determined primarily by the operating supply
voltage.
The start-up current can be substantially reduced by
limiting the slew rate at the gate of an N-channel switch as
shown in Figure 1. The gate drive output of the LTC1157
Logic Level MOSFET Switches at 3.3V
3.3V
Logic level switches should be used with the LTC1157
when powered from 2.7V to 4V. Although there is some
variation among manufacturers, logic level MOSFET
switchesaretypicallyratedwithVGS =4Vwithamaximum
continuous VGS rating of ±10V. RDS(ON) and maximum
VDS ratings are similar to standard MOSFETs and there is
generally little price differential. Logic level MOSFETs are
frequently designated by an “L” and are usually available
in surface mount packaging. Some logic level MOSFETs
areratedupto±15Vandcanbeusedinapplicationswhich
require operation over the entire 2.7V to 5.5V range.
V
IN
LT1129-3.3
+
3.3µF
R1
100k
R2
1k
V
S
MTD3055EL
ON/0FF
IN1
G1
1/2 LTC1157
GND
+
C1
0.1µF
C
3.3V
LOAD
LOAD
100µF
LTC1157 • TA02
Figure 1. Powering a Large Capacitive Load
Standard MOSFET Switches at 5V
Standard N-channel MOSFET switches should be used
with the LTC1157 when powered from 4V to 5.5V supply
as the built-in charge pump produces ample gate drive to
fully enhance these switches when powered from a 5V
nominal supply. Standard N-channel MOSFET switches
are rated with VGS = 10V and are generally restricted to a
maximum of ±20V.
is passed through a simple RC network, R1 and C1, which
substantially slows the slew rate of the MOSFET gate to
approximately 1.5 × 10–4V/µs. Since the MOSFET is
operating as a source follower, the slew rate at the source
is essentially the same as that at the gate, reducing the
start-up current to approximately 15mA which is easily
managed by the system regulator. R2 is required to
eliminate the possibility of parasitic MOSFET oscillations
during switch transitions. Also, it is good practice to
isolate the gates of paralleled MOSFETs with 1k resistors
todecreasethepossibilityofinteractionbetweenswitches.
Powering Large Capacitive Loads
Electrical subsystems in portable battery-powered equip-
ment are typically bypassed with large filter capacitors to
reduce supply transients and supply induced glitching. If
not properly powered however, these capacitors may
themselves become the source of supply glitching.
Reverse Battery Protection
The LTC1157 can be protected against reverse battery
conditions by connecting a 300Ω resistor in series with
the ground pin. The resistor limits the supply current to
less than 12mA with –3.6V applied. Since the LTC1157
draws very little current while in normal operation, the
drop across the ground resistor is minimal. The 3.3V µP
(or control logic) can be protected by adding 10k resistors
in series with the input pins.
For example, if a 100µF capacitor is powered through a
switchwithaslewrateof0.1V/µs, thecurrentduringstart-
up is:
ISTART = C(dV/dt)
= (100 × 10–6) (1 × 105)
= 10A
5
LTC1157
TYPICAL APPLICATIO S
U
Ultra Low Drop 3 to 4 Cell Dual High-Side Switch
+
3 TO 4
CELL
0.47µF
BATTERY
PACK
Si9956DY
7,8 5,6
V
S
2
IN1
G1
G2
CONTROL
LTC1157
GND
LOGIC
OR µP
1
4
3
IN2
LOAD
LOAD
LTC1157 • TA03
Mixed 5V and 3.3V Dual High-Side Switch
5V
3.3V
+
10µF
6.3V
+
RFD16N05SM MTD10N05E
51k
10µF
4V
V
S
IN1
IN2
G1
G2
CONTROL
LOGIC
OR µP
LTC1157
GND
51k
5V
LOAD
3.3V
LOAD
LTC1157 • TA04
Mixed 3.3V and 12V High- and Low-Side Switching
3.3V
12V
+
10µF
4V
+
10µF
16V
IRLR024
12V
LOAD
V
S
IN1
IN2
G1
G2
CONTROL
LTC1157
GND
LOGIC
OR µP
30k
MTD3055EL
3.3V
LOAD
LTC1157 • TA05
6
LTC1157
U
TYPICAL APPLICATIO S
Ultra Low Voltage Drop Battery Switch with Reverse Battery
Protection, Ramped Output and 3µA Standby Current
5,6,7,8
1
3
SWITCHED (RAMPED)
BATTERY
+
Si9956DY
3 TO 4
CELL
0.47µF
2
4
BATTERY
PACK
+
100µF
6.3V
V
S
IN1
G1
G2
CONTROL
LOGIC
OR µP
LTC1157
GND
100k
1k
IN2
0.1µF
300Ω
LTC1157 • TA06
Generating 3.3V and 5V from a 3.3V or 5V Source
(Automatic Switching)
1
7,8
5,6
3.3V OR 5V
5V/150mA
2
3
1M
1M
Si9956DY
4
V
S
7,8
1
3
IN1
IN2
G1
G2
3.3V/150mA
LTC1157
GND
2
5,6
2N7002
Si9956DY
4
120µF/10V
MBRS12OT3
*20µH
+
1
2
3
SW1
2N7002
1M
I
V
IN
LIM
*20µH
39Ω
6
7
4
8
ZTX869-M1
AO
SW2
+
174k
1%
140k
1%
180µF
6V
LT1111
SET
FB
GND
5
+
105k
1%
100µF
6V
47Ω
430k
LTC1157 • TA07
*CTX20-3 COILTRONICS
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
7
LTC1157
TYPICAL APPLICATIO S
U
3.3V Ultra Low Voltage Drop Regulator with Optional Reverse
Battery Protection and 3µA Standby Current
Q1
IRLR024*
Q2
IRLR024
+
+
3 TO 4
CELL
BATTERY
PACK
C1
10µF
V
S
3.3V/1A
IN1
IN2
G1
G2
1
3
CONTROL
LOGIC
OR µP
R5
100k
C2
330pF
R3
3.3k
LTC1157
GND
LT1431
8
+
C3
220µF
5
6
R1
300Ω*
R2
680Ω
R4
10k
LTC1157 • TA08
*OPTIONAL REVERSE BATTERY PROTECTION. ADD R1 IN SERIES WITH THE
GROUND LEAD AND ADD Q1 IN SERIES WITH THE BATTERY AS SHOWN.
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N Package
8-Lead Plastic DIP
0.400
(10.160)
MAX
0.130 ± 0.005
0.300 – 0.320
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.128)
8
1
7
6
5
4
0.065
(1.651)
TYP
0.250 ± 0.010
(6.350 ± 0.254)
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.025
–0.015
2
3
0.045 ± 0.015
(1.143 ± 0.381)
0.325
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
N8 0392
S Package
8-Lead SOIC
0.189 – 0.197
(4.801 – 5.004)
0.010 – 0.020
(0.254 – 0.508)
7
5
8
6
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0.228 – 0.244
0.150 – 0.157
(5.791 – 6.197)
(3.810 – 3.988)
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
0°– 8° TYP
SO8 0392
1
3
4
2
LT/GP 0193 10K REV 0
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
8
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1993
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