LT3420-1_15 [Linear]
Photoflash Capacitor Chargers with Automatic Refresh;
| 型号： | LT3420-1_15 |
| 厂家： | 
Linear |
| 描述： | Photoflash Capacitor Chargers with Automatic Refresh |
| 文件： | 总20页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3420/LT3420-1
Photoflash Capacitor
Chargers with Automatic Refresh
U
FEATURES
DESCRIPTIO
The LT®3420/LT3420-1 charge high voltage photoflash
capacitorsquicklyandefficiently. Designedforuseinboth
digital and film cameras, these devices use a flyback
topology to achieve efficiencies up to four times better
than competing flash modules. A unique adaptive off-time
control algorithm* maintains current-limited continuous
mode transformer operation throughout the entire charge
cycle, eliminating the high inrush current often found in
modules.
■
Charges 220µF to 320V in 3.7 Seconds
from 5V (LT3420)
■
Charges 100µF to 320V in 3.5 Seconds
from 5V (LT3420-1)
Charges Any Size Photoflash Capacitor
Supports Operation from Two AA Cells or Any
Supply from 1.8V to 16V
Controlled Peak Switch Current: 1.4A (LT3420)
1.0A (LT3420-1)
■
■
■
■
Controlled Input Current: 840mA (LT3420)
450mA (LT3420-1)
The LT3420/LT3420-1 output voltage sensing scheme*
monitors the flyback voltage to indirectly regulate the
output voltage, eliminating an output resistor divider or
discrete zener diode. This feature allows the capacitor to
be held at a fully charged state without excessive power
consumption. Automatic refresh (which can be defeated)
allows the capacitor to remain charged while consuming
an average input current of about 2mA, at a user-defined
refresh rate. A logic high on the CHARGE pin initiates
charging, while the DONE pin signals that the capacitor is
fully charged.
■
■
■
■
■
■
■
■
■
Uses Standard Transformers
Efficient Flyback Operation (>75% Typical)
Adjustable Output
Automatic Refresh
Charge Complete Indicator
No High Voltage Zener Diode Required
No Output Voltage Divider Required
Small 10-Lead MSOP Package
Small 10-Lead (3mm × 3mm) DFN Package
U
The LT3420/LT3420-1 are available in 10-Lead MSOP and
(3mm × 3mm) DFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. *Protected by U.S. Patents
including 6518733.
APPLICATIO S
■
Digital Camera Flash Unit
Film Camera Flash Unit
High Voltage Power Supplies
■
■
U
TYPICAL APPLICATIO
T1
1:10
T1
1:12
V
(3mm TALL)
BAT
V
BAT
320V
320V
1.8V TO 6V
INPUT CURRENT
≈450mA
1.8V TO 6V
INPUT CURRENT
≈350mA
5
8
4
5,6
C1
4.7µF
C1
4.7µF
D1
D1
3
6
3,4
51.1k
1
60.4k
2
3
6
SW
2
3
R
FB
6
SW
SEC
C3
100µF
330V
C3
220µF
330V
V
R
BAT
FB
V
BAT
+
+
4
V
7
4
CC
V
CC
7
V
SEC
CC
V
2.5V TO 6V
CC
C2
2.5V TO 10V
C2
PHOTOFLASH
CAPACITOR
PHOTOFLASH
CAPACITOR
4.7µF
LT3420-1
4.7µF
LT3420
9
9
CHARGE
DONE
CHARGE
DONE
CHARGE
DONE
CHARGE
DONE
1
1
8
8
R
REF
R
REF
GND
C
GND
T
C
T
10
5
10
5
2k
2k
0.1µF
0.1µF
C1, C2: 4.7µF, X5R or X7R, 6.3V
C3: RUBYCON 100µF PHOTOFLASH CAPACITOR
T1: KIJIMA MUSEN SBL-5.6S-2
D1: VISHAY GSD2004S SOT-23
DUAL DIODE. DIODES CONNECTED IN SERIES
C1, C2: 4.7µF, X5R or X7R, 10V
C3: RUBYCON 220µF PHOTOFLASH CAPACITOR
T1: TDK SRW10EPC-U01H003 FLYBACK TRANSFORMER
D1: VISHAY GSD2004S SOT-23
DUAL DIODE. DIODES CONNECTED IN SERIES
DANGER HIGH VOLTAGE
OPERATION BY HIGH VOLTAGE
TRAINED PERSONNEL ONLY
3420 F02
3420 F01
Figure 1. High Charge Rate LT3420 Photoflash Circuit
Figure 2. Small Size LT3420-1 Photoflash Circuit
3420fb
1
LT3420/LT3420-1
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
DONE Voltage .......................................................... 16V
Current into DONE Pin .......................................... ±1mA
Maximum Junction Temperature .......................... 125°C
Operating Ambient Temperature Range
VCC Voltage .............................................................. 16V
VBAT Voltage ............................................................ 16V
SW Voltage (Note 2)
LT3420 ................................................................ 38V
LT3420-1............................................................ 50V
SEC Current ...................................................... ±200mA
(Note 3) .............................................. –40°C to 85°C
Storage Temperature Range ................. –40°C to 125°C
Lead Temperature (Soldering, 10 sec)
R
FB Current........................................................... ±3mA
(For MS Package only) ..................................... 300°C
R
REF Voltage ........................................................... 2.5V
CHARGE Voltage...................................................... 16V
CT Voltage .............................................................. 1.5V
U
W U
PACKAGE/ORDER INFORMATION
ORDER PART
ORDER PART
TOP VIEW
NUMBER
NUMBER
TOP VIEW
R
V
1
2
3
4
5
10
9
C
T
REF
R
1
2
3
4
5
10 C
T
REF
BAT
FB
CHARGE
DONE
SEC
LT3420EDD
LT3420EDD-1
BAT
LT3420EMS
LT3420EMS-1
V
9
8
7
6
CHARGE
DONE
SEC
R
11
8
FB
R
V
GND
V
7
CC
CC
SW
GND
6
SW
DD PART
MARKING
MS PACKAGE
10-LEAD PLASTIC MSOP
MS PART MARKING
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 100°C/W, θJC = 45°C/W
LTYH
LTAJG
(4-LAYER BOARD)
LBJW
LBJX
TJMAX = 125°C, θJA = 43°C/W, θJC = 3°C/W
EXPOSED PAD IS GND (PIN 11)
AND MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VBAT = 3.3V, VCHARGE = VCC unless otherwise noted. (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
2.5
UNITS
Minimum Operating Voltage, V
●
2.2
V
V
CC
Maximum Operating Voltage, V
16
CC
V
UVLO Hysteresis
40
mV
V
CC
Minimum V
Voltage
Voltage
1.6
1.8
16
BAT
Maximum V
V
BAT
V
UVLO Hysteresis
Threshold Voltage
275
mV
BAT
R
0.98
0.975
1.00
1.02
1.025
V
V
REF
●
R
Pin Bias Current
V
V
= 0V, Switching
2
4
µA
REF
RREF
= V – 0.2V (Note 4)
RFB
BAT
Quiescent Current
V
V
= 1.1V, Not Switching
90
130
1
µA
µA
RREF
Quiescent Current in Shutdown
= 0V, V = 3.3V
0.01
CHARGE
IN
3420fb
2
LT3420/LT3420-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VBAT = 3.3V, VCHARGE = VCC unless otherwise noted. (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Primary Side Current Limit
LT3420 (Note 5)
LT3420-1 (Note 5)
1.20
0.75
1.4
0.9
1.60
1.05
A
A
Secondary Side Current Limit
Leakage Blanking Pulse Width
LT3420 (Note 5)
LT3420-1 (Note 5)
20
5
40
15
50
25
mA
mA
LT3420
LT3420-1
200
0
ns
ns
Refresh Timer Charge/Discharge Current
Refresh Timer Upper Threshold
Refresh Timer Lower Threshold
V
= 0.75V
1.5
0.9
2.5
1.0
0.5
3.5
1.1
µA
V
CT
0.45
0.55
V
Switch V
LT3420, SW = 1A (Note 5)
LT3420-1, SW = 0.5A (Note 5)
220
130
340
230
mV
mV
CESAT
Switch Leakage Current
V
= 38V (LT3420), V = 50V (LT3420-1)
0.01
1
µA
V
SW
SW
CHARGE Input Voltage High
CHARGE Input Voltage Low
CHARGE Pin Bias Current
1.5
0.2
V
V
V
= 3V
= 0V
4.5
0.01
15
0.1
µA
µA
CHARGE
CHARGE
DONE Output Signal High
DONE Output Signal Low
100k from V to DONE
3.3
V
CC
33µA into DONE Pin
100
200
mV
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 2: Rated breakdown with LT3420 in power delivery mode and power
Note 4: Bias current flows out of R pin.
FB
switch off.
Note 5: Current limit and V
guaranteed by design and/or correlation
CESAT
Note 3: The LT3420/LT3420-1 are guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
to static test for DD package.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Graphs apply to both the LT3420 and LT3420-1 unless otherwise noted.
Output Voltage in Refresh Mode,
LT3420
Output Voltage in Refresh Mode,
LT3420
Charge Time, LT3420
335
330
325
320
315
310
305
300
295
335
330
325
320
315
310
305
300
295
10
FIGURE 1 CIRCUIT
UNLESS OTHERWISE
NOTED.
V
CHARGED
OUT
FROM
50V TO 320V
8
6
4
2
0
T
= 25°C
A
C
= 220µF
OUT
C
= 100µF
OUT
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
V
V
T
= V
CC
BAT
= 25°C
IN
V
V
= 3.3V
= 3.3V
= V
IN
CC
BAT
A
6
2
3
4
5
–25
0
25
50
75
125
–50
100
3.0 3.5 4.0 4.5 5.0 5.5 6.0
(V)
2.5
V
(V)
TEMPERATURE (°C)
V
IN
BAT
3420 G03
3420 G01
3420 G02
3420fb
3
LT3420/LT3420-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Graphs apply to both the LT3420 and LT3420-1 unless otherwise noted.
Output Voltage in Refresh Mode,
LT3420-1
Output Voltage in Refresh Mode,
LT3420-1
Charge Time, LT3420-1
335
330
325
320
315
310
305
300
295
335
330
325
320
315
310
305
300
295
10
8
FIGURE 2 CIRCUIT
CHARGED
V
OUT
FROM 50V TO 320V
= 25°C
T
A
6
C
= 100µF
OUT
4
C
= 40µF
OUT
FIGURE 2 CIRCUIT
2
FIGURE 2 CIRCUIT
V
V
A
= V
CC
BAT
= 25°C
IN
V
V
= 3.3V
BAT
CC
= V
IN
= 3.3V
T
0
–25
0
25
50
75
125
–50
100
3.0 3.5 4.0 4.5 5.0
(V)
6.0
2.5
5.5
4
2
3
5
6
TEMPERATURE (°C)
V
IN
V
(V)
BAT
3420 G04
3420 G05
3420 G06
Charge Pin Input Current
Primary Current Limit, LT3420
Secondary Current Limit, LT3420
1.7
1.5
1.3
1.1
0.9
60
55
50
45
40
35
30
25
20
10
8
T
= 25°C
A
6
4
2
0
–50
–25
25
50
75
100
0
125
–25
0
25
50
75
125
6
–50
100
2
3
4
5
7
8
9
10
TEMPERATURE (°C)
TEMPERATURE (°C)
CHARGE PIN VOLTAGE (V)
3420 G08
3420 G09
3420 G07
Efficiency of Figure 1 Circuit,
LT3420
Primary Current Limit, LT3420-1
Secondary Current Limit, LT3420-1
1.2
1.1
1.0
0.9
0.8
90
80
70
60
50
40
35
30
25
20
15
10
5
T
= 25°C
A
V
= 5V
IN
V
= 3.3V
IN
V
= V
= V
BAT IN
CC
–25
25
50
75
100
–50
50
150
250
350
0
125
100
200
(V)
300
–25
0
25
50
75
125
–50
100
TEMPERATURE (°C)
V
TEMPERATURE (°C)
OUT
3420 G11
3420 G10
3420 G12
3420fb
4
LT3420/LT3420-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Graphs apply to both the LT3420 and LT3420-1 unless otherwise noted.
Efficiency for Figure 2 Circuit,
LT3420-1
Input Current, LT3420
Input Current, LT3420-1
90
80
70
60
50
40
1000
900
800
700
600
500
600
T
= 25°C
FIGURE 1 CIRCUIT
FIGURE 2 CIRCUIT
A
V
T
= V
= 3.3V
V
T
= V
= 3.3V
CC
A
BAT
CC
A
BAT
= 25°C
550
500
450
400
350
300
= 25°C
V
= 5V
IN
V
= 3.3V
IN
V
= V
= V
BAT IN
CC
50
150
250
350
50
150
250
350
100
200
(V)
300
100
200
(V)
300
50
150
200
(V)
250
300
350
100
V
V
V
OUT
OUT
OUT
3420 G13
3420 G14
3420 G15
Quiescent Current in Refresh Mode
V
CC Minimum Operating Voltage
VBAT Minimum Operating Voltage
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
140
120
100
80
2.0
1.8
1.6
1.4
1.2
1.0
ENABLE VOLTAGE
IS HYSTERETIC
T
= 25°C
ENABLE VOLTAGE
IS HYSTERETIC
A
+
V
+
–
V
–
V
V
60
–25
0
25
50
75
125
–50
100
–25
0
25
50
75
125
4.0
5.5
7.0
(V)
8.5
–50
100
2.5
10
TEMPERATURE (°C)
V
TEMPERATURE (°C)
CC
3420 G17
3420 G16
3420 G18
3420fb
5
LT3420/LT3420-1
U
U
U
PI FU CTIO S
RREF (Pin 1):Reference Resistor Pin. Place a resistor (R2)
GND (Pin 5): Ground. Tie directly to local ground plane.
from the RREF pin to GND. 2k is recommended.
SW (Pin 6): Switch Pin. This is the collector of the internal
NPN power switch. Minimize the metal trace area con-
nected to this pin to minimize EMI.
VBAT (Pin 2): Battery Voltage Input. This pin should be
connected to the power supply or battery, which supplies
power to transformer T1. Must be locally bypassed.
SEC (Pin 7): Transformer Secondary Pin. Tie one end of
the transformer secondary to this pin. Take care to use the
correct phasing of the transformer (Refer to Figures 1
and 2).
RFB (Pin 3): Feedback Resistor Pin. Place a resistor (R1)
from the SW pin to the RFB pin. Set R1 according to the
following formula:
DONE (Pin 8): Done Output Pin. Open collector NPN
output. DONE is pulled low whenever the chip is delivering
power to the output and goes high when power delivery
stops.
R2
R1=
R1=
(1.4 •RSEC)+ N(VOUT + 2VD)
(LT3420)
[
]
N2
R2
N2
(RSEC)+N(VOUT + 2V )
(LT3420-1)
[
]
D
CHARGE (Pin 9):Charge Pin. Drive CHARGE high (1.5V or
more) to commence charging of the output capacitor.
Drive to 0.2V or less to put the part in shutdown mode.
VOUT : Desired Output Voltage
N: Transformer Turns Ratio
CT (Pin10):RefreshTimerCapacitorPin.Placeacapacitor
from the CT pin to GND to set the refresh timer sample rate
according to the following formula:
RSEC: Transformer Secondary Resistance
VD: Diode Forward Voltage Drop
CT = 2.5 • 10–6 • tREFRESH
R2: Resistor from the RREF Pin to GND. 2k is a Typical
Choice
tREFRESH: Desired Refresh Period in Seconds.
VCC (Pin 4): Input Supply Pin. Must be locally bypassed
with a 4.7µF or larger ceramic capacitor.
EXPOSEDPAD(Pin11)(DDPackageonly):GND.Mustbe
soldered to local ground plane on PCB.
3420fb
6
LT3420/LT3420-1
W
BLOCK DIAGRA S
T1
1:12
V
BAT
V
OUT
D1
C1
SECONDARY
PRIMARY
R1
R2
DONE
8
SW
R
FB
V
BAT
R
REF
2
3
1
6
+
C4
PHOTOFLASH
CAPACITOR
D3
R
Q
Q1
S
REFRESH
TIMER
10
CT
C3
Q5
Q3
DRIVER
A1
+
–
ONE-
SHOT
Q2
0.014Ω
20mV
BLOCK
ENABLE
+
–
Q
Q
R
MASTER
LATCH
Q4
5
7
–
+
+
–
S
GND
SEC
A3
A2
0.25Ω
10mV
1V
REFERENCE
+
–
ONE-
9
4
CHARGE
SHOT
POWER DELIVERY BLOCK
CHIP
ENABLE
V
CC
V
CC
LT3420
C2
3420 F03
Figure 3. Block Diagram, LT3420
T1
1:10
V
BAT
V
OUT
D1
C1
SECONDARY
PRIMARY
R1
R2
DONE
SW
R
FB
V
BAT
R
REF
8
2
3
1
6
+
C4
PHOTOFLASH
CAPACITOR
D3
R
Q
Q1
S
REFRESH
TIMER
10
CT
Q5
Q3
DRIVER
A1
C3
+
–
ONE-
SHOT
Q2
0.02Ω
20mV
BLOCK
ENABLE
+
–
Q
Q
MASTER
LATCH
Q4
5
7
–
+
+
–
R
S
GND
SEC
A3
A2
0.66Ω
10mV
1V
REFERENCE
+
–
ONE-
9
4
CHARGE
SHOT
POWER DELIVERY BLOCK
CHIP
ENABLE
V
V
CC
CC
LT3420-1
C2
3420 F04
Figure 4. Block Diagram, LT3420-1
3420fb
7
LT3420/LT3420-1
U
OPERATIO
Overview
(high→low→high). The low to high transition on the
CHARGE pin fires a one-shot that sets the master latch,
putting the part in charging mode. Bringing CHARGE low
puts the part in shutdown. The refresh timer can be
programmed to wait indefinitely by simply grounding the
CT pin. In this configuration, the LT3420 will only reenter
the charging mode by toggling the CHARGE pin.
The following text focuses on the operation of the LT3420.
The operation of the LT3420-1 is nearly identical with the
differences discussed at the end of this section.
The LT3420 uses an adaptive on-time/off-time control
scheme to provide excellent efficiency and precise control
of switching currents. Please refer to Figure 3 for the fol-
lowingoverviewofthepart’soperation.Atanygiveninstant, Power Delivery Block
the master latch determines which mode the LT3420 is in:
The power delivery block consists of all circuitry enclosed
“charging” or “refresh”. In charging mode, the circuitry
enclosed by the smaller dashed box is enabled, providing
power to charge photoflash capacitor C1. The output volt-
ageismonitoredviatheflybackpulseontheprimaryofthe
transformer.Whenthetargetoutputvoltageisreached,the
chargingmodeisterminatedandthepartenterstherefresh
mode.Inrefreshmode,thepowerdeliveryblockisdisabled,
reducing quiescent current, while the refresh timer is en-
abled. The refresh timer simply generates a user program-
mable delay, after which the part reenters the charging
mode. Once in the charging mode, the LT3420 will again
provide power to the output until the target voltage is
reached.Figure5isanoscillographphotoshowingboththe
initial charging of the photoflash capacitor and the subse-
quent refresh action. The upper waveform is the output
voltage. The middle waveform is the voltage on the CT pin.
The lower waveform shows the input current. The mode of
the part is indicated below the photo.
by the smaller dashed box in Figure 3. This circuit block
contains all elements needed for charging and output
voltage detection. To better understand the circuit opera-
tion, follow the subsequent description of one cycle of
operation and refer to Figure 6. Assume that initially there
is no current in the primary or secondary of the trans-
former, so the output of comparator A1 is low, while that
of A2 is high (note the small offset voltages at the inputs
of A1 and A2). The SR latch is thus set and the power NPN
switch, Q1, is turned on. Current increases linearly in the
primaryofthetransformerataratedeterminedbytheVBAT
voltage and the primary inductance of the transformer. As
the current builds up, the voltage across the 14mΩ
resistor increases. When this voltage exceeds the 20mV
offset voltage of A1, the output of A1 goes high, resetting
the SR latch and turning off Q1. The current needed to
reset the latch is approximately 1.4A (~20mV/14mΩ).
When Q1 turns off, the secondary side current quickly
jumps from zero current to the primary side current di-
vided by N (the turns ratio of transformer T1). In this ex-
ample, the peak secondary current is 116mA (1.4A/12).
Diode D1 now conducts, providing power to the output.
Since a positive voltage exists across the secondary wind-
ing of the transformer, the secondary current decreases
linearly at a rate determined by the secondary inductance
andtheoutputvoltage(neglectingthediodevoltagedrop).
When the secondary side current drops below 40mA
(10mV/0.25Ω), the output of A2 goes high, setting the SR
latch and turning on Q1. The initial primary current is sim-
ply the minimum secondary current times N, in this case
0.48A (40mA • 12) . Q1 will now remain on until the pri-
mary current again reaches 1.4A. This cycle of operation
repeatsitself, automaticallyadjustingtheOnandOfftimes
The user can defeat the refresh timer and force the part
into charging mode by toggling the CHARGE pin
V
OUT
100V/DIV
V
CT
1V/DIV
I
IN
1A/DIV
MODE
REFRESH
SHUTDOWN CHARGING
1s/DIV
3420 F05
Figure 5. Demonstrating 3 Operating Modes of LT3420:
Shutdown, Charging and Refresh of Photoflash Capacitor
3420fb
8
LT3420/LT3420-1
U
OPERATIO
I
I
SW
SW
1A/DIV
1A/DIV
I
I
SEC
SEC
200mA/DIV
200mA/DIV
V
V
SW
SW
20V/DIV
20V/DIV
3420 F06a
3420 F06b
2µs/DIV
2µs/DIV
Figure 6a. Switching Waveforms with
VOUT = 100V, VCC = VBAT = 3.3V
Figure 6b. Switching Waveforms with
VOUT = 300V, VCC = VBAT = 3.3V
of Q1 so that the peak current of Q1 is 1.4A and the mini-
mum secondary current is 40mA (typical values).
C3, from its initial voltage towards 1V. When the voltage
onC3reaches1V,thepolarityofthecurrentsourcechanges
and2.5µAdischargesC3. WhenthevoltageonC3reaches
0.5V,therefreshtimersendsasetpulsetothemasterlatch,
which puts the LT3420 into the charging mode.
The previously described charging cycle must be halted
when the output voltage reaches the desired value. The
LT3420 monitors the output voltage via the flyback pulse
on the SW pin. When Q1 turns off, the secondary side
conducts current turning on diode D1. Since the diode is
conductingandtheSECpinisatnearlyground,thevoltage
across the secondary is nearly equal to VOUT. The voltage
across the primary is therefore close to VOUT/N. A current
proportional to VOUT/N flows through R1 and into the RFB
pin. The current flows out of the RREF pin through a resis-
tor creating a ground referred voltage. When this voltage
exceeds an internal 1V reference voltage, the output of
comparatorA3goeshighwhichresetsthemasterlatch.The
Q output of the master latch goes low, disabling the entire
power delivery block and enabling the refresh timer.
Interface/Control
The CHARGE pin serves two functions. The first is to
enable or shutdown the part depending on the level of the
pin (high = enable, low =shutdown). The second is to
force the part into the charging mode (low→high transi-
tion). The LT3420 also has a DONE pin, which signals
whether or not the part is done charging the photoflash
capacitor. The DONE pin is an open collector NPN switch
(Q5) so an external pull-up resistor is needed. Whenever
the part is in charging mode, DONE will be low. DONE will
go high when the charging mode is complete. Both the
CHARGE and DONE pins can be easily interfaced to a
microprocessor in a digital or film camera.
Leakage Spike Blanking
Another function of the LT3420 is leakage spike blanking
when the power switch, Q1, turns off. Right after Q1 turns
off, a one-shot turns on Q2 for 200ns (typ). With Q2 on,
comparator A3 is disabled. This function may prevent A3
from false tripping on the leakage inductance spike on the
SW pin. In practice, the PNP transistor Q3 filters out the
leakage spike.
LT3420-1 Differences
The LT3420-1 has different primary and secondary cur-
rent limit levels. The primary current limit level of the
LT3420-1 is 1A (typ) and the secondary current limit is
15mA (typ). The LT3420-1 has no leakage spike blanking
which causes no problems since the PNP transistor, Q3,
providesadequatefiltering.Finally,thebreakdownvoltage
of the SW pin of the LT3420-1 is higher at 50V.
Refresh Timer
When the refresh timer is enabled, a 2.5µA current source
is switched on, charging up the external timing capacitor,
3420fb
9
LT3420/LT3420-1
W U U
U
APPLICATIO S I FOR ATIO
COMPONENT SELECTION
Transformer Primary Inductance
A flyback transformer needs to store substantial amounts
of energy in the core during each switching cycle. The
transformer, therefore, will generally require an air gap.
The use of an air gap in the core makes the energy storage
ability, or inductance, much more stable with temperature
and variations in the core material. Most core manufactur-
ers will supply standard sizes of air gaps with a given type
of core, resulting in different AL values. AL is the induc-
tance of a particular core per square turns of winding. To
get a certain inductance, simply divide the desired induc-
tance by the AL value and take the square root of the result
to find the number of turns needed on the primary of the
transformer.
Choosing the Right Transformer
The flyback transformer plays a key role in any LT3420/
LT3420-1 application. A poorly designed transformer can
result in inefficient operation. Linear Technology Corpora-
tionhasworkedwithanumberoftransformermanufactur-
ers to develop specific transformers for use with the
LT3420/LT3420-1. These predesigned transformers are
sufficient for a large majority of the applications that may
be encountered. In some cases, the reader may choose to
designhisowntransformerormaysimplybecuriousabout
the issues involved in designing the transformer. The fol-
lowing is a brief discussion of the issues relating to trans-
former design.
The LT3420/LT3420-1 detect the output voltage via the
flyback pulse on the SW pin. Since this can only occur
while the power switch is off, an important criteria is that
the value of the primary inductance of the transformer be
larger than a certain minimum value. The switch off time
should be 500ns or larger for the LT3420 and 350ns or
larger for the LT3420-1. The minimum inductance can be
calculated with the following formula:
Transformer Turns Ratio
The turns ratio for the transformer, N, should be high
enough so that the absolute maximum voltage rating for
the NPN power switch is not exceeded. When the power
switch turns off, the voltage on the collector of the switch
(SW Pin) will “fly” up to the output voltage divided by N
plus the battery voltage (neglecting the voltage drop
across the rectifying diodes). This voltage should not
exceed the 38V (LT3420) or 50V (LT3420-1) breakdown
rating of the power switch.
500 •10–9 • VOUT
N •(1.4 – 0.04N)
350 •10–9 • VOUT
N •(1.0 – 0.015N)
LPRI
LPRI
≥
≥
(LT3420)
(LT3420 − 1)
Choose the minimum N by the following formula.
VOUT
38 – VBAT
VOUT
VOUT: Target Output Voltage
N: Transformer Turns Ratio
NMIN
NMIN
≥
≥
(LT3420)
(LT3420 − 1)
Transformer Leakage Inductance
50 – VBAT
The leakage inductance of the transformer must be care-
fully minimized for both proper and efficient operation of
thepart.TheDCvoltageratingoftheSWpinontheLT3420
is 38V while on the LT3420-1 it is 50V. These ratings are
for DC blocking voltages only and additional precautions
For an LT3420 design, a 5V battery voltage and a 330V
outputresultsinaNMINof10soaturnsratioof10orgreater
should be used.
3420fb
10
LT3420/LT3420-1
W U U
APPLICATIO S I FOR ATIO
U
must be taken into account for the dynamic blocking
voltagecapabilitiesoftheLT3420/LT3420-1.Thedynamic
blocking voltage capability of both parts is 38V.
Note also the magnitude of the initial current spike in the
primary of the transformer labeled “C” when the power
switch turns on. If the leakage inductance is lowered to a
verylowlevel, theinternalcapacitancesofthetransformer
will be high. This will result in the initial spike of current in
the primary becoming excessively high. The level of “C”
should be kept to 4A or less in a typical design for both the
LT3420andLT3420-1. Pleasenotethatbyinsertingaloop
of wire in the primary to measure the primary current, the
leakage inductance of the primary will be made artificially
high. This may result in erroneous voltage measurements
on the SW pin.
Table1summarizesthevariousbreakdownvoltagesofthe
SW pin for both parts.
Table 1. SW Pin Voltage Ratings
PART
SW PIN DC RATING
SW PIN DYNAMIC RATING
LT3420
LT3420-1
38V
50V
38V
38V
Figure 7 shows what to examine in a new transformer
design to determine if the specifications for the SW pin are
met.
The measurements shown in Figure 7 should be made
with both VOUT and VBAT at the maximum levels for the
given application. This results in the highest voltage and
current stress on the SW pin.
The first leakage inductance spike labeled “A” must not
exceed the dynamic rating of the SW pin. If it does exceed
the rating, then the transformer leakage inductance must
be lowered. The flyback waveform after the initial spike
labeled “B” must not exceed the DC rating of the SW pin.
If it does exceed the rating, then the turns ratio of the
transformermustbelowered. Inmeasuringthevoltageon
the SW pin, care must be taken in minimizing the ground
loop of the voltage probe. Careless probing will result in
inaccurate readings.
Transformer Secondary Capacitance
The total capacitance of the secondary should be mini-
mizedforbothefficientandproperoperationoftheLT3420/
LT3420-1. Since the secondary of the transformer under-
goes large voltage swings (approaching 600VP-P), any
capacitance on the secondary can severely affect the
MUST BE LESS THAN 4A
FOR BOTH THE LT3420
AND LT3420-1
“C”
I
PRI
0A
MUST BE LESS THAN 38V
FOR THE LT3420
MUST BE LESS THAN 50V
FOR THE LT3420-1
“B”
“A”
MUST BE LESS THAN 38V
FOR BOTH THE LT3420
AND LT3420-1
V
SW
0V
3420 F07
Figure 7. New Transformer Design Check (Not to Scale)
3420fb
11
LT3420/LT3420-1
U
W U U
APPLICATIO S I FOR ATIO
efficiency of the circuit. In addition, the effective capaci-
tance on the primary is largely dominated by the actual
secondary capacitance. This is simply a result of any
secondary capacitance being multiplied by N2 when re-
flected to the primary. Since N is generally 10 or higher, a
small capacitance of 10pF on the secondary is 100 times
larger, or 1.0nF, on the primary. This capacitance forms a
resonantcircuitwiththeprimaryleakageinductanceofthe
transformer. As such, both the primary leakage induc-
tance and secondary side capacitance should be mini-
mized.
DIODE SELECTION
The rectifying diode(s) should be low capacitance type
with sufficient reverse voltage and forward current rat-
ings. The peak reverse voltage that the diode(s) will see is
approximately:
VPK-R ≈ VOUT +(N • VBAT) •1.65
(
)
The peak current of the diode is simply:
1.4A
N
1.0A
N
IPK-SEC
IPK-SEC
=
=
(LT3420)
Table 2 shows various predesigned transformers along
with relevant parameters. Contact the individual trans-
former manufacturer for additional information or
customization.
(LT3420 − 1)
For the circuit of Figure 1 with VBAT of 3.3V, VPK-R is 590V
and IPK-SEC is 116mA. Table 3 shows various diodes that
canworkwiththeLT3420/LT3420-1.Thesearechosenfor
low capacitance and high reverse blocking voltage. Use
theappropriatenumberofdiodestoachievethenecessary
reverse breakdown voltage.
Table 2a. Predesigned Transformers, LT3420
TURNS
L
SIZE
PART
RATIO (µH) LxWxH (mm) VENDOR
SRW10EPC
-U01H003
1:12
1:12
1:12
24 10.9x10.8x5.2 TDK
(847) 803-6100
www.components.tdk.com
6375-T108
SBL-6.4
15 10.8x9.5x3.6 Sumida
Table 3
(847) 956-0666
www.sumida.com
MAX REVERSE CAPACITANCE
VOLTAGE (V)
PART
(pF)
VENDOR
17.5 10.3x6.4x5.2 Kijima Musen
852-2489-8266
GSD2004S
(Dual diode)
2x300
5
Vishay
(402) 563-6866
www.vishay.com
kijimahk@netvigator.com
BAS21
250
1.5
5
Philips Semiconductor
(800) 234-7381
Table 2b. Predesigned Transformers, LT3420-1
(Single diode)
TURNS
L
SIZE
www.philips.com
PART
RATIO (µH) LxWxH (mm) VENDOR
MMBD3004S
2x300
Diodes Inc.
(805) 446-4800
www.diodes.com
SBL-5.6S-2
1:10
15
5.6x8.5x3.0 Kijima Musen
852-2489-8266
kijimahk@netvigator.com
LDT565630T 1:10.2 14.5 5.8x5.8x3.0 TDK
-002
(847) 803-6100
www.components.tdk.com
3420fb
12
LT3420/LT3420-1
W U U
APPLICATIO S I FOR ATIO
U
CAPACITOR SELECTION
and significant voltage coefficients. A much more accu-
rate, and easier, method is to measure the efficiency as a
function of the output voltage. In place of the photoflash
capacitor, use a smaller, high quality capacitor, reducing
errorsassociatedwiththenon-idealphotoflashcapacitor.
Using an adjustable load, the output voltage can be set
anywhere between ground and the maximum output
voltage. The efficiency is measured as the output power
(VOUT • IOUT) divided by the input power (VIN • IIN). This
method also provides a good means to compare various
charging circuits since it removes the variability of the
photoflash capacitor from the measurement. The total
efficiencyofthecircuit,charginganidealcapacitor,would
bethetimeaverageofthegivenefficiencycurve,overtime
as VOUT changes.
The VBAT and VCC decoupling capacitors should be multi-
layerceramictypewithX5RorX7Rdielectric. Thisinsures
adequate decoupling across wide ambient temperature
ranges. A good quality ceramic capacitor is also recom-
mended for the timing capacitor on the CT pin. Avoid Y5V
or Z5U dielectrics.
Selectively Disabling the LT3420/LT3420-1
The LT3420/LT3420-1 can be disabled at any time, even
duringthechargephase. Thismaybeusefulwhenadigital
camera enters a sensitive data acquisition phase. Figure 8
illustrates this feature. Midway through the charge cycle,
the CHARGE pin is brought low, which disables the part.
Afterthesensitivedataoperationiscomplete,theCHARGE
pin is brought high and the charging operation continues.
Adjustable Input Current
With many types of modern batteries, the maximum
allowable current that can be drawn from the battery is
limited. This is generally accomplished by active circuitry
or a polyfuse. Different parts of a digital camera may
require high currents during certain phases of operation
and very little at other times. A photoflash charging circuit
should be able to adapt to these varying currents by
drawing more current when the rest of the camera is
drawing less, and vice-versa. This helps to reduce the
chargetimeofthephotoflashcapacitor,whileavoidingthe
Measuring Efficiency
Measuring the efficiency of a circuit designed to charge
large capacitive loads is a difficult issue, particularly with
photoflash capacitors. The ideal way to measure the
efficiency of a capacitor charging circuit would be to find
the energy delivered to the output capacitor (0.5 • C • V2)
and divide it by the total input energy. This method does
not work well here because photoflash capacitors are far
from ideal. Among other things, they have relatively high
leakage currents, large amounts of dielectric absorption,
V
OUT
50V/DIV
CHARGE
NO
CHARGE
5V/
DIV
V
CHARGE
3420 F08
0.5s/DIV
Figure 8. Halting the Charge Cycle at Any Time
3420fb
13
LT3420/LT3420-1
W U U
U
APPLICATIO S I FOR ATIO
risk of drawing too much current from the battery. The
input current to the LT3420/LT3420-1 circuit can be
adjusted by driving the CHARGE pin with a PWM (pulse
width modulation) signal. The microprocessor can adjust
the duty cycle of the PWM signal to achieve the desired
level of input current. Many schemes exist to achieve this
function. Once the target output voltage is reached, the
PWM signal should be halted to avoid overcharging the
photoflash capacitor, since the signal at the CHARGE pin
overrides the refresh timer.
1kHz. When ON is logic high, the circuit is enabled and the
CHARGE pin is driven by the PWM signal. When the target
output voltage is reached, DONE goes high while CHARGE
is also high. The output of A1 goes high, which forces
CHARGE high regardless of the PWM signal. The part is
now in the Refresh mode. Once the refresh period is over,
the DONE pin goes low, allowing the PWM signal to drive
the CHARGE pin once again. This function can be easily
implemented in a microcontroller. Figure 10 shows the
input current for the LT3420 and LT3420-1 as the duty
cycle of the PWM signal is varied.
A simple method to achieve adjustable input current is
shown in Figure 9. The PWM signal has a frequency of
DONE
CHARGE
A1
1kHz PWM
SIGNAL
A2
TO
LT3420
A3
CIRCUIT
3420 F09
ON
Figure 9. Simple Logic for Adjustable Input Current
800
600
LT3420
400
LT3420-1
200
0
10
30
50
70
90
DUTY CYCLE (%)
3420 F10
Figure 10. Input Current as Duty Cycle is Varied
3420fb
14
LT3420/LT3420-1
W U U
APPLICATIO S I FOR ATIO
U
BOARD LAYOUT
necessary to meet the breakdown specifications for the
circuit board. If the Photoflash capacitor is placed far
from the LT3420/LT3420-1 circuit, place a small (20nF-
50nF) ceramic capacitor with sufficient voltage rating
close to the part. This insures adequate bypassing.
Remember that LETHAL VOLTAGES ARE PRESENT in
this circuit. Use caution when working with the circuit.
The high voltage operation of the LT3420/LT3420-1
demands careful attention to board layout. You will not
get advertised performance with careless layout. Fig-
ures 11 and 12 show the recommended component
placement. Keep the area for the high voltage end of the
secondary as small as possible. Note the larger than
minimum spacing for all high voltage nodes. This is
CHARGE DONE
R2
C3
PHOTOFLASH
CAPACITOR
–
V
CC
+
C2
R1
T1
GND
C1
V
OUT
D1B
D1A
V
BAT
3420 F11
Figure 11. Suggested Layout (MS10 Package)
CHARGE DONE
R2
C3
PHOTOFLASH
CAPACITOR
–
V
CC
+
C2
R1
T1
GND
C1
V
OUT
D1B
D1A
V
BAT
3420 F12
Figure 12. Suggested Layout (DD Package)
3420fb
15
LT3420/LT3420-1
U
TYPICAL APPLICATIO S
Professional Charger uses Multiple LT3420 Circuits in Parallel to Charge Large Photoflash Capacitors Quickly
D1
V
BAT
320V
1.8V TO 6V
5, 6
8
C1
4.7µF
+
650µF*
350V
PHOTOFLASH
CAPACITOR
T1
1:12
3, 4
R1
1
DANGER HIGH VOLTAGE
OPERATION BY HIGH VOLTAGE
TRAINED PERSONEL ONLY
52.3k
2
3
6
V
R
FB
SW
BAT
V
4
CC
7
V
SEC
CC
2.5V TO 10V
C2
MASTER
4.7µF
9
LT3420
CHARGER
CHARGE
CHARGE
DONE
1
8
R
REF
GND
C
T
R2
2k
10
5
C3
0.1µF
D2
V
BAT
8
C4
5, 6
4.7µF
T2
1:12
3, 4
2
3
6
1
7
V
R
SW
BAT
FB
4
V
V
SEC
CC
CC
C5
R3
R4
4.7µF
9
SLAVE**
LT3420
100k 100k
CHARGER
CHARGE
DONE
1
8
R
REF
GND
C
T
Q1
2N3904
10
5
D3
V
BAT
5, 6
8
T3
1:12
C6
4.7µF
3, 4
2
3
6
1
7
V
R
SW
BAT
FB
4
V
V
SEC
CC
CC
C7
4.7µF
SLAVE**
CHARGER
LT3420
9
CHARGE
DONE
C1, C2, C4, C5, C6, C7: 4.7µF, X5R or X7R, 10V
T1-T3: TDK SRW10EPC-U01H003 FLYBACK TRANSFORMER
D1-D3: VISHAY GSD2004S SOT-23
1
8
R
REF
GND
C
T
DUAL DIODE. DIODES CONNECTED IN SERIES
Q1: 2N3904 OR EQUIVALENT
10
5
*
CAN CHARGE ANY SIZE PHOTOFLASH CAPACITOR
3420 TA01
** USE AS MANY SLAVE CHARGERS AS NEEDED.
3420fb
16
LT3420/LT3420-1
U
TYPICAL APPLICATIO S
LT3420 Photoflash Charging Circuit Uses Small Transformer
DANGER HIGH VOLTAGE
OPERATION BY HIGH VOLTAGE
TRAINED PERSONEL ONLY
T1*
1:12
V
BAT
300V
1.8V TO 5V
3
5
1
C1
D1
4.7µF
2
R1
47.5k
3
2
6
C4
220µF
330V
V
R
SW
BAT
FB
+
4
V
7
CC
V
SEC
CC
2.5V TO 10V
C2
PHOTOFLASH
CAPACITOR
4.7µF
LT3420
9
CHARGE
DONE
CHARGE
DONE
1
8
R
REF
GND
C
T
10
5
R2
2k
C3
0.1µF
C1: 4.7µF, X5R or X7R, 6.3V
C2: 4.7µF, X5R or X7R, 10V
C4: RUBYCON 220µF PHOTOFLASH CAPACITOR
D1: VISHAY GSD2004S SOT-23
3420 TA02
DUAL DIODE. DIODES CONNECTED IN SERIES
T1: KIJIMA MUSEN SBL-6.4
* MAXIMUM AMBIENT TEMPERATURE OF 60°C DICTATED BY TRANSFORMER
Efficiency
90
V
= V
= V
BAT IN
CC
80
70
60
50
40
V
= 5V
IN
V
= 3.3V
IN
50
150
200
(V)
250
300
350
100
V
OUT
3420 TA03
3420fb
17
LT3420/LT3420-1
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889
(.035
±
±
0.127
.005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
0.50
(.0197)
BSC
0.305
±
±
0.038
(.0120
.0015)
10 9
8
7 6
TYP
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4 5
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MS) 0603
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3420fb
18
LT3420/LT3420-1
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
R = 0.115
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.38 ± 0.10
TYP
6
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD10) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3420fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT3420/LT3420-1
U
TYPICAL APPLICATIO
LT3420-1 Photoflash Circuit Uses Tiny (3mm Tall) Transformer
T1
1:10.2
V
BAT
320V
1.8V TO 6V
4
1
5
C1
4.7µF
D1
Charge Time
8
10
8
V
CHARGED
OUT
DANGER HIGH VOLTAGE
OPERATION BY HIGH VOLTAGE
TRAINED PERSONEL ONLY
FROM 50V TO 320V
60.4k
2
3
6
SW
C3
100µF
330V
V
R
BAT
FB
+
4
V
7
CC
6
V
SEC
CC
2.5V TO 6V
C2
C
= 100µF
OUT
PHOTOFLASH
CAPACITOR
4.7µF
LT3420-1
9
4
CHARGE
DONE
CHARGE
DONE
1
8
R
REF
C
= 40µF
OUT
GND
C
2
T
10
5
2k
0.1µF
0
4
2
3
5
6
C1, C2: 4.7µF, X5R or X7R, 6.3V
V
(V)
3420 TA04
BAT
C3: RUBYCON 100µF PHOTOFLASH CAPACITOR
T1: TDK LDT565630T-002 FLYBACK TRANSFORMER
D1: VISHAY GSD2004S SOT-23
3420 TA05
DUAL DIODE. DIODES CONNECTED IN SERIES
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC®3400/LTC3400B 600mA (I ), 1.2MHz, Synchronous Step-Up
V
I
= 0.85V to 5V, V
= 5V, I = 19µA/300µA,
SW
IN
OUT(MAX) Q
DC/DC Converters
= <1µA, ThinSOTTM Package
SD
LTC3401/LTC3402
LTC3405/LTC3405A
LTC3406/LTC3406B
LTC3407
1A/2A (I ), 3MHz, Synchronous Step-Up
DC/DC Converters
V
= 0.5V to 5V, V
= 6V, I = 38µA, I = <1µA,
SW
IN
OUT(MAX) Q SD
MS Package
300mA (I ), 1.5MHz, Synchronous Step-Down
95% Efficiency, V = 2.7V to 6V, V
= 0.8V , I = 20µA,
Q
OUT
IN
OUT(MIN)
DC/DC Converters
I
= <1µA, ThinSOT Package
SD
600mA (I ), 1.5MHz, Synchronous Step-Down
95% Efficiency, V = 2.5V to 5.5V, V
= 0.6V, I = 20µA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
DC/DC Converters
I
= <1µA, ThinSOT Package
SD
Dual 600mA (I ), 1.5MHz, Synchronous Step-Down
95% Efficiency, V = 2.5V to 5.5V, V
= 0.6V, I = 40µA,
Q
OUT
IN
DC/DC Converter
I
= <1µA, ThinSOT Package
SD
LTC3411
1.25A (I ), 4MHz, Synchronous Step-Down
95% Efficiency, V = 2.5V to 5.5V, V
= 0.8V, I = 60µA,
Q
OUT
IN
DC/DC Converter
I
= <1µA, MS Package
SD
LTC3425
5A (I ), 8MHz, Multiphase Synchronous Step-Up
95% Efficiency, V = 0.5V to 4.5V, V
= 5.25V, I = 12µA,
Q
SW
IN
DC/DC Converter
I
= <1µA, QFN Package
SD
LTC3440/LTC3441
LT3464
600mA/1A (I ), 2MHz/1MHz, Synchronous Buck-Boost
95% Efficiency, V = 2.5V to 5.5V, V
= 2.5V, I = 25µA,
Q
OUT
IN
DC/DC Converters
I
= <1µA, MS Package
SD
85mA (I ), Constant Off-Time, High Efficiency
V
= 2.3V to 10V, V
= 34V, I = 25µA, I = <0.5µA,
Q SD
SW
IN
OUT(MAX)
Step-Up DC/DC Converter with Integrated Schottky
ThinSOT Package
and Output Disconnect
LTC3467
1.1A (I ), 1.3MHz, High Efficiency Step-Up
DC/DC Converter
V
= 2.4V to 16V, V
= 40V, I = 1.2mA, I = <1µA,
Q SD
SW
IN
OUT(MAX)
ThinSOT Package
LTC3468/LTC3468-1/ Photoflash Capacitor Charger in ThinSOT
LTC3468-2
Fast Photoflash Charge Times; 4.6sec for LT3468, 5.5sec for
LT3468-1, 5.7sec for LT3468-2
ThinsSOT is a trademark of Linear Technology Corporation.
3420fb
LT/LT 0305 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2002
相关型号：
LT3420EDD
LT3420 - Photoflash Capacitor Chargers with Automatic Refresh; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3420EDD#PBF
LT3420 - Photoflash Capacitor Chargers with Automatic Refresh; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3420EDD#TR
LT3420 - Photoflash Capacitor Chargers with Automatic Refresh; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3420EDD#TRPBF
LT3420 - Photoflash Capacitor Chargers with Automatic Refresh; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3420EDD-1
LT3420 - Photoflash Capacitor Chargers with Automatic Refresh; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3420EDD-1#PBF
LT3420 - Photoflash Capacitor Chargers with Automatic Refresh; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3420EDD-1#TRPBF
LT3420 - Photoflash Capacitor Chargers with Automatic Refresh; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3420EMS#PBF
LT3420 - Photoflash Capacitor Chargers with Automatic Refresh; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3420EMS#TR
LT3420 - Photoflash Capacitor Chargers with Automatic Refresh; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3420EMS#TRPBF
LT3420 - Photoflash Capacitor Chargers with Automatic Refresh; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明