LT1161 [Linear]
Quad Protected High-Side MOSFET Driver; 四受保护的高边MOSFET驱动器
| 型号： | LT1161 |
| 厂家： | 
Linear |
| 描述： | Quad Protected High-Side MOSFET Driver |
| 文件： | 总12页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1161
Quad Protected High-Side
MOSFET Driver
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FEATURES
DESCRIPTION
■
Fully Enhances N-Channel MOSFET Switches
The LT1161 is a quad high-side gate driver allowing the
use of low cost N-channel power MOSFETs for high-side
switching applications. It has four independent switch
channels, each containing a completely self-contained
charge pump to fully enhance an N-channel MOSFET
switch with no external components.
■
8V to 48V Power Supply Range
■
Protected from –15V to 60V Supply Transients
■
Individual Short-Circuit Protection
■
Individual Automatic Restart Timers
Programmable Current Limit, Delay Time, and
Auto-Restart Period
Voltage-Limited Gate Drive
Defaults to OFF State with Open Input
Flowthrough Input to Output Pinout
■
Also included in each switch channel is a drain sense
comparator that is used to sense switch current. When a
preset current level is exceeded, the switch is turned off.
The switch remains off for a period of time set by an
external timing capacitor and then automatically attempts
to restart. If the fault is still present, this cycle repeats until
the fault is removed, thus protecting the MOSFET.
■
■
■
■
Available in 20-Lead DIP or SOL Package
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APPLICATIONS
■
The LT1161 has been specifically designed for harsh
operating environments such as industrial, avionics, and
automotive applications where poor supply regulation
and/or transients may be present. The device will not
sustain damage from supply voltages of –15V to 60V.
Industrial Control
Avionics Systems
Automotive Switches
Stepper Motor and DC Motor Control
Electronic Circuit Breaker
■
■
■
■
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TYPICAL APPLICATION
24V
+
Switch Drop vs Load Current
50µF
50V
C
T
R
+
+
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
S
V
V
0.1µF
0.1µF
0.1µF
0.01Ω
DS1
G1
T1
T2
T3
T4
IRFZ34
LOAD
#1
0.01Ω
DS2
G2
IRFZ34
0.1µF
LT1161
LOAD
#2
0.01Ω
DS3
G3
IN1
IN2
IN3
IN4
INPUTS
IRFZ34
LOAD
#3
DS4
G4
0.01Ω
GND
GND
IRFZ34
0
1
2
3
4
5
LOAD
#4
LOAD CURRENT (A)
1161 TA01
1161 F01
Figure 1. Protected Quad High-Side Switch
1
LT1161
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
Supply Voltages (Pins 11, 20) ................... –15V to 60V
Input Voltages (Pins 3, 5, 7, 9) ...... (GND – 0.3V) to 15V
Gate Voltages (Pins 12, 14, 16, 18) ........................ 75V
Sense Voltages (Pins 13, 15, 17, 19)..................V+ ±5V
Current (Any Pin).................................................. 50mA
Operating Temperature Range
TOP VIEW
ORDER PART
+
NUMBER
1
2
V
20
19
18
17
16
15
GND
TIMER1
INPUT 1
TIMER 2
INPUT 2
TIMER 3
INPUT 3
TIMER 4
INPUT 4
GND
SENSE 1
GATE 1
SENSE 2
GATE 2
SENSE 3
LT1161CN
LT1161CS
LT1161IN
LT1161IS
3
4
5
LT1161C............................................... 0°C to 70°C
LT1161I............................................ – 40°C to 85°C
Junction Temperature Range (Note 1)
LT1161C.............................................. 0°C to 125°C
LT1161I......................................... – 40°C to 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
6
7
14 GATE 3
8
SENSE 4
GATE 4
13
12
11
9
+
10
V
N PACKAGE
20-LEAD PLASTIC DIP
S PACKAGE
20-LEAD PLASTIC SOL
θJA = 70°C/ W (N)
θJA = 110°C/ W (S)
Consult factory for Military grade parts.
TA = 25°C, V+ = 12V to 48V each channel, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
4.5
1
MAX
6.5
UNITS
mA
mA
V
I
Supply Current
All Channels OFF (Note 2)
3
S
∆I
Delta Supply Current (ON State) Measure Increase in I per Channel
1.35
S(ON)
S
V
V
Input High Voltage
Input Low Voltage
●
●
2
INH
0.8
V
INL
I
Input Current
V
V
= 2V
= 5V
●
●
15
55
30
110
50
185
µA
µA
IN
IN
IN
C
V
V
Input Capacitance
5
3
3.5
14
pF
V
V
IN
Timer Threshold Voltage
Timer Clamp Voltage
Timer Charge Current
V
V
V
= 2V, Adjust V
= 0.8V
●
2.7
3.2
9
3.3
3.8
20
T(TH)
T(CL)
IN
IN
IN
T
I
= V = 2V
µA
T
T
V
Drain Sense Threshold Voltage
Temperature Coefficient
50
65
+0.33
80
mV
%/°C
SEN
+
I
Drain Sense Input Current
Gate Voltage Above Supply
V
= 48V, V
= 65mV
0.5
1.5
µA
SEN
SEN
+
+
+
+
+
V
GATE
– V
V
V
V
V
= 8V
4
7
10
10
4.5
8.5
12
6
V
V
V
V
= 12V
= 24V
= 48V
●
●
●
10
14
14
12
+
+
+
t
t
t
Turn-ON Time
Turn-OFF Time
V
V
V
= 24V, V
= 24V, V
> 32V, C = 1000pF
GATE
100
220
75
400
200
50
µs
µs
µs
ON
OFF
OFF(CL)
GATE
< 2V, C
= 1000pF
GATE
+
GATE
Current Limit Turn-OFF Time
= 24V, (V – V
) → 0.1V, C
= 1000pF
GATE
25
SENSE
+
The
●
denotes specifications which apply over the full operating
Note 2: Both V pins (11, 20) must be connected together and both
temperature range.
ground pins (1, 10) must be connected together.
Note 1: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formulas:
D
LT1161CN, LT1161IN: T = T + (P × 70°C/W)
J
A
D
LT1161CS, LT1161IS: T = T + (P × 110°C/W)
J
A
D
2
LT1161
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TYPICAL PERFORMANCE CHARACTERISTICS
MOSFET Gate Voltage Above V+
MOSFET Gate Drive Current
Supply Current
20
18
16
14
12
10
8
16
14
12
10
8
100
10
1
T = 85°C
J
+
V
≥ 24V
T = –40°C
J
T = 25°C
J
+
V
= 12V
ALL CHANNELS ON
+
V
= 8V
6
ALL CHANNELS OFF
6
4
4
2
2
0.1
0
0
10
20
40
0
50
30
0
10
20
30
40
50
0
2
4
6
8
10 12 14 16
+
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
GATE VOLTAGE ABOVE V (V)
1161 G03
1161 G01
1161 G02
Supply Current
Input Threshold Voltage
Drain Sense Threshold Voltage
20
18
16
14
12
10
8
2.4
110
100
90
80
70
60
50
40
30
20
10
+
+
+
V
= 24V
V
= 24V
V
= 24V
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
TURN-ON
TURN-OFF
ALL CHANNELS ON
ALL CHANNELS OFF
6
4
2
0
–50
–25
25
50
75
100
–50
–25
25
50
75
100
–50
–25
25
50
75
100
0
0
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1161 G06
1161 G04
1161 G05
Turn-ON Time Driving MOSFET
Turn-OFF Time Driving MOSFET
Automatic Restart Period
100
90
80
70
60
50
40
30
20
10
0
1000
100
10
500
450
400
350
300
250
200
150
100
50
+
V
= 24V
IRFZ34
C
= 3.3µF
IRFZ34
T
C
T
= 1µF
T
NORMAL
C
= 0.33µF
CURRENT LIMIT
C
= 0.1µF
T
0
0
10
20
30
40
50
–50 –25
0
25
50
75
100
0
10
20
30
40
50
TEMPERATURE (°C)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1161 G08
1161 G07
1161 G09
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LT1161
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PIN FUNCTIONS
supply,theMOSFETgateforthatchannelisdrivenlowand
the corresponding timing capacitor discharged. Each cur-
rent-sensecomparatoroperatescompletelyindependently.
The 65mV typical threshold has a +0.33%/°C temperature
coefficient, which closely matches the TC of drain sense
resistors formed from copper PC traces.
Supply Pins:The two supply pins are internally connected
and must also be externally connected. In addition to
providingthe operatingcurrentfortheLT1161, the supply
pins also serve as the Kelvin connection for the current
sensecomparators.Thesupplypinsmustbeconnectedto
the positive side of the drain sense resistors for proper
operation of the current sense.
Some loads require high in-rush currents. An RC time
delay can be added between the drain sense resistor and
the sense pin to ensure that the current-sense comparator
does not false trigger during start-up (see Applications
Information). However, a maximum of 10kΩ can be in-
serted between a drain sense resistor and the sense pin. If
current sense is not required in any channel, the sense pin
for that channel is tied to supply.
Input Pins: The input pins are active high and each pin
activates a separate internal charge pump when switched
ON. The input threshold is TTL/CMOS compatible but may
be taken as high as 15V with or without the supply
powered. Each input has approximately 200mV of hyster-
esis and an internal 75k pull-down resistor.
Gate Pins: The gate pins drive the power MOSFET gates.
When an input is ON, the corresponding gate pin is
pumped approximately 12V above the supply. These pins
have a relatively high impedance when above the rail (the
equivalent of a few hundred kilohms). Care should be
taken to minimize any loading by parasitic resistance to
ground or supply.
Timer Pins: A timing capacitor CT from each timer pin to
ground sets the restart time following overcurrent detec-
tion. CT is rapidly discharged to less than 1V and then
recharged by a 14µA nominal current source back to the
timerthreshold,whereuponrestartisattempted.Ifcurrent
sense is not required in any channel, the timer pin for that
channel is left open.
Sense Pins: Each sense pin connects to the input of a
supply-referenced comparator with a 65mV nominal off-
set. When a sense pin is taken more than 65mV below
Ground Pins: The two ground pins are internally con-
nected and must also be externally connected.
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FUNCTIONAL DIAGRA
(Each Channel)
+
V
+
–
3V
14µA
65mV
+
TIMER
SENSE
–
+
–
OSCILLATOR
1.4V
GATE
AND
CHARGE PUMP
1.4V
75k
+
–
INPUT
75k
1161 FD
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LT1161
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OPERATIO (Each Channel, Refer to Functional Diagram)
The LT1161 gate pin has two states, OFF and ON. In the
OFF state it is held low, while in the ON state it is pumped
to 12V above supply by a self-contained 750kHz charge
pump. The OFF state is activated when either the input pin
is below 1.4V or the timer pin is below 3V. Conversely, for
the ON state to be activated, both the input and timer pins
must be above their thresholds.
WhentheMOSFETgatevoltageislessthan1.4V, thetimer
pin is released. The 14µA current source then slowly
charges the timing capacitor back to 3V where the charge
pump again starts to drive the gate pin high. If a fault still
exists, such as a short circuit, the sense comparator
threshold will again be exceeded and the timer cycle will
repeat until the fault is removed (see Figure 2).
Ifleftopen, theinputpinisheldlowbya75kresistor, while
the timer pin is held a diode drop above 3V by a 14µA pull-
up current source. Thus the timer pin automatically re-
verts to the ON state, subject to the input also being high.
The input has approximately 200mV of hysteresis.
OFF
NORMAL
OVERCURRENT
NORMAL
INPUT
12V
+
V
The sense pin normally connects to the drain of the power
MOSFET, which returns through a low valued drain sense
resistor to supply. When the gate is ON and the MOSFET
drain current exceeds the level required to generate a
65mV drop across the drain sense resistor, the sense
comparator activates a pull-down NPN which rapidly pulls
the timer pin below 3V. This in turn causes the timer
comparator to override the input pin and activate the gate
pinOFFstate, thusprotectingthepowerMOSFET. Inorder
for the sense comparator to accurately sense MOSFET
drain current, the LT1161 supply pins must be connected
directly to the positive side of the drain sense resistors.
GATE
0V
3V
TIMER
0V
1161 F02
Figure 2. Timing Diagram
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APPLICATIONS INFORMATION
Input/Supply Sequencing
rating, for supply voltages of 12V to 48V over the entire
temperature range. In order to maintain the OFF state, the
opto must have less than 20µA of dark current (leakage)
There are no input/supply sequencing requirements for
the LT1161. The input may be taken up to 15V with the
supply at 0V. When the supply is turned on with an input
high, the MOSFET turn-on will be inhibited until the timing
capacitor charges to 3V (i.e., for one restart cycle). The
two V+ pins (11, 20) must always be connected to each
other.
hot.
12V TO 48V
100k
1/4 NEC PS2501-4
2k
LOGIC
INPUT
IN
LT1161
51k
Isolating the Inputs
LOGIC
GND
GND
GND
Operation in harsh environments may require isolation to
prevent ground transients from damaging control logic.
The LT1161 easily interfaces to low cost opto-isolators.
The network shown in Figure 3 ensures that the input will
be pulled above 2V, but not exceed the absolute maximum
POWER
GROUND
1161 F03
Figure 3. Isolating the Inputs
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LT1161
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APPLICATIONS INFORMATION
Automatic Restart Period
Drain Sense Configuration
The timing capacitor CT shown in Figure 4 determines the
length of time the power MOSFET is held off following a
current limit trip. Curves are given in the Typical Perfor-
mance Characteristics to show the restart period for
various values of CT. For example, CT = 0.33µF yields a
50ms restart period.
The LT1161 uses supply-referenced current sensing. One
input of each channel’s current-sense comparator is con-
nectedtoadrainsensepin, whilethesecondinputisoffset
65mV below the supply bus inside the device. For this
reason, pins 11 and 20 of the LT1161 must be treated not
only as supply pins, but as the reference inputs for the
current-sense comparators.
Defeating Automatic Restart
Figure 4 shows the proper drain sense configuration for
the LT1161. Note that the sense pin goes to the drain end
of the sense resistor, while the two V+ pins are tied to each
other and connected to supply at the same point as the
positive ends of the sense resistors. Local supply
decoupling at the LT1161 is important at high input
voltages (see Protecting Against Supply Transients).
Some applications are required to remain off after a fault
occurs. When the LT1161 is being driven from CMOS
logic, this can be easily implemented by connecting
resistor R1 between the input and timer pins as shown in
Figure 5. R1 supplies the sustaining current for an SCR
whichlatchesthetimerpinlow.ThispreventstheMOSFET
gate from turning ON until the input has been recycled.
The drain sense threshold voltage has a positive tempera-
ture coefficient, allowing PTC sense resistors to be used
(see Printed Circuit Board Shunts). The selection of RS
should be based on the minimum threshold voltage:
TIMER
R1
2k
LT1161
50mV
5V
CMOS
LOGIC
ON = 5V
R =
S
INPUT
I
OFF = 0V
SET
Thusthe0.02ΩdrainsenseresistorinFigure4wouldyield
a minimum trip current of 2.5A. This simple configuration
is appropriate for resistive or inductive loads which do not
generate large current transients at turn-on.
1161 F05
Figure 5. Latch-Off Input Network (Auto-Restart Defeated)
Inductive vs Capacitive Loads
24V
+
100µF
Turning on an inductive load produces a relatively benign
ramp in MOSFET current. However, when an inductive
load is turned off, the current stored in the inductor needs
somewhere to decay. A clamp diode connected directly
across each inductive load normally serves this purpose.
If a diode isnotemployed the LT1161clampsthe MOSFET
gate 0.7V below ground. This causes the MOSFET to
resume conduction during the current decay with (V+ +
VGS + 0.7V) across it, resulting in high dissipation peaks.
50V
+
V
V
+
+
R
S
10µF
0.02Ω
LT1161
(PTC)
DS1
G1
1161 F04
IRFZ34
T1
C
T
GND
GND
1µF
24V, 2A
SOLENOID
Capacitive loads exhibit the opposite behavior. Any load
that includes a decoupling capacitor will generate a cur-
rent equal to CLOAD × (∂V/∂t) during capacitor in-rush.
With large electrolytic capacitors, the resulting current
Figure 4. Drain Sense Configuration
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LT1161
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APPLICATIONS INFORMATION
spike can play havoc with the power supply and false trip and CD delay the overcurrent trip for drain currents up to
the current-sense comparator.
approximately 10 × ISET, above which the diode conducts
and provides immediate turn-off (see Figure 7). To ensure
proper operation of the timer, CD must be ≤ CT.
Turn-on ∂V/∂t is controlled by the addition of the simple
network shown in Figure 6. This network takes advantage
of the fact that the MOSFET acts as a source follower
during turn-on. Thus the ∂V/∂t on the source can be
controlled by controlling the ∂V/∂t on the gate:
10
1
+
∂V V − V
TH
=
5
∂t
10 ×C1
0.1
0.01
whereVTH istheMOSFETgatethresholdvoltage. Multiply-
ing CLOAD times this ∂V/∂t yields the value of the current
spike. For example, if V+ = 24V, VTH = 2V, and C1 = 0.1µF,
∂V/∂t = 2.2V/ms, resulting in a 2.2A turn-on spike into
1000µF. The diode and second resistor in the network
ensure fast current limit turn-off.
1
10
100
MOSFET DRAIN CURRENT (1 = SET CURRENT)
L1161 F07
Figure 7. Current Limit Delay Time
When turning off a capacitive load, the source of the
MOSFET can “hang up” if the load resistance does not
discharge CLOAD as fast as the gate is being pulled down.
If this is the case, a diode may have to be added from
source to gate to prevent VGS(MAX) from being exceeded.
Printed Circuit Board Shunts
The sheet resistance of 1oz. copper clad is approximately
5 × 10–4Ω/square with a temperature coefficient of
+0.39%/°C. Since the LT1161 drain sense threshold has a
similar temperature coefficient (+0.33%/°C), this offers
the possibility of nearly zero TC current sensing using
“free” drain sense resistors made out of PC trace material.
CURRENT LIMIT
24V
DELAY NETWORK
+
V
+
+
1N4148
(≤10k)
V
C
D
R
D
DS
A conservative approach is to use 0.02" of width for each
1Aofcurrentfor1oz.copper.CombiningtheLT1161drain
sense threshold with the 1oz. copper sheet resistance
results in a simple expression for width and length:
LT1161
∂V/∂t CONTROL NETWORK
1N4148
100k
100k
C1
1RFZ24
G
+
Width (1oz. Cu) = 0.02" × ISET
C
LOAD
1161 F06
Length (1oz. Cu) = 2"
Thewidthfor2oz. copperwouldbehalvedwhilethelength
would remain the same.
Figure 6. ∂V/∂t Control and Current Limit Delay
Bends may be incorporated into the resistor to reduce
space; each bend is equivalent to approximately 0.6 ×
width of straight length. Kelvin connections should be
employed by running separate traces from the ends of the
resistors back to the LT1161 V+ and sense pins. See
Application Note 53 for further information on printed
circuit board shunts.
Adding Current Limit Delay
When capacitive loads are being switched or in very noisy
environments, it is desirable to add delay in the drain
current-sense path to prevent false tripping (inductive
loads normally do not need delay). This is accomplished
by the current limit delay network shown in Figure 6. RD
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LT1161
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APPLICATIONS INFORMATION
The second method shown in Figure 8 uses a quad
exclusive-NOR gate to indicate when the output of the
switchhasnotobeyedtheinputcommand(i.e.,outputlow
whenitshouldbehighorviceversa). Inadditiontocurrent
limit, this gives a fault indication if the switch is shorted or
Low Voltage/Wide Supply Range Operation
When the supply is <12V, the LT1161 charge pumps do
not produce sufficient gate voltage to fully enhance stan-
dard N-channel MOSFETs. For these applications, logic-
level MOSFETs can be used to extend operation down to
8V. If the MOSFET has a maximum VGS rating of 15V or
greater, then it can also be used up to the 60V (absolute
maximum) rating of the LT1161. MOSFETs are available
from both Motorola and Siliconix which meet these
criteria.
if the load is open.
24V
+
V
V
+
+
R
S
DS
G
LT1161
100k
R
INPUT
IN
OL
ADD FOR
Protecting Against Supply Transients
OPEN-LOAD
DETECTION
FAULT
1/4 MM74HC266A
The LT1161 is 100% tested and guaranteed to be safe
fromdamagewith60VappliedbetweentheV+ andground
pins. However, when this voltage is exceeded, even for a
fewmicroseconds, theresultcanbeacatastrophicfailure.
For this reason it is imperative that the LT1161 not be
exposed to supply transients above 60V.
LOAD
1161 F08
Figure 8. Fault Feedback Using Exclusive-NOR Gate
For proper current-sense operation, the V+ pins are re-
quired to be connected to the positive side of the drain
sense resistors (see Drain Sense Configuration). There-
fore, the best way to prevent supply transients is to ensure
that the supply is adequately decoupled at the point where
the V+ pins and drain sense resistors meet. Several
hundred microfarads may be required with high current
switches.
Low-Side Driving
Although the LT1161 is primarily targeted at high-side
(grounded load) switch applications, it can also be used
for low-side (supply-connected load), or mixed high- and
low-side switch applications. Figures 9a and 9b illustrate
LT1161switchchannelsdrivinglow-sidepowerMOSFETs.
Because the LT1161 charge pump tries to pump the gate
of the N-channel MOSFET above supply, a clamp zener is
required to prevent the VGS (absolute maximum) of the
MOSFET from being exceeded. The LT1161 gate drive is
current limited for this purpose so that no resistance is
needed between the gate pin and zener.
Whenoperatingvoltagesapproachthe60Vabsolutemaxi-
mum rating of the LT1161, local supply decoupling be-
tweentheV+ pins(11,20)andgroundpins(1,10)ishighly
recommended. A small ferrite bead between the supply
connection and local capacitor can also be effective in
suppressing transients. Note however, that resistance
should not be added in series with the V+ pins because it
will cause an error in the current sense threshold.
12V TO 48V
+
V
V
+
+
R
S
100µF
0.01Ω
(PTC)
DS
G
Fault Feedback
T
LT1161
1µF
4A
LOAD
Two methods can be used to derive switch status. First,
the timer pin voltage can be monitored to indicate when
the switch is turned off due to current limit. During normal
operation (ON or OFF), the timer voltage is 3.5V and only
during current limit does the voltage drop below 3V.
IRFZ44
15V
1N4744
1161 F09a
Figure 9a. Low-Side Driver with Load Current Sensing
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LT1161
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APPLICATIONS INFORMATION
8V TO 24V
HV
1N4148
supplyoperatingrangeoftheLT1161. Thisallowstheload
to be returned to supply through current-sense resistor
RS, providing normal operation of the LT1161 protection
circuitry.
10µF
+
HV
LOAD
HV
LOAD
+
+
V
V
DS1
G1
T1
51Ω
1µF
1µF
IRF630
If the load cannot be returned to supply through RS, or the
load supply voltage is higher than the LT1161 supply, the
currentsensemustbemovedtothesourceofthelow-side
MOSFET. Figure 9b shows two approaches to source
sensing. On channel 1, current limit occurs when the
voltageacrosssenseresistorRS1 thresholdstheVBE ofthe
NPN transistor, causing the LT1161 drain sense pin to be
pulled down.
LT1161
2N2222
15V
R
S1
1N4744
0.2Ω
51Ω
DS2
G2
T2
IRF630
+
1/2
LT1013
2N2222
15V
1N4744
R
S2
0.02Ω
–
51Ω
1161 F09b
The channel 2 circuit of Figure 9b uses an operational
amplifier(mustcommonmodetoground)tolevelshiftthe
voltage across RS2 up to the drain sense pin. This ap-
proach allows the use of a much smaller sense resistor
Figure 9b. Low-Side Drivers with Two Approaches
for Source Current Sensing
Current sensing for protecting low-side drivers can be which could be made from PC trace material. In both
done in several different ways. In the Figure 9a circuit, the cases, the LT1161 restart timers function the same as in
supply voltage for the load is assumed to be within the high-side switch applications.
U
TYPICAL APPLICATIONS
Using an Extra Channel to Do Common Current Limit for Multiple/Paralleled Switches
24V
100k
1
2
20
19
18
17
16
15
14
13
12
11
+
+
GND
T1
V
10µF
50V
1µF
R
S
DS1
G1
+
15k
3
IN1
T2
4
DS2
G2
5
IRFZ44
IRFZ44
IRFZ44
IN2
T3
LT1161
6
DS3
G3
7
INPUTS
(MAY BE PARALLELED)
IN3
T4
OUTPUTS
(MAY BE PARALLELED)
8
DS4
G4
9
IN4
GND
10
+
1161 TA05
V
9
LT1161
TYPICAL APPLICATIONS
U
Protected Quad 1A Automotive Solenoid Driver with Overvoltage Shutdown
8V TO 28V OPERATING
32V TO 60V SHUTDOWN
1
2
20
19
18
17
16
15
14
13
12
11
+
GND
T1
V
+
0.33µF
0.33µF
0.33µF
0.33µF
10µF
100V
0.03Ω
MTD3055EL
0.03Ω
DS1
G1
1N4148
3
IN1
T2
4
DS2
G2
1N4148
5
IN2
T3
MTD3055EL
LT1161
6
0.03Ω
INPUTS
DS3
G3
1N4148
7
MTD3055EL
0.03Ω
IN3
T4
8
DS4
G4
1N4148
9
MTD3055EL
IN4
GND
10
+
V
2N3904
10k
30V
1N6011B
5.1k
1161 TA03
Protected Quad Switch with Mixed Low- and High-Side Driving
10µF
24V
0.01Ω
+
1
2
20
19
18
17
16
15
14
13
12
11
+
GND
T1
V
0.33µF
MTP36N06E
24V/3A
LOAD
DS1
G1
0.01Ω
3
+
IN1
T2
100µF
0.33µF
HIGH-SIDE DRIVER
INPUTS
MTP36N06E
1N4148
50V
4
DS2
G2
24V/3A
LOAD
(SEE NOTE 1)
5
IN2
T3
LT1161
2k
2k
6
150V/1A
LOAD
150V
DS3
G3
51Ω
7
MTP10N40E
IN3
T4
15V
1N4744
LOW-SIDE DRIVER
INPUTS
8
DS4
G4
2N2222
2N2222
(SEE NOTE 2)
1N4148
9
0.4Ω
IN4
GND
10
+
150V/1A
LOAD
V
51Ω
MTP10N40E
15V
1N4744
NOTE 1: THE HIGH-SIDE DRIVER CHANNELS ARE CONFIGURED
TO AUTOMATICALLY RESTART FOLLOWING A FAULT.
NOTE 2: THE LOW-SIDE DRIVER CHANNELS ARE CONFIGURED
TO LATCH OFF FOLLOWING A FAULT. 5V CMOS LOGIC INPUTS
ARE REQUIRED.
0.4Ω
1161 TA04
10
LT1161
U
TYPICAL APPLICATIONS
Protected Quad 2A Industrial Switch with Isolated Inputs and Fault Output
24V
1
2
NEC PS2501-4
20
19
18
17
16
15
14
13
12
11
+
GND
T1
V
5.1k
5.1k
+
50µF
50V
1µF
1µF
1µF
1µF
+
0.015Ω
DS1
G1
3
RFD16N05
0.015Ω
IN1
T2
LOAD
#1
4
+
+
+
DS2
G2
INPUTS
100k
5
RFD16N05
0.015Ω
IN2
T3
5.1k
5.1k
LT1161
LOAD
#2
6
DS3
G3
7
100k
IN3
T4
RFD16N05
LOAD
#3
8
0.015Ω
DS4
G4
9
100k
IN4
GND
RFD16N05
LOAD
#4
10
+
V
24V
MM74HC266A
100k
18k
2N3904
1161 TA02
5.6V
1N5994B
4N28
5.1k
0.1µF
FAULT
OUTPUT
2k
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LT1161
U
PACKAGE DESCRIPTION
Dimension in inches (millimeters) unless otherwise noted.
N Package
20-Lead Plastic DIP
1.040
(26.416)
MAX
20
19
18
17
16
15
14
13
12
11
10
0.260 ± 0.010
(6.604 ± 0.254)
3
4
5
6
7
8
9
1
2
0.300 – 0.325
0.045 – 0.065
0.130 ± 0.005
(7.620 – 8.255)
(1.143 – 1.651)
(3.302 ± 0.127)
0.015
(0.381)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.025
–0.015
0.325
0.125
(3.175)
MIN
0.065 ± 0.015
(1.651 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
N20 0592
S Package
20-Lead Plastic SOL
0.496 – 0.512
(12.598 – 13.005)
(NOTE 2)
19 18
16
14 13 12 11
20
17
15
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
2
3
5
7
8
9
10
1
4
6
0.291 – 0.299
(7.391 – 7.595)
(NOTE 2)
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.005
(0.127)
RAD MIN
0.010 – 0.029
× 45°
(0.254 – 0.737)
0° – 8° TYP
0.050
(1.270)
TYP
0.004 – 0.012
0.009 – 0.013
(0.229 – 0.330)
(0.102 – 0.305)
NOTE 1
0.014 – 0.019
0.016 – 0.050
(0.406 – 1.270)
SOL20 0392
(0.356 – 0.482)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
LT/GP 0494 10K • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
12
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1994
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