LD7591GN_技术文档

LD7591

3/4/2010

Transition-Mode PFC Controller with Fault Condition Protection

REV. 00

General Description

Features

The LD7591 is a voltage mode PFC controller operating on

transition mode, with several integrated functions of

protection, such as OVP, OCP, and Brown-in protection. It

reduces the components counts and is available in a

SOP-8 or DIP-8 package. Those make it an ideal design

for low cost applications.

z

Transition mode of PFC pre-regulator

Voltage mode control

Programmable max. on-time

Low Startup Current (<30μA)

UVLO (Under Voltage Lockout)

LEB (Leading-Edge Blanking) on CS Pin

Open-Feedback Protection and Disable Function

OVP (Over Voltage Protection)

OCP (Cycle by cycle current limiting)

800/-1200mA Driving Capability

Internal OTP function

It provides functions of low startup current, over voltage

protection, open feedback protection, disable function,

over current protection, under voltage lockout and

integrated LEB of current sensing. Unlike the traditional

current mode PFC controller, LD7591 is free from extra

rectified AC line voltage information to minimize the power

loss.

Applications

z

Adaptor of Output above 65W.

Open Frame Switching Power Supply

LCD TV Power Supply

The LD7591 will be disabled if INV pin voltage falls below

0.45V and the operating current rises over 65μA

LED Power Supply

Typical Application for Boost PFC

AC

EMI

Input

Filter

7

GATE

8

VCC

ZCD

4

CS

LD7591

5

1

2

INV

3

RAMP

COMP

GND

6

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LD7591

Typical Application for LED (Flyback PFC)

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LD7591

Pin Configuration

SOP-8 & DIP-8 (TOP VIEW)

8

7

6

5

YY:

WW:

PP:

Year code (D:2004, E:2005…)

Week code

Production code

TOP MARK

YYWWPP

1

2

3

4

Ordering Information

Part number

Package

Top Mark

Shipping

LD7591 GS

LD7591 GN

SOP-8

DIP-8

Green package

LD7591GS

LD7591GN

2500 /tape & reel

3600 /tube /Carton

Pin Descriptions

NAME

FUNCTION

Output voltage feed back control

1

INV

COMP

RAMP

CS

Output of the error amplifier for voltage loop compensation to achieve stable

Ramp generator, connecting a resistor to GND pin to set the saw tooth signal

Current sense pin, connect to sense the MOSFET current for OCP

Detecting zero crossing of input signal

2

3

4

5

ZCD

Ground

6

GND

OUT

VCC

Gate drive output to drive the external MOSFET

Power source VCC pin

7

8

Recommended Operating Conditions

Item

Vcc pin capacitor

Comp pin capacitor

RAMP pin resistor

Min.

Max.

47

Unit

μF

Ω

22

0.1

4.7

4.7k

100k

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Block Diagram

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Absolute Maximum Ratings

Supply Voltage VCC

-0.3 ~26V

-0.3 ~VCC +0.3V

-0.3 ~7V

OUT

COMP, INV, CS, RAMP, ZCD

Maximum Junction Temperature

150°C

Operating Junction Temperature Range

Operating Ambient Temperature Range

Storage Temperature Range

-40°C to 125°C

-40°C to 85°C

-65°C to 150°C

160°C/W

Package Thermal Resistance (SO-8, θ_JA)

Package Thermal Resistance (DIP-8, θ_JA)

Power Dissipation (SOT-8, at Ambient Temperature = 85°C)

Power Dissipation (DIP-8, at Ambient Temperature = 85°C)

Lead temperature (Soldering, 10sec)

ESD Voltage Protection, Human Body Model

ESD Voltage Protection, Machine Model

Gate Output Current

100°C/W

400mW

650mW

260°C

2.5 KV

250 V

800mA/-1200mA

Caution:

Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only

rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification

is not implied.

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Electrical Characteristics

(V_CC=14.0V, T_A= 25^°C unless otherwise specified.)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage (VCC Pin)

Startup Current

VCC<UVLO ON

V_COMP=0V

20

2.0

2.5

0.45

65

30

μA

mA

μA

V

Operating Current

V_COMP=3V

V_CCOVP

V_INV=0V

(with 1nF load on OUT pin)

95

UVLO (off)

7.5

11.0

19.5

8.5

12.0

21

9.5

UVLO (on)

13.0

22.5

V

VCC OVP Level

V

Error Amplifier (Comp Pin)

Feedback Input Voltage, V_REF

Input Bias Current

Transconductance

Output Sink Current

Output Source Current

2.465

-0.5

2.500

2.535

0.5

V

μA

V_INV=1V~4V

140

14

μmho

μA

V_INV= V_REF+0.1V

V_INV= V_REF-0.1V

V_INV= V_REF-0.5V

V_INV= V_REF-0.1V

-14

μA

-200

μA

Output Upper Clamp Voltage

5.4

5.9

0.95

50

6.4

V

Burst Mode COMP pin Threshold

voltage

Hysteresis

mV

INV pin

2.62

0.4

2.675

0.175

0.45

0.1

2.73

0.5

V

OVP Trip Level

OVP Hysteresis

Enable Threshold Voltage

Enable Hysteresis

Current Sensing (CS Pin)

Current Sense Input Threshold Voltage

0.75

0

0.8

0.85

1.0

V

Input bias current

V_CS=0V~1V

μA

LEB time

250

ns

Zero Current Detector (ZCD Pin)

Upper Clamp Voltage

Lower Clamp Voltage

I_DET=100μA

6.0

-0.7

0.1

1.0

250

V

0.05

0.0

0.15

V

Input Voltage Threshold

Hysteresis

V

Input bias current

V_ZCD=1V~4V, OUT=OFF

μA

ns

Maximum Delay from ZCD to Output

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PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Maximum ON-Time, Ton-max (Ramp Pin)

V

Maximum On Time Voltage

Maximum On Time Programming

Maximum On Time

R_RAMP=40.5K

2.784

19

2.900V

24

3.016

29

μs

R_RAMP≥ 100K

40

Minimum OFF-Time

1

μs

Minimum OFF-Time

Ton-

max

Minimum OFF-Time Programming

0.10

Gate Drive Output (OUT Pin)

Output Low Level

Output High Level

Output High Clamp Level

Rising Time

V_CC=12V, I_SINK=20mA

V_CC=12V, I_SOURCE=20mA

V_CC=18V

0.5

12

V

9

13

75

25

V

V_CC=12V, CL=1000pF

150

100

ns

Falling Time

Starter

Start Timer Period

OTP (Over Temp. Protection)

OTP Trip level

50

150

300

μs

140

30

°C

OTP Hysteresis

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Typical Performance Characteristics

10

13.5

9.5

13.0

12.5

12.0

11.5

11.0

9.0

8.5

8.0

7.5

-40

0

40

80

120 125

-40

40

80

120 125

0

Temperature (°C)

Fig. 1 UVLO (on) vs. Temperature

Fig. 2 UVLO (off ) vs. Temperature

30

35

30

25

20

15

10

28

26

24

22

20

18

125

120

-40

0

40

80

-40

40

80

120 125

0

Temperature (°C)

Fig. 4 VCC OVP vs. Temperature

Fig. 3 Startup Current vs. Temperature

2.54

2.75

2.52

2.50

2.48

2.46

2.44

2.7

2.65

2.6

2.55

2.5

-40

40

80

120 125

-40

40

80

120 125

0

Temperature (°C)

Fig. 5 Vref vs. Temperature

Fig. 6 INV OVP vs. Temperature

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0.55

0.5

0.83

0.82

0.81

0.80

0.79

0.78

0.45

0.4

0.35

0.3

-40

40

80

120 125

-40

0

40

80

120 125

0

Temperature (°C)

Fig. 8 V_CS(off) vs. Temperature

Fig. 7 Enable Voltage vs. Temperature

2.96

2.94

2.92

2.9

26

25

24

23

22

21

2.88

2.86

-40

0

40

80

120 125

-40

40

80

120 125

0

Temperature (°C)

Fig. 9 Maximum On-Time Voltage vs. Temperature

Fig. 10 Maximum On-Time vs. Temperature

165

160

155

150

145

140

-40

40

80

120 125

0

Temperature (°C)

Fig. 11 Start Timer Period vs. Temperature

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Application Information

Vcc voltage is high enough to turn on the LD7591 and

further to deliver the gate drive signal, the supply current

is provided from the auxiliary winding of the PFC choke.

Lower startup current requirement on the PFC controller

will help to increase the value of R1 and then reduce the

power consumption on R1. By using CMOS process and

the special circuit design, the maximum startup current of

LD7591 is only 30μA. If a higher resistance value of R1 is

chosen, it usually takes more time to start up. To carefully

select the value of R1 and C1 will optimize the power

consumption and startup time.

Operation Overview

The LD7591 is an excellent voltage mode PFC controller.

It meets the IEC61000-3-2 requirement and is intended

for the use in those pre-regulator that demand low power

harmonics distortion. It integrated more functions to

reduce the external components counts and the size. Its

major features are described as below.

Under Voltage Lockout (UVLO)

An UVLO comparator is implemented in it to detect the

voltage on the VCC pin. It would assure the supply

voltage enough to turn on the LD7591 PFC controllers

and further to drive the power MOSFET. As shown in

Fig. 12, a hysteresis is built in to prevent the shutdown

from the voltage dip during start up. The turn-on and

turn-off threshold level are set at 12.0V and 8.5V,

respectively.

Vcc

UVLO(on)

UVLO(off)

Fig. 13

Output Voltage Setting

The LD7591 monitors the output voltage signal at INV pin

t

through

a

resistor divider pair Ra and Rb.

A

I(Vcc)

operating current

(~ mA)

transconductance amplifier is used instead of the

conventional voltage amplifier. The transconductance

amplifier (voltage controlled current source) aids the

implementation of OVP and disables function. The output

current of the amplifier changes according to the voltage

difference of the inverting and non-inverting input of the

amplifier. The output voltage of the amplifier is compared

with the internal ramp signal to generate the turn-off

signal. The output voltage is determined by the following

startup current

(~uA)

t

Fig. 12

Startup Current and Startup Circuit

The typical startup circuit to generate the LD7591 Vcc is

shown in Fig. 13. During the startup transient, the Vcc is

lower than the UVLO threshold thus there is no gate pulse

produced from LD7591 to drive power MOSFET.

Therefore, the current through R1 will provide the startup

current and to charge the capacitor C1. Whenever the

relationship.

Ra

V_OUT= 2.5V(1+

)

Rb

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LD7591

Where Ra and Rb are top and bottom feedback resistor

values (as shown in the Fig. 14).

Fig. 15

Fig. 14

Zero Current Detection (ZCD)

OVP and Disable on INV pin

Fig. 16 shows typical ZCD-block. The Zero Current

Detection block will switch on the external MOSFET as

the current through the boost inductor drops to zero in

using an auxiliary winding coupled with the inductor. This

feature allows transition-mode operation. If the voltage of

the ZCD pin goes higher than 0.2V, the ZCD comparator

waits until the voltage rises above 0.1V. If the voltage

goes below 0.1V, the zero current detector will turn on the

MOSFET. The ZCD pin is protected internally by two

clamps, 6.0V-high clamp and -0.7V-low clamp. The

150μs timer generates a MOSFET turn on signal if the

driver output has been low for more than 150μs from the

falling edge of the driver output.

To prevent the over voltage on the output capacitor from

the fault condition, LD7591 is implemented with an OVP

function on INV pin. Whenever the INV voltage is higher

than the OVP threshold voltage 2.675V, the output gate

drive circuit will be shutdown simultaneously thus to stop

the switching of the power MOSFET until the INV pin

down to 2.5V. The OVP function in LD7591 is an

auto-recovery type protection. The Fig. 15 shows its

operation. On the other hand, if the OVP condition is

removed, the Vcc level will get back to normal level and

the output will automatically return to the normal

operation.

The disable comparator disables the operation of the

LD7591 when the voltage of the inverting input is lower

than 0.35V and there is 100mV hysteresis. An external

small signal MOSFET can be used to disable the IC,

referring to Fig. 14. The IC operating current decreases

below 65μA to reduce power consumption if the IC is

disabled.

Fig. 16

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Fig. 17 shows typical ZCD-related waveforms. Rz1 will

produce some delay because of the capacitance carried

by ZCD pin, it therefore delay the turn-on time accordingly.

The switch will be turned on when the inductor current

reaches zero; because of the structure of the ZCD delay,

it will be turned on after some delay time. During this

delay time, the stored charge of the COSS (MOSFET

output capacitor) will be discharged through the path

indicated in Fig. 18. This charge is transferred into a small

filter capacitor C_IN1, which is connected to the bridge

diode. Therefore, there is no current flowing from the

input side. That is, the input current I_INis zero during this

period. In order to reduce the negative current flowing to

the internal diode, a larger resistance of R_Z1over 47kΩ is

recommended.

Fig. 18

Ramp Generator Block

The output of the gm error amplifier and the output of the

ramp generator block are compared to determine the

MOSFET on time, as shown in Fig. 19. The slope of the

ramp is determined by an external resistor connected to

the RAMP pin. The voltage of the RAMP pin is 2.9V and

the slope is proportional to the current flowing out of the

RAMP pin. The internal ramp signal has a 1V offset;

therefore, the drive output will be shut down if the voltage

of the COMP pin is lower than 0.95V. The programmed

on-time will be at its maximum when the COMP pin is

open. The COMP pin open voltage is about 5.4~6.6V.

According to the slope of the internal ramp, the maximum

on-time can be programmed. The necessary maximum

on-time will be achieved depending on the boost inductor,

lowest AC line voltage, and maximum output power. The

resistor value should be designed properly. The

maximum on-time can be obtained from below

R_RAMP

T_{ON−Time(MAX)}

=

1.58 ⋅10⁹

Fig. 19

Fig. 17

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and PCB layout. It is strongly recommended to adopt a

smaller R-C filter for higher power application to avoid the

CS pin being damaged by the negative turn-on spike.

Output Drive Stage

An output stage of

a CMOS buffer, with typical

800mA/-1200mA driving capability, is incorporated to

drive a power MOSFET directly. The output voltage is

clamped at 13V to protect the MOSFET gate even when

the VCC voltage is higher than 13V.

Current

Sensing

and

Leading-edge

Blanking

The typical voltage mode of PFC controller feedbacks the

voltage signals to close the control loop and achieve

regulation. The LD7591 detects the primary MOSFET

current from the CS pin, which is for the pulse-by-pulse

current limit. The maximum voltage threshold of the

current sensing pin is set at 0.8V. From above, the

Fig. 20

Fault Protection

There are several critical protections integrated in the

LD7591 to prevent the power supply or adapter from

being damaged. Those damages usually come from open

or short condition on the pins of LD7591.

MOSFET peak current can be obtained from below.

0.8V

I_PEAK(MAX)

=

R_S

A 250ns leading-edge blanking (LEB) time is included in

the input of CS pin to prevent the false-trigger from the

current spike. The R-C filter may be eliminated in some

low power applications, such as the pulse width of the

turn-on spikes is below 250ns and the negative spike on

the CS pin is below -0.3V.

Under the conditions listed below, the gate output will turn

off immediately to protect the power circuit ---

1.

2.

3.

Ramp pin short to ground

Ramp pin floating

CS pin floating

However, the pulse width of the turn-on spike is

determined according to the output power, circuit design

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Reference Application Circuit --- 400V/100W (90~264V_AC)

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LD7591

BOM

P/N

Component Value

250V,T2A

Note

P/N

C1

Component Value

0.1μF,X-cap

Note

Fuse

NTC

R1

3A,5Ω

C2

0.22μF,X-cap

2200pF,Y1-cap

NC

24 kΩ, 0805

620 kΩ, 0805

330 kΩ, 1206

270 Ω, 1206

110 kΩ, 0805

24 Ω, 0805

0.18 Ω

C3

R2

C4

R3

CY1

C5

MPF

R3B

R4

0.47μF,400V

33μF, 50V

MPF

C5B

C6

Electrolytic Capacitor

R5

R6

C61

C7

100nF, 25V ,0805

100nF, 50V, 0805

220nF, 25V, 0805

100μF, 450V

1000pF, 1kV, 1206

10nF, 100V, 1206

NC

R61

R7

C8

1/2W

Electrolytic Capacitor

R8

10 kΩ, 0805

22 kΩ, 1206

2 MΩ, 1206

27 kΩ, 0805

360 kΩ, 0805

1 MΩ, 1206

11 kΩ, 0805

0 Ω, 0805

C9

R9

C91

C10

C11

C12

C13

C14

CB2

D1

R10

R10B

R11

R12

R13

RZ2

RZ3

RB4

RZ3

RB4

100pF/ 16V, 0805

330pF/ 1kV/1206

100pF/ 1kV/1206

100pF/16V, 0805

LL4148

SOD-80

600V/ 2A, DO-15

SOD-80

200 Ω, 0805

0 Ω, 0805

D2

ER206

D3

LL4148

600V/2A, DO-15

SOD-80

DB

ZD1

BD

L1

UF206G

200 Ω, 0805

GLZ18C, 18V Zener

SBU4J or GBU4J

Leadtrend’s Design

FQP13N50C

LD7591

600V/4A

220uH

LF1

LF2

Q1

500V, 13A, TO-220

SOP-8

IC1

V1

Varistor

NC

EI30, 44/6

400uH

T1

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Reference Application Circuit --- LED -42V/350mA (90~264V_AC)

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LD7591

BOM

P/N

Component Value

2A/250V

Note

P/N

Component Value

0.1μF / 275VAC

4.7nF/1kV,1206

0.047μF / 400V

0.1μF / 400V

22uF/ 50V

Note

Fuse

NTC

V1

C1

C2

C5

X-cap

0Ω, 1206

Varisitor

471

MPF 塑膠電容

R1

27kΩ, 0805

300kΩ, 0805

110kΩ, 1206

39Ω, 1206

100kΩ, 0805

10kΩ, 0805

51Ω, 0805

0Ω, 0805

C5B

C6

MPF 塑膠電容

R2

Electrolytic Capacitor

R3

C61

C62

C9

104pF/25V/0805

33uF/ 50V

R3B

R4

330μF, 50V

NC, 0805

Electrolytic Capacitor

R5

C9A

C11

C12

C13

C14

C15

C16

C101

C102

C103

C104

C105

CB2

D1

R5B

R6

10pF, 0805

470pF/500V, 1206

0.47μF/ 16V, 0805

2200pF,

R61

R7

0.75Ω

1/2W

2W

R9

20kΩ, 0805

0.68Ω,

Y 電容

R12

R12B

R13

R14

R15

R15B

R16

R17

RB4

R101

R102

R103

R104

R104B

R105

R106

R107

R108

R109

R110

R111

R112

R113

R114

IC1

NC /1kV,1206

2.2uF/ 50V

4.7μF/10V/0805

0.1μF/ 25V, 0805

1μF/ 25V, 0805

473pF/25V/0805

220pF/16V, 0805

BAV103

NC,1206

100Ω, 1206

1kΩ, 0805

7.5MEGΩ, 0805

620kΩ, 0805

100kΩ, 1206

200Ω, 0805

NC, 0805

D2

ER502

200V/ 5A,

SOD-80

1000V/1A

SOD-80

D3

LL4148

8.2V Zener

91k

D4

LL4148

D5

1N4007

0Ω, 0805

D6

LL4148

10kΩ, 0805

20kΩ, 0805

75kΩ, 0805

5.6kΩ, 0805

39kΩ, 0805

10kΩ, 0805

100kΩ, 0805

15kΩ

D7

LL4148

DZ1

DZ2

DZ3

BD

NC

P6KE200A

DI106

DO-15

600V/1A

106/32/13

T1

EF20, 1150uH

UU9.8

LF1

LF2

Q1

1000uH

4.7kΩ, 0805

NC, 0805

FQPF5N60C

330R, 0805

600V, 4.5A, TO-220

Q2

0Ω, 0805

LD7591

SOP-8

IC2

PC817

IC3

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Package Information

SOP-8

Dimensions in Millimeters

Dimensions in Inch

Symbols

MIN

MAX

MIN

MAX

A

B

C

D

4.801

3.810

1.346

0.330

5.004

3.988

1.753

0.508

0.189

0.150

0.053

0.013

0.197

0.157

0.069

0.020

F

H

I

1.194

0.178

0.102

5.791

0.406

0°

1.346

0.229

0.254

6.198

1.270

8°

0.047

0.007

0.004

0.228

0.016

0°

0.053

0.009

0.010

0.244

0.050

8°

J

M

θ

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Package Information

DIP-8

Dimension in Millimeters

Dimensions in Inches

Symbol

Min

Max

10.160

7.112

5.334

0.584

1.778

2.743

3.556

8.255

------

Min

Max

0.400

0.280

0.210

0.023

0.070

0.108

0.140

0.325

--------

A

B

C

D

E

F

I

9.017

6.096

-----

0.355

0.240

------

0.356

1.143

2.337

2.921

7.366

0.381

0.014

0.045

0.092

0.115

0.29

J

L

0.015

Important Notice

Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers

should verify the datasheets are current and complete before placing order.

19

Leadtrend Technology Corporation www.leadtrend.com.tw

LD7591-DS-00 March 2010

LD7591

Revision History

Rev.

00

Date

Change Notice

3/4/2010

Original Specification

20

Leadtrend Technology Corporation www.leadtrend.com.tw

LD7591-DS-00 March 2010


型号：	LD7591GN
厂家：	Leadtrend Technology
描述：	Transition-Mode PFC Controller with Fault Condition Protection 功率因数校正
文件：	总20页 (文件大小：432K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LD7591GN [LEADTREND]

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