PALLV16V8-10PC [LATTICE]
Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic; 低电压，零功耗的20引脚EE CMOS通用可编程阵列逻辑
| 型号： | PALLV16V8-10PC |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic |
| 文件： | 总22页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
COM’L:-10
IND:-20
PALLV16V8-10 and PALLV16V8Z-20
Low Voltage, Zero Power 20-Pin EE CMOS
Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
Low -voltage operation, 3.3 V JEDEC compatible
— V = +3.0 V to +3.6 V
Pin and function compatible w ith all 20-pin PAL devices
Electrically-erasable CMOS technology provides reconfigurable logic and full testability
Direct plug-in replacement for the PAL16R8 series
CC
®
Designed to interface w ith both 3.3-V and 5-V logic
Outputs programmable as registered or combinatorial in any combination
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on pow er up
Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
Extensive third-party softw are and programmer support
Fully tested for 100% programming and functional yields and high reliability
GENERAL DESCRIPTION
The PALLV16V8 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable
CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells
provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8, with the
exception of the PAL16C1.
The PALLV16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALLV16V8Z allows battery powered operation for an extended period.
The PALLV16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can
always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate cells
in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The sum
of these products feeds the output macrocell. Each macrocell can be programmed as registered or
combinatorial with an active-high or active-low output. The output configuration is determined by
two global bits and one local bit controlling four multiplexers in each macrocell.
Publication# 1 771 3
Amendment/0
Rev: E
Issue Date: November 1 998
BLOCK DIAGRAM
I - I
CLK/
1
8
I0
8
Programmable AND Array
32 x 64
MACRO
MACRO
MC
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MC
0
MC
2
MC
3
MC
4
MC
5
MC
6
MC
7
1
OE/I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
0
1
2
3
4
5
6
7
17713D-1
FUNCTIONAL DESCRIPTION
The PALLV16V8 is a low-voltage, EE CMOS version of the PALCE16V8.
The PALLV16V8Z is a low-voltage, EE CMOS version of the PALCE16V8. In addition, the
PALLV16V8Z has zero standby power and an unused product term disable feature for reduced
power consumption.
The PALLV16V8 is a universal PAL device. It has eight independently configurable macrocells
(MC -MC ). Each macrocell can be configured as registered output, combinatorial output,
0
7
combinatorial I/O or dedicated input. The programming matrix implements a programmable AND
logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary
outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either as array
inputs or as clock (CLK) and output enable (OE), respectively, for all flip-flops.
Unused input pins should be tied directly to V or GND. Product terms with all bits
CC
unprogrammed (disconnected) assume the logical HIGH state and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALLV16V8 are automatically configured from the user’s
design specification. The design specification is processed by development software to verify the
design and create a programming file. This file, once downloaded to a programmer, configures the
device according to the user’s desired function.
2
PALLV16V8-10 and PALLV16V8Z-20 Families
The user is given two design options with the PALLV16V8. First, it can be programmed as a
standard PAL device from the PAL16R8 and PAL10H8 series. The PAL programmer manufacturer
will supply device codes for the standard PAL device architectures to be used with the PALLV16V8.
The programmer will program the PALLV16V8 in the corresponding architecture. This allows the
user to use existing standard PAL device JEDEC files without making any changes to them.
Alternatively, the device can be programmed as a PALLV16V8. Here the user must use the
PALLV16V8 device code. This option allows full utilization of the macrocell.
To
Adjacent
Macrocell
1 1
1 0
0 0
0 1
OE
CC
1 1
V
0 X
1 0
SL0
X
SG1
1 1
0 X
I/O
X
D
Q
Q
1 0
SL1
X
CLK
1 0
1 1
0 X
From
Adjacent
Pin
SL0
*SG1
X
*In macrocells MC and MC , SG1 is replaced by SG0 on the feedback multiplexer.
17713D-004
0
7
Figure 1. PALLV16V8 Macrocell
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial output,
combinatorial I/O, or dedicated input. In the registered output configuration, the output buffer is
enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a
product term or always enabled. In the dedicated input configuration, it is always disabled. With
the exception of MC0 and MC7, a macrocell configured as a dedicated input derives the input signal
from an adjacent I/O. MC0 derives its input from pin 11 (OE) and MC7 from pin 1 (CLK).
The macrocell configurations are controlled by the configuration control word. It contains 2 global
bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0 determines
whether registers will be allowed. SG1 determines whether the PALLV16V8 will emulate a PAL16R8
family. Within each macrocell, SL0x, in conjunction with SG1, selects the configuration of the
macrocell, and SL1x sets the output as either active low or active high for the individual macrocell.
The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There
are four multiplexers: a product term input, an enable select, an output select, and a feedback
select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0 and MC7,
PALLV16V8-10 and PALLV16V8Z-20 Families
3
SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being the adjacent pin for
MC7 and OE the adjacent pin for MC0.
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0x=0. There is only one registered
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1x The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback
.
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Configurations
The PALLV16V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output In a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x=0. All eight product terms are available to
the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception
of MC3 and MC4. MC3 and MC4 do not use feedback in this mode. Because CLK and OE are not
used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will use the
feedback path of MC , and pin 11 will use the feedback path of MC0.
7
Combinatorial I/O In a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0x=1. Only seven product terms are available
to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O
pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as
an input.
Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as inputs.
Pin 1 will use the feedback path of MC , and pin 11 will use the feedback path of MC0.
7
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0x=1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0x=1. The output buffer is disabled. Except for
MC0 and MC7, the feedback signal is an adjacent I/O. For MC0 and MC7, the feedback signals are
pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.
4
PALLV16V8-10 and PALLV16V8Z-20 Families
Table 1. Macrocell Configuration
Devices
Cell
Cell
Devices
SG0
SG1
SL0
Configuration
Emulated
SG0
SG1
SL0
Configuration
Emulated
X
X
Device Uses Registers
Device Uses No Registers
PAL10H8, 12H6,
14H4, 16H2, 10L8, 12L6,
14L4, 16L2
Registered
Output
PAL16R8, 16R6,
16R4
Combinatorial
0
0
1
1
0
1
0
0
Output
Combinatorial
PAL12H6, 14H4, 16H2, 12L6,
14L4, 16L2
1
PAL16R6, 16R4
1
1
0
1
1
1
Input
I/O
Combinatorial
I/O
PAL16L8
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal
needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written
in their most compact form (true or inverted), and the output can still be of the desired polarity.
It can also save “DeMorganizing” efforts.
Selection is through a programmable bit SL1x which controls an exclusive-OR gate at the output
of the AND/OR logic. The output is active high if SL1x is 1 and active low if SL1x is 0.
PALLV16V8-10 and PALLV16V8Z-20 Families
5
OE
OE
D
Q
Q
D
Q
Q
CLK
CLK
a. Registered active low
b. Registered active high
c. Combinatorial I/O active low
d. Combinatorial I/O active high
V
V
CC
CC
Note 1
Note 1
e. Combinatorial output active low
f. Combinatorial output active high
Notes:
Adjacent I/O pin
Note 2
. Feedback is not available on pins 15 and 16 in the
combinatorial output mode.
. The dedicated-input configuration is not available
on pins 15 and 16.
17713D-5
g. Dedicated input
Figure 2. Macrocell Configurations
6
PALLV16V8-10 and PALLV16V8Z-20 Families
Benefits of Low er Operating Voltage
The PALLV16V8 has an operating voltage range of 3.0V to 3.6 V. Low voltage allows for lower
operating power consumption, longer battery life, and/or smaller batteries for notebook
applications. The PALLV16V8 inputs accept up to 5.5 V, so they are safe for mixed voltage design.
Because power is proportional to the square of the voltage, reduction of the supply voltage from
5.0 V to 3.3 V significantly reduces power consumption. This directly translates to longer battery
life for portable applications. Lower power consumption can also be used to reduce the size and
weight of the battery. Thus, 3.3-V designs facilitate a reduction in the form factor.
A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise
generation and provides a less hostile environment for board design. A lower operating voltage
also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.
Pow er-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
PALLV16V8 will depend on whether they are selected as registered or combinatorial. If registered
is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of
the logic.
Register Preload
The register on the PALLV16V8 can be preloaded from the output pins to facilitate functional testing
of complex state machine designs. This feature allows direct loading of arbitrary states, making it
unnecessary to cycle through long test vector sequences to reach a desired state. In addition,
transitions from illegal states can be verified by loading illegal states and observing proper
recovery.
The preload function is not disabled by the security bit. This allows functional testing after the
security bit is programmed.
Security Bit
A security bit is provided on the PALLV16V8 as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by
a device programmer, securing proprietary designs from competitors. However, programming and
verification are also defeated by the security bit. The bit can only be erased in conjunction with
the array during an erase cycle.
Electronic Signature Word
An electronic signature word is provided in the PALLV16V8 device. It consists of 64 bits of
programmable memory that can contain user-defined data. The signature data is always available
to the user independent of the security bit.
Programming and Erasing
The PALLV16V8 can be programmed on standard logic programmers. It also may be erased to reset
a previously configured device back to its unprogrammed state. Erasure is automatically performed
by the programming hardware. No special erase operation is required.
PALLV16V8-10 and PALLV16V8Z-20 Families
7
Quality and Testability
The PALLV16V8 offers a very high level of built-in quality. The erasability if the device provides a
direct means of verifying performance of all the AC and DC parameters. In addition, this verifies
complete programmability and functionality of the device to yield the highest programming yields
and post-programming function yields in the industry.
Technology
The high-speed PALLV16V8Z is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven EE cells. This technology provides strong
input-clamp diodes and a grounded substrate for clean switching.
Zero-Standby Pow er Mode
The PALLV16V8 features a zero-standby power mode. When none of the inputs switch for an
extended period (typically 50 ns), the PALLV16V8Z will go into standby mode, shutting down most
of its internal circuitry. The current will go to almost zero (I < 30 µA). The outputs will maintain
CC
the states held before the device went into the standby mode. There is no speed penalty associated
with coming out of standby mode.
When any input switches, the internal circuitry is fully enabled, and power consumption returns
to normal. This feature results in considerable power savings for operation at low to medium
frequencies. This saving is illustrated in the I vs. frequency graph.
CC
The PALLV16V8Z-20 has the free-running-clock feature. This means that if one or more registers
are used, switching only the CLK will not wake up the logic array or any macrocell. The device
will not be in standby mode because the CLK buffer will draw some current, but dynamic I will
CC
typically be less than 2 mA.
Product-Term Disable
On a programmed PALLV16V8Z, any product terms that are not used are disabled. Power is cut off
from these product terms so that they do not draw current. As shown in the I vs. frequency
CC
graph, product-term disabling results in considerable power savings. This saving is greater at the
higher frequencies.
Further hints on minimizing power consumption can be found in a separate document entitled,
Minimizing Power Consumption with Zero-Power PLDs.
8
PALLV16V8-10 and PALLV16V8Z-20 Families
LOGIC DIAGRAM
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
CLK/I
1
2
3
4
0
20
19
1 1
1 0
0 0
0 1
V
CC
1 1
V
CC
0 X
1 0
SL07
0
7
SG1
1 1
0 X
I/O
7
D
Q
Q
1 0
SL17
1 0
1 1
0 X
I
1
SG0
SL07
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL06
8
SG1
1 1
0 X
18 I/O
6
D
Q
1 0
Q
15
SL16
1 0
1 1
0 X
I
2
SG1
SL06
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL05
16
23
SG1
1 1
0 X
17 I/O
5
D
Q
Q
1 0
SL15
1 0
1 1
0 X
I
3
SG1
SL05
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL04
24
31
SG1
1 1
0 X
16
I/O
4
D
Q
Q
1 0
SL14
1 0
1 1
0 X
5
I
4
SG1
SL04
CLK OE
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
17713D-17
PALLV16V8-10 and PALLV16V8Z-20 Families
9
LOGIC DIAGRAM (CONTINUED)
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
CLK OE
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL03
32
39
SG1
1 1
0 X
15
14
13
I/O
3
D
Q
Q
1 0
SL13
1 0
1 1
0 X
6
7
8
I
5
SG1
SL03
SL02
SL01
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL02
40
47
SG1
1 1
0 X
I/O
2
D
Q
Q
1 0
SL12
1 0
1 1
0 X
I
6
SG1
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL01
48
55
SG1
1 1
0 X
I/O
1
D
Q
Q
1 0
SL11
1 0
1 1
0 X
I
7
SG1
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL00
56
63
SG1
1 1
0 X
12 I/O
0
D
Q
Q
1 0
SL10
1 0
1 1
0 X
9
I
8
SL00
SG0
11
OE/I
9
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
GND 10
17713D-18
10
PALLV16V8-10 and PALLV16V8Z-20 Families
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature (T )
Ambient Temperature
A
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage (V )
Supply Voltage with
CC
with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V
Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latch-up Current
(T = 0°C to 75°C) . . . . . . . . . . . . . . . . . . . . . 100 mA
A
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Conditions
Min
Max
Unit
V
I
= –2 mA
= –75 mA
= 2 mA
2.4
OH
V = V or V
IL
IN
IH
V
OH
V = Min
CC
I
V - 0.2 V
V
OH
CC
I
0.4
0.2
V
OL
V = V or V
IL
IN
IH
V
Output LOW Voltage
OL
V = Min
CC
I
= 100 mA
V
OL
V
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1)
Guaranteed Input Logical LOW Voltage for all Inputs (Note 1)
2.0
5.5
V
IH
V
Input LOW Voltage
0.8
V
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
Off-State Output Leakage Current HIGH
Off-State Output Leakage Current LOW
Output Short-Circuit Current
Supply Current
V = V , V = Max (Note 2)
10
µA
µA
µA
µA
mA
mA
IH
IN
CC CC
I
V = 0 V, V = Max (Note 2)
–100
10
IL
IN
CC
I
V
= V , V = Max, V = V or V (Note 2)
OZH
OUT CC CC IN IH IL
I
V
= V , V = Max, V = V or V (Note 2)
-100
-130
55
OZL
OUT
CC CC
IN
IH
IL
I
V
= 0.5 V, V = Max (Note 3)
-50
SC
OUT
CC
I
Outputs Open (I = 0 mA), V = Max, f = 15 MHz (Note 4)
OUT CC
CC
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IL
OZL
3. Not more than one output should be shortened at a time, and the duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
V
OUT
4. This parameter is guaranteed worst case under test conditions. Refer to the I vs. frequency graph for typical measurements.
CC
PALLV16V8-10 (Com’l)
11
CAPACITANCE 1
Parameter
Symbol
Parameter Description
Test Condition
Typ
5
Unit
pF
C
Input Capacitance
Output Capacitance
V = 2.0 V
IN
IN
V - 3.3 V, T = 25°C,
CC
A
f = 1 MHz
C
V
= 2.0 V
8
pF
OUT
OUT
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1
-10
Parameter
Symbol
Parameter Description
Input or Feedback to Combinatorial Output (Note 2)
Setup Time from Input or Feedback to Clock
Hold Time
Min
Max
Unit
ns
t
10
PD
t
7
0
ns
S
t
ns
H
t
Clock to Output
7
ns
CO
t
LOW
6
ns
WL
Clock Width
HIGH
t
6
ns
WH
External Feedback
1/(t + t )
71.4
83.3
83.3
MHz
MHz
MHz
ns
S
CO
Maximum Frequency
Internal Feedback (fCNT
(Notes 2 and 3)
f
1/(t + t )
S CF
MAX
No Feedback
1/(t + t )
S H
t
OE to Output Enable
10
10
12
12
PZX
t
OE to Output Disable
ns
PXZ
t
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
ns
EA
t
ns
ER
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
frequency may be affected.
3. t is a calculated value and is not guaranteed. t can be found using the following equation:
CF
CF
t
= 1/f
(internal feedback) - tS.
CF
MAX
12
PALLV16V8-10 (Com’l)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Industrial (I) Devices
Ambient Temperature
Ambient Temperature (T ) . . . . . . . . . . -40°C to +85°C
A
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage (V ) with
CC
Supply Voltage with
Respect to Ground. . . . . . . . . . . . . . . +3.0 V to +3.6 V
Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latch-up Current
(T = -40°C to 85°C) . . . . . . . . . . . . . . . . . . . . 100 mA
A
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
V
I
= –2 mA
= –75 µA
= 2 mA
2.4
OH
V = V or V
IL
IN
IH
V
Output HIGH Voltage
OH
V = Min
CC
I
V – 0.2 V
V
OH
CC
I
0.4
0.2
5.5
0.8
10
V
OL
V = V or V
IL
IN
IH
V
Output LOW Voltage
OL
V = Min
CC
I
= 100 µA
V
OL
V
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1)
Guaranteed Input Logical LOW Voltage for all Inputs (Note 1)
2.0
V
IH
V
Input LOW Voltage
V
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
Off-State Output Leakage Current HIGH
Off-State Output Leakage Current LOW
Output Short-Circuit Current
V = V , V = Max (Note 2)
µA
µA
µA
µA
mA
µA
mA
IH
IN
CC CC
I
V = 0 V, V = Max (Note 2)
–10
10
IL
IN
CC
I
V
= V , V = Max, V = V or V (Note 2)
OZH
OUT CC CC IN IH IL
I
V
= V , V = Max, V = V or V (Note 2)
-10
-75
30
OZL
OUT
CC CC
IN
IH
IL
I
V
= 0.5 V, V = Max (Note 3)
-15
SC
OUT
CC
f = 0 MHz
Outputs Open (I = 0 mA)
V = Max, f = 15 MHz (Note 4)
OUT
I
Supply Current
CC
CC
f = 15 MHz
45
Note:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IH
OZH
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is guaranteed worst case under test conditions. Refer to the I vs. frequency graph for typical measurements.
CC
PALLV16V8Z-20 (Ind)
13
CAPACITANCE 1
Parameter
Symbol
Parameter Description
Test Condition
Typ
5
Unit
pF
C
Input Capacitance
Output Capacitance
V = 2.0 V
IN
IN
V = 5.0 V, T = 25°C,
CC
A
f = 1 MHz
C
V
= 2.0 V
8
pF
OUT
OUT
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES 1
-20
Parameter
Symbol
Parameter Description
Input or Feedback to Combinatorial Output (Note 2)
Setup Time from Input or Feedback to Clock
Hold Time
Min
Max
Unit
ns
t
20
PD
t
15
0
ns
S
t
ns
H
t
Clock to Output
10
ns
CO
t
LOW
8
8
ns
WL
Clock Width
HIGH
t
ns
WH
External Feedback
1/(t + t )
40
50
66.7
MHz
MHz
MHz
ns
S
CO
Maximum Frequency
Internal Feedback (fCNT)
(Notes 3 and 4)
f
1/(t + t )
S CF
MAX
No Feedback
1/(t + t )
S H
t
OE to Output Enable
20
20
20
20
PZX
t
OE to Output Disable
ns
PXZ
t
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
ns
EA
t
ns
ER
Notes:
1. See “Switching Test Circuit” for test conditions.
2. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the t will typically be about 2 ns faster.
PD
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
frequency may be affected.
4. t is a calculated value and is not guaranteed. t can be found using the following equation:
CF
CF
t
= 1/f
(internal feedback) - t .
CF
MAX S
14
PALLV16V8Z-20 (Ind)
SWITCHING WAVEFORMS
Input or
Feedback
V
T
Input or
Feedback
t
t
H
S
V
T
V
T
t
t
PD
Clock
CO
Combinatorial
Output
V
TO
Registered
Output
V
TO
17713D-7
17713D-8
a. Combinatorial output
b. Registered output
V
Input
T
t
WH
t
t
ER
EA
V
- 0.5V
Clock
V
T
OH
V
Output
TO
V
+ 0.5V
OL
t
WL
17713D-10
17713D-9
d. Input to output disable/enable
c. Clock w idth
V
T
OE
t
t
PZX
PXZ
V
- 0.5V
OH
V
Output
TO
V
+ 0.5V
OL
17713D-11
e. OE to output disable/enable
Notes:
1. V = 1.5 V for input signals and V /2 for output signals.
T
CC
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns to 5 ns typical.
PALLV16V8-10 and PALLV16V8Z-20 Families
15
KEY TO SWITCHING WAVEFORM
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Will be
Changing
from H to L
Change
from H to L
May
Will be
Changing
from L to H
Change
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
V
CC
S
1
R
1
Output
Test Point
R
2
2
C
L
S
17713D-12
Specification
t , t
S
S
C
R
R
2
Measured Output Value
V /2
1
2
L
1
Closed
Closed
PD CO
CC
30 pF
5 pF
Z → H: Open
Z → L: Closed
Z → H: Closed
Z → L: Open
t
, t
V /2
CC
PZX EA
1.6K
1.6K
H → Z: Open
L → Z: Closed
H → Z: Closed
L → Z: Open
H → Z: V – 0.5 V
OH
t
, t
PXZ ER
L → Z: V + 0.5 V
OL
16
PALLV16V8-10 and PALLV16V8Z-20 Families
TYPICAL ICC CHARACTERISTICS
VCC = 3.3 V, TA = 25°C
150
125
100
PALLV16V8-10
PALLV16V8Z-20
I
(mA)
75
50
25
0
CC
0
10
20
30
40
50
17713D-13
Frequency (MHz)
I
vs. Frequency
CC
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and
the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any
vector, half of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for I . From this midpoint, a designer may scale the I graphs up or down
CC
CC
to estimate the I requirements for a particular design.
CC
PALLV16V8-10 and PALLV16V8Z-20 Families
17
ENDURANCE CHARACTERISTICS
The PALLV16V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process.
This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, devices
can be erased and reprogrammed—a feature which allows 100% testing at the factory.
Symbol
Parameter
Test Conditions
Value
10
Unit
Years
Years
Cycles
Max Storage Temperature
Max Operating Temperature
Normal Programming Conditions
t
Min Pattern Data Retention Time
Max Reprogramming Cycles
DR
20
N
100
ROBUSTNESS FEATURES
The PALLV16V8 has some unique features that make it extremely robust, especially when operating
in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected
pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the
possibility of false clocking caused by subsequent ringing. A special noise filter makes the
programming circuitry completely insensitive to any positive overshoot that has a pulse width of
less than about 100 ns.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
V
V
CC
CC
> 50 kΩ
ESD
Protection
and
Programming
Pins only
Programming
Circuitry
Programming
Voltage
Detection
Positive
Overshoot
Filter
Clamping
Typical Input
17713D-14
V
V
CC
CC
> 50 kΩ
5-V Protection
Provides ESD
Protection and
Clamping
Preload Feedback
Circuitry
Input
17713D-15
Typical Output
PALLV16V8-10 and PALLV16V8Z-20 Families
18
POWER-UP RESET
The PALLV16V8 has been designed with the capability to reset during system power-up. Following
power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the
logic polarity. This feature provides extra flexibility to the designer and is especially valuable in
simplifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise
to its steady state, two conditions are required to ensure a valid power-up reset. These conditions
are:
The V rise must be monotonic.
CC
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter
Symbol
Parameter Descriptions
Min
Max
Unit
t
Power-Up Reset Time
1000
ns
PR
t
Input or Feedback Setup Time
Clock Width LOW
S
See Switching Characteristics
t
WL
V
CC
2.7 V
Power
t
PR
Registered
Output
t
S
Clock
t
WL
17713D-16
Figure 3. Pow er-Up Reset Waveform
PALLV16V8-10 and PALLV16V8Z-20 Families
19
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Typ
Parameter
Symbol
Parameter Description
PDIP
20
PLCC
19
Unit
θ
θ
Thermal impedance, junction to case
Thermal impedance, junction to ambient
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
jc
65
57
ja
200 lfpm air
400 lfpm air
600 lfpm air
800 lfpm air
58
41
51
37
θ
Thermal impedance, junction to ambient with air flow
jma
47
35
44
33
Plastic θ Considerations
jc
The data listed for plastic θ are for reference only and are not recommended for use in calculating junction temperatures. The heat-
jc
flow paths in plastic-encapsulated devices are complex, making the θ measurement relative to a specific location ion the package
jc
surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package.
Furthermore, θ tests on packages are performed in a constant temperature. Therefore, the measurements can only be used in a
jc
similar environment.
20
PALLV16V8-10 and PALLV16V8Z-20 Families
CONNECTION DIAGRAMS (TOP VIEW)
DIP/SOIC
PLCC
V
CLK/I 0
CC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE/I9
I 1
I 2
I 3
3
2
1
20
19
I/O6
I/O5
I/O4
I/O3
18
17
16
15
4
5
6
7
I3
I4
I5
I6
I 4
I 5
I 6
I 7
14
I/O2
I7
8
I 8
9
10 11 12 13
GND
17713D-2
17713D-3
PIN DESIGNATIONS
CLK = Clock
Note:
Pin 1 is marked for orientation.
GND = Ground
I
= Input
I/O
NC
= Input/Output
= No Connect
= Supply Voltage
V
CC
PALLV16V8-10 and PALLV16V8Z-20 Families
21
ORDERING INFORMATION
Commercial and Industrial Products
Vantis programmable logic products for industrial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
-10
P C
PAL LV 16 V
8
Z
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
OPERATING CONDITIONS
LV
= Low-Voltage
C
I
= Commercial (0°C to +75°C)
= Industrial (–40°C to 85°C)
NUMBER OF
ARRAY INPUTS
PACKAGE TYPE
P
J
= 20-Pin Plastic DIP (PD 020)
= 20-Pin Plastic Leaded Chip
Carrier (PL 020)
OUTPUT TYPE
V
= Versatile
S
= 20-Pin Plastic Gull-Wing Small
Outline Package (SO 020)
NUMBER OF OUTPUTS
Z
= Zero Power
(30 µA I Standby)
CC
SPEED
–10
= 10 ns t
PD
–20
= 20 ns t
PD
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
Vantis sales office to confirm availability of specific
valid combinations and to check on newly released
PALLV16V8-10
PALLV16V8Z-20
PC, JC, SC
PI, JI
22
PALLV16V8-10 and PALLV16V8Z-20 Families
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