OR3L165B-8PS240 [LATTICE]
Field Programmable Gate Array, 8192-Cell, CMOS, PQFP240;
| 型号： | OR3L165B-8PS240 |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | Field Programmable Gate Array, 8192-Cell, CMOS, PQFP240 栅 可编程逻辑 |
| 文件： | 总88页 (文件大小：1435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Addendum
January 2002
ORCA® OR3LxxxB Series
Field-Programmable Gate Arrays
shared inputs and the logic flexibility of LUTs with
independent inputs.
Introduction
■ Fast-carry logic and routing to adjacent PFUs for
nibble-wide, byte-wide, or longer arithmetic func-
tions, with the option to register the PFU carry-out.
■ Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
■ Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL*-like AND-OR-INVERT (AOI) in each pro-
grammable logic cell (PLC).
■ Abundant hierarchical routing resources based on
routing two data nibbles and two control lines per
set provide for faster place and route implementa-
tions and less routing delay.
■ Individually programmable drive capability: 12 mA
sink/6 mA source or 6 mA sink/3 mA source.
■ Built-in boundary scan (IEEE †1149.1 JTAG) and
testability function to 3-state all I/O pins.
■ Enhanced system clock routing for low-skew, high-
speed clocks originating on-chip or at any I/O.
■ Up to four ExpressCLK inputs allow extremely fast
clocking of signals on- and off-chip plus access to
internal general clock routing.
This data addendum refers to the information found
in the ORCA Series 3C and 3T Field-Programmable
Gate Arrays Data Sheet.
®
Features
■ High-performance, cost-effective, 0.25 µm 5-level
metal technology.
■ 2.5 V internal supply voltage and 3.3 V I/O supply
voltage for speed and compatibility.
■ Up to 340,000 usable gates‡ in 0.25 µm.
■ Up to 612 user I/Os in 0.25 µm. (OR3LxxxB I/Os
are 5 V tolerant to allow interconnection to both
3.3 V and 5 V devices, selectable on a per-pin
basis, when using 3.3 V I/O supply.)
■ Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables (LUTs)
per PFU, organized in two nibbles for use in nibble-
or byte-wide functions. Allows for mixed arithmetic
and logic functions in a single PFU.
■ Nine user registers per PFU, one following each
LUT, plus one extra. All have programmable clock
enable and local set/reset, plus a global set/reset
that can be disabled per PFU.
■ StopCLK feature to glitchlessly stop/start the
ExpressCLKs independently by user command.
* PAL is a trademark of Lattice Semiconductor
†IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
■ Flexible input structure (FINS) of the PFUs pro-
vides a routability enhancement for LUTs with
Table 1. ORCA OR3LxxxB Series FPGAs
System
Max User
RAM
Process
Technology
Device
LUTs
Registers
User I/Os Array Size
Gates‡
OR3L165B 120K—244K
8192
10752
14820
131K
185K
516
612
32 × 32
38 × 38
0.25 µm/5 LM
0.25 µm/5 LM
OR3L225B 166K—340K 11552
‡The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (three FFs, fast-capture latch, output
logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 × 4 RAM
(or 512 gates) per PFU.
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Table of Contents
Page Contents
Contents
Page
Introduction................................................................ 1
Features .................................................................... 1
System-Level Features.............................................. 4
Support...................................................................... 5
Description ................................................................ 5
FPGA Overview ...................................................... 5
PLC Logic ............................................................... 5
PIC Logic ................................................................ 8
System Features..................................................... 9
Routing.................................................................... 9
Configuration........................................................... 9
Configuration Data Format...................................... 9
Series 3L I/Os and 5 V Tolerance......................... 10
Designing with ORCA Series 3T Parts with
Series 3L in Mind................................................ 10
Powerup Sequencing for Series 3L Devices......... 10
ORCA Foundry Development System .................. 11
Additional Information ........................................... 11
Timing Characteristics............................................. 12
Configuration Timing............................................. 12
PFU Timing........................................................... 13
PLC Timing ........................................................... 19
SLIC Timing .......................................................... 19
PIO Timing............................................................ 20
Special Function Blocks Timing............................ 23
Clock Timing ......................................................... 25
Description............................................................ 35
Estimating Power Dissipation................................. 37
OR3LxxxB............................................................ 37
Pin Information ....................................................... 38
Absolute Maximum Ratings.................................... 76
Recommended Operating Conditions .................... 76
Electrical Characteristics........................................ 77
Package Thermal Characteristics .......................... 78
ΘJA ...................................................................... 78
ψJC ...................................................................... 78
ΘJC ...................................................................... 78
ΘJB ...................................................................... 78
FPGA Maximum Junction Temperature .............. 79
Package Coplanarity .............................................. 80
Package Parasitics................................................. 80
Package Outline Diagrams..................................... 81
Terms and Definitions.......................................... 81
208-Pin SQFP2.................................................... 82
240-Pin SQFP2.................................................... 83
352-Pin PBGA ..................................................... 84
432-Pin EBGA ..................................................... 85
680-Pin PBGAM .................................................. 86
Ordering Information .............................................. 87
2
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Table of Contents (continued)
Figure
Page
Table
Page
Figure 1. Simplified PFU Diagram...............................6
Figure 2. SLIC All Modes Diagram..............................7
Figure 3. OR3Lxxx Programmable Input/Output
Table 14. ExpressCLK (ECLK) and Fast Clock
(FCLK) Timing Characteristics ............................ 25
Table 15. General-Purpose Clock Timing
Image from ORCA Foundry....................................8
Figure 4. Synchronous Memory
Characteristics (Internally Generated Clock)....... 26
Table 16. OR3Lxxx ExpressCLK to
Write Characteristics ............................................17
Figure 5. Synchronous Memory Read Cycle.............18
Figure 6. ExpressCLK to Output Delay .....................27
Figure 7. Fast Clock to Output Delay.........................28
Figure 8. System Clock to Output Delay ...................29
Figure 9. Input to ExpressCLK Setup/Hold Time.......31
Figure 10. Input to Fast Clock Setup/Hold Time........33
Figure 11. Input to System Clock Setup/Hold Time...34
Figure 12. Package Parasitics...................................80
Output Delay (Pin-to-Pin) .................................... 27
Table 17. OR3Lxxx Fast Clock (FCLK) to
Output Delay (Pin-to-Pin) .................................... 28
Table 18. OR3Lxxx General System Clock
(SCLK) to Output Delay (Pin-to-Pin).................... 29
Table 19. OR3Lxxx Input to ExpressCLK (ECLK)
Fast-Capture Setup/Hold Time (Pin-to-Pin)......... 30
Table 20. OR3Lxxx Input to Fast Clock
Setup/Hold Time (Pin-to-Pin)............................... 32
Table 21. OR3Lxxx Input to General System Clock
(SCLK) Setup/Hold Time (Pin-to-Pin).................. 34
Table 22. Derating for Commercial/Industrial
Table
Page
OR3Lxxx Devices (I/O Supply VDD) .................... 36
Table 23. Derating for Commercial/Industrial
Table 1. ORCA OR3LxxxB Series FPGAs ..................1
Table 2. ORCA Series 3L System Performance..........4
Table 3. Configuration Frame Size ..............................9
Table 4. General Configuration Mode Timing
Characteristics .....................................................12
Table 5. Combinatorial PFU Timing Characteristics..13
Table 6. Sequential PFU Timing Characteristics .......14
Table 7. Ripple Mode PFU Timing Characteristics ....15
Table 8. Synchronous Memory
Write Characteristics............................................17
Table 9. Synchronous Memory
Read Characteristics............................................18
Table 10. PFU Output MUX and
Direct Routing Timing Characteristics..................19
Table 11. Supplemental Logic and
Interconnect Cell Timing Characteristics..............19
Table 12. Programmable I/O
Timing Characteristics .........................................20
Table 13. Microprocessor Interface (MPI) Timing
Characteristics......................................................23
OR3Lxxx Devices (I/O Supply VDD2) .................. 36
Table 24. 208-Pin SQFP2 Pinout .............................. 38
Table 25. 240-Pin SQFP2 Pinout ............................. 41
Table 26. 352-Pin PBGA Pinout................................ 44
Table 27. 432-Pin EBGA Pinout ............................... 49
Table 28. 680-Pin PBGAM Pinout............................. 60
Table 29. Absolute Maximum Ratings....................... 76
Table 30. Recommended Operating Conditions ....... 76
Table 31. Electrical Characteristics ........................... 77
Table 32. Plastic Package Thermal Characteristics
for the ORCA Series............................................ 79
Table 33. Package Coplanarity.................................. 80
Table 34. Package Parasitics .................................... 80
Table 35. Voltage Options ......................................... 87
Table 36. Temperature Options ................................. 87
Table 37. Package Options ....................................... 87
Table 38. ORCA OR3LxxxB Series
Package Matrix.................................................... 87
Lattice Semiconductor
3
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Features (continued)
■ Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to i960* and
PowerPC† processors with user-configurable
address space provided.
■ Programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF)/
latch for reduced input setup time and zero hold
time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and PAL-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain drive capability.
■ Parallel readback of configuration data capability with
the built-in microprocessor interface.
■ Programmable clock manager (PCM) adjusts clock
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers.Two PCMs are provided
per device.
■ New programmable I/O 3-state FF allows 3-state
buffer control signals to be set up a clock cycle early
for improved clock to output delays.
■ True internal 3-state, bidirectional buses with simple
System-Level Features
control provided by the SLIC.
■ 32 × 4 RAM per PFU, configurable as single- or dual-
port. Create large, fast RAM/ROM blocks (128 × 8 in
only eight PFUs) using the SLIC decoders as bank
drivers.
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the ORCA OR3LxxxB include the following:
■ Full PCI local bus compliance for all devices in
3.3 V and 5 V PCI systems. Pin-selectable I/O
clamping diodes provide 3.3 V and 5 V compliance
and 5 V tolerance.
■ Full UTOPIA Level III I/O compliance (6.0 ns
CLK -> OUT, 2.0 ns setup with 0 ns hold).
* i960 is a registered trademark of Intel Corporation.
† PowerPC is a registered trademark of International Business
Machines, Inc.
Table 2. ORCA Series 3L System Performance
Parameter
# PFUs
-7
-8
Unit
16-bit Loadable Up/Down Counter
16-bit Accumulator
2
2
151
151
176
176
MHz
MHz
8 × 8 Parallel Multiplier:
Multiplier Mode, Unpipelined1
ROM Mode, Unpipelined2
Multiplier Mode, Pipelined3
32 × 16 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
11.5
8
15
38
93
129
46
116
152
MHz
MHz
MHz
4
4
173
231
209
277
MHz
MHz
128 × 8 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
8
8
151
151
181
181
MHz
MHz
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs6
0.25
0
2.30
1.29
2.00
1.12
ns
ns
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs7
2
0
2
7.97
3.75
7.97
6.84
3.16
6.84
ns
ns
ns
36-bit Parity Check (internal)
1. Implemented using 8 × 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 × 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 × 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 PFUs contain
only pipelining registers).
4. Implemented using 32 × 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 × 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
4
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
PLC Logic
Support
Each PFU within a PLC contains eight 4-input (16-bit)
LUTs, eight latches/FFs, and one additional FF that
may be used independently or with arithmetic func-
tions.
■ ORCA Foundry development system support.
■ Supported by industry-standard CAE tools for design
entry, synthesis, simulation, and timing analysis.
The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled indepen-
dently. LUTs may also be combined for use in arith-
metic functions using fast-carry chain logic in either
4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32 × 4 sin-
gle- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
Description
FPGA Overview
The ORCA OR3LxxxB FPGAs are a new generation of
SRAM-based FPGAs built on the successful Series 2
and Series 3 FPGA lines, with enhancements and
innovations geared toward today’s high-speed designs
and tomorrow’s systems on a single chip. Designed
from the start to be synthesis friendly and to reduce
place and route times while maintaining the complete
routability of the ORCA Series 2 devices, the
OR3LxxxB Series more than doubles the logic avail-
able in each logic block and incorporates system-level
features that can further reduce logic requirements and
increase system speed. ORCA OR3LxxxB devices
contain many new patented enhancements and are
offered in a variety of packages, speed grades, and
temperature ranges.
The SLIC is connected to PLC routing resources and to
the outputs of the PFU. It contains 3-state, bidirectional
buffers and logic to perform up to a 10-bit AND function
for decoding, or an AND-OR with optional INVERT to
perform PAL-like functions. The 3-state drivers in the
SLIC and their direct connections to the PFU outputs
make fast, true 3-state buses possible within the
FPGA, reducing required routing and allowing for real-
world system performance.
The ORCA OR3LxxxB Series FPGAs consist of three
basic elements: PLCs, programmable input/output
cells (PICs), and system-level features. An array of
PLCs is surrounded by PICs. Each PLC contains a
PFU, a SLIC, local routing resources, and configuration
RAM. Most of the FPGA logic is performed in the PFU
(see Figure 1), but decoders, PAL-like functions, and
3-state buffering can be performed in the SLIC (see
Figure 2). The PICs provide device inputs and outputs
and can be used to register signals and to perform
input demultiplexing, output multiplexing, and other
functions on two output signals (see Figure 3). Some of
the system-level functions include the MPI and the
PCM.
Lattice Semiconductor
5
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Description (continued)
F7
F5D
REG7
Q7
0
D0
DIN7
0
K7_0
K7
A
B
D1
DSEL
CE
K7_1
K7_2
CK
S/R
C
D
F6
K7_3
K6_0
REG6
Q6
DIN6
0
K6
D0
D1
A
B
C
K6_1
K6_2
DSEL
CE
1
0
CK
S/R
K6_3
D
F5MODE67
F5
K5
REG5
Q5
K5_0
K5_1
K5_2
K5_3
DIN5
0
A
B
C
D
D0
D1
DSEL
CE
CK
S/R
K4
K4_0
K4_1
K4_2
K4_3
A
B
C
D
1
0
F4
REG4
Q4
DIN4
0
D0
F5C
D1
DSEL
CE
F5MODE45
0
CK
S/R
CLK
0
SEL
0
CIN
COUT
0
CE
1
FF8
1
REGCOUT
D
CE
CK
S/R
ASWE
1
1
0
LSR
0
0
0
F3
F5B
REG3
Q3
0
D0
DIN3
0
K3_0
K3
A
B
D1
DSEL
CE
K3_1
K3_2
CK
S/R
C
D
F2
K3_3
K2_0
REG2
DIN2
0
Q2
K2
D0
D1
A
B
C
K2_1
K2_2
DSEL
CE
1
0
CK
S/R
K2_3
D
F5MODE23
F1
K1
REG1
K1_0
K1_1
K1_2
K1_3
DIN1
0
Q1
A
B
C
D
D0
D1
DSEL
CE
CK
S/R
K0
K0_0
K0_1
K0_2
K0_3
A
B
C
D
1
0
F0
REG0
DIN0
0
Q0
D0
F5A
D1
DSEL
CE
F5MODE01
0
CK
S/R
5-5743
Note: All multiplexers without select inputs are configuration selector multiplexers.
Figure 1. Simplified PFU Diagram
6
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Description (continued)
BRI9
I9
BL09
BR09
BLI9
BRI8
I8
BL08
BR08
BLI8
BRI7
I7
BL07
BR07
BLI7
BRI6
I6
BL06
BR06
BLI6
BRI5
I5
BL05
BR05
BLI5
DEC
BRI4
I4
BL04
BR04
BLI4
TRI
0/1
0/1
0/1
DEC
HIGH Z WHEN LOW
0/1
BRI3
I3
BL03
BR03
BLI3
BRI2
I2
BL02
BR02
BLI2
BRI1
I1
BL01
BR01
BLI1
BRI0
I0
BL00
BR00
BLI0
5-5744(F)
Figure 2. SLIC All Modes Diagram
Lattice Semiconductor
7
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
On the output side of each PIO, two outputs from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
nals.
Description (continued)
PIC Logic
The OR3LxxxB PIC addresses the demand for ever-
increasing system clock speeds. Each PIC contains
four programmable inputs/outputs (PIOs) and routing
resources. On the input side, each PIO contains a fast-
capture latch that is clocked by an ExpressCLK. This
latch is followed by a latch/FF that is clocked by a sys-
tem clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the sig-
nals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the ORCA Series 2 capability to use any input
pin as a clock or other global input is maintained.
The output FF, in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The I/O
buffer associated with each pad is very similar to the
Series 2 buffer with a new, fast, open-drain option for
ease of use on system buses.These features may also
be combined with the new 3-state FF that allows the
3-state control signal to be registered. This allows for
early control setup and faster clock-to-out times.
PIO LOGIC
AND
NAND
OR
NOR
XOR
XNOR
PULL-MODE
UP
DOWN
NONE
PMUX
OUT1OUTREG
OUT2OUTREG
OUT1OUT2
CLKIN
IN1
OUT1
OUT2
D0
D1 Q
0
0
PD
Q
D
CK
PAD
ECLK
SCLK
NORMAL
INVERTED
CK
SP
SD
LSR
LEVEL MODE
1
TS
ECLK
SCLK
D
CK
SP
LSR
Q
TTL
CMOS
INREGMODE
1
RESET
SET
BUFFER
MODE
LATCHFF
LATCH
FF
CE
D0 Q
CK
RESET
SET
FAST
SLEW
SINK
1
IN2
LSR
LSR
CE_OVER_LSR
LSR_OVER_CE
ASYNC
0
ENABLE_GSR
DISABLE_GSR
5-5805(F).a
Figure 3. OR3Lxxx Programmable Input/Output Image from ORCA Foundry
8
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Routing
Description (continued)
The abundant routing resources of the ORCA 3LxxxB
FPGAs are organized to route signals individually or as
buses with related control signals. Clocks are routed
on a low-skew, high-speed distribution network and
may be sourced from PLC logic, externally from any
I/O pad, or from the very fast ExpressCLK pins.
ExpressCLKs may be glitchlessly and independently
enabled and disabled with a programmable control sig-
nal using the new StopCLK feature. The improved PIC
routing resources are now similar to the patented intra-
PLC routing resources and provide great flexibility in
moving signals to and from the PIOs. This flexibility
translates into an improved capability to route designs
at the required speeds when the I/O signals have been
locked to specific pins.
System Features
The OR3LxxxB Series also provides system-level func-
tionality by means of its dual-use MPI and its innovative
PCM. These functional blocks allow for easy glueless
system interfacing and the capability to adjust to vary-
ing conditions in today’s high-speed systems.
The MPI provides a glueless interface between the
FPGA, PowerPC, and i960 microprocessors. It can be
used for configuration and readback, as well as for
monitoring FPGA status. The MPI also provides a gen-
eral-purpose microprocessor interface to the FPGA
user-defined logic following configuration.
Two PCMs are provided on each ORCA 3L device.
Each PCM can be used to manipulate the frequency,
phase, and duty cycle of a clock signal. Clocks may be
input from the dedicated corner ExpressCLK input (in
the same corner as the PCM block) or from general
routing. Output clocks from the PCM can be sent to the
system clock spines, and/or to the ExpressCLK and
fast clock spines on the edges of the device adjacent to
the PCM. ExpressCLK/fast clock and system clock out-
put frequencies can differ by up to a factor of eight to
allow slow I/O clocking with fast internal processing (or
vice versa). Each PCM is capable of manipulating
clocks from 5 MHz to 120 MHz. Frequencies can be
adjusted from 1/8× to 64× the input clock frequency,
duty cycles, and phase delays can be adjusted from
3.125% to 96.875%.
Configuration
The FPGA’s functionality is determined by internal con-
figuration RAM. The FPGA’s internal initialization/con-
figuration circuitry loads the configuration data at
powerup or under system control. The RAM is loaded
by using one of several configuration modes. The con-
figuration data resides externally in an EEPROM or
any other storage media. Serial EEPROMs provide a
simple, low pin count method for configuring FPGAs. A
new, easy method for configuring the devices is
through the microprocessor interface.
Configuration Data Format
The length and number of data frames and information on the PROM size for the Series OR3LxxxB FPGAs are
given in Table 3.
Table 3. Configuration Frame Size
Devices
3L165B
3L225B
Number of Frames
Data Bits/Frame
2136
502
2520
592
Configuration Data
1,072,272
1,552,320
(number of frames × number of data bits/frame)
Maximum Total Number Bits/Frame
520
610
(align bits, 01 frame start, 8-bit checksum, eight stop bits)
Maximum Configuration Data
(number bits/frame × number of frames)
1,110,720
1,110,760
1,537,200
1,537,240
Maximum PROM Size (bits)
(add configuration header and postamble)
Lattice Semiconductor
9
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Design with two power planes: one for the internal sup-
ply (2.5 V), and one for the I/O supply (3.3 V). For
Series 3T operation, connect both the internal supply
and I/O voltage planes to 3.3 V. For Series 3L opera-
tion, change the core plane connection from 3.3 V to
2.5 V.
Description (continued)
Series 3L I/Os and 5 V Tolerance
Series 3L devices use the same I/O structure as ORCA
Series 3T devices. ORCA Series 3L devices use a
3.3 V supply (VDD) to power the I/Os and a 2.5 V sup-
ply (VDD2) to power the internal logic. Because the I/O
structure and voltage is common between 3T and 3L
devices, the Series 3L devices maintain 5 V tolerance
and the same I/O characteristics as Series 3T devices.
Powerup Sequencing for Series 3L Devices
ORCA Series 3L devices use two power supplies: one
to power the device I/Os (VDD) which is set to 3.3 V for
3.3 V operation and 5 V tolerance, and another supply
for the internal logic (VDD2) which is set to 2.5 V. It is
understood that many users will derive the 2.5 V core
logic supply from a 3.3 V power supply, so the following
recommendations are made as to the powerup
The OR3LxxxB uses a default mode that maintains a
5 V tolerant setting on all I/Os.
Designing with ORCA Series 3T Parts with
Series 3L in Mind
sequence of the supplies and allowable delays
between power supplies reaching stable voltages.
Due to many package compatibilities across device
sizes and families, it is possible to design using a
Series 3T device today, and migrate to a Series 3L
device later. The pinouts are the same on both families
with the exception of additional I/O voltage pins for the
Series 3L family.
In general, both the 3.3 V and the 2.5 V supplies should
ramp-up and become stable as close together in time
as possible. There is no delay requirement if the VDD2
(2.5 V) supply becomes stable prior to the VDD (3.3 V)
supply. There is a delay requirement imposed if the
VDD supply becomes stable prior to the VDD2 supply.
To design a board that is both Series 3T compatible
and Series 3L compatible, using the following proce-
dures will allow easy and fast component swapping
from Series 3T to Series 3L.
The requirement is that the VDD2 (2.5 V) supply transi-
tions from 0.8 V to 2.3 V within 15.7 ms when the VDD
(3.3 V) supply is already stable at a minimum of 3.0 V. If
the chosen power supplies cannot meet this delay
requirement, it is always possible to delay configuration
of the FPGA by asserting INIT or PRGM until the VDD2
supply has reached 2.3 V. This process eliminates any
power supply sequencing issues.
Design to the Series 3L pinouts, especially if planning
to use the OR3L225B pinout. The OR3L225B has addi-
tional power pins that are not on smaller Series 3L
parts. (Note that if the designer is using a Series 3L
device smaller than the OR3L225B, but may eventually
migrate to a OR3L225B, the OR3L225B pinout should
also be used). Designing for Series 3L in this manner
does sacrifice some user I/O pins available in the
Series 3T (or smaller Series 3L devices if using the
OR3L225B). These I/Os will have power applied to
them when a Series 3T device is used on the board.
However, this is acceptable and these I/Os will default
to 3-state outputs which eliminates any contention risk.
10
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing and simulation output files from ORCA Foundry
are also compatible with many third-party analysis
tools. Its bit stream generator is then used to generate
the configuration data, which is loaded into the FPGA’s
internal configuration RAM.
Description (continued)
ORCA Foundry Development System
The ORCA Foundry development system is used to
process a design from a netlist to a configured FPGA.
This system is used to map a design onto the ORCA
architecture and then place and route it using ORCA
Foundry’s timing-driven tools.The development system
also includes interfaces to, and libraries for, other popu-
lar CAE tools for design entry, synthesis, simulation,
and timing analysis.
When using the bit stream generator, the user selects
options that affect the functionality of the FPGA. Com-
bined with the front-end tools, ORCA Foundry pro-
duces configuration data that implements the various
logic and routing options discussed in this product
brief.
The ORCA Foundry development system interfaces to
front-end design entry tools and provides the tools to
produce a configured FPGA. In the design flow, the
user defines the functionality of the FPGA at two points
in the design flow: at design entry and at the bit stream
generation stage.
Additional Information
Contact your local Lattice representative for additional
information regarding the ORCA OR3LxxxB FPGA
devices, or visit our website at:
http://www.lattice.com.
Following design entry, the development system’s map,
place, and route tools translate the netlist into a routed
FPGA. A static timing analysis tool is provided to deter-
mine device speed, and a back-annotated netlist can
be created to allow simulation.
Lattice Semiconductor
11
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics
Configuration Timing
Table 4. General Configuration Mode Timing Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
Symbol
Parameter
Min
Max
Unit
All Configuration Modes
TSMODE
THMODE
TRW
M[3:0] Setup Time to INIT High
0.00
600.00
50.00
50.00
—
—
—
—
ns
ns
ns
ns
M[3:0] Hold Time from INIT High
RESET Pulse Width Low to Start Reconfiguration
PRGM Pulse Width Low to Start Reconfiguration
TPGW
Master and Asynchronous Peripheral Modes
TPO
TCCLK
Power-on Reset Delay
CCLK Period (M3 = 0)
(M3 = 1)
15.70
60.00
480.00
52.40
200.00
1600.00
ms
ns
ns
TCL
Configuration Latency (autoincrement mode):
OR3L165B (M3 = 0)
(M3 = 1)
66.65
533.16
92.23
222.15*
1777.22*
307.45*
2459.8*
ms
ms
ms
ms
OR3L225B (M3 = 0)
(M3 = 1)
737.88
Microprocessor (MPI) Mode
TPO
TCL
Power-on Reset Delay
Configuration Latency (autoincrement mode):
15.70
52.40
ms
OR3L165B
OR3L225B
147,405
202,251
—
—
write cycles
write cycles
TPR
Partial Reconfiguration (explicit mode):
OR3L165B
69
81
—
—
write cycles
write cycles
OR3L225B
Slave Serial Mode
TPO
TCCLK
TCL
Power-on Reset Delay
CCLK Period
Configuration Latency (autoincrement mode):
3.90
15.00
13.10
ms
ns
OR3L165B
OR3L225B
16.66
23.06
—
—
ms
ms
Slave Parallel Mode
TPO
TCCLK
TCL
Power-on Reset Delay
CCLK Period:
Configuration Latency (normal mode):
OR3L165B
3.90
15.00
13.10
ms
ns
2.08
2.88
—
—
OR3L225B
TPR
Partial Reconfiguration (explicit mode):
OR3L165B
1.0
1.2
—
—
µs/frame
µs/frame
OR3L225B
* Not applicable to asynchronous peripheral mode.
Note: TPO is triggered when VDD reaches between 2.7 V and 3.0 V for the OR3LxxxB.
12
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
The waveform test points are given in the Input/Output
Buffer Measurement Conditions section of this data
sheet. The timing parameters given in the electrical
characteristics tables in this data sheet follow industry
practices, and the values they reflect are described
below.
Timing Characteristics (continued)
In addition to supply voltage, process variation, and
operating temperature, circuit and process improve-
ments of the ORCA Series FPGAs over time will result
in significant improvement of the actual performance
over those listed for a speed grade. Even though lower
speed grades may still be available, the distribution of
yield to timing parameters may be several speed
grades higher than that designated on a product brand.
Design practices need to consider best-case timing
parameters (e.g., delays = 0), as well as worst-case
timing.
Propagation Delay—The time between the specified
reference points. The delays provided are the worst
case of the tphh and tpll delays for noninverting func-
tions, tplh and tphl for inverting functions, and tphz and
tplz for 3-state enable.
Setup Time—The interval immediately preceding the
transition of a clock or latch enable signal, during which
the data must be stable to ensure it is recognized as
the intended value.
The routing delays are a function of fan-out and the
capacitance associated with the configurable interface
points (CIPs) and metal interconnect in the path. The
number of logic elements that can be driven (fan-out)
by PFUs is unlimited, although the delay to reach a
valid logic level can exceed timing requirements. It is
difficult to make accurate routing delay estimates prior
to design compilation based on fan-out. This is
Hold Time—The interval immediately following the
transition of a clock or latch enable signal, during which
the data must be held stable to ensure it is recognized
as the intended value.
because the CAE software may delete redundant logic
inserted by the designer to reduce fan-out, and/or it
may also automatically reduce fan-out by net splitting.
3-State Enable—The time from when a 3-state control
signal becomes active and the output pad reaches the
high-impedance state.
PFU Timing
Table 5. Combinatorial PFU Timing Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Symbol
Parameter
Unit
Min Max Min Max
Combinatorial Delays (TJ = +85 °C, VDD = min, VDD2 = min):
Four-input Variables (Kz[3:0] to F[z])*
F4_DEL
F5_DEL
—
—
—
—
—
—
—
1.03
0.85
2.30
1.91
3.40
3.02
1.66
—
—
—
—
—
—
—
0.90 ns
0.74 ns
2.00 ns
1.66 ns
2.96 ns
2.63 ns
1.44 ns
Five-input Variables (F5[A:D] to F[0, 2, 4, 6])
Two-level LUT Delay (Kz[3:0] to F w/feedbk)*
Two-level LUT Delay (F5[A:D] to F w/feedbk)
Three-level LUT Delay (Kz[3:0] to F w/feedbk)*
Three-level LUT Delay (F5[A:D] to F w/feedbk)
CIN to COUT Delay (logic mode)
SWL2_DEL
SWL2F5_DEL
SWL3_DEL
SWL3F5_DEL
CO_DEL
* Four-input variables’ (KZ[3:0]) path delays are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.
Lattice Semiconductor
13
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 6. Sequential PFU Timing Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Symbol
Parameter
Unit
Min Max Min Max
Input Requirements
CLKL_MPW
CLKH_MPW
GSR_MPW
LSR_MPW
Clock Low Time
Clock High Time
1.00
0.76
1.00
1.00
—
—
—
—
0.87
0.66
0.87
0.87
—
—
—
—
ns
ns
ns
ns
Global S/R Pulse Width (GSRN)
Local S/R Pulse Width
Combinatorial Setup Times (TJ = +85 °C,
VDD = min, VDD2 = min):
F4_SET
F5_SET
DIN_SET
CINDIR_SET
CE1_SET
CE2_SET
LSR_SET
SEL_SET
SWL2_SET
SWL2F5_SET
SWL3_SET
SWL3F5_SET
Four-input Variables to Clock (Kz[3:0] to CLK)*
Five-input Variables to Clock (F5[A:D] to CLK)
Data In to Clock (DIN[7:0] to CLK)
Carry-in to Clock, DIRECT to REGCOUT (CIN to CLK) 0.68
Clock Enable to Clock (CE to CLK)
Clock Enable to Clock (ASWE to CLK)
Local Set/Reset to Clock (SYNC) (LSR to CLK)
Data Select to Clock (SEL to CLK)
Two-level LUT to Clock (Kz[3:0] to CLK w/feedbk)*
Two-level LUT to Clock (F5[A:D] to CLK w/feedbk)
Three-level LUT to Clock (Kz[3:0] to CLK w/feedbk)*
Three-level LUT to Clock (F5[A:D] to CLK w/feedbk)
0.90
0.51
0.21
—
—
—
—
—
—
—
—
—
—
—
—
0.78
0.44
0.18
0.59
1.23
0.97
0.60
0.55
1.55
1.27
2.66
2.32
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.41
1.11
0.69
0.64
1.79
1.46
3.06
2.67
Combinatorial Hold Times (TJ = all, VDD = all):
Data In (DIN[7:0] from CLK)
Carry-in from Clock, DIRECT to REGCOUT (CIN from 0.0
CLK)
DIN_HLD
CINDIR_HLD
0.0
—
—
0.0
0.0
—
—
ns
ns
CE1_HLD
CE2_HLD
LSR_HLD
SEL_HLD
—
Clock Enable (CE from CLK)
0.0
0.0
0.0
0.0
0.0
—
—
—
—
—
0.0
0.0
0.0
0.0
0.0
—
—
—
—
—
ns
ns
ns
ns
ns
Clock Enable from Clock (ASWE from CLK)
Local Set/Reset from Clock (sync) (LSR from CLK)
Data Select from Clock (SEL from CLK)
All Others
Output Characteristics
Sequential Delays (TJ = +85 °C,
VDD = min, VDD2 = min):
LSR_DEL
Local S/R (async) to PFU Out (LSR to Q[7:0], REG-
COUT)
—
2.82
—
2.46 ns
GSR_DEL
REG_DEL
Global S/R to PFU Out (GSRN to Q[7:0], REGCOUT)
Clock to PFU Out—Register (CLK to Q[7:0], REG-
COUT)
—
—
2.21
1.22
—
—
1.92 ns
1.06 ns
LTCH_DEL
LTCHD_DEL
Clock to PFU Out—Latch (CLK to Q[7:0])
Transparent Latch (DIN[7:0] to Q[7:0])
—
—
1.30
1.43
—
—
1.13 ns
1.25 ns
* Four-input variables’ (KZ[3:0]) setup times are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.
Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the
same timing parameter and may accurately report delays that are less than those listed.
14
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 7. Ripple Mode PFU Timing Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Parameter
(TJ = +85 °C, VDD = min, VDD2 = min)
Symbol
Unit
Min Max Min Max
Full Ripple Setup Times (byte-wide):
Operands to Clock (Kz[1:0] to CLK)
Bitwise Operands to Clock (Kz[1:0] to CLK at F[z])
Fast Carry-in to Clock (FCIN to CLK)
Carry-in to Clock (CIN to CLK)
Add/Subtract to Clock (ASWE to CLK)
Operands to Clock (Kz[1:0] to CLK at REGCOUT)
Fast Carry-in to Clock (FCIN to CLK at REGCOUT) 1.03
Carry-in to Clock (CIN to CLK at REGCOUT) 1.48
RIP_SET
FRIP_SET
FCIN_SET
CIN_SET
1.58
0.90
1.21
1.68
4.70
1.02
—
—
—
—
—
—
—
—
1.37
0.78
1.05
1.46
4.09
0.89
0.90
1.29
3.92
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS_SET
RIPRC_SET
FCINRC_SET
CINRC_SET
ASRC_SET
Add/Subtract to Clock (ASWE to CLK at REGCOUT) 4.51
Full Ripple Hold Times (TJ = all, VDD = all):
FCINRC_HLD
——
Fast Carry-in from Clock (FCIN from CLK at REG-
COUT)
All Others
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Half Ripple Setup Times (nibble wide):
Operands to Clock (Kz[1:0] to CLK)
Bitwise Operands to Clock (Kz[1:0] to CLK at F[z])
Fast Carry-in to Clock (FCIN to CLK)
Carry-in to Clock (CIN to CLK)
Add/Subtract to Clock (ASWE to CLK)
Operands to Clock (Kz[1:0] to CLK at REGCOUT)
Fast Carry-in to Clock (FCIN to CLK at REGCOUT) 1.03
Carry-in to Clock (CIN to CLK at REGCOUT) 1.48
HRIP_SET
HFRIP_SET
HFCIN_SET
HCIN_SET
1.74
0.90
1.21
1.68
4.70
1.37
—
—
—
—
—
—
—
—
—
1.51
0.78
1.05
1.46
4.09
1.19
0.90
1.29
3.92
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
HAS_SET
HRIPRC_SET
HFCINRC_SET
HCINRC_SET
HASRC_SET
Add/Subtract to Clock (ASWE to CLK at REGCOUT) 4.51
Half Ripple Hold Times (TJ = all, VDD = all):
HFCINRC_HLD
——
Fast Carry-in from Clock (HFCIN from CLK at RE-
COUT)
All Others
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Note: The table shows worst-case delay for the ripple chain. ORCA Foundry reports the delay for individual paths within the ripple chain
that will be less than or equal to those listed above.
Lattice Semiconductor
15
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 7. Ripple Mode PFU Timing Characteristics (continued)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Parameter
(TJ = +85 °C, VDD = min, VDD2 = min)
Symbol
Unit
Min Max Min Max
Full Ripple Delays (byte-wide):
RIPCO_DEL
RIPFCO_DEL
RIP_DEL
Operands to Carry-out (Kz[1:0] to COUT)
Operands to Carry-out (Kz[1:0] to FCOUT)
Operands to PFU Out (Kz[1:0] to F[7:0])
Bitwise Operands to PFU Out (Kz[1:0] to F[z])
Fast Carry-in to Carry-out (FCIN to COUT)
Fast Carry-in to Fast Carry-out (FCIN to FCOUT)
Carry-in to Carry-out (CIN to COUT)
Carry-in to Fast Carry-out (CIN to FCOUT)
Fast Carry-in PFU Out (FCIN to F[7:0])
Carry-in PFU Out (CIN to F[7:0])
—
—
—
—
—
—
—
—
—
—
—
—
—
2.26
2.23
3.21
1.03
1.36
1.33
1.66
1.61
2.03
2.65
4.67
4.58
5.61
—
—
—
—
—
—
—
—
—
—
—
—
—
1.97 ns
1.94 ns
2.79 ns
0.90 ns
1.18 ns
1.15 ns
1.44 ns
1.40 ns
1.77 ns
2.31 ns
4.06 ns
3.98 ns
4.88 ns
FRIP_DEL
FCINCO_DEL
FCINFCO_DEL
CINCO_DEL
CINFCO_DEL
FCIN_DEL
CIN_DEL
ASCO_DEL
ASFCO_DEL
AS_DEL
Add/Subtract to Carry-out (ASWE to COUT)
Add/Subtract to Carry-out (ASWE to FCOUT)
Add/Subtract to PFU Out (ASWE to F[7:0])
Half Ripple Delays (nibble wide):
HRIPCO_DEL
HRIPFCO_DEL
HRIP_DEL
HFRIP_DEL
HFCINCO_DEL
Operands to Carry-out (Kz[1:0] to COUT)
Operands to Fast Carry-out (Kz[1:0] to FCOUT)
Operands to PFU Out (Kz[1:0] to F[3:0])
Bitwise Operands to PFU Out (Kz[1:0] to F[z])
Fast Carry-in to Carry-out (FCIN to COUT)
—
—
—
—
—
—
—
—
—
—
—
—
—
2.26
2.23
2.61
1.03
1.36
1.33
1.66
1.61
1.72
2.40
4.67
4.58
5.00
—
—
—
—
—
—
—
—
—
—
—
—
—
1.97 ns
1.94 ns
2.27 ns
0.90 ns
1.18 ns
1.15 ns
1.44 ns
1.40 ns
1.50 ns
2.09 ns
4.06 ns
3.98 ns
4.34 ns
HFCINFCO_DEL Fast Carry-in to Fast Carry-out (FCIN to FCOUT)
HCINCO_DEL
HCINFCO_DEL
HFCIN_DEL
HCIN_DEL
HASCO_DEL
HASFCO_DEL
HAS_DEL
Carry-in to Carry-out (CIN to COUT)
Carry-in to Carry-out (CIN to FCOUT)
Fast Carry-in PFU Out (FCIN to F[3:0])
Carry-in PFU Out (CIN to F[3:0])
Add/Subtract to Carry-out (ASWE to COUT)
Add/Subtract to Carry-out (ASWE to FCOUT)
Add/Subtract to PFU Out (ASWE to F[3:0])
Note: The table shows worst-case delay for the ripple chain. ORCA Foundry reports the delay for individual paths within the ripple chain
that will be less than or equal to those listed above.
16
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 8. Synchronous Memory Write Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Symbol
Parameter
Unit
Min Max Min Max
Write Operation for RAM Mode
SMCLK_FRQ
SMCLKL_MPW
SMCLKH_MPW
MEM_DEL
Maximum Frequency
Clock Low Time
Clock High Time
—
1.03
1.96
—
266.4
—
—
—
0.90
1.71
—
333.0 MHz
—
—
ns
ns
ns
Clock to Data Valid (CLK to F[6, 4, 2, 0])*
4.39
3.82
Write Operation Setup Time
WA4_SET
WA_SET
WD_SET
WE_SET
WPE0_SET
WPE1_SET
Address to Clock (CIN to CLK)
Address to Clock (DIN[7, 5, 3, 1] to CLK)
Data to Clock (DIN[6, 4, 2, 0] to CLK)
Write Enable (WREN) to Clock (ASWE to CLK)
Write-port Enable 0 (WPE0) to Clock (CE to CLK)
Write-port Enable 1 (WPE1) to Clock (LSR to CLK)
0.68
0.35
0.21
0.37
0.87
1.10
—
—
—
—
—
—
0.59
0.30
0.18
0.32
0.75
0.95
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Write Operation Hold Time
WA4_HLD
WA_HLD
WD_HLD
WE_HLD
WPE0_HLD
WPE1_HLD
Address from Clock (CIN from CLK)
Address from Clock (DIN[7, 5, 3, 1] from CLK)
Data from Clock (DIN[6, 4, 2, 0] from CLK)
Write Enable (WREN) from Clock (ASWE from CLK)
Write-port Enable 0 (WPE0) from Clock (CE from CLK)
Write-port Enable 1 (WPE1) from Clock (LSR from CLK)
0.0
0.0
0.33
0.0
0.0
0.0
—
—
—
—
—
—
0.0
0.0
0.29
0.0
0.0
0.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
* The RAM is written on the inactive clock edge following the active edge that latches the address, data, and control signals.
Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same
timing parameter and may accurately report delays that are less than those listed.
WA4_SET
WA_SET
WA4_HLD
WA_HLD
CIN, DIN[7, 5, 3, 1]
DIN[6, 4, 2, 0]
WD_SET
WD_HLD
WE_HLD
WE_SET
ASWE (WREN)
WPE0_HLD
WPE1_HLD
WPE0_SET
WPE1_SET
CE (WPE0),
LSR(WPE1)
SMCLKH_MPW
SMCLKL_MPW
CK
MEM_DEL
F[6, 4, 2, 0]
5-4621 (F)b
Figure 4. Synchronous Memory Write Characteristics
Lattice Semiconductor
17
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 9. Synchronous Memory Read Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Parameter
(TJ = 85 °C, VDD = min, VDD2 = min)
Symbol
Unit
Min Max Min Max
Read Operation
RA_DEL
RA4_DEL
Data Valid After Address (Kz[3:0] to F[6, 4, 2, 0])
Data Valid After Address (F5[A:D] to F[6, 4, 2, 0])
—
—
1.03
0.85
—
—
0.90 ns
0.74 ns
Read Operation, Clocking Data into Latch/FF
RA_SET
RA4_SET
RA_HLD
RA4_HLD
REG_DEL
SMRD_CYC
Address to Clock Setup Time (Kz[3:0] to CLK)
0.90
0.51
0.0
0.0
—
—
—
—
—
1.22
5.38
0.78
0.44
0.0
0.0
—
—
—
—
—
ns
ns
ns
ns
Address to Clock Setup Time (F5[A:D] to CLK)
Address from Clock Hold Time (Kz[3:0] from CLK)
Address from Clock Hold Time (F5[A:D] from CLK)
Clock to PFU Output—Register (CLK to Q[6, 4, 2, 0])
Read Cycle Delay
1.06 ns
4.68 ns
—
—
Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing
the same timing parameter and may accurately report delays that are less than those listed.
Kz[3:0], F5[A:D]
RA_DEL
RA4_DEL
f[6, 4, 2, 0]
RA_HLD
RA4_HLD
RA_SET
RA4_SET
CK
REG_DEL
Q[3:0]
5-4622(F)
Figure 5. Synchronous Memory Read Cycle
18
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
PLC Timing
Table 10. PFU Output MUX and Direct Routing Timing Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Parameter
(TJ = 85 °C, VDD = min, VDD2 = min)
Symbol
Unit
Min Max Min Max
PFU Output MUX (Fan-out = 1)
OMUX_DEL Output MUX Delay (F[7:0]/Q[7:0] to O[9:0])
COO9_DEL Carry-out MUX Delay (COUT to O9)
RCOO8_DEL Registered Carry-out MUX Delay (REGCOUT to O8)
—
—
—
0.76
0.74
0.74
—
—
—
0.66 ns
0.64 ns
0.64 ns
Direct Routing
FDBK_DEL PFU Feedback (xSW)*
ODIR_DEL PFU to Orthogonal PFU Delay (xSW to xSW)
DDIR_DEL PFU to Diagonal PFU Delay (xBID to xSW)
—
—
—
0.75
0.89
1.61
—
—
—
0.65 ns
0.78 ns
1.40 ns
* This is general feedback using switching segments. See the combinatorial PFU timing table for softwired look-up table feedback timing.
SLIC Timing
Table 11. Supplemental Logic and Interconnect Cell Timing Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Parameter
(TJ = 85 °C, VDD = min, VDD2 = min)
Symbol
Unit
Min Max Min Max
3-Statable BIDIs
BUF_DEL
BIDI Delay (BRx to BLx, BLx to BRx)
—
—
—
—
0.70
0.61
1.18
2.01
—
—
—
—
0.61 ns
0.53 ns
1.03 ns
1.75 ns
OBUF_DEL BIDI Delay (Ox to BRx, Ox to BLx)
TRI_DEL
DECTRI_DEL BIDI 3-state Enable/Disable Delay
(BL, BR via DEC, TRI to BL, BR)
BIDI 3-state Enable/Disable Delay (TRI to BL, BR)
Decoder
DEC98_DEL Decoder Delay (BR[9:8], BL[9:8] to DEC)
—
—
1.16
1.29
—
—
1.01 ns
1.12 ns
DEC_DEL
Decoder Delay (BR[7:0], BL[7:0] to DEC)
Lattice Semiconductor
19
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
PIO Timing.
Table 12. Programmable I/O Timing Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Symbol
Parameter
Unit
Min Max Min Max
Input Delays (TJ = 85 °C, VDD = min, VDD2 = min)
IN_RIS
IN_FAL
Input Rise Time
Input Fall Time
—
—
575
575
—
—
500
500
ns
ns
PIO Direct Delays:
CKIN_DEL
IN_DEL
IND_DEL
Pad to In (pad to CLK IN)
Pad to In (pad to IN1, IN2)
Pad to In Delayed (pad to IN1, IN2)
PIO Transparent Latch Delays:
Pad to In (pad to IN1, IN2)
Pad to In Delayed (pad to IN1, IN2)
Input Latch/FF Setup Timing:
Pad to ExpressCLK (fast-capture latch/FF)
—
—
—
0.77
1.35
11.55
—
—
—
0.55
1.07
9.89
ns
ns
ns
LATCH_DEL
LATCHD_DEL
—
—
2.79
12.46
—
—
2.42
10.87 ns
ns
INREGE_SET
INREGED_SET Pad Delayed to ExpressCLK
(fast-capture latch/FF)
4.54
14.53
—
—
2.62
11.63
—
—
ns
ns
INREG_SET
INREGD_SET
INCE_SET
Pad to Clock (input latch/FF)
0.65
10.90
0.92
—
—
—
—
0.46
9.50
0.82
0.73
—
—
—
—
ns
ns
ns
ns
Pad Delayed to Clock (input latch/FF)
Clock Enable to Clock (CE to CLK)
Local Set/Reset (sync) to Clock (LSR to CLK)
Input FF/Latch Hold Timing:
INLSR_SET
0.81
INREGE_HLD
INREGED_HLD Pad Delayed from ExpressCLK
(fast-capture latch/FF)
Pad from ExpressCLK (fast-capture latch/FF)
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
INREG_HLD
INREGD_HLD
INCE_HLD
Pad from Clock (input latch/FF)
Pad Delayed from Clock (input latch/FF)
Clock Enable from Clock (CE from CLK)
Local Set/Reset (sync) from Clock
(LSR from CLK)
0.0
0.0
0.0
0.0
—
—
—
—
0.0
0.0
0.0
0.0
—
—
—
—
ns
ns
ns
ns
INLSR_HLD
INREG_DEL
INLTCH_DEL
INLSR_DEL
INLSRL_DEL
Clock-to-in Delay (FF CLK to IN1, IN2)
Clock-to-in Delay (latch CLK to IN1, IN2)
Local S/R (async) to IN (LSR to IN1, IN2)
Local S/R (async) to IN (LSR to IN1, IN2) Latch/FF in
Latch Mode
—
—
—
—
1.94
1.94
2.95
2.64
—
—
—
—
1.68
1.68
2.55
2.30
ns
ns
ns
ns
INGSR_DEL
Global S/R to In (GSRN to IN1, IN2)
—
2.69
—
2.34
ns
Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns.
20
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 12. Programmable I/O Timing Characteristics (continued)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Symbol
Parameter
Unit
Min Max Min Max
Output Delays (TJ = 85 °C, VDD = min, CL = 50 pF)
Output to Pad (OUT2, OUT1 direct to pad):
Fast
OUTF_DEL
OUTSL_DEL
OUTSI_DEL
—
—
—
3.79
4.71
10.14
—
—
—
3.21
3.91
8.84
ns
ns
ns
Slewlim
Sinklim
3-state Enable/Disable Delay (TS to pad):
TSF_DEL
TSSL_DEL
TSSI_DEL
Fast
Slewlim
Sinklim
—
—
—
3.86
4.66
10.24
—
—
—
3.29
3.99
8.92
ns
ns
ns
Local Set/Reset (async) to Pad (LSR to pad):
Fast
OUTLSRSL_DEL Slewlim
OUTLSRF_DEL
—
—
—
5.70
6.58
12.09
—
—
—
4.90
5.60
10.52 ns
ns
ns
OUTLSRSI_DEL
Sinklim
Global Set/Reset to Pad (GSRN to pad):
Fast
OUTGSRSL_DEL Slewlim
OUTGSRSI_DEL Sinklim
OUTGSRF_DEL
—
—
—
5.05
5.75
10.60
—
—
—
4.81
5.51
10.43 ns
ns
ns
Output FF Setup Timing:
OUTE_SET
OUT_SET
OUTCE_SET
OUTLSR_SET
Out to ExpressCLK (OUT[2:1] to ECLK)
Out to Clock (OUT[2:1] to CLK)
Clock Enable to Clock (CE to CLK)
Local Set/Reset (sync) to Clock (LSR to CLK)
Output FF Hold Timing:
0.0
0.0
0.44
0.05
—
—
—
—
0.0
0.0
0.39
0.04
—
—
—
—
ns
ns
ns
ns
OUTE_HLD
OUT_HLD
OUTCE_HLD
OUTLSR_HLD
Out from ExpressCLK (OUT[2:1] from ECLK)
Out from Clock (OUT[2:1] from CLK)
Clock Enable from Clock (CE from CLK)
0.32
0.32
0.0
—
—
—
—
0.28
0.28
0.0
—
—
—
—
ns
ns
ns
ns
Local Set/Reset (sync) from Clock (LSR from CLK) 0.0
0.0
Clock to Pad Delay (ECLK, SCLK to pad):
OUTREGF_DEL
OUTREGSL_DEL Slewlim
OUTREGSI_DEL Sinklim
Fast
—
—
—
—
4.67
5.55
11.05
—
—
—
—
4.02
4.72
9.64
0.09
ns
ns
ns
ns
OD_DEL
Additional Delay If Using Open Drain
0.11
Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns
Lattice Semiconductor
21
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 12. Programmable I/O Timing Characteristics (continued)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Symbol
Parameter
Unit
Min Max Min Max
PIO Logic Block Delays
Out to Pad (OUT[2:1] via logic to pad):
OUTLF_DEL
OUTLSL_DEL
OUTLSI_DEL
Fast
Slewlim
Sinklim
—
—
—
3.79
4.71
10.14
—
—
—
3.21
3.91
8.84
ns
ns
ns
Outreg to Pad (OUTREG via logic to pad):
OUTRF_DEL
OUTRSL_DEL
OUTRSI_DEL
Fast
Slewlim
Sinklim
—
—
—
4.67
5.55
11.05
—
—
—
4.02
4.72
9.64
ns
ns
ns
Clock to Pad (ECLK, CLK via logic to pad):
OUTCF_DEL
OUTCSL_DEL
OUTCSI_DEL
Fast
Slewlim
Sinklim
—
—
—
4.54
5.44
10.92
—
—
—
3.90
4.60
9.53
ns
ns
ns
3-State FF Delays
3-state Enable/Disable Delay (TS direct to pad):
TSF_DEL
TSSL_DEL
TSSI_DEL
Fast
Slewlim
Sinklim
—
—
—
3.86
4.66
10.24
—
—
—
3.29
3.99
8.92
ns
ns
ns
Local Set/Reset (async) to Pad (LSR to pad):
TSLSRF_DEL
TSLSRSL_DEL
TSLSRSI_DEL
Fast
Slewlim
Sinklim
—
—
—
5.13
5.93
11.51
—
—
—
4.38
5.08
10.01 ns
ns
ns
Global Set/Reset to Pad (GSRN to pad):
Fast
TSGSRSL_DEL Slewlim
TSGSRF_DEL
—
—
—
4.65
5.35
10.20
—
—
—
4.28
4.98
9.91
ns
ns
ns
TSGSRSI_DEL
Sinklim
3-State FF Setup Timing:
TS to ExpressCLK (TS to ECLK)
TS to Clock (TS to CLK)
TSE_SET
TS_SET
TSLSR_SET
0.0
0.0
—
—
—
0.0
0.0
0.0
—
—
—
ns
ns
ns
Local Set/Reset (sync) to Clock (LSR to CLK) 0.0
3-State FF Hold Timing:
TSE_HLD
TS_HLD
TSLSR_HLD
TS from ExpressCLK (TS from ECLK)
TS from Clock (TS from CLK)
Local Set/Reset (sync) from Clock
(LSR from CLK)
0.34
0.34
0.0
—
—
—
0.30
0.30
0.0
—
—
—
ns
ns
ns
Clock to Pad Delay (ECLK, SCLK to pad):
Fast
TSREGSL_DEL Slewlim
TSREGSI_DEL Sinklim
TSREGF_DEL
—
—
—
4.09
4.90
10.48
—
—
—
3.49
4.19
9.12
ns
ns
ns
Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns.
22
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Special Function Blocks Timing
Table 13. Microprocessor Interface (MPI)Timing Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
–7
–8
Symbol
Parameter
Unit
Min Max Min Max
PowerPC Interface Timing (TJ = 85 °C, VDD = min, VDD2 = min)
TA_DEL
BI_DEL
Transfer Acknowledge Delay (CLK to TA)
Burst Inhibit Delay (CLK to BIN)
—
—
—
—
0.0
9.50
9.40
—
—
—
—
—
—
—
—
—
—
2.20
4.60
—
—
—
8.30 ns
8.20 ns
2
TA_DELZ
BI_DELZ
WD_SET
WD_HLD
A_SET
Transfer Acknowledge Delay to High Impedance
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
Burst Inhibit Delay to High Impedance
—
Write Data Setup Time (data to TS)
Write Data Hold Time (data from CLK while MPI_ACK low) 0.0
Address Setup Time (addr to TS)
Address Hold Time (addr from CLK while MPI_ACK low)
Read/Write Setup Time (R/W to TS)
0.0
0.0
0.0
0.0
0.0
0.0
0.40
0.0
—
0.0
0.0
0.0
A_HLD
RW_SET
RW_HLD
CS_SET
CS_HLD
UA_DEL
Read/Write Hold Time (R/W from CLK while MPI_ACK low) 0.0
Chip Select Setup Time (CS0, CS1 to TS)
Chip Select Hold Time (CS0, CS1 from CLK)
User Address Delay (pad to UA[3:0])
0.46
0.0
—
1.90 ns
4.00 ns
URDWR_DEL User Read/Write Delay (pad to URDWR_DEL)
—
—
i960 Interface Timing (TJ = 85 °C, VDD = min, VDD2 = min)
ADSN_SET
ADSN_HLD
Addr/Data Select to ALE (ADS, to ALE low)
Addr/Data Select to ALE (ADS, from ALE low)
—
0.0
—
—
—
—
—
0.80
—
0.80
—
—
9.50
—
—
—
0.12
—
0.12
—
—
0.0
—
—
—
—
—
0.70
—
0.70
—
—
ns
ns
RDYRCV_DEL Ready/Receive Delay (CLK to RDYRCV)
RDYRCV_DELZ Ready/Receive Delay to High Impedance
8.30 ns
2
—
—
—
ns
ns
ns
3
WD_SET
WD_HLD
A_SET
A_HLD
BE_SET
BE_HLD
Write Data Setup Time
Write Data Hold Time
4
Address Setup Time (addr to ALE low)
Address Hold Time (addr from ALE low)
Byte Enable Setup Time (BE0, BE1 to ALE low)
Byte Enable Hold Time (BE0, BE1 from ALE low)
0.10 ns
ns
0.10 ns
ns
—
—
1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge
when MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and
CS1 may go inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle.
6. USTART_DEL is based on the falling clock edge.
7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle.
8. The user must assert interrupt request low until a service routine is executed.
9. This should be at least one MPI_CLK cycle.
10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA.
PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
Lattice Semiconductor
23
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 13. Microprocessor Interface (MPI)Timing Characteristics (continued)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
–7
–8
Symbol
Parameter
Unit
Min Max Min Max
i960 Interface Timing (TJ = 85 °C, VDD = min, VDD2 = min) (continued)
3
RW_SET
RW_HLD
CS_SET
CS_HLD
UA_DEL
Read/Write Setup Time
Read/Write Hold Time
—
—
0.80
0.0
—
—
—
—
—
6.21
4.60
—
—
0.70
0.0
—
—
—
—
—
ns
ns
ns
ns
4
1
Chip Select Setup Time (CS0, CS1 to CLK)
Chip Select Hold Time (CS0, CS1 from CLK)
User Address Delay (CLK low to UA[3:0])
1
5.40 ns
4.00 ns
URDWR_DEL
User Read/Write Delay (pad to URDWR_DEL)
—
—
5
User Logic Delay
6
USTART_DEL
User Start Delay (MPI_CLK falling to USTART)
—
—
—
3.80
6.90
—
—
—
—
3.30 ns
6.00 ns
USTARTCLR_DEL User Start Clear Delay (MPI_CLK to USTART)
7
UEND_DEL
User End Delay (USTART low to UEND low)
—
ns
Synchronous User Timing
UEND_SET
UEND_HLD
RDS_SET
RDS_HLD
User End Setup (UEND to MPI_CLK)
0.0
1.40
—
—
—
—
—
0.0
1.20
—
—
—
—
—
ns
ns
ns
ns
User End Hold (UEND to MPI_CLK)
9
Data Setup for Read (D[7:0] to MPI_CLK)
9
Data Hold for Read (D[7:0] from MPI_CLK)
—
—
Asynchronous User Timing
10
RDA_DEL
RDA_HLD
TUIRQ_PW
User End to Read Data Delay (UEND to D[7:0])
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
9
Data Hold from User Start (low)
8
Interrupt Request Pulse Width
1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge
when MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and
CS1 may go inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle.
6. USTART_DEL is based on the falling clock edge.
7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle.
8. The user must assert interrupt request low until a service routine is executed.
9. This should be at least one MPI_CLK cycle.
10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA.
PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
24
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Clock Timing
Table 14. ExpressCLK (ECLK) and Fast Clock (FCLK) Timing Characteristics
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Device
Symbol
Unit
ns
(TJ = 85 °C, VDD = min, VDD2 = min)
Min Max Min Max
ECLKC_DEL Clock Control Timing Delay Through CLKCNTRL
(input from corner)
0.31
1.06
—
—
0.27
0.92
—
—
ECLKM_DEL Delay Through CLKCNTRL (input from
internal clock controller PAD)
ns
Clock Shutoff Timing:
OFFM_SET
OFFM_HLD
OFFC_SET
OFFC_HLD
Setup from Middle ECLK (shut off to CLK)
Hold from Middle ECLK (shut off from CLK)
Setup from Corner ECLK (shut off to CLK)
Hold from Corner ECLK (shut off from CLK)
0.41
0.0
0.41
0.0
—
—
—
—
0.36
0.0
0.36
0.0
—
—
—
—
ns
ns
ns
ns
ECLKM_DEL ECLK Delay (middle pad):
OR3L165
OR3L225
—
—
2.32
2.37
—
—
2.02 ns
2.07 ns
ECLKC_DEL ECLK Delay (corner pad):
OR3L165
OR3L225
—
—
5.02
5.27
—
—
4.23 ns
4.45 ns
FCLKM_DEL FCLK Delay (middle pad):
OR3L165
OR3L225
—
—
5.74
6.04
—
—
5.06 ns
5.35 ns
FCLKC_DEL FCLK Delay (corner pad):
OR3L165
OR3L225
—
—
8.41
8.89
—
—
7.24 ns
7.68 ns
Notes:
The ECLK delays are to all of the PICs on one side of the device for middle pin input, or two sides of the device for corner pin input.
The delay includes both the input buffer delay and the clock routing to the PIC clock input.
The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the
input buffer delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.
Lattice Semiconductor
25
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 15. General-Purpose Clock Timing Characteristics (Internally Generated Clock)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Device
Symbol
Unit
(TJ = 85 °C, VDD = min, VDD2 = min)
Min
Max
Min
Max
CLK_DEL
CLK_DEL
OR3L165
OR3L225
—
—
4.56
4.58
—
—
3.98
3.99
ns
ns
Notes:
This table represents the delay for an internally generated clock from the clock tree input in one of the four middle
PICs (using pSW routing) on any side of the device which is then distributed to the PFU/PIO clock inputs. If the clock
tree input used is located at any other PIC, see the results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the general clock network. The delay will be reduced if any of
the clock branches are not used. See pin-to-pin timing in Table 18 for clock delays of clocks input on general I/O pins.
26
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 16. OR3Lxxx ExpressCLK to Output Delay (Pin-to-Pin)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Description
(TJ = 85 °C, VDD = min, VDD2 = min)
Device
Unit
Min Max Min Max
ECLK Middle Input Pin→OUTPUT
Pin (Fast)
OR3L165
OR3L225
—
—
6.94
6.99
—
—
5.84 ns
5.89 ns
ECLK Middle Input Pin→OUTPUT
Pin (Slewlim)
OR3L165
OR3L225
—
—
7.79
7.84
—
—
6.64 ns
6.69 ns
ECLK Middle Input Pin→OUTPUT
Pin (Sinklim)
OR3L165
OR3L225
—
—
12.91
12.96
—
—
11.08 ns
11.13 ns
Additional Delay if ECLK Corner Pin
Used
OR3L165
OR3L225
—
—
2.70
2.90
—
—
2.21 ns
2.38 ns
Notes:
Timing is without the use of the PCM.
This clock delay is for a fully routed clock tree that uses the ExpressCLK network. It includes both the input
buffer delay, the clock routing to the PIO CLK input, the clock→Q of the FF, and the delay through the output
buffer. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the
device, and that a PIO FF be used.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
ECLK
5-4846 (F)c
Figure 6. ExpressCLK to Output Delay
Lattice Semiconductor
27
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 17. OR3Lxxx Fast Clock (FCLK) to Output Delay (Pin-to-Pin)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Description
(TJ = 85 °C, VDD = min, VDD2 = min)
Device
Unit
Min Max Min Max
Output Not on Same Side of Device as Input Clock (Fast Clock Delays Using
ExpressCLK Inputs)
ECLK Middle Input Pin →OUTPUT Pin
(Fast)
OR3L165
OR3L225
—
—
10.37
10.66
—
—
8.89 ns
9.17 ns
ECLK Middle Input Pin →OUTPUT Pin
(Slewlim)
OR3L165
OR3L225
—
—
11.22
11.54
—
—
9.69 ns
9.97 ns
ECLK Middle Input Pin →OUTPUT Pin
(Sinklim)
OR3L165
OR3L225
—
—
16.33
16.63
—
—
14.13 ns
14.41 ns
Additional Delay if ECLK Corner Pin
Used
OR3L165
OR3L225
—
—
2.66
2.85
—
—
2.17 ns
2.33 ns
Notes:
Timing is without the use of the PCM.
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input
buffer delay, the clock routing to the PIO CLK input, the clock→Q of the FF, and the delay through the output
buffer. The delay will be reduced if any of the clock branches are not used. The given timing requires that the
input clock pin be located at one of the six ExpressCLK inputs of the device and that a PIO FF be used.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
CLKCNTRL
FCLK
ECLK
5-4846(F).b
Figure 7. Fast Clock to Output Delay
28
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 18. OR3Lxxx General System Clock (SCLK) to Output Delay (Pin-to-Pin)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Description
(TJ = 85 °C, VDD = min, VDD2 = min)
Device
Unit
Min
Max
Min
Max
Output On Same Side of Device As Input Clock (System Clock Delays Using General
User I/O Inputs)
Clock Input Pin (mid-PIC) →OUTPUT Pin OR3L165
(Fast) OR3L225
Clock Input Pin (mid-PIC) →OUTPUT Pin OR3L165
(Slewlim) OR3L225
Clock Input Pin (mid-PIC) →OUTPUT Pin OR3L165
—
—
11.81
12.32
—
—
10.06 ns
10.54 ns
—
—
12.66
13.16
—
—
11.85 ns
11.34 ns
—
—
17.78
18.28
—
—
15.29 ns
15.78 ns
(Sinklim)
OR3L225
Additional Delay if Non-mid-PIC Used as
Clock Pin
OR3L165
OR3L225
—
—
1.04
1.43
—
—
1.03
1.43
ns
ns
Output Not on Same Side of Device As Input Clock (System Clock Delays Using
General User I/O Inputs)
Additional Delay if Output Not on Same
Side as Input Clock Pin
OR3L165
OR3L225
—
—
1.04
1.43
—
—
1.03
1.43
ns
ns
Note: This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input
buffer delay, the clock routing to the PIO CLK input, the clock→Q of the FF, and the delay through the output
buffer. The delay will be reduced if any of the clock branches are not used. The given timing requires that the
input clock pin be located at one of the four center PICs on any side of the device and that a PIO FF be used.
For clock pins located at any other PIO, see the results reported by ORCA Foundry.
PIOFF
D
Q
OUTPUT (50 pF LOAD)
SCLK
5-4846(F)
Figure 8. System Clock to Output Delay
Lattice Semiconductor
29
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 19. OR3Lxxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Description
(TJ = 85 °C, VDD = min, VDD2 = min)
Device
Unit
Min
Max
Min
Max
Input to ECLK Setup Time
(middle ECLK pin)
OR3L165 2.63
OR3L225 2.61
—
—
0.96
0.95
—
—
ns
ns
Input to ECLK Setup Time
(middle ECLK pin, delayed data input) OR3L225 12.60
OR3L165 12.62
—
—
9.97
9.96
—
—
ns
ns
Input to ECLK Setup Time
(corner ECLK pin)
OR3L165
OR3L225
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Input to ECLK Setup Time
(corner ECLK pin, delayed data input) OR3L225 10.13
OR3L165 10.33
—
—
8.09
7.93
—
—
ns
ns
Input to ECLK Hold Time
(middle ECLK pin)
OR3L165
OR3L225
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Input to ECLK Hold Time
(middle ECLK pin, delayed data input) OR3L225
OR3L165
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the
device for corner pin input. The delay includes both the input buffer delay and the clock routing to the PIO
clock input.
30
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 19. OR3Lxxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) (continued)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Description
(TJ = 85 °C, VDD = min, VDD2 = min)
Device
Unit
Min
Max
Min
Max
Input to ECLK Hold Time
(corner ECLK pin)
OR3L165
OR3L225
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Input to ECLK Hold Time
(corner ECLK pin, delayed data input) OR3L225
OR3L165
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device
for corner pin input. The delay includes both the input buffer delay and the clock routing to the PIO clock input.
PIO ECLK LATCH
INPUT
CLK
D
Q
CLKCNTRL
ECLK
5-4847(F).b
Figure 9. Input to ExpressCLK Setup/Hold Time
Lattice Semiconductor
31
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 20. OR3Lxxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Description
(TJ = 85 °C, VDD = min, VDD2 = min)
Device
Unit
Min
Max
Min
Max
Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using
ExpressCLK Inputs)
Input to FCLK Setup Time
(middle ECLK pin)
OR3L165
OR3L225
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Input to FCLK Setup Time
(middle ECLK pin, delayed data input) OR3L225
OR3L165
6.39
6.37
—
—
5.56
5.55
—
—
ns
ns
Input to FCLK Setup Time
(corner ECLK pin)
OR3L165
OR3L225
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Input to FCLK Setup Time
(corner ECLK pin, delayed data input) OR3L225
OR3L165
4.17
3.97
—
—
3.76
3.58
—
—
ns
ns
Input to FCLK Hold Time
(middle ECLK pin)
OR3L165
OR3L225
4.93
5.22
—
—
4.44
4.72
—
—
ns
ns
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network.
It includes both the input buffer delay and the clock routing to the PFU CLK input. The delay will be reduced
if any of the clock branches are not used.
32
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 20. OR3Lxxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Description
(TJ = 85 °C, VDD = min, VDD2 = min)
Unit
Device
Min
Max
Min
Max
Input to FCLK Hold Time
(middle ECLK pin, delayed data input) OR3L225
OR3L165
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Input to FCLK Hold Time
(corner ECLK pin)
OR3L165
OR3L225
7.59
8.08
—
—
6.61
7.06
—
—
ns
ns
Input to FCLK Hold Time
(corner ECLK pin, delayed data input) OR3L225
OR3L165
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network.
It includes both the input buffer delay and the clock routing to the PFU CLK input. The delay will be reduced
if any of the clock branches are not used.
PIO FF
INPUT
ECLK
D
Q
CLKCNTRL
FCLK
5-4847(F).a
Figure 10. Input to Fast Clock Setup/Hold Time
Lattice Semiconductor
33
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
Table 21. OR3Lxxx Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin)
OR3LxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
-7
-8
Description
(TJ = 85 °C, VDD = min, VDD2 = min)
Device
Unit
Min
Max
Min
Max
Input to SCLK Setup Time
OR3L165
OR3L225
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Input to SCLK Setup Time (delayed
data input)
OR3L165
OR3L225
5.69
5.57
—
—
5.07
4.96
—
—
ns
ns
Input to SCLK Hold Time
OR3L165
OR3L225
6.46
6.96
—
—
5.67
6.16
—
—
ns
ns
Input to SCLK Hold Time (delayed data
input)
OR3L165
OR3L225
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
Additional Hold Time if Non-mid-PIC
Used as SCLK Pin
OR3L165
OR3L225
1.04
1.43
—
—
1.03
1.43
—
—
ns
ns
(no delay on data input)
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the clock network. It includes both the input buffer
delay and the clock routing to the PIO FF CLK input. The delay will be reduced if any of the clock branches
are not used. The given setup (delayed and no delay) and hold (delayed) timing allows the input clock pin
to be located in any PIO on any side of the device, but a PIO FF must be used. The hold (no delay) timing
assumes the clock pin is located at one of the four middle PICs on any side of the device and that a PIO FF
is used. If the clock pin is located elsewhere, then the last parameter in the table must be added to the hold
(no delay) timing.
PIO ECLK LATCH
INPUT
CLK
D
Q
CLKCNTRL
ECLK
5-4847 (F)
Figure 11. Input to System Clock Setup/Hold Time
34
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
The values given for the parameters are the same as
those used during production testing and speed bin-
ning of the devices. The junction temperature and sup-
ply voltage used to characterize the devices are listed
in the delay tables. Actual delays at nominal tempera-
ture and voltage for best-case processes can be much
better than the values given.
Timing Characteristics (continued)
Description
To define speed grades, the ORCA Series part number
designation (see Ordering Information) uses a single-
digit number to designate a speed grade. This number
is not related to any single ac parameter. Higher num-
bers indicate a faster set of timing parameters. The
actual speed sorting is based on testing the delay in a
path consisting of an input buffer, combinatorial delay
through all PLCs in a row, and an output buffer. Other
tests are then done to verify other delay parameters,
such as routing delays, setup times to FFs, etc.
It should be noted that the junction temperature used in
the tables is generally 85 °C. The junction temperature
for the FPGA depends on the power dissipated by the
device, the package thermal characteristics (ΘJA), and
the ambient temperature, as calculated in the following
equation and as discussed further in the Package
Thermal Characteristics section:
The most accurate timing characteristics are reported
by the timing analyzer in the ORCA Foundry Develop-
ment System. A timing report provided by the develop-
ment system after layout divides path delays into logic
and routing delays. The timing analyzer can also pro-
vide logic delays prior to layout. While this allows rout-
ing budget estimates, there is wide variance in routing
delays associated with different layouts.
TJmax = TAmax + (P • ΘJA) °C
Note: The user must determine this junction tempera-
ture to see if the delays from ORCA Foundry
should be derated based on the following derat-
ing tables.
Table 22 and Table 23 provide approximate power sup-
ply and junction temperature derating for OR3Lxxx
commercial and industrial devices. The delay values in
this data sheet and reported by ORCA Foundry are
shown as 1.00 in the tables. The method for determin-
ing the maximum junction temperature is defined in the
Package Thermal Characteristics section. Taken cumu-
latively, the range of parameter values for best-case vs.
worst-case processing, supply voltage, and junction
temperature can approach three to one.
The logic timing parameters noted in the Electrical
Characteristics section of this data sheet are the same
as those in the design tools. In the PFU timing, symbol
names are generally a concatenation of the PFU oper-
ating mode and the parameter type. The setup, hold,
and propagation delay parameters, defined below, are
designated in the symbol name by the SET, HLD, and
DEL characters, respectively.
Lattice Semiconductor
35
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Timing Characteristics (continued)
In addition to supply voltage, process variation, and
operating temperature, circuit and process improve-
ments of the ORCA Series FPGAs over time will result
in significant improvement of the actual performance
over those listed for a speed grade. Even though lower
speed grades may still be available, the distribution of
yield to timing parameters may be several speed
grades higher than that designated on a product brand.
Design practices need to consider best-case timing
parameters (e.g., delays = 0), as well as worst-case
timing.
Table 22. Derating for Commercial/Industrial
OR3Lxxx Devices (I/O Supply VDD)
Power Supply Voltage
T
J
(°C)
3.0 V
3.3 V
3.6 V
–40
0
0.82
0.91
0.98
1.00
1.23
1.34
0.72
0.80
0.85
0.99
1.07
1.15
0.66
0.72
0.77
0.90
0.94
1.01
25
85
The routing delays are a function of fan-out and the
capacitance associated with the CIPs and metal inter-
connect in the path. The number of logic elements that
can be driven (fan-out) by PFUs is unlimited, although
the delay to reach a valid logic level can exceed timing
requirements. It is difficult to make accurate routing
delay estimates prior to design compilation based on
fan-out. This is because the CAE software may delete
redundant logic inserted by the designer to reduce fan-
out, and/or it may also automatically reduce fan-out by
net splitting.
100
125
Table 23. Derating for Commercial/Industrial
OR3Lxxx Devices (I/O Supply VDD2)
Power Supply Voltage
T
J
(°C)
2.3 V
2.5 V
2.6 V
–40
0
0.86
0.94
0.99
1.00
1.23
1.33
0.71
0.79
0.84
0.99
1.05
1.13
0.67
0.73
0.77
0.92
0.96
1.03
25
85
100
125
Note: The derating tables shown above are for a typical critical path
that contains 33% logic delay and 66% routing delay. Since the
routing delay derates at a higher rate than the logic delay, paths
with more than 66% routing delay will derate at a higher rate
than shown in the table. The approximate derating values vs.
temperature are 0.26% per °C for logic delay and 0.45% per °C
for routing delay. The approximate derating values vs. voltage
are 0.13% per mV for both logic and routing delays at 25 °C.
36
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
OR3L165B Clock Power
= [0.039 mW/MHz
Estimating Power Dissipation
P
OR3LxxxB
+ (0.046 mW/MHz/Branch) (# Branches)
+ (0.008 mW/MHz/PFU) (# PFUs)
+ (0.002 mW/MHz/PIO (# PIOs)]
The total operating power dissipated is estimated by
adding the standby (IDDSB), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respec-
tively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
For a quick estimate, the worst-case (typical circuit)
OR3L165B clock power = 9.8 mW/MHz
OR3L225B Clock Power
PT = Σ PPLC + Σ PPIC
P
= [0.045 mW/MHz
The internal operating power is made up of two parts:
clock generation and PFU output power. The PFU out-
put power can be estimated based upon the number of
PFU outputs switching when driving an average fan-out
of two:
+ (0.053 mW/MHz/Branch) (# Branches)
+ (0.008 mW/MHz/PFU) (# PFUs)
+ (0.002 mW/MHz/PIO (# PIOs)]
For a quick estimate, the worst-case (typical circuit)
OR3L225B clock power = 13.5 mW/MHz
PPFU = 0.078 mW/MHz
The power dissipated in a PIC is the sum of the power
dissipated in the four PIOs in the PIC. This consists of
power dissipated by inputs and ac power dissipated by
outputs.The power dissipated in each PIO depends on
whether it is configured as an input, output, or input/
output. If a PIO is operating as an output, then there is
a power dissipation component for PIN, as well as
POUT. This is because the output feeds back to the
input.
For each PFU output that switches, 0.136 mW/MHz
needs to be multiplied times the frequency (in MHz)
that the output switches. Generally, this can be esti-
mated by using one-half the clock rate, multiplied by
some activity factor; for example, 20%.
The power dissipated by the clock generation circuitry
is based upon four parts: the fixed clock power, the
power/clock branch row or column, the clock power dis-
sipated in each PFU that uses this particular clock, and
the power from the subset of those PFUs that are con-
figured as synchronous memory. Therefore, the clock
power can be calculated for the four parts using the fol-
lowing equations.
The power dissipated by an input buffer is (VIH =
VDD – 0.3 V or higher)estimated as:
PIN = 0.09 mW/MHz
The ac power dissipation from an output or bidirec-
tional is estimated by the following:
2
POUT = (CL + 8.8 pF) × VDD × F Watts
where the unit for CL is farads, and the unit for F is Hz.
Lattice Semiconductor
37
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information
Table 24. 208-Pin SQFP2 Pinout
Pin
OR3L165B
Function
Pin
OR3L165B
Function
1
VSS
VSS
VSS
VSS
I/O
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
PL24D
PL24B
PL25D
PL27A
PL29D
PL30D
PL30A
PL32A
VSS
I/O
I/O-A13
I/O
2
3
PL1D
PL3D
VDD2
4
I/O-A14
I/O
I/O-A0/MPI_BE0
5
VDD2
I/O
6
PL6D
PL8D
PL9A
I/O
7
I/O-SECKLL
I/O-A15
VSS
I/O-A1/MPI_BE1
8
I/O-A2
9
PL10D
PL10B
PL10A
VDD
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
I/O
PCCLK
VSS
CCLK
VSS
I/O-A3
VDD
VSS
VSS
PL11D
PL11A
PL12D
PL12A
PL13D
PL13A
PL14D
PL14A
VSS
I/O
PB1A
PB3A
VDD2
I/O-A16
I/O
I/O
I/O
VDD2
I/O
I/O-A4
PB4D
PB5D
PB6D
PB7D
PB8D
PB9D
PB10D
VDD
I/O-A5
I/O-A17
I/O
I/O
I/O
I/O
I/O-A6
I/O
VSS
I/O
PECKL
PL15A
PL16C
PL16A
VDD
I/O-ECKL
I/O
I/O
VDD
I/O
I/O
PB11A
PB11D
PB12A
PB12D
PB13A
PB13D
PB14A
PB14D
VSS
I/O-A7/MPI_CLK
I/O
VDD
I/O
PL17D
VDD2
I/O
VDD2
I/O
I/O
PL18C
PL18A
VSS
I/O
I/O
I/O-A8/MPI_RW
VSS
I/O
I/O
PL19D
PL19A
PL20D
PL20A
PL21D
PL21A
PL22D
PL22A
VDD
VSS
I/O-A9/MPI_ACK
I/O
I/O
PB15A
PB15D
PB16B
PB16D
VSS
I/O
I/O
I/O
I/O-A10/MPI_BI
I/O
I/O
I/O
I/O
VSS
PECKB
PB17D
PB18B
PB18D
VSS
I/O-ECKB
I/O
I/O-A11/MPI_IRQ
VDD
I/O-A12
I/O
I/O
PL23D
PL23B
I/O
VSS
38
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 24. 208-Pin SQFP2 Pinout (continued)
Pin
OR3L165B
Function
Pin
OR3L165B
Function
85
86
VDD2
PB19D
PB20A
PB20D
PB21A
PB21D
PB22A
PB22D
VDD
VDD2
I/O
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
PR18D
PR17B
PR17D
VDD
I/O
I/O
87
I/O
I/O
88
I/O
VDD
I/O-ECKR
I/O
89
I/O-HDC
I/O
PECKR
PR16D
PR15B
PR15D
VSS
90
91
I/O
I/O
92
I/O
I/O
93
VDD
VSS
VDD2
I/O
94
PB23A
PB24D
PB25A
PB26D
PB27A
PB28A
PB29A
PB30D
PB32D
VSS
VDD2
I/O-LDC
I/O
95
PR14D
PR13A
PR13D
PR12A
PR12D
PR11A
PR11D
VDD
96
I/O
I/O
97
I/O
I/O
98
I/O-CS1
I/O
I/O-INIT
I/O
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
I/O
I/O
I/O
I/O
I/O
VDD
VSS
DONE
VSS
PR10A
PR10B
PR9B
I/O-CS0
I/O
PDONE
VSS
I/O
PRESETN
PPRGMN
PR32A
PR30A
PR29A
PR28A
PR25D
PR24A
VDD2
PR9D
PR8A
I/O
RESET
PRGM
I/O-M0
I/O
I/O-RD/MPI_STRB
PR6A
I/O
I/O
PR5A
I/O
PR4A
I/O-WR
I/O
I/O
PR3A
I/O-M1
I/O
PR2A
I/O
VSS
VSS
VDD2
I/O
PRD_CFGN
VSS
RD_CFG
PR23A
VDD
VSS
VDD
I/O-M2
I/O
VSS
VSS
PR22A
PR22D
PR21A
PR21D
PR20A
PR20D
PR19A
PR19D
VSS
PT32D
PT30A
PT28D
PT28A
PT27D
VDD2
I/O-SECKUR
I/O-RDY/RCLK/MPI_ALE
I/O
I/O
I/O
I/O
I/O-M3
I/O
I/O-D7
VDD2
I/O
I/O
PT25D
PT24D
PT23D
VDD
I/O
I/O
VSS
I/O-D6
VDD
PR18A
I/O
Lattice Semiconductor
39
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 24. 208-Pin SQFP2 Pinout (continued)
Pin
OR3L165B
Function
Pin
OR3L165B
Function
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
PT22D
PT22A
PT21D
PT21A
PT20D
PT20A
PT19D
PT19A
VSS
I/O
I/O
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
PT14A
PT13D
PT13A
PT12D
PT12A
PT11D
PT11A
VDD
I/O
I/O
I/O
I/O-D0/DIN
I/O
I/O-D5
I/O
I/O
I/O
I/O
I/O
I/O-DOUT
VDD
I/O-D4
VSS
PT10D
PT9A
I/O
PECKT
PT18B
PT17D
PT17A
VSS
I/O-ECKT
I/O
I/O
PT8A
I/O
I/O
PT7A
I/O-TDI
I/O
I/O-D3
VSS
PT6A
PT5A
I/O-TMS
I/O
PT16D
PT16C
VDD2
I/O
PT4A
I/O
PT3A
I/O
VDD2
I/O-D2
VSS
PT2D
I/O
PT15A
VSS
PT1A
I/O-TCK
VSS
VSS
PT14D
I/O-D1
PRD_DATA
RD_DATA/TDO
40
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 25. 240-Pin SQFP2 Pinout
Pin
OR3L165B
Function
Pin
OR3L165B
Function
1
VSS
VDD
VSS
VDD
I/O
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
PL22D
PL22A
VDD
I/O
2
I/O-A11/MPI_IRQ
VDD
3
PL1D
PL1A
4
I/O
PL23D
PL23B
PL24D
PL24B
PL24A
PL25D
PL26D
PL27A
VSS
I/O-A12
I/O
5
PL2D
PL3D
VSS
I/O
6
I/O
I/O-A0/MPI_BE0
7
VSS
VDD2
I/O
I/O-A13
I/O
8
VDD2
9
PL6D
PL7D
PL8D
PL9A
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
I/O
I/O
I/O-A14
VSS
I/O-A1/MPI_BE1
I/O-A2
PL10D
PL10B
PL10A
VDD
I/O
PL29D
PL30D
PL30A
PL32A
VSS
I/O
I/O
I/O
I/O-A3
I/O-SECKLL
I/O-A15
VSS
VDD
PL11D
PL11A
PL12D
PL12A
PL13D
PL13A
PL14D
PL14A
VSS
I/O
I/O
PCCLK
VDD
CCLK
VDD
I/O
I/O-A4
VSS
VSS
I/O-A5
VSS
VSS
I/O
PB1A
PB3A
VDD2
I/O-A16
I/O
I/O
I/O-A6
VDD2
I/O
VSS
PB4D
VSS
PECKL
PL15A
PL16C
PL16A
VDD
I/O-ECKL
VSS
I/O
PB5D
PB6D
PB7A
PB7D
PB8D
PB9A
PB9D
PB10D
VDD
I/O-A17
I/O
I/O
I/O-A7/MPI_CLK
I/O
VDD
I/O
PL17D
VDD2
I/O
I/O
VDD2
I/O
PL18C
PL18A
VSS
I/O
I/O
I/O-A8/MPI_RW
I/O
VSS
VDD
PL19D
PL19A
PL20D
PL20A
PL21D
PL21A
I/O-A9/MPI_ACK
PB11A
PB11D
PB12A
PB12D
PB13A
PB13D
I/O
I/O
I/O
I/O
I/O
I/O-A10/MPI_BI
I/O
I/O
I/O
I/O
I/O
Lattice Semiconductor
41
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 25. 240-Pin SQFP2 Pinout (continued)
Pin
OR3L165B
Function
Pin
OR3L165B
Function
83
84
PB14A
PB14D
VSS
I/O
I/O
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
PR31D
PR30A
PR29A
VSS
I/O
I/O
85
VSS
I/O
I/O
86
PB15A
PB15D
PB16B
PB16D
VSS
VSS
I/O
87
I/O
PR28A
PR27A
PR26A
PR26D
PR25D
PR24A
VDD2
88
I/O
I/O
89
I/O
I/O
90
VSS
I/O-ECKB
I/O
I/O
91
PECKB
PB17D
PB18B
PB18D
VSS
I/O-M1
I/O
92
93
I/O
VDD2
I/O
94
I/O
PR23A
VDD
95
VSS
VDD2
I/O
VDD
I/O-M2
I/O
96
VDD2
PR22A
PR22D
PR21A
PR21D
PR20A
PR20D
PR19A
PR19D
VSS
97
PB19D
PB20A
PB20D
PB21A
PB21D
PB22A
PB22D
VDD
98
I/O
I/O
99
I/O
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
I/O-HDC
I/O
I/O-M3
I/O
I/O
I/O
I/O
I/O
VDD
VSS
I/O
PB23A
PB24D
PB25A
PB26D
PB27A
PB27D
PB28A
PB28D
VSS
PR18A
PR18D
PR17B
PR17D
VDD
I/O-LDC
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O-ECKR
I/O
I/O-INIT
I/O
PECKR
PR16D
PR15B
PR15D
VSS
I/O
I/O
I/O
VSS
I/O
I/O
PB29A
PB30A
PB30D
PB32D
VSS
VSS
VDD2
I/O
I/O
VDD2
I/O
PR14D
PR13A
PR13D
PR12A
PR12D
PR11A
PR11D
VDD
I/O
I/O
VSS
DONE
VDD
VSS
I/O
PDONE
VDD
I/O-CS1
I/O
VSS
I/O
PRESETN
PPRGMN
PR32A
I/O
RESET
PRGM
I/O-M0
VDD
I/O-CS0
PR10A
42
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 25. 240-Pin SQFP2 Pinout (continued)
Pin
OR3L165B
Function
Pin
OR3L165B
Function
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
PT19D
PT19A
VSS
I/O
I/O-D4
VSS
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
PR10B
PR9B
PR9D
PR8A
PR7A
PR6A
PR5A
VSS
I/O
I/O
I/O
PECKT
PT18B
PT17D
PT17A
VSS
I/O-ECKT
I/O
I/O-RD/MPI_STRB
I/O
I/O
I/O
I/O-D3
VSS
I/O
VSS
PT16D
PT16C
VDD2
I/O
PR4A
PR3A
PR2A
PR1D
VSS
I/O-WR
I/O
I/O
VDD2
I/O-D2
VSS
I/O
PT15A
VSS
I/O
VSS
PT14D
PT14A
PT13D
PT13A
PT12D
PT12A
PT11D
PT11A
VDD
I/O-D1
I/O
PRD_CFGN
VSS
RD_CFG
VSS
I/O
VDD
VDD
I/O-D0/DIN
I/O
VSS
VSS
PT32D
PT31A
PT30D
PT30A
VSS
I/O-SECKUR
I/O
I/O
I/O
I/O
I/O-DOUT
VDD
I/O-RDY/RCLK/MPI_ALE
VSS
I/O
PT10D
PT9A
I/O
PT28D
PT28C
PT28A
PT27D
VDD2
I/O
I/O
PT8A
I/O
I/O
PT7A
I/O-TDI
I/O
I/O-D7
VDD2
I/O
PT6D
PT6A
I/O
PT25D
PT24D
PT23D
VDD
PT5D
PT5A
I/O
I/O
I/O-TMS
VSS
I/O-D6
VDD
I/O
VSS
PT4A
I/O
PT22D
PT22A
PT21D
PT21A
PT20D
PT20A
PT3A
I/O
I/O
PT2D
PT1A
I/O
I/O
I/O-TCK
VSS
I/O-D5
I/O
VSS
PRD_DATA
RD_DATA/TDO
I/O
Lattice Semiconductor
43
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 26. 352-Pin PBGA Pinout
Pin
OR3L165B
Function
Pin
OR3L165B
Function
B1
C2
C1
D2
D3
D1
E2
E4
E3
E1
F2
G4
F3
F1
G2
G1
G3
H2
J4
PL1D
PL1A
I/O
P2
P4
PL17D
VDD2
I/O
I/O
VDD2
PL2D
PL2A
I/O
P1
PL18C
PL18A
PL19D
PL19A
PL20D
PL20A
PL21D
PL21A
PL22D
PL22A
PL23D
PL23C
PL23B
PL23A
PL24D
PL24C
PL24B
PL24A
PL25D
PL25C
PL26D
PL27D
PL27A
PL28C
PL28B
PL28A
VDD2
I/O
I/O
N3
I/O-A8/MPI_RW
PL3D
PL3A
I/O-A0/MPI_BE0
R2
I/O-A9/MPI_ACK
I/O
P3
I/O
PL4D
PL4B
I/O
R1
I/O
I/O
T2
I/O-A10/MPI_BI
PL4A
I/O
R3
I/O
VDD2
VDD2
T1
I/O
PL5C
PL5B
I/O
R4
I/O
I/O
U2
I/O-A11/MPI_IRQ
PL6D
PL7D
PL7C
PL7B
I/O
T3
I/O-A12
I/O
I/O
U1
I/O
U4
I/O
I/O
V2
I/O
PL8D
PL9D
PL9C
PL9B
I/O-A1/MPI_BE1
U3
I/O
I/O
V1
I/O
I/O
W2
W1
V3
I/O-A13
I/O
H1
H3
J2
I/O
PL9A
I/O-A2
I/O
PL10D
PL10C
PL10B
PL10A
PL11D
PL11A
PL12D
PL12A
PL13D
PL13A
PL14D
PL14A
PECKL
PL15A
PL16C
PL16A
I/O
Y2
I/O
J1
I/O
W4
Y1
I/O
K2
J3
I/O
I/O-A3
I/O
I/O
W3
AA2
Y4
I/O-A14
I/O
K1
K4
L2
I/O
I/O
I/O
AA1
Y3
I/O
K3
L1
I/O-A4
I/O-A5
I/O
VDD2
I/O
AB2
AB1
AA3
AC2
AB4
AC1
AB3
AD2
PL29C
PL29A
PL30D
PL30C
PL30A
PL31A
PL32C
PL32B
M2
M1
L3
I/O
I/O
I/O
I/O-A6
I/O-ECKL
I/O
I/O
N2
M4
N1
M3
I/O-SECKLL
I/O
I/O
I/O
I/O-A7/MPI_CLK
I/O
44
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 26. 352-Pin PBGA Pinout (continued)
Pin
OR3L165B
Function
Pin
OR3L165B
Function
AC3
AD1
AF2
PL32A
PCCLK
PB1A
PB1B
PB2A
PB2D
PB3A
VDD2
I/O-A15
CCLK
I/O-A16
I/O
AE14
AC14
AF14
AD13
AE15
AD14
AF15
AE16
AD15
AF16
AC15
AE17
AD16
AF17
AC17
AE18
AD17
AF18
AE19
AF19
AD18
AE20
AC19
AF20
AD19
AE21
AC20
AF21
AD20
AE22
AF22
AD21
AE23
AC22
AF23
AD22
AE24
AD23
AF24
PECKB
PB17D
PB18B
PB18D
VDD2
I/O-ECKB
I/O
I/O
AE3
I/O
AF3
I/O
VDD2
I/O
AE4
I/O
PB19D
PB20A
PB20D
PB21A
PB21D
PB22A
PB22D
PB23A
PB23D
PB24A
PB24D
PB25A
PB26A
PB26C
PB26D
PB27A
PB27B
PB27C
PB27D
VDD2
AD4
AF4
I/O
I/O
VDD2
I/O
I/O
AE5
PB4A
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7D
PB8A
PB8D
PB9A
PB9D
PB10A
PB10D
PB11A
PB11D
PB12A
PB12D
PB13A
PB13D
PB14A
PB14D
PB15A
PB15D
PB16B
PB16D
I/O-HDC
I/O
AC5
AD5
AF5
I/O
I/O
I/O
I/O
I/O
AE6
I/O
I/O-LDC
I/O
AC7
AD6
AF6
I/O
I/O-A17
I/O
I/O
I/O
AE7
I/O
I/O
AF7
I/O
I/O
AD7
AE8
I/O
I/O
I/O
I/O
AC9
AF8
I/O
I/O-INIT
I/O
I/O
AD8
AE9
I/O
I/O
I/O
I/O
AF9
I/O
VDD2
I/O
AE10
AD9
AF10
AC10
AE11
AD10
AF11
AE12
AF12
AD11
AE13
AC12
AF13
AD12
I/O
PB28B
PB28C
PB28D
PB29A
PB29B
PB29D
PB30A
PB30B
PB30D
PB31A
PB31D
PB32C
PB32D
PDONE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DONE
Lattice Semiconductor
45
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 26. 352-Pin PBGA Pinout (continued)
Pin
OR3L165B
Function
Pin
OR3L165B
Function
AE26
AD25
AD26
AC25
AC24
AC26
AB25
AB23
AB24
AB26
AA25
Y23
PRESETN
PPRGMN
PR32A
PR31A
PR31D
PR30A
PR30D
PR29A
PR29B
PR29D
PR28A
PR28B
PR28C
PR27A
PR26A
PR26B
PR26D
PR25D
PR24A
PR24B
PR24C
VDD2
N26
P24
M25
N24
M26
L25
M24
L26
M23
K25
L24
K26
K23
J25
PR16D
PR15B
PR15D
VDD2
I/O
I/O
RESET
PRGM
I/O-M0
I/O
I/O
VDD2
I/O
I/O
PR14D
PR13A
PR13D
PR12A
PR12D
PR11A
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
I/O
I/O
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-CS0
I/O
AA24
AA26
Y25
I/O
I/O
I/O
I/O
K24
J26
I/O
Y26
I/O
I/O
Y24
I/O
H25
H26
J24
PR9B
I/O
W25
V23
I/O-M1
I/O
PR9C
I/O
PR9D
I/O
W26
W24
V25
I/O
G25
H23
G26
H24
F25
G23
F26
G24
E25
E26
F24
D25
E23
D26
E24
C25
D24
C26
A25
B24
PR8A
I/O-RD/MPI_STRB
I/O
PR7A
I/O
I/O
VDD2
I/O
PR7C
V26
PR23A
PR23B
PR23C
PR23D
PR22A
PR22D
PR21A
PR21D
PR20A
PR20D
PR19A
PR19D
PR18A
PR18D
PR17B
PR17D
PECKR
PR6A
I/O
U25
I/O
VDD2
VDD2
I/O
V24
I/O
PR5B
U26
I/O
PR5C
I/O
U23
I/O-M2
I/O
PR5D
I/O
T25
PR4A
I/O-WR
I/O
U24
I/O
PR4B
T26
I/O
PR4D
I/O
R25
I/O-M3
I/O
PR3A
I/O
R26
PR3D
I/O
T24
I/O
PR2A
I/O
P25
I/O
PR2D
I/O
R23
I/O
PR1A
I/O
P26
I/O
PR1D
I/O
R24
I/O
PRD_CFGN
PT32D
PT32A
RD_CFG
I/O-SECKUR
I/O
N25
I/O
N23
I/O-ECKR
46
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 26. 352-Pin PBGA Pinout (continued)
Pin
OR3L165B
Function
Pin
OR3L165B
Function
A24
B23
C23
A23
B22
D22
C22
A22
B21
D20
C21
A21
B20
A20
C20
B19
D18
A19
C19
B18
A18
B17
C18
A17
D17
B16
C17
A16
B15
A15
C16
B14
D15
A14
C15
B13
D13
A13
C14
PT31B
PT31A
PT30D
PT30A
PT29D
PT29C
PT29A
PT28D
PT28C
PT28B
PT28A
PT27D
PT27C
PT27B
PT27A
VDD2
I/O
B12
C13
A12
B11
C12
A11
D12
B10
C11
A10
D10
B9
PT14D
PT14A
PT13D
PT13A
PT12D
PT12A
PT11D
PT11A
PT10D
PT10A
PT9D
PT9A
PT8D
PT8A
PT7D
PT7A
PT6D
PT6C
PT6B
VDD2
I/O-D1
I/O
I/O
I/O
I/O
I/O-RDY/RCLK/MPI_ALE
I/O-D0/DIN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-DOUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D7
I/O
I/O
C10
A9
I/O
I/O
I/O
I/O
B8
I/O
VDD2
I/O
A8
I/O-TDI
I/O
PT26C
PT26B
PT25D
PT24D
PT24A
PT23D
PT23A
PT22D
PT22A
PT21D
PT21A
PT20D
PT20A
PT19D
PT19A
PECKT
PT18B
PT17D
PT17A
PT16D
PT16C
VDD2
C9
I/O
B7
I/O
I/O
D8
I/O
I/O
A7
VDD2
I/O
I/O
C8
PT5D
PT5C
PT5B
PT5A
PT4D
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2A
PT1D
PT1A
PRD_DATA
VSS
I/O-D6
I/O
B6
I/O
D7
I/O
I/O
A6
I/O-TMS
I/O
I/O
C7
I/O
B5
I/O
I/O-D5
I/O
A5
I/O
C6
I/O
I/O
B4
I/O
I/O
D5
I/O
I/O-D4
I/O-ECKT
I/O
A4
I/O
C5
I/O
B3
I/O
I/O
C4
I/O-TCK
RD_DATA/TDO
VSS
I/O-D3
I/O
A3
A1
I/O
A2
VSS
VSS
VDD2
I/O-D2
A26
AC13
VSS
VSS
PT15A
VSS
VSS
Lattice Semiconductor
47
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 26. 352-Pin PBGA Pinout (continued)
Pin
OR3L165B
Function
Pin
OR3L165B
Function
AC18
AC23
AC4
AC8
AD24
AD3
AE1
AE2
AE25
AF1
AF25
AF26
B2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N11
N12
N13
N14
N15
N16
P11
P12
P13
P14
P15
P16
R11
R12
R13
R14
R15
R16
T11
T12
T13
T14
T15
T16
AA23
AA4
AC11
AC16
AC21
AC6
D11
D16
D21
D6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B25
B26
C24
C3
D14
D19
D23
D4
D9
H4
J23
N4
P23
V4
W23
L11
L12
L13
L14
L15
L16
M11
M12
M13
M14
M15
M16
F23
F4
L23
L4
T23
T4
48
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout
Pin
OR3L165B
OR3L225B
Function
E4
D3
D2
D1
F4
E3
E2
E1
F3
F2
F1
H4
G3
G2
G1
J4
PRD_CFGN
PR1D
PR1A
PRD_CFGN
PR1D
PR1A
RD_CFG
I/O
I/O
PR2D
PR2A
PR2D
PR2A
I/O
I/O
PR3D
PR3C
PR3B
PR3D
PR3C
PR3B
I/O
I/O
I/O
PR3A
PR3A
I/O
PR4D
PR4C
PR4B
PR4D
PR4C
PR4B
I/O
I/O
I/O
PR4A
PR4A
I/O-WR
I/O
PR5D
PR5C
PR5B
PR5D
PR5C
PR5B
I/O
I/O
H3
H2
J3
VDD2
VDD2
VDD2
I/O
PR6A
PR6A
PR7C
PR7A
PR7C
PR7A
I/O
K4
J2
I/O
PR8A
PR8A
I/O-RD/MPI_STRB
J1
PR9D
PR9C
PR9B
PR9D
PR9A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K3
K2
K1
L3
PR10D
PR10C
PR10A
PR11D
PR11C
PR11A
PR12D
PR12A
PR13D
PR13A
PR14D
PR14A
PR15A
PR16D
PR16A
VDD2
PR9A
PR10D
PR10C
PR10B
PR10A
PR11D
PR11A
PR12D
PR12A
PR13D
PR13C
PR13A
PR14D
PR14C
VDD2
M4
L2
L1
I/O-CS0
I/O
M3
N4
M2
N3
N2
P4
N1
P3
P2
P1
R3
R2
I/O
I/O
I/O-CS1
I/O
I/O
I/O
I/O
I/O
VDD2
I/O
PR15D
PR15B
PR18D
PR18B
I/O
Lattice Semiconductor
49
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
R1
T2
PR16D
PECKR
PR17D
PR17B
PR18D
PR18A
PR19D
PR19B
PR19A
PR20D
PR20A
PR21D
PR21B
PR21A
PR22D
PR22A
PR23D
PR23C
PR23B
PR23A
VDD2
PR19D
PECKR
PR20D
PR20B
PR21D
PR21A
PR22D
PR23D
PR23A
PR24D
PR25A
PR26D
PR26B
PR26A
PR27D
PR27A
PR28D
PR28C
PR28B
PR28A
VDD2
I/O
I/O-ECKR
I/O
T4
T3
I/O
U1
I/O
U2
I/O
U3
I/O
V1
I/O
V2
I/O
V3
I/O
W1
V4
I/O-M3
I/O
W2
W3
Y2
I/O
I/O
I/O
W4
Y3
I/O-M2
I/O
AA1
AA2
Y4
I/O
I/O
I/O
AA3
AB1
AB2
AB3
AC1
AC2
AB4
AC3
AD2
AD3
AC4
AE1
AE2
AE3
AD4
AF1
AF2
AF3
AG1
AG2
AG3
VDD2
I/O
PR24C
PR24B
PR24A
PR25D
PR26D
PR26B
PR26A
PR27A
PR28C
PR28B
PR28A
PR29D
PR29C
PR29B
PR29A
PR30D
PR30C
PR30B
VDD2
PR29A
PR30D
PR30A
PR31D
PR32D
PR32B
PR32A
PR33A
PR34C
PR34B
PR34A
PR35D
PR35C
PR35B
PR35A
PR36D
PR36C
PR36B
VDD2
I/O
I/O
I/O-M1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD2
I/O
PR31D
PR37D
50
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AF4
AH1
AH2
AH3
AG4
AH5
AJ4
PR31A
PR32B
PR32A
PPRGMN
PRESETN
PDONE
PB32D
PB32C
PB31D
PB31A
PB30D
PB30C
PB30B
PB30A
PB29D
PB29C
PB29B
PB29A
PB28D
PB28C
PB28B
VDD2
PR37A
PR38B
PR38A
PPRGMN
PRESETN
PDONE
PB38D
PB38C
PB37D
PB37A
PB36D
PB36C
PB36B
PB36A
PB35D
PB35C
PB35B
PB35A
PB34D
PB34C
PB34B
VDD2
I/O
I/O
I/O-M0
PRGM
RESET
DONE
I/O
AK4
AL4
I/O
I/O
AH6
AJ5
I/O
I/O
AK5
AL5
I/O
I/O
AJ6
I/O
AK6
AL6
I/O
I/O
AH8
AJ7
I/O
I/O
AK7
AL7
I/O
I/O
AH9
AJ8
I/O
VDD2
I/O
AK8
AJ9
PB27D
PB27C
PB27B
PB27A
PB26D
PB26C
PB26A
PB25A
PB24D
PB24A
PB23D
PB23A
PB22D
PB22B
PB22A
PB21D
PB21B
PB21A
PB20D
PB33D
PB33C
PB33B
PB33A
PB32D
PB32C
PB32A
PB31A
PB30D
PB30A
PB29D
PB29A
PB28D
PB27D
PB27A
PB26D
PB25D
PB25A
PB24D
I/O
AH10
AK9
AL9
I/O
I/O-INIT
I/O
AJ10
AK10
AL10
AJ11
AH12
AK11
AL11
AJ12
AH13
AK12
AJ13
AK13
AH14
AL13
I/O
I/O
I/O
I/O
I/O
I/O
I/O-LDC
I/O
I/O
I/O
I/O
I/O
I/O-HDC
I/O
Lattice Semiconductor
51
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AJ14
AK14
AL14
AJ15
AK15
AL15
AK16
AH16
AJ16
AL17
AK17
AJ17
AL18
AK18
AJ18
AL19
AH18
AK19
AJ19
AK20
AH19
AJ20
AL21
AK21
AH20
AJ21
AL22
AK22
AJ22
AL23
AK23
AH22
AJ23
AK24
AJ24
AH23
AL25
AK25
AJ25
AH24
AL26
PB20B
PB20A
PB19D
VDD2
PB24B
PB24A
PB23D
VDD2
I/O
I/O
I/O
VDD2
I/O
PB18D
PB18B
PB17D
PECKB
PB16D
PB16B
PB15D
PB15A
PB14D
PB14B
PB14A
PB13D
PB13A
PB12D
PB12B
PB12A
PB11D
PB11B
VDD2
PB22D
PB21D
PB20D
PECKB
PB19D
PB18D
PB17D
PB17A
PB16D
PB15D
PB15A
PB14D
PB13A
PB12D
PB12B
PB12A
PB11D
PB11B
VDD2
I/O
I/O
I/O-ECKB
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD2
I/O
PB10D
PB10A
PB9D
PB10D
PB10A
PB9D
I/O
I/O
PB9A
PB9A
I/O
PB8D
PB8D
I/O
PB8A
PB8A
I/O
PB7D
PB7D
I/O
PB7A
PB7A
I/O
PB6D
PB6D
I/O
PB6C
PB6C
I/O
PB6B
PB6B
I/O
PB6A
PB6A
I/O
PB5D
PB5D
I/O-A17
I/O
PB5C
PB5C
PB5B
PB5B
I/O
PB5A
PB5A
I/O
PB4D
PB4D
I/O
PB4C
PB4C
I/O
52
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AK26
AJ26
AL27
AK27
AJ27
AH26
AL28
AK28
AJ28
AH27
AG28
AH29
AH30
AH31
AF28
AG29
AG30
AG31
AF29
AF30
AF31
AD28
AE29
AE30
AE31
AC28
AD29
AD30
AC29
AB28
AC30
AC31
AB29
AB30
AB31
AA29
Y28
PB4B
PB4A
PB4B
PB4A
I/O
I/O
VDD2
VDD2
VDD2
I/O
PB3C
PB3C
PB3B
PB3B
I/O
PB3A
PB3A
I/O
PB2D
PB2D
I/O
PB2A
PB2A
I/O
PB1B
PB1B
I/O
PB1A
PB1A
I/O-A16
CCLK
I/O-A15
I/O
PCCLK
PL32A
PL32B
PL32C
PL31A
PL30A
PL30B
PL30C
PL30D
PL29A
PL29B
PL29C
VDD2
PCCLK
PL38A
PL38B
PL38C
PL37A
PL36A
PL36B
PL36C
PL36D
PL35A
PL35B
PL35C
VDD2
I/O
I/O
I/O-SECKLL
I/O
I/O
I/O
I/O
I/O
I/O
VDD2
I/O
PL28A
PL28B
PL28C
PL27A
PL27D
PL26D
PL25C
PL25D
PL24A
PL24B
PL24C
PL24D
PL23A
PL23B
PL23C
PL23D
PL22A
PL22D
PL34A
PL34B
PL34C
PL33A
PL33D
PL32D
PL31C
PL31D
PL30A
PL30B
PL30C
PL30D
PL29C
PL29D
PL28B
PL28D
PL27A
PL27D
I/O
I/O
I/O-A14
I/O
I/O
I/O
I/O
I/O
I/O-A13
I/O
I/O
I/O
I/O
AA30
AA31
Y29
I/O
I/O-A12
I/O-A11/MPI_IRQ
I/O
W28
Lattice Semiconductor
53
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
Y30
W29
W30
V28
W31
V29
V30
V31
U29
U30
U31
T30
T28
T29
R31
R30
R29
P31
P30
P29
N31
P28
N30
N29
M30
N28
M29
L31
L30
M28
L29
K31
K30
K29
J31
PL21A
PL21C
PL21D
PL20A
PL20C
PL20D
PL19A
PL19C
PL19D
PL18A
PL18C
VDD2
PL26A
PL26C
PL26D
PL25A
PL24A
PL24D
PL23A
PL22A
PL22D
PL21A
PL21C
VDD2
I/O
I/O
I/O
I/O-A10/MPI_BI
I/O
I/O
I/O
I/O
I/O-A9/MPI_ACK
I/O-A8/MPI_RW
I/O
VDD2
I/O
PL17D
PL16A
PL16C
PL15A
PECKL
PL14A
PL14D
PL13A
PL13C
PL13D
PL12A
PL12C
PL12D
PL11A
PL11C
VDD2
PL20D
PL19A
PL19C
PL18A
PECKL
PL17A
PL16D
PL15A
PL14A
PL14D
PL13A
PL13C
PL13D
PL12A
PL12C
VDD2
I/O-A7/MPI_CLK
I/O
I/O
I/O-ECKL
I/O-A6
I/O
I/O
I/O
I/O-A5
I/O-A4
I/O
I/O
I/O
I/O
VDD2
I/O-A3
I/O
PL10A
PL10B
PL10C
PL10D
PL9A
PL11A
PL11D
PL10A
PL10D
PL9A
I/O
I/O
I/O-A2
I/O
PL9B
PL9B
PL9C
PL9C
I/O
J30
PL9D
PL9D
I/O
K28
J29
PL8D
PL8D
I/O-A1/MPI_BE1
PL7B
PL7B
I/O
I/O
I/O
I/O
H30
H29
J28
PL7C
PL7C
PL7D
PL7D
PL6D
PL6D
54
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
G31
G30
G29
H28
F31
F30
F29
E31
E30
E29
F28
D31
D30
D29
E28
D27
C28
B28
A28
D26
C27
B27
A27
C26
B26
A26
D24
C25
B25
A25
D23
C24
B24
C23
D22
B23
A23
C22
B22
A22
C21
PL5B
PL5C
VDD2
PL4A
PL4B
PL4C
PL4D
PL3A
PL3B
PL3C
PL3D
PL2A
PL2D
PL1A
PL1D
PRD_DATA
PT1A
PT1D
PT2A
PT2D
PT3A
PT3B
PT3C
PT3D
PT4A
PT4B
PT4C
PT4D
PT5A
PT5B
PT5C
PT5D
VDD2
PT6B
PT6C
PT6D
PT7A
PT7D
PT8A
PT8D
PT9A
PL5B
PL5C
VDD2
PL4A
PL4B
PL4C
PL4D
PL3A
PL3B
PL3C
PL3D
PL2A
PL2D
PL1A
PL1D
PRD_DATA
PT1A
PT1D
PT2A
PT2D
PT3A
PT3B
PT3C
PT3D
PT4A
PT4B
PT4C
PT4D
PT5A
PT5B
PT5C
PT5D
VDD2
PT6B
PT6C
PT6D
PT7A
PT7D
PT8A
PT8D
PT9A
I/O
I/O
VDD2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A0/MPI_BE0
I/O
I/O
I/O
I/O
RD_DATA/TDO
I/O-TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TMS
I/O
I/O
I/O
VDD2
I/O
I/O
I/O
I/O-TDI
I/O
I/O
I/O
I/O
Lattice Semiconductor
55
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
D20
B21
A21
C20
D19
B20
C19
B19
D18
A19
C18
B18
A18
C17
B17
A17
B16
D16
C16
A15
B15
C15
A14
B14
C14
A13
D14
B13
C13
B12
D13
C12
A11
B11
D12
C11
A10
B10
C10
A9
PT9D
PT10A
PT10D
PT11A
PT11D
PT12A
PT12C
PT12D
PT13A
PT13C
PT13D
PT14A
PT14C
PT14D
PT15A
VDD2
PT9D
PT10A
PT10D
PT11A
PT12D
PT13A
PT14A
PT14D
PT15A
PT15C
PT15D
PT16A
PT16C
PT16D
PT17A
VDD2
I/O
I/O
I/O
I/O-DOUT
I/O
I/O
I/O
I/O
I/O-D0/DIN
I/O
I/O
I/O
I/O
I/O-D1
I/O-D2
VDD2
I/O
PT16C
PT16D
PT17A
PT17D
PT18B
PECKT
PT19A
PT19B
PT19D
PT20A
PT20B
PT20D
PT21A
PT21B
VDD2
PT18D
PT19D
PT20A
PT21A
PT22A
PECKT
PT23A
PT23D
PT24D
PT25A
PT25D
PT26D
PT27A
PT27B
VDD2
I/O
I/O-D3
I/O
I/O
I/O-ECKT
I/O-D4
I/O
I/O
I/O
I/O
I/O
I/O-D5
I/O
VDD2
I/O
PT22A
PT22D
PT23A
PT23D
PT24A
PT24D
PT25D
PT26B
PT26C
VDD2
PT28A
PT28D
PT29A
PT29D
PT30A
PT30D
PT31D
PT32B
PT32C
VDD2
I/O
I/O
I/O-D6
I/O
I/O
I/O
I/O
I/O
B9
VDD2
56
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
D10
C9
PT27A
PT27B
PT27C
PT27D
PT28A
PT28B
PT28C
PT28D
PT29A
PT29B
PT29C
PT29D
PT30A
PT30B
PT30C
PT30D
PT31A
PT31B
PT32A
PT32D
VSS
PT33A
PT33B
PT33C
PT33D
PT34A
PT34B
PT34C
PT34D
PT35A
PT35B
PT35C
PT35D
PT36A
PT36B
PT36C
PT36D
PT37A
PT37B
PT38A
PT38D
VSS
I/O
I/O
B8
I/O
C8
I/O-D7
D9
I/O
A7
I/O
B7
I/O
C7
I/O
D8
I/O
A6
I/O
B6
I/O
C6
I/O
A5
I/O-RDY/RCLK/MPI_ALE
B5
I/O
I/O
C5
D6
I/O
A4
I/O
B4
I/O
C4
I/O
D5
I/O-SECKUR
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A12
A16
A2
VSS
VSS
VSS
VSS
A20
A24
A29
A3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A30
A8
VSS
VSS
VSS
VSS
AD1
AD31
AJ1
AJ2
AJ30
AJ31
AK1
AK29
AK3
AK31
AL12
AL16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Lattice Semiconductor
57
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AL2
AL20
AL24
AL29
AL3
AL30
AL8
B1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B29
B3
B31
C1
C2
C30
C31
H1
H31
M1
M31
T1
T31
Y1
Y31
A1
A31
AA28
AA4
AE28
AE4
AH11
AH15
AH17
AH21
AH25
AH28
AH4
AH7
AJ29
AJ3
AK2
AK30
58
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 27. 432-Pin EBGA Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AL1
AL31
B2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B30
C29
C3
D11
D15
D17
D21
D25
D28
D4
D7
G28
G4
L28
L4
R28
R4
U28
U4
Lattice Semiconductor
59
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout
Pin
OR3L165B
OR3L225B
Function
D1
E2
E1
F4
F3
F2
F1
G5
G4
G2
G1
H5
H4
H2
H1
J5
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10A
PL11D
PL11A
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A0/MPI_BE0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J4
J3
J2
J1
K5
K4
K3
K2
K1
L5
I/O-A1/MPI_BE1
L4
I/O
I/O
L2
L1
I/O
M5
M4
M2
M1
N5
N4
N3
N2
N1
P5
P4
P3
P2
P1
I/O
I/O
I/O
I/O-A2
I/O
I/O
I/O
I/O-A3
I/O
I/O
I/O
I/O
I/O
I/O
60
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
R5
R4
PL12A
PL13D
PL13C
PL13B
PL14D
PL14C
PL14B
PL14A
PECKL
PL15C
PL15A
PL16C
PL16A
PL17D
PL18C
PL18A
PL19D
PL19C
PL19B
PL19A
PL20D
PL20C
PL20B
PL20A
PL21D
PL21C
PL21B
PL21A
PL22D
PL22C
PL22B
PL22A
PL23D
PL23C
PL23A
PL24D
PL24C
PL24B
PL24A
PL25D
PL25C
PL25B
PL25A
PL13A
PL14D
PL14A
PL15D
PL16D
PL16A
PL17D
PL17A
PECKL
PL18C
PL18A
PL19C
PL19A
PL20D
PL21C
PL21A
PL22D
PL22A
PL23D
PL23A
PL24D
PL24A
PL25D
PL25A
PL26D
PL26C
PL26B
PL26A
PL27D
PL27C
PL27B
PL27A
PL28D
PL28B
PL29C
PL30D
PL30C
PL30B
PL30A
PL31D
PL31C
PL31B
PL31A
I/O-A4
I/O-A5
R2
I/O
R1
I/O
T5
I/O
T4
I/O
T2
I/O
T1
I/O-A6
U5
I/O-ECKL
U4
I/O
U3
I/O
U2
I/O
I/O-A7/MPI_CLK
I/O
U1
V1
V2
I/O
V3
I/O-A8/MPI_RW
V4
I/O-A9/MPI_ACK
V5
I/O
I/O
I/O
I/O
I/O
I/O
W1
W2
W4
W5
Y1
Y2
I/O-A10/MPI_B1
Y4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Y5
AA1
AA2
AA3
AA4
AA5
AB1
AB2
AB3
AB4
AB5
AC1
AC2
AC4
AC5
AD1
AD2
AD4
I/O-A11/MPI_IRQ
I/O-A12
I/O
I/O
I/O
I/O
I/O-A13
I/O
I/O
I/O
I/O
I/O
Lattice Semiconductor
61
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AD5
AE1
AE2
AE3
AE4
AE5
AF1
AF2
AF3
AF4
AF5
AG1
AG2
AG4
AG5
AH1
AH2
AH4
AH5
AJ1
AJ2
AJ3
AJ4
AK1
AK2
AL1
AP4
AN5
AP5
AL6
AM6
AN6
AP6
AK7
AL7
AN7
AP7
AK8
AL8
AN8
AP8
AK9
AL9
PL26D
PL26C
PL26B
PL26A
PL27D
PL27C
PL27B
PL27A
PL28D
PL28C
PL28B
PL28A
PL29C
PL29B
PL29A
PL30D
PL30C
PL30B
PL30A
PL31D
PL31C
PL31A
PL32C
PL32B
PL32A
PCCLK
PB1A
PL32D
PL32C
PL32B
PL32A
PL33D
PL33C
PL33B
PL33A
PL34D
PL34C
PL34B
PL34A
PL35C
PL35B
PL35A
PL36D
PL36C
PL36B
PL36A
PL37D
PL37C
PL37A
PL38C
PL38B
PL38A
PCCLK
PB1A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-SECKLL
I/O
I/O
I/O
I/O
I/O
I/O-A15
CCLK
I/O-A16
I/O
PB1B
PB1B
PB1C
PB1D
PB2A
PB1C
PB1D
PB2A
I/O
I/O
I/O
PB2D
PB3A
PB2D
PB3A
I/O
I/O
PB3B
PB3B
I/O
PB3C
PB4A
PB3C
PB4A
I/O
I/O
PB4B
PB4B
I/O
PB4C
PB4D
PB5A
PB4C
PB4D
PB5A
I/O
I/O
I/O
PB5B
PB5B
I/O
PB5C
PB5D
PB5C
PB5D
I/O
I/O-A17
62
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AM9
AN9
PB6A
PB6B
PB6A
PB6B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-ECKB
I/O
I/O
AP9
PB6C
PB6C
AK10
AL10
AM10
AN10
AP10
AK11
AL11
AN11
AP11
AK12
AL12
AN12
AP12
AK13
AL13
AM13
AN13
AP13
AK14
AL14
AM14
AN14
AP14
AK15
AL15
AN15
AP15
AK16
AL16
AN16
AP16
AK17
AL17
AM17
AN17
AP17
AP18
AN18
AM18
AL18
PB6D
PB6D
PB7A
PB7A
PB7B
PB7B
PB7C
PB7C
PB7D
PB7D
PB8A
PB8A
PB8B
PB8B
PB8C
PB8C
PB8D
PB8D
PB9A
PB9A
PB9B
PB9B
PB9C
PB9C
PB9D
PB9D
PB10A
PB10B
PB10C
PB10D
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
PB14C
PB14D
PB15B
PB15D
PB16A
PB16B
PB16D
PECKB
PB17D
PB18B
PB10A
PB10B
PB10C
PB10D
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13D
PB14A
PB14D
PB15A
PB15D
PB16A
PB16D
PB17B
PB17D
PB18A
PB18D
PB19D
PECKB
PB20D
PB21D
Lattice Semiconductor
63
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AK18
AP19
AN19
AL19
AK19
AP20
AN20
AL20
AK20
AP21
AN21
AM21
AL21
AK21
AP22
AN22
AM22
AL22
AK22
AP23
AN23
AL23
AK23
AP24
AN24
AL24
AK24
AP25
AN25
AM25
AL25
AK25
AP26
AN26
AM26
AL26
AK26
AP27
AN27
AL27
AK27
AP28
AN28
PB18D
PB19B
PB19C
PB19D
PB20A
PB20B
PB20C
PB20D
PB21A
PB21B
PB21C
PB21D
PB22A
PB22B
PB22C
PB23A
PB23B
PB23C
PB23D
PB24A
PB24B
PB24C
PB24D
PB25A
PB25B
PB25C
PB25D
PB26A
PB26B
PB26C
PB26D
PB27A
PB27B
PB27C
PB27D
PB28B
PB28C
PB28D
PB29A
PB29B
PB29C
PB29D
PB30A
PB22D
PB23B
PB23C
PB23D
PB24A
PB24B
PB24C
PB24D
PB25A
PB25D
PB26A
PB26D
PB27A
PB27D
PB28A
PB29A
PB29B
PB29C
PB29D
PB30A
PB30B
PB30C
PB30D
PB31A
PB31B
PB31C
PB31D
PB32A
PB32B
PB32C
PB32D
PB33A
PB33B
PB33C
PB33D
PB34B
PB34C
PB34D
PB35A
PB35B
PB35C
PB35D
PB36A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-HDC
I/O
I/O
I/O
I/O
I/O
I/O
I/O-LDC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-INIT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
64
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AL28
AK28
AP29
AN29
AM29
AL29
AP30
AN30
AP31
AL34
AK33
AK34
AJ31
AJ32
AJ33
AJ34
AH30
AH31
AH33
AH34
AG30
AG31
AG33
AG34
AF30
AF31
AF32
AF33
AF34
AE30
AE31
AE32
AE33
AE34
AD30
AD31
AD33
AD34
AC30
AC31
AC33
AC34
AB30
PB30B
PB30C
PB30D
PB31A
PB31D
PB32A
PB32C
PB32D
PDONE
PRESETN
PPRGMN
PR32A
PR32B
PR31A
PR31D
PR30B
PR30C
PR30D
PR29A
PR29B
PR29C
PR29D
PR28A
PR28B
PR28C
PR28D
PR27A
PR27B
PR27C
PR27D
PR26A
PR26B
PR26C
PR26D
PR25A
PR25B
PR25C
PR25D
PR24A
PR24B
PR24C
PR23A
PR23B
PB36B
PB36C
PB36D
PB37A
PB37D
PB38A
PB38C
PB38D
PDONE
PRESETN
PPRGMN
PR38A
PR38B
PR37A
PR37D
PR36B
PR36C
PR36D
PR35A
PR35B
PR35C
PR35D
PR34A
PR34B
PR34C
PR34D
PR33A
PR33B
PR33C
PR33D
PR32A
PR32B
PR32C
PR32D
PR31A
PR31B
PR31C
PR31D
PR30A
PR30D
PR29A
PR28A
PR28B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DONE
RESET
PRGM
I/O-M0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O
I/O
I/O
I/O
Lattice Semiconductor
65
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AB31
AB32
AB33
AB34
AA30
AA31
AA32
AA33
AA34
Y30
Y31
Y33
Y34
W30
W31
W33
W34
V30
V31
V32
V33
V34
U34
U33
U32
U31
U30
T34
PR23C
PR23D
PR22A
PR22B
PR22C
PR22D
PR21A
PR21B
PR21C
PR21D
PR20A
PR20B
PR20C
PR20D
PR19A
PR19B
PR19C
PR18A
PR18B
PR18D
PR17B
PR17D
PECKR
PR16D
PR15B
PR15D
PR14B
PR14C
PR14D
PR13A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR10A
PR10B
PR10C
PR28C
PR28D
PR27A
PR27B
PR27C
PR27D
PR26A
PR26B
PR26C
PR26D
PR25A
PR25D
PR24A
PR24D
PR23A
PR23D
PR22B
PR21A
PR21B
PR21D
PR20B
PR20D
PECKR
PR19D
PR18B
PR18D
PR17D
PR16A
PR16D
PR15A
PR15D
PR14A
PR14D
PR13A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR11A
PR11C
PR11D
I/O
I/O
I/O-M2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-ECKR
I/O
I/O
I/O
I/O
I/O
T33
I/O
T31
I/O
T30
I/O
R34
R33
R31
R30
P34
P33
P32
P31
P30
N34
N33
N32
I/O
I/O
I/O-CS1
I/O
I/O
I/O
I/O
I/O
I/O
I/O-CS0
I/O
I/O
66
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
N31
N30
M34
M33
M31
M30
L34
L33
L31
L30
K34
K33
K32
K31
K30
J34
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PR2A
PR2B
PR2D
PR1A
PR1B
PR1D
PRD_CFGN
PT32D
PT32C
PT32A
PT31D
PT31B
PT31A
PT30D
PT30C
PR10A
PR10C
PR10D
PR9A
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PR2A
PR2B
PR2D
PR1A
PR1B
PR1D
PRD_CFGN
PT38D
PT38C
PT38A
PT37D
PT37B
PT37A
PT36D
PT36C
I/O
I/O
I/O
I/O
I/O
I/O-RD/MPI_STRB
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J33
J32
J31
J30
H34
H33
H31
H30
G34
G33
G31
G30
F34
F33
F32
F31
E34
E33
D34
A31
B30
A30
D29
C29
B29
A29
E28
I/O-WR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RD_CFG
I/O-SECKUR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Lattice Semiconductor
67
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
D28
B28
A28
E27
D27
B27
A27
E26
D26
C26
B26
A26
E25
D25
C25
B25
A25
E24
D24
B24
A24
E23
D23
B23
A23
E22
D22
C22
B22
A22
E21
D21
C21
B21
A21
E20
D20
B20
A20
E19
D19
B19
A19
PT30B
PT30A
PT29D
PT29C
PT29B
PT29A
PT28D
PT28C
PT28B
PT28A
PT27D
PT27C
PT27B
PT27A
PT26C
PT26B
PT26A
PT25D
PT25C
PT25B
PT25A
PT24D
PT24C
PT24B
PT24A
PT23D
PT23C
PT23B
PT23A
PT22D
PT22C
PT22B
PT22A
PT21C
PT21B
PT21A
PT20D
PT20C
PT20B
PT20A
PT19D
PT19C
PT19B
PT36B
PT36A
PT35D
PT35C
PT35B
PT35A
PT34D
PT34C
PT34B
PT34A
PT33D
PT33C
PT33B
PT33A
PT32C
PT32B
PT32A
PT31D
PT31C
PT31B
PT31A
PT30D
PT30C
PT30B
PT30A
PT29D
PT29C
PT29B
PT29A
PT28D
PT28C
PT28B
PT28A
PT27C
PT27B
PT27A
PT26D
PT26A
PT25D
PT25A
PT24D
PT24A
PT23D
I/O
I/O-RDY/RCLK/MPI_ALE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
68
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
E18
D18
C18
B18
A18
A17
B17
C17
D17
E17
A16
B16
D16
E16
A15
B15
D15
E15
A14
B14
C14
D14
E14
A13
B13
C13
D13
E13
A12
B12
D12
E12
A11
B11
D11
E11
A10
B10
C10
D10
E10
A9
PT19A
PECKT
PT17D
PT17C
PT17A
PT16D
PT16C
PT15A
PT14D
PT14C
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10C
PT10B
PT10A
PT9D
PT23A
PECKT
PT21A
PT20D
PT20A
PT19D
PT18D
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
PT15B
PT15A
PT14D
PT14A
PT13D
PT13A
PT12D
PT12A
PT11D
PT11A
PT10C
PT10B
PT10A
PT9D
I/O-D4
I/O-ECKT
I/O
I/O
I/O-D3
I/O
I/O
I/O-D2
I/O-D1
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D0/DIN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-DOUT
I/O
I/O
I/O
I/O
PT9C
PT9C
I/O
PT9B
PT9B
I/O
PT9A
PT9A
I/O
PT8D
PT8D
I/O
PT8C
PT8C
I/O
PT8B
PT8B
I/O
PT8A
PT8A
I/O
PT7D
PT7D
I/O
PT7C
PT7C
I/O
PT7B
PT7B
I/O
PT7A
PT7A
I/O-TDI
I/O
PT6D
PT6D
PT6C
PT6C
I/O
PT6B
PT6B
I/O
B9
PT5D
PT5D
I/O
Lattice Semiconductor
69
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
C9
D9
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2A
PT1D
PT1C
PT1A
PRD_DATA
VSS
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2A
PT1D
PT1C
PT1A
PRD_DATA
VSS
I/O
I/O
E9
I/O-TMS
I/O
A8
B8
I/O
D8
I/O
E8
I/O
A7
I/O
B7
I/O
D7
I/O
E7
I/O
A6
I/O
B6
I/O
C6
I/O
D6
I/O
A5
I/O
B5
I/O-TCK
RD_DATA/TDO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A4
A1
A2
VSS
VSS
A33
A34
B1
VSS
VSS
VSS
VSS
VSS
VSS
B2
VSS
VSS
B33
B34
C3
VSS
VSS
VSS
VSS
VSS
VSS
C8
VSS
VSS
C12
C16
C19
C23
C27
C32
D4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D31
H3
VSS
VSS
VSS
VSS
H32
M3
M32
N13
N14
N15
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
70
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
N20
N21
N22
P13
P14
P15
P20
P21
P22
R13
R14
R15
R20
R21
R22
T3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T16
T17
T18
T19
T32
U16
U17
U18
U19
V16
V17
V18
V19
W3
W16
W17
W18
W19
W32
Y13
Y14
Y15
Y20
Y21
Y22
AA13
AA14
Lattice Semiconductor
71
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AA15
AA20
AA21
AA22
AB13
AB14
AB15
AB20
AB21
AB22
AC3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
AC32
AG3
AG32
AL4
AL31
AM3
AM8
AM12
AM16
AM19
AM23
AM27
AM32
AN1
AN2
AN33
AN34
AP1
AP2
AP33
AP34
C5
C30
D5
D30
E3
E4
E5
E6
E29
E30
E31
72
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
E32
F5
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
F30
N16
N17
N18
N19
P16
P17
P18
P19
R16
R17
R18
R19
T13
T14
T15
T20
T21
T22
U13
U14
U15
U20
U21
U22
V13
V14
V15
V20
V21
V22
W13
W14
W15
W20
W21
W22
Y16
Y17
Y18
Y19
Lattice Semiconductor
73
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
AA16
AA17
AA18
AA19
AB16
AB17
AB18
AB19
AJ5
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD
AJ30
AK3
AK4
AK5
AK6
AK29
AK30
AK31
AK32
AL5
AL30
AM5
AM30
A3
A32
B3
VDD
VDD
VDD
VDD
VDD
VDD
B4
VDD
VDD
VDD
B31
B32
C1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C2
VDD
VDD
VDD
C4
VDD
VDD
VDD
C7
VDD
VDD
VDD
C11
C15
C20
C24
C28
C31
C33
C34
D2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D3
VDD
VDD
VDD
D32
VDD
VDD
VDD
74
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Pin Information (continued)
Table 28. 680-Pin PBGAM Pinout (continued)
Pin
OR3L165B
OR3L225B
Function
D33
G3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
G32
L3
L32
R3
R32
Y3
Y32
AD3
AD32
AH3
AH32
AL2
AL3
AL32
AL33
AM1
AM2
AM4
AM7
AM11
AM15
AM20
AM24
AM28
AM31
AM33
AM34
AN3
AN4
AN31
AN32
AP3
AP32
Lattice Semiconductor
75
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
The ORCA Series FPGAs include circuitry designed to protect the chips from damaging substrate injection cur-
rents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed
during storage, handling, and use to avoid exposure to excessive electrical stress.
Table 29. Absolute Maximum Ratings
Parameter
Storage Temperature
Symbol
Min
Max
Unit
Tstg
VDD
–65
—
150
<4.2
<3.2
°C
V
I/O Supply Voltage with Respect to Ground
Internal Supply Voltage
VDD2
—
V
Input Signal with Respect to Ground
CMOS I/O
—
—
–0.5
–0.5
VDD + 0.3
5.8
V
V
5 V tolerant I/O
Signal Applied to High-impedance Output
Maximum Package Body Temperature
Junction Temperature
—
—
–0.5
—
VDD + 0.3
220
V
°C
°C
T
–40
125
J
Recommended Operating Conditions
Table 30. Recommended Operating Conditions
OR3LxxxB
Temperature
Range
(Ambient)
I/O
Supply Voltage
(VDD)
Mode
Internal Supply
Voltage (VDD2)
Commercial
Industrial
0 °C to 70 °C
3.0 V to 3.6 V
3.0 V to 3.6 V
2.5 V ± 5%
2.5 V ± 5%
–40 °C to +85 °C
76
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Electrical Characteristics
Table 31. Electrical Characteristics
OR3LxxxB Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V
to 3.6 V, VDD2 = 2.38 V to 2.63 V, –40 °C < TA < +85 °C.
OR3LxxxB
Parameter
Input Voltage:
Symbol
Test Conditions
Unit
Min
Max
Input configured as CMOS (clamped to VDD)
High
Low
VIH
VIL
50% VDD
GND – 0.5
VDD + 0.5
30% VDD
V
V
Input Voltage:
High
Low
Input configured as TTL (5 V tolerant)
VIH
VIL
50% VDD
GND – 0.5
5.8 V
30% VDD
V
V
Output Voltage:
High
Low
VOH
VOL
VDD = min, IOH = 6 mA or 3 mA
VDD = min, IOL = 12 mA or 6 mA
2.4
—
—
0.4
V
V
Input Leakage Current
IL
VDD = max, VIN = VSS or VDD
–10
10
µA
Standby Current:
OR3L165B
OR3L225B
IDDSB (TA = 25 °C, VDD = 3.3 V, VDD2 = 2.5 V)
internal oscillator running, no output loads,
inputs VDD or GND
VDD2
VDD
—
—
mA
mA
1.5
2.0
1.0
1.0
Standby Current:
OR3L165B
OR3L225B
IDDSB (TA = 25 °C, VDD = 3.3 V, VDD2 = 2.5 V)
internal oscillator stopped, no output loads,
inputs VDD or GND (after configuration)
—
—
1.1
1.5
1.0
1.0
mA
mA
Powerup Current:
OR3L165B
OR3L225B
Ipp
Power supply current at approximately 1 V,
within a recommended power supply ramp
rate of 1 ms—200 ms
0.4
0.8
—
—
mA
mA
Input Capacitance
CIN
TA = 25 °C,
—
8
pF
VDD = 3.3 V, VDD2 = 2.5 V
Test frequency = 1 MHz
Output Capacitance
COUT TA = 25 °C,
VDD = 3.3 V, VDD2 = 2.5 V
—
8
pF
Test frequency = 1 MHz
DONE Pull-up
Resistor*
RDONE
RM
—
100
100
14.4
26
—
—
kΩ
kΩ
µA
µA
kΩ
kΩ
M[3:0] Pull-up
Resistors*
—
I/O Pad Static Pull-up
Current*
IPU
VDD = 3.6 V,
VIN = VSS, TA = 0 °C
50.9
103
—
I/O Pad Static
Pull-down Current
IPD
VDD = 3.6 V,
VIN = VSS, TA = 0 °C
I/O Pad Pull-up
Resistor*
RPU
RPD
VDD = all, VIN = VSS, TA = 0 °C
VDD = all, VIN = VSS, TA = 0 °C
100
50
I/O Pad Pull-down
Resistor
—
* On the Series 3L devices, the pull-up resistor will externally pull the pin to a level 1.0 V below VDD.
Lattice Semiconductor
77
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
ψJC
Package Thermal Characteristics
This JEDEC designated parameter correlates the junc-
tion temperature to the case temperature. It is generally
used to infer the junction temperature while the device
is operating in the system. It is not considered a true
thermal resistance, and it is defined by the following:
There are four thermal parameters that are in common
ψ
use: ΘJA, JC, ΘJC, and ΘJB. It should be noted that all
the parameters are affected, to varying degrees, by
package design (including paddle size) and choice of
materials, the amount of copper in the test board or
system board, and system airflow.
TJ – TC
ψ
JC =
--------------------
Q
Table 32 contains the currently available thermal speci-
fications for Lattice’s FPGA packages mounted on both
JEDEC and non-JEDEC test boards. The thermal val-
ues for the newer package types correspond to those
packages mounted on a JEDEC four-layer board. The
values for the older packages, however, correspond to
those packages mounted on a non-JEDEC, single-
layer, sparse copper board (see Note 2). It should also
be noted that the values for the older packages are
considered conservative.
where TC is the case temperature at top dead center,
TJ is the junction temperature, and Q is the chip power.
During the ΘJA measurements described above,
besides the other parameters measured, an additional
temperature reading, TC, is made with a thermocouple
ψ
attached at top-dead-center of the case. JC is also
expressed in units of °C/watt.
ΘJC
ΘJA
This is the thermal resistance from junction to case. It
is most often used when attaching a heat sink to the
top of the package. It is defined by the following:
This is the thermal resistance from junction to ambient
(a.k.a. Θ-JA, R-Θ, etc.). It is defined by the following:
TJ – TC
TJ – TA
ΘJC =
--------------------
Q
ΘJA =
-------------------
Q
The parameters in this equation have been defined
above. However, the measurements are performed with
the case of the part pressed against a water-cooled
heat sink so as to draw most of the heat generated by
the chip out the top of the package. It is this difference
in the measurement process that differentiates ΘJC
where TJ is the junction temperature, TA is the ambient
air temperature, and Q is the chip power.
Experimentally, ΘJA is determined when a special ther-
mal test die is assembled into the package of interest,
and the part is mounted on the thermal test board. The
diodes on the test chip are separately calibrated in an
oven. The package/board is placed either in a JEDEC
natural convection box or in the wind tunnel, the latter
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip’s
heater resistor, the chip’s temperature (TJ) is deter-
mined by the forward drop on the diodes, and the ambi-
ent temperature (TA) is noted. Note that ΘJA is
expressed in units of °C/watt.
ψ
from JC. ΘJC is a true thermal resistance and is
expressed in units of °C/watt.
ΘJB
This is the thermal resistance from junction to board
(a.k.a. ΘJL). It is defined by the following:
TJ – TB
ΘJB =
-------------------
Q
where TB is the temperature of the board adjacent to a
lead measured with a thermocouple. The other param-
eters on the right-hand side have been defined above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board so as to draw most of the
heat out of the leads. Note that ΘJB is expressed in
units of °C/watt, and that this parameter and the way it
is measured is still in JEDEC committee.
78
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Package Thermal Characteristics (continued)
FPGA Maximum Junction Temperature
Once the power dissipated by the FPGA has been determined (see the Estimating Power Dissipation section), the
maximum junction temperature of the FPGA can be found. This is needed to determine if speed derating of the
device from the 85 °C junction temperature used in all of the delay tables is needed. Using the maximum ambient
temperature, TAmax, and the power dissipated by the device, Q (expressed in °C), the maximum junction tempera-
ture is approximated by the following:
TJmax = TAmax + (Q × ΘJA)
Table 32 lists the plastic package thermal characteristics for the ORCA Series FPGAs.
Table 32. Plastic Package Thermal Characteristics for the ORCA Series1
ΘJA (°C/W)
TA = 70 °C max
TJ = 125 °C max
at 0 fpm (W)
Package
0 fpm
200 fpm
500 fpm
208-Pin SQFP21
240-Pin SQFP21
352-Pin PBGA1, 2
352-Pin PBGA1, 3
432-Pin EBGA1
680-Pin PBGAM1
12.8
13.0
19.0
25.5
11.0
14.5
10.3
10.0
16.0
22.0
8.5
9.1
9.0
4.3
4.2
2.9
2.1
5.0
3.8
15.0
20.5
7.5
TBD
TBD
1. Mounted on 4-layer JEDEC standard test board with two power/ground planes.
2. With thermal balls connected to board ground plane.
3. Without thermal balls connected to board ground plane.
Lattice Semiconductor
79
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
package, which include the bond wires, all internal
package routing, and the external leads.
Package Coplanarity
The coplanarity limits of the ORCA Series 3 packages
are as follows.
Four inductances in nH are listed: LSW and LSL, the
self-inductance of the lead; and LMW and LML, the
mutual inductance to the nearest neighbor lead. These
parameters are important in determining ground
bounce noise and inductive crosstalk noise. Three
capacitances in pF are listed: CM, the mutual capaci-
tance of the lead to the nearest neighbor lead; and C1
and C2, the total capacitance of the lead to all other
leads (all other leads are assumed to be grounded).
These parameters are important in determining capaci-
tive crosstalk and the capacitive loading effect of the
lead. The lead resistance value, RW, is in mΩ.
Table 33. Package Coplanarity
Coplanarity Limit
Package Type
(mils)
EBGA
PBGA
8.0
8.0
SQFP2
PBGAM1
3.15
8.0
The parasitic values in Table 34 are for the circuit
model of bond wire and package lead parasitics. If the
mutual capacitance value is not used in the designer’s
model, then the value listed as mutual capacitance
should be added to each of the C1 and C2 capacitors.
Package Parasitics
The electrical performance of an IC package, such as
signal quality and noise sensitivity, is directly affected
by the package parasitics. Table 34 lists eight parasitics
associated with the ORCA packages. These parasitics
represent the contributions of all components of a
Table 34. Package Parasitics
Package Type
LSW
LMW
RW
C1
C2
CM
LSL
LML
208-Pin SQFP2
240-Pin SQFP2
352-Pin PBGA
432-Pin EBGA
680-Pin PBGAM1
4
4
2
2
200
200
220
500
250
1
1
1
1
1
6—9
7—11
4—6
4—7
1
5
2
1.5
1
1.5
1
1.5
0.3
0.3
7—12
3—6
4
1.5
1.3
3—5.5
2.8—5.0
0.5—1
0.5—1
3.8
1
1
LSW
RW
LSL
BOARD PAD
C2
PAD N
C1
LMW
LSW
LML
LSL
CM
PAD N + 1
RW
C1
C2
5-3862(F).a
Figure 12. Package Parasitics
80
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Package Outline Diagrams
Terms and Definitions
Basic Size (BSC):
Design Size:
The basic size of a dimension is the size from which the limits for that dimension are derived
by the application of the allowance and the tolerance.
The design size of a dimension is the actual size of the design, including an allowance for fit
and tolerance.
Typical (TYP):
When specified after a dimension, this indicates the repeated design size if a tolerance is
specified or repeated basic size if a tolerance is not specified.
Reference (REF):
The reference dimension is an untoleranced dimension used for informational purposes only.
It is a repeated dimension or one that can be derived from other values in the drawing.
Minimum (MIN) or
Maximum (MAX):
Indicates the minimum or maximum allowable size of a dimension.
Lattice Semiconductor
81
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Package Outline Diagrams (continued)
208-Pin SQFP2
Dimensions are in millimeters.
30.60 ± 0.20
28.00 ± 0.20
21.0 REF
PIN #1 IDENTIFIER ZONE
208
1.30 REF
157
156
0.25
GAGE PLANE
SEATING PLANE
21.0
REF
0.50/0.75
28.00
± 0.20
DETAIL A
30.60
± 0.20
0.090/0.200
0.17/0.2
105
M
0.10
DETAIL B
53
104
EXPOSED HEAT SINK APPEARS ON BOTTOM
SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.)
DETAIL A
DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
5-3828(F)
0.50 TYP
0.25 MIN
CHIP BONDED FACE UP
CHIP
COPPER HEAT SINK
DETAIL C (SQFP2 CHIP-UP)
5-4946(F)
82
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Package Outline Diagrams (continued)
240-Pin SQFP2
Dimensions are in millimeters.
34.60 ± 0.20
32.00 ± 0.20
24. 2 REF
1.30 REF
PIN #1 IDENTIFIER ZONE
240
181
1
180
0.25
GAGE PLANE
SEATING PLANE
0.50/0.75
24.2
RE F
DETAIL A
32.00
± 0.20
34.60
± 0.20
0.090/0.200
0.17/0.27
M
0.10
DETAIL B
60
121
61
120
EXPOSED HEAT SINK APPEARS ON BOTTOM
SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.)
DETAIL B
DETAIL A
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
0.25 MIN
5-3825 (F).a
CHIP BONDED FACE UP
CHIP
COPPER HEAT SINK
DETAIL C (SQFP2 CHIP-UP)
5-4946(F)
Lattice Semiconductor
83
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Package Outline Diagrams (continued)
352-Pin PBGA
Dimensions are in millimeters.
35.00 ± 0.20
+0.70
30.00
–0.00
A1 BALL
IDENTIFIER ZONE
+0.70
–0.00
30.00
35.00
± 0.20
MOLD
COMPOUND
PWB
1.17 ± 0.05
0.56 ± 0.06
2.33 ± 0.21
SEATING PLANE
0.20
SOLDER BALL
25 SPACES @ 1.27 = 31.75
0.60 ± 0.10
AF
AE
AD
AC
AB
AA
Y
W
0.75 ± 0.15
V
U
T
R
P
N
25 SPACES
@ 1.27 = 31.75
M
L
K
J
H
CENTER ARRAY
FOR THERMAL
ENHANCEMENT
(OPTIONAL)
G
F
E
D
C
B
A
(SEE NOTE BELOW)
1 2 3
4
5 6
7
8 9 10 12 14 16 18 20 22 24 26
11 13 15 17 19 21 23 25
A1 BALL
CORNER
5-4407(F)
Note: Although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 FPGA package.
84
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Package Outline Diagrams (continued)
432-Pin EBGA
Dimensions are in millimeters.
40.00 ± 0.10
A1 BALL
IDENTIFIER ZONE
40.00
± 0.10
0.91 ± 0.06
1.54 ± 0.13
SEATING PLANE
0.20
SOLDER BALL
0.63 ± 0.07
30 SPACES @ 1.27 = 38.10
AL
AJ
AK
AH
AG
AE
AC
AF
AD
0.75 ± 0.15
AB
Y
AA
W
V
U
R
N
30 SPACES
@ 1.27 = 38.10
T
P
M
K
L
J
H
F
G
E
D
C
A
B
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31
10 12 14 16 18 20 22 24 26 28 30
A1 BALL
CORNER
2
4
6
8
5-4409(F)
Lattice Semiconductor
85
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Package Outline Diagrams (continued)
680-Pin PBGAM
Dimensions are in millimeters.
35.00
+ 0.70
– 0.00
30.00
A1 BALL
IDENTIFIER ZONE
35.00
+ 0.70
– 0.00
30.00
1.170
0.61 ± 0.08
SEATING PLANE
0.20
SOLDER BALL
33 SPACES @ 1.00 = 33.00
2.51 MAX
0.50 ± 0.10
AP
AM
AK
AH
AF
AD
AB
Y
AN
AL
AJ
AG
AE
AC
AA
W
U
0.64 ± 0.15
33 SPACES
@ 1.00 = 33.00
V
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31 33
10 12 14 16 18 20 22 24 26 28 30 32 34
A1 BALL
CORNER
2
4
6
8
5-4406(F)
86
Lattice Semiconductor
Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Ordering Information
OR3L165B -7 PS 240
TEMPERATURE RANGE
NUMBER OF PINS
PACKAGE TYPE
DEVICE TYPE
SPEED GRADE
OR3L165B, -7 Speed Grade, 240-pin Power Quad Shrink Flat Package (SQFP2), Commercial Temperature
Table 35. Voltage Options
Device
Voltage
OR3LxxxB
2.5 V internal/3.3 V I/O
Table 36.Temperature Options
Symbol
Description
Temperature
(Blank)
I
Commercial
Industrial
0 °C to 70 °C
–40 °C to +85 °C
Table 37. Package Options
Symbol
Description
BA
BC
BM
Plastic Ball Grid Array (PBGA)
Enhanced Ball Grid Array (EBGA)
Plastic Ball Grid Array, Multilayer
(PBGAM1)
PS
Power Quad Shrink Flat Package
(SQFP2)
Table 38. ORCA OR3LxxxB Series Package Matrix
208-Pin
EIAJ/SQ
240-Pin
EIAJ/SQ
352-Pin
PBGA
432-Pin
EBGA
680-Pin
PBGAM
Devices
OR3L165B
OR3L225B
CI
—
CI
—
CI
—
CI
CI
CI
CI
Note: C = commercial, I = industrial.
Lattice Semiconductor
87
www.latticesemi.com
Copyright © 2002 Lattice Semiconductor
All Rights Reserved
January 2002
DA99-011FPGA (Replaces DA99-008FPGA and must accompany DS99-087FPGA)
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