ISPLSI3256E_技术文档

®

ispLSI 3256E

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 256 I/O Pins

— 12000 PLD Gates

ORP

Boundary

Scan

H3 H2 H1 H0

G3 G2 G1 G0

— 512 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

A0

A1

A2

A3

F3

F2

F1

F0

D

Q

OR

Array

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 100 MHz Maximum Operating Frequency

— tpd = 10 ns Propagation Delay

Twin

GLB

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

OR

B0

B1

B2

B3

E3

E2

E1

E0

Array

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

Global Routing Pool

• IN-SYSTEM PROGRAMMABLE

— 5V In-System Programmable (ISP™) using Lattice

ISP or Boundary Scan Test (IEEE 1149.1) Protocol

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

C0 C1 C2 C3

ORP ORP

D1 D2

D0

D3

ORP

— Reprogram Soldered Devices for Faster Debugging

0139A/3256E

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

Description

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

The ispLSI 3256E is a High Density Programmable Logic

Device containing 512 Registers, 256 Universal I/O pins,

five Dedicated Clock Input Pins, 16 Output Routing Pools

(ORP) and a Global Routing Pool (GRP) which allows

complete inter-connectivity between all of these ele-

ments. The ispLSI 3256E features 5V in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3256E offers non-volatile reprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

mize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

The basic unit of logic on the ispLSI 3256E device is the

TwinGenericLogicBlock(TwinGLB)labelledA0,A1...H3.

There are a total of 32 Twin GLBs in the ispLSI 3256E

device. Each Twin GLB has 24 inputs, a programmable

AND array and two OR/Exclusive-OR Arrays and eight

outputs which can be configured to be either combinato-

rial or registered. All Twin GLB inputs come from the

GRP.

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

March 2007

3256e_09

1

Specifications ispLSI 3256E

Functional Block Diagram

Figure 1. ispLSI 3256E Functional Block Diagram

Input Bus

Generic

Input Bus

TDI/SDI

ISP and

TOE

Logic

ORP

TRST

Boundary

Scan TAP

Blocks

TDO/SDO

H3

H2

H1

H0

G3

G2

G1 G0

I/O 191

I/O 189

I/O 187

I/O 185

I/O 190

I/O 188

I/O 186

I/O 184

I/O 1 I/O 0

I/O 3 I/O 2

I/O 5 I/O 4

I/O 7 I/O 6

A0

F3

I/O 183

I/O 181

I/O 179

I/O 177

I/O 182

I/O 180

I/O 178

I/O 176

I/O 9

I/O 8

I/O 11 I/O 10

I/O 13 I/O 12

I/O 15 I/O 14

A1

A2

A3

F2

F1

F0

I/O 175

I/O 173

I/O 171

I/O 169

I/O 174

I/O 172

I/O 170

I/O 168

I/O 17 I/O 16

I/O 19 I/O 18

I/O 21 I/O 20

I/O 23 I/O 22

I/O 167

I/O 165

I/O 163

I/O 161

I/O 166

I/O 164

I/O 162

I/O 160

I/O 25 I/O 24

I/O 27 I/O 26

I/O 29 I/O 28

I/O 31 I/O 30

Global Routing Pool

(GRP)

I/O 32

I/O 34

I/O 36

I/O 38

I/O 33

I/O 35

I/O 37

I/O 39

I/O 158 I/O 159

I/O 156 I/O 157

I/O 154 I/O 155

I/O 152 I/O 153

B0

B1

B2

B3

E3

E2

E1

E0

I/O 40

I/O 42

I/O 44

I/O 46

I/O 41

I/O 43

I/O 45

I/O 47

I/O 150 I/O 151

I/O 148 I/O 149

I/O 146 I/O 147

I/O 144 I/O 145

I/O 48

I/O 50

I/O 52

I/O 54

I/O 49

I/O 51

I/O 53

I/O 55

I/O 142 I/O 143

I/O 140 I/O 141

I/O 138 I/O 139

I/O 136 I/O 137

I/O 56

I/O 58

I/O 60

I/O 62

I/O 57

I/O 59

I/O 61

I/O 63

I/O 134 I/O 135

I/O 132 I/O 133

I/O 130 I/O 131

I/O 128 I/O 129

C0

C1

ORP

C2

C3

ORP

D0

D1

ORP

D2

D3

ORP

Megablock

Input Bus

RESET

0139isp/3256E

2

Specifications ispLSI 3256E

Description (continued)

All local logic block outputs are brought back into the Clocks in the ispLSI 3256E device are provided through

GRP so they can be connected to the inputs of any other five dedicated clock pins. The five pins provide three

logic block on the device. The device also has 256 I/O clocks to the Twin GLBs and two clocks to the I/O cells.

cells, each of which is directly connected to an I/O pin.

The table below lists key attributes of the device along

with the number of resources available.

Each I/O cell can be individually programmed to be a

combinatorialinput,aregisteredinput,alatchedinput,an

output or a bidirectional I/O pin with 3-state control. The

An additional feature of the ispLSI 3256E is its Boundary

signal levels are TTL compatible voltages and the output

Scan capability, which is composed of cells connected

drivers can source 4 mA or sink 8 mA. Each output can

between the on-chip system logic and the device’s input

be programmed independently for fast or slow output

and output pins. All I/O pins have associated boundary

slew rate to minimize overall output switching noise.

scan registers, with 3-state I/O using three boundary

scan registers and inputs using one.

The 256 I/O Cells are grouped into 16 sets of 16 bits.

Pairs of these I/O groups are associated with a logic

The ispLSI 3256E supports all IEEE 1149.1 mandatory

MegablockthroughtheuseoftheORP. EachMegablock

instructions, which include BYPASS, EXTEST and

is able to provide one Product Term Output Enable

SAMPLE.

(PTOE) signal which is globally distributed to all I/O cells.

ThatPTOEsignalcanbegeneratedwithinanyGLBinthe

Megablock. Each I/O cell can select either a Global OE

Key Attributes of the ispLSI 3256E

or a PTOE.

Attribute

Twin GLBs

Quantity

Four Twin GLBs, 32 I/O Cells and two ORPs are con-

nected together to make a logic Megablock. The

Megablockisdefinedbythe resourcesthatitshares. The

outputs of the four Twin GLBs are connected to a set of

32 I/O cells by the ORP. The ispLSI 3256E device

contains eight of these Megablocks.

32

512

256

5

Registers

I/O Pins

Global Clocks

Global OE

Test OE

2

The GRP has as its inputs the outputs from all of the Twin

GLBs and all of the inputs from the bidirectional I/O cells.

All of these signals are made available to the inputs of the

Twin GLBs. Delays through the GRP have been equal-

ized to minimize timing skew and logic glitching.

1

Table - 003/3256E

3

Specifications ispLSI 3256E

1

Absolute Maximum Ratings

Supply Voltage V ........................................................................... -0.5 to +7.0V

cc

Input Voltage Applied........................................................................ -2.5 to V +1.0V

CC

Off-State Output Voltage Applied ..................................................... -2.5 to V +1.0V

CC

Storage Temperature........................................................................ -65 to 150°C

Case Temp. with Power Applied ...................................................... -55 to 125°C

Max. Junction Temp. (T ) with Power Applied (304-Pin PQFP) ...... 150°C

J

Max. Junction Temp. (T ) with Power Applied (320-Ball BGA) ........ 140°C

J

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

SYMBOL

PARAMETER

MIN.

0

MAX.

70

UNITS

Ambient Temperature

Supply Voltage

°C

V

TA

4.75

0

5.25

0.8

V

CC

Input Low Voltage

Input High Voltage

V

IL

2.0

V_CC+1

V

IH

Table 2-0005/3256E

Capacitance (T_A=25°C,f=1.0 MHz)

SYMBOL

PARAMETER

TYPICAL

UNITS

TEST CONDITIONS

_CC= 5.0V, V_I/O= 2.0V

V_CC= 5.0V, V_Y= 2.0V

10

pf

V

I/O Capacitance

C₁

C₂

15

pf

Clock Capacitance

Table 2-0006/3256E

Data Retention Specifications

PARAMETER

Data Retention

MINIMUM

MAXIMUM

UNITS

20

–

Years

ispLSI Erase/Reprogram Cycles

10000

Cycles

Table 2-0008/3256E

4

Specifications ispLSI 3256E

Switching Test Conditions

Figure 2. Test Load

Input Pulse Levels

GND to 3.0V

≤ 3ns 10% to 90%

1.5V

Input Rise and Fall Time

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

+ 5V

1.5V

R

1

2

See Figure 2

Device

Output

Test

Point

Table 2-0003/3256E

3-state levels are measured 0.5V from

steady-state active level.

R

C

*

L

Output Load conditions (See Figure 2)

*

C includes Test Fixture and Probe Capacitance.

L

0213A

TEST CONDITION

R1

470Ω

∞

R2

CL

A

B

390Ω

35pF

Active High

Active Low

470Ω

Active High to Z

∞

390Ω

5pF

at V_OH-0.5V

C

Active Low to Z

at V_OL+0.5V

470Ω

5pF

Table 2 - 0004A

DC Electrical Characteristics

Over Recommended Operating Conditions

3

SYMBOL

PARAMETER

CONDITION

I_OL= 8 mA

MIN.

–

TYP. MAX. UNITS

Output Low Voltage

–

0.4

–

V

OL

Output High Voltage

I_OH= -4 mA

2.4

–

OH

Input or I/O Low Leakage Current

Input or I/O High Leakage Current

Bscan/ispEN Input Low Leakage Current

I/O Active Pull-Up Current

0V ≤ V ≤ V (Max.)

-10

10

μA

mA

I

IL

IH

IN

IL

3.5V ≤ V ≤ V

–

IN

CC

0V ≤ V ≤ V

–

-150

-200

IL-isp

IL-PU

OS¹

IN

IL

0V ≤ V ≤ V

–

IN

IL

Output Short Circuit Current

V = 5V, V_OUT= 0.5V

–

CC

V = 0.0V, V = 3.0V

I

CC^2,4

IL

IH

Operating Power Supply Current

–

300

–

mA

f_TOGGLE= 1 MHz

1. One output at a time for a maximum duration of one second. V_OUT= 0.5V was selected to avoid test problem^Ts^{able 2 - 0007isp/3256E}

by tester ground degradation. Characterized but not 100% tested.

2. Measured using sixteen 16-bit counters.

3. Typical values are at V_CC= 5V and T_A= 25°C.

4. Maximum I_CCvaries widely with specific device configuration and operating frequency. Refer to the Power Consumption

section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate

maximum I_CC

.

5

Specifications ispLSI 3256E

External Switching Characteristics^{1, 2, 3}

Over Recommended Operating Conditions

TEST⁵

COND.

-100

-70

2

DESCRIPTION¹

UNITS

PARAMETER

#

MIN. MAX. MIN. MAX.

A

1

Data Prop. Delay, 4PT Bypass, ORP Bypass

Data Propagation Delay

Clock Frequency with Internal Feedback³

Clock Freq. with Ext. Feedback,1/(tsu2 + tco1)

Clock Frequency, Max Toggle⁴

—

10.0

13.0

—

15.0

18.0

—

ns

t

pd1

2

3

4

5

6

7

8

9

t

f

t

pd2

A

100

77.0

100

5.5

—

70.0

50.0

83.0

9.0

—

MHz

ns

max

—

A

—

max (Ext.)

max (Tog.)

su1

—

GLB Reg. Setup Time before Clock, 4PT bypass

GLB Reg. Clock to Output Delay, ORP bypass

GLB Reg. Hold Time after Clock, 4PT bypass

GLB Reg. Setup Time before Clock

—

6.5

—

9.0

—

ns

co1

—

A

0.0

6.5

—

0.0

11.0

—

ns

h1

—

ns

su2

10 GLB Reg. Clock to Output Delay

11 GLB Reg. Hold Time after Clock

12 Ext. Reset Pin to Output Delay

13 Ext. Reset Pulse Duration

7.0

—

10.0

—

ns

co2

0.0

—

0.0

—

ns

h2

13.5

—

15.0

—

ns

r1

—

B

6.5

—

12.0

—

ns

rw1

14 Input to Output Enable

16.0

9.0

12.0

—

19.0

12.0

15.0

—

ns

ptoeen

ptoedis

goeen

goedis

toeen

toedis

wh

C

15 Input to Output Disable

—

ns

B

16 Global OE Output Enable

—

ns

C

17 Global OE Output Disable

—

ns

—

18 Test OE Output Enable

—

ns

19 Test OE Output Disable

—

ns

20 Ext. Sync. Clock Pulse Duration, High

21 Ext. Sync. Clock Pulse Duration, Low

22 I/O Reg. Setup Time before Ext. Sync. Clock (Y3, Y4)

23 I/O Reg. Hold Time after Ext. Sync. Clock (Y3, Y4)

5.0

4.5

0.0

6.0

5.0

0.0

ns

—

ns

wl

—

ns

su3

—

ns

h3

1. Unless noted otherwise, all parameters use 20 PTXOR path and ORP.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.

5. Reference Switching Test Conditions section.

Timing Ext.3256E.eps

6

Specifications ispLSI 3256E

Internal Timing Parameters¹

Over Recommended Operating Conditions

-100

-70

2

PARAMETER

Inputs

#

DESCRIPTION

UNITS

MIN. MAX. MIN. MAX.

24 I/O Register Bypass

25 I/O Latch Delay

—

2.4

10.3

—

4.0

14.0

—

ns

t

iobp

iolat

iosu

ioh

26 I/O Register Setup Time before Clock

27 I/O Register Hold Time after Clock

28 I/O Register Clock to Out Delay

29 I/O Register Reset to Out Delay

4.8

-1.6

—

5.8

-2.5

—

5.8

8.5

7.5

ioco

ior

—

GRP

grp

GLB

30 GRP Delay

—

2.3

—

3.2

ns

t

31 4 Product Term Bypass Path Delay (Comb.)

32 4 Product Term Bypass Path Delay (Reg.)

33 1 Product Term/XOR Path Delay

—

3.2

3.1

4.0

4.1

4.3

1.5

—

3.6

4.8

5.1

5.2

5.7

1.6

—

ns

t

4ptbp

4ptbr

1ptxor

20ptxor

xoradj

gbp

—

34 20 Product Term/XOR Path Delay

35 XOR Adjacent Path Delay³

—

36 GLB Register Bypass Delay

—

37 GLB Register Setup Time before Clock

38 GLB Register Hold Time after Clock

39 GLB Register Clock to Output Delay

40 GLB Register Reset to Output Delay

41 GLB Product Term Reset to Register Delay

42 GLB Product Term Output Enable to I/O Cell Delay

43 GLB Product Term Clock Delay

0.3

5.0

—

1.2

7.6

—

gsu

—

gh

1.6

5.2

4.0

6.5

3.6

3.0

5.2

4.4

6.9

4.2

gco

—

gro

—

ptre

—

ptoe

ptck

3.0

3.4

ORP

44 ORP Delay

—

1.2

0.7

—

1.9

0.9

ns

t

orp

45 ORP Bypass Delay

torpbp

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

Timing Int.3256E.eps

7

Specifications ispLSI 3256E

Internal Timing Parameters¹

Over Recommended Operating Conditions

-100

-70

2

PARAMETER

Outputs

#

DESCRIPTION

UNITS

MIN. MAX. MIN. MAX.

46 Output Buffer Delay

—

2.6

17.6

5.5

—

3.3

18.3

5.7

ns

t

ob

47 Output Buffer Delay, Slew Limited Adder

48 I/O Cell OE to Output Enabled

obs

oen

odis

49 I/O Cell OE to Output Disabled

5.5

5.7

Clocks

50 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clk Line

51 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line

1.6

0.3

1.6

1.8

0.8

1.8

2.5

ns

t

gy0/1/2

ioy3/4

t

Global Reset

52 Global Reset to GLB and I/O Registers

53 Global OE Pad Buffer

—

4.5

5.9

6.1

—

4.6

7.5

8.9

ns

t

gr

goe

toe

54 Test OE Pad Buffer

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

Timing Int.2.3256E.eps

8

Specifications ispLSI 3256E

ispLSI 3256E Timing Model

I/O Cell

GRP

GLB

#31

ORP

I/O Cell

Feedback

I/O Reg Bypass

#24

GRP

#30

4 PT Bypass

#32

GLB Reg Bypass

#36

ORP Bypass

#45

#46, 47

I/O Pin

(Output)

I/O Pin

(Input)

Input

20 PT

XOR Delays

GLB Reg

Delay

ORP

Delay

Register

Q

D

RST

D

Q

#44

#33 - 35

#52

#25 - 29

#48, 49

RST

#37 - 40

Reset

Y3,4

#51

Control

PTs

RE

OE

CK

#41 - 43

#50

Y0,1,2

#53

#54

GOE0,1

TOE

0902/3256E

Derivations of

t

su,

= Logic + Reg su - Clock (min)

= ( iobp + grp + 20ptxor) + ( gsu) - (tiobp + tgrp + tptck(min))

th and t

co from the Product Term Clock¹

t

su

t

= (#24+ #30+ #34) + (#37) - (#24+ #30+ #43)

1.4 ns = (2.4 + 2.3 + 4.1) + (0.3) - (2.4 + 2.3 + 3.0)

h

= Clock (max) + Reg h - Logic

= (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor)

= (#24+ #30+ #43) + (#38) - (#24+ #30+ #34)

4.5 ns = (2.4 + 2.3 + 3.6) + (5.0) - (2.4 + 2.3 + 4.1)

co

= Clock (max) + Reg co + Output

= (

= (#24 + #30 + #43) + (#39) + (#44 + #46)

13.7 ns = (2.4 + 2.3 + 3.6) + (1.6) + (1.2 + 2.6)

tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob)

Table 2- 0042-3256E

Note: Calculations are based upon timing specifications for the ispLSI 3256E-100L.

9

Specifications ispLSI 3256E

Power Consumption

Power consumption in the ispLSI 3256E device depends Figure 3 shows the relationship between power and

on two primary factors: the speed at which the device is operating speed.

operating and the number of product terms used.

Figure 3. Typical Device Power Consumption vs fmax

ispLSI 3256E

600

500

400

300

200

0

20

40 60

80 100

fmax (MHz)

Notes: Configuration of 16 16-bit Counters

Typical Current at 5V, 25° C

I

can be estimated for the ispLSI 3256E using the following equation:

CC

= 60 + (# of PTs 0.48) + (# of nets Max. freq 0.0106) where:

*

# of PTs = Number of Product Terms used in design

# of nets = Number of Signals used in device

Max. freq = Highest Clock Frequency to the device

The I

estimate is based on typical conditions (V

= 5.0V, room temperature) and an assumption of two

CC

GLB loads on average exists. These values are for estimates only. Since the value of I

operating conditions and the program in the device, the actual I

is sensitive to

CC

should be verified.

CC

0127/3256E

10

Specifications ispLSI 3256E

Pin Description

Pin Name

I/O

Description

Input/Output pins – These are the general purpose I/O pins used by the logic array.

GOE0, GOE1

TOE

Global Output Enable input pins.

Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven.

Active Low (0) Reset pin – Resets all of the GLB and I/O registers in the device.

RESET

Y0, Y1, Y2

Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on

the device.

Y3, Y4

Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells

on the device.

BSCAN/ispEN

Input – Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP

controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP State

Machine control pins MODE, SDI, SDO and SCLK are enabled. High-to-low transition of this pin will put

the device in the programming mode and put all I/O pins in the high-Z state.

TDI/SDI

Input – This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When

ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also

used as one of the two control pins for the ISP State Machine.

TCK/SCLK

Input – This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When

ispEN is logic low, it functions as a clock pin for the Serial Shift Register.

TMS/MODE

Input – This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high.

When ispEN is logic low, it functions as a pin to control the operation of the ISP State Machine.

TRST/NC¹

Input – Test Reset, active low to reset the Boundary Scan State Machine.

TDO/SDO

Output – This pin performs two functions. When ispEN is logic low, it functions as the pin to read the

ISP data. When ispEN is high, it functions as Test Data Out.

GND

VCC

NC¹

Ground (GND)

Vcc

No Connect.

1. NC pins are not to be connected to any active signals, VCC or GND.

Pin Locations

Signal

GOE0, GOE1

TOE

304-Pin PQFP

320-Ball BGA

195, 185

215

AD11, AC14

AC6

RESET

53

A17

Y0, Y1, Y2, Y3, Y4 43, 33, 205, 175, 165

A14, B11, AD8, AB16, AA18

ispEN/BSCAN

SDI/TDI

63

B19

C9

23

SCLK/TCK

MODE/TMS

TRST/NC¹

SDO/TDO

GND

73

D20

D7

13

225

155

AA5

AB21

9, 19, 39, 49, 69, 85, 95, 115, 125, 145, 161, 171, D6, C8, B13, A16, D19, F21, H22, N23, T24, W21,

191, 201, 221, 237, 247, 267, 277, 297

AA19, AB17, AC12, AD9, AA6, W4, U3, M2, J1, F4

VCC

NC¹

1, 29, 59, 77, 105, 135, 153, 181, 211, 229, 257,

287, 304

D4, B10, B18, D21, K23, V23, AA21, AC15, AC7,

AA4, R2, G2, C3

A1, A2, A23, A24, B1, B2, B23, B24, AC1, AC2,

AC23, AC24, AD1, AD2, AD23, AD24

1. NC pins are not to be connected to any active signals, VCC or GND.

11

Specifications ispLSI 3256E

I/O Locations

Signal PQFP BGA

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

40

41

42

44

45

46

47

48

50

51

52

54

55

56

57

58

60

61

62

64

65

66

67

68

70

71

72

74

75

76

78

79

80

81

82

83

84

86

87

88

89

90

91

92

93

94

96

97

98

99

C13

D13

A13

B14

C14

D14

A15

B15

C15

D15

B16

C16

B17

D16

A18

C17

A19

D17

C18

A20

D18

C19

B20

A21

C20

B21

A22

C21

B22

C22

C23

D22

C24

E21

D23

E22

D24

E23

F22

E24

G21

F23

G22

F24

H21

G23

G24

J21

I/O 53 103 K22

I/O 54 104 J24

I/O 55 106 K24

I/O 56 107 L21

I/O 57 108 L22

I/O 58 109 L23

I/O 59 110 L24

I/O 60 111 M24

I/O 61 112 M21

I/O 62 113 M22

I/O 63 114 M23

I/O 64 116 N22

I/O 65 117 N21

I/O 66 118 N24

I/O 67 119 P24

I/O 68 120 P23

I/O 69 121 P22

I/O 70 122 P21

I/O 71 123 R24

I/O 72 124 R23

I/O 73 126 R22

I/O 74 127 R21

I/O 75 128 T23

I/O 76 129 U24

I/O 77 130 T22

I/O 78 131 U23

I/O 79 132 T21

I/O 80 133 V24

I/O 81 134 U22

I/O 82 136 W24

I/O 83 137 U21

I/O 84 138 V22

I/O 85 139 W23

I/O 86 140 Y24

I/O 87 141 V21

I/O 88 142 W22

I/O 89 143 Y23

I/O 90 144 AA24

I/O 91 146 Y22

I/O 92 147 AA23

I/O 93 148 AB24

I/O 94 149 Y21

I/O 95 150 AA22

I/O 96 151 AB23

I/O 97 152 AB22

I/O 98 154 AC22

I/O 99 156 AD22

I/O 100 157 AA20

I/O 101 158 AC21

I/O 102 159 AB20

I/O 103 160 AD21

I/O 104 162 AC20

I/O 105 163 AB19

I/O 106 164 AD20

I/O 107 166 AC19

I/O 108 167 AB18

I/O 109 168 AD19

I/O 110 169 AA17

I/O 111 170 AC18

I/O 112 172 AD18

I/O 113 173 AA16

I/O 114 174 AC17

I/O 115 176 AD17

I/O 116 177 AC16

I/O 117 178 AA15

I/O 118 179 AB15

I/O 119 180 AD16

I/O 120 182 AD15

I/O 121 183 AA14

I/O 122 184 AB14

I/O 123 186 AD14

I/O 124 187 AD13

I/O 125 188 AA13

I/O 126 189 AB13

I/O 127 190 AC13

I/O 128 192 AB12

I/O 129 193 AA12

I/O 130 194 AD12

I/O 131 196 AC11

I/O 132 197 AB11

I/O 133 198 AA11

I/O 134 199 AD10

I/O 135 200 AC10

I/O 136 202 AB10

I/O 137 203 AA10

I/O 138 204 AC9

I/O 139 206 AB9

I/O 140 207 AC8

I/O 141 208 AA9

I/O 142 209 AD7

I/O 143 210 AB8

I/O 144 212 AD6

I/O 145 213 AA8

I/O 146 214 AB7

I/O 147 216 AD5

I/O 148 217 AA7

I/O 149 218 AB6

I/O 150 219 AC5

I/O 151 220 AD4

I/O 152 222 AB5

I/O 153 223 AC4

I/O 154 224 AD3

I/O 155 226 AB4

I/O 156 227 AC3

I/O 157 228 AB3

I/O 158 230 AB2

I/O 212 290

I/O 213 291

I/O 214 292

I/O 215 293

I/O 216 294

I/O 217 295

I/O 218 296

I/O 219 298

I/O 220 299

I/O 221 300

I/O 222 301

I/O 223 302

I/O 224 303

G3

F2

E1

G4

F3

E2

D1

E3

D2

C1

E4

D3

C2

B3

C4

A3

D5

B4

C5

A4

B5

C6

A5

B6

C7

A6

D8

B7

A7

I/O 159 231 AA3

I/O 160 232 AB1

I/O 161 233

I/O 162 234 AA2

I/O 163 235 Y3

I/O 164 236 AA1

Y4

I/O 165 238

I/O 166 239

I/O 167 240

I/O 168 241

I/O 169 242

I/O 170 243

I/O 171 244

I/O 172 245

I/O 173 246

I/O 174 248

I/O 175 249

I/O 176 250

I/O 177 251

I/O 178 252

I/O 179 253

I/O 180 254

I/O 181 255

I/O 182 256

I/O 183 258

I/O 184 259

I/O 185 260

I/O 186 261

I/O 187 262

I/O 188 263

I/O 189 264

I/O 190 265

I/O 191 266

I/O 192 268

I/O 193 269

I/O 194 270

I/O 195 271

I/O 196 272

I/O 197 273

I/O 198 274

I/O 199 275

I/O 200 276

I/O 201 278

I/O 202 279

I/O 203 280

I/O 204 281

I/O 205 282

I/O 206 283

I/O 207 284

I/O 208 285

I/O 209 286

I/O 210 288

I/O 211 289

Y2

W3

Y1

V4

W2

V3

W1

U4

V2

V1

T4

U2

T3

U1

T2

R4

R3

T1

R1

P4

P3

P2

P1

N1

N4

N3

N2

M3

M4

M1

L1

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 32

I/O 33

I/O 34

I/O 35

I/O 36

I/O 37

I/O 38

I/O 39

I/O 40

I/O 41

I/O 42

I/O 43

I/O 44

I/O 45

I/O 46

I/O 47

I/O 48

I/O 49

I/O 225

I/O 226

I/O 227

I/O 228

I/O 229

I/O 230

I/O 231

2

3

4

5

6

7

8

I/O 232 10

I/O 233 11

I/O 234 12

I/O 235 14

I/O 236 15

I/O 237 16

I/O 238 17

I/O 239 18

I/O 240 20

I/O 241 21

I/O 242 22

I/O 243 24

I/O 244 25

I/O 245 26

I/O 246 27

I/O 247 28

I/O 248 30

I/O 249 31

I/O 250 32

I/O 251 34

I/O 252 35

I/O 253 36

I/O 254 37

I/O 255 38

D9

B8

A8

B9

D10

C10

A9

A10

D11

C11

A11

A12

D12

C12

B12

L2

L3

L4

K1

K2

K3

K4

J2

H1

J3

H2

J4

G1

H3

F1

H4

H23

J22

I/O 50 100 H24

I/O 51 101 J23

I/O 52 102 K21

12

Specifications ispLSI 3256E

Pin Configuration

ispLSI 3256E 304-Pin PQFP Pinout Diagram

1

2

3

4

5

6

7

8

228

227

226

225

224

223

222

221

220

219

218

217

216

215

214

213

212

211

210

209

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

VCC

I/O 225

I/O 226

I/O 227

I/O 228

I/O 229

I/O 230

I/O 231

GND

I/O 232

I/O 233

I/O 234

MODE/TMS

I/O 235

I/O 236

I/O 237

I/O 238

I/O 239

GND

I/O 240

I/O 241

I/O 242

SDI/TDI

I/O 243

I/O 244

I/O 245

I/O 246

I/O 247

VCC

I/O 248

I/O 249

I/O 250

Y1

I/O 251

I/O 252

I/O 253

I/O 254

I/O 255

GND

I/O 0

I/O 1

I/O 2

Y0

I/O 3

I/O 4

I/O 5

I/O 6

I/O 157

I/O 156

I/O 155

TRST/NC¹

I/O 154

I/O 153

I/O 152

GND

I/O 151

I/O 150

I/O 149

I/O 148

I/O 147

TOE

I/O 146

I/O 145

I/O 144

VCC

I/O 143

I/O 142

I/O 141

I/O 140

I/O 139

Y2

I/O 138

I/O 137

I/O 136

GND

I/O 135

I/O 134

I/O 133

I/O 132

I/O 131

GOE0

I/O 130

I/O 129

I/O 128

GND

I/O 127

I/O 126

I/O 125

I/O 124

I/O 123

GOE1

I/O 122

I/O 121

I/O 120

VCC

I/O 119

I/O 118

I/O 117

I/O 116

I/O 115

Y3

I/O 114

I/O 113

I/O 112

GND

I/O 111

I/O 110

I/O 109

I/O 108

I/O 107

Y4

I/O 106

I/O 105

I/O 104

GND

I/O 103

I/O 102

I/O 101

I/O 100

I/O 99

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

ispLSI 3256E

Top View

I/O 7

GND

I/O 8

I/O 9

I/O 10

RESET

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

VCC

I/O 16

I/O 17

I/O 18

ispEN/BSCAN

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

GND

I/O 24

I/O 25

I/O 26

SCLK/TCK

I/O 27

I/O 28

I/O 29

SDO/TDO

I/O 98

VCC

1. NC pins are not to be connected to any active signals, VCC or GND.

13

Specifications ispLSI 3256E

Signal Configuration

ispLSI 3256E 320-Ball BGA Signal Diagram

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

I/O

26

I/O

23

I/O

19

I/O

16

I/O

14

I/O

6

I/O

2

I/O

I/O I/O

NC¹NC¹

RESET GND

Y0

NC¹NC¹

A

B

A

B

252 251 248 247 243 240 237 234 231 227

I/O

28

I/O

25

I/O ispEN/

22 BSCAN

I/O

12

I/O

10

I/O

7

I/O

3

I/O

255

I/O

I/O I/O

VCC

GND

Y1 VCC

I/O

244 242 239 235 232 229 225

I/O

32

I/O I/O

30 29

I/O

27

I/O

24

I/O

21

I/O

18

I/O

15

I/O

11

I/O

8

I/O

4

I/O

0

I/O

I/O SDI/

I/O

GND

VCC

I/O

C

254 250 246 TDI

236 233 230 226

224 221

I/O

36

I/O I/O

34 31

SCLK/

TCK

I/O

20

I/O

17

I/O

13

I/O

9

I/O

5

I/O

1

I/O

I/O MODE/

I/O

228

I/O I/O

VCC

GND

VCC

D

253 249 245 241 238 TMS

223 220 218

I/O

39

I/O I/O

37 35

I/O

33

I/O I/O I/O I/O

E

222 219 217 214

I/O I/O I/O

I/O

43

I/O I/O

41 38

GND

F

216 213 210

I/O I/O

215 212

I/O

46

I/O I/O

I/O

40

VCC

I/O

G

H

G

H

208

45

42

I/O I/O

211 209 206 204

I/O

50

I/O

48

I/O

44

GND

I/O I/O

I/O

54

I/O I/O

I/O

47

GND

I/O

J

207 205 203

51

49

I/O I/O I/O

I/O

55

I/O

53

I/O

52

VCC

K

202 201 200 199

I/O I/O I/O I/O

198 197 196 195

I/O

59

I/O I/O

58 57

I/O

56

L

I/O I/O

193 192

I/O

60

I/O I/O

I/O

61

GND

I/O

M

N

M

N

194

63

62

ispLSI 3256E

I/O

66

I/O

64

I/O

65

I/O I/O

189 190 191 188

I/O

GND

Bottom View

I/O

67

I/O I/O

68 69

I/O

70

I/O I/O

184 185 186 187

I/O

P

I/O I/O

180 181

I/O

71

I/O I/O

72 73

I/O

74

VCC

I/O

R

183

I/O I/O

175 177 179 182

I/O

I/O I/O

75 77

I/O

79

GND

T

I/O

76

I/O I/O

I/O

83

I/O

172

I/O

GND

U

78

81

176 178

I/O

80

I/O

84

I/O

87

I/O I/O

I/O

VCC

V

168 170 173 174

I/O I/O I/O

166 169 171

I/O I/O I/O I/O

161 163 165 167

I/O I/O I/O

159 162 164

I/O I/O I/O I/O

I/O

82

I/O I/O

85 88

GND

W

Y

W

Y

I/O

86

I/O I/O

89 91

I/O

94

I/O

90

I/O I/O

92 95

I/O

100

I/O

TRST/

GND

I/O

VCC

AA

AB

AC

AD

VCC

GND Y4

AA

AB

AC

AD

1

110 113 117 121 125 129 133 137 141 145 148

NC

I/O

93

I/O I/O SDO/ I/O

96 97 TDO 102 105 108

I/O

GND Y3

I/O I/O

118 122 126 128 132 136 139 143 146 149 152 155 157 158 160

I/O I/O I/O I/O I/O

98 101 104 107 111 114 116

I/O I/O I/O I/O I/O I/O I/O

GOE I/O

1

I/O

I/O I/O

150 153 156

NC¹NC¹

VCC

I/O

GND

VCC TOE

I/O I/O

NC¹NC¹

127

131 135 138 140

I/O

I/O GOE I/O

134

I/O I/O I/O

142 144 147 151 154

GND Y2

99 103 106 109 112 115 119 120 123 124 130

0

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

1. NC pins are not to be connected to any active signals, VCC or GND.

Note: Ball A1 indicator dot on top side of package.

14

Specifications ispLSI 3256E

Part Number Description

ispLSI 3256E– XXX X XXXX X

Device Family

Grade

Blank = Commercial

Device Number

Package

Q = PQFP (With Heat Sink)

QA = PQFP (Without Heat Sink)

B320 = BGA

Speed

100 = 100 MHz fmax

70 = 70 MHz fmax

Power

L = Low

Ordering Information

COMMERCIAL

FAMILY

fmax (MHz)

tpd (ns)

10

ORDERING NUMBER

ispLSI 3256E-100LQ¹

ispLSI 3256E-100LQA

ispLSI 3256E-100LB320

ispLSI 3256E-70LQ¹

ispLSI 3256E-70LQA

ispLSI 3256E-70LB320

PACKAGE

100

70

304-Pin PQFP (With Heat Sink)

304-Pin PQFP (Without Heat Sink)

320-Ball BGA

10

ispLSI

15

304-Pin PQFP (With Heat Sink)

304-Pin PQFP (Without Heat Sink)

320-Ball BGA

70

15

70

15

1. Converted to ispLSI 3256E-xxxLQA per PCN #03A-07.

Revision History

Date

—

Version

—

Change Summary

Previous Lattice releases.

Updated Part Number Description and Ordering Information.

March 2007

09

15


型号：	ISPLSI3256E
厂家：	LATTICE SEMICONDUCTOR
描述：	In-System Programmable High Density PLD 在系统可编程高密度PLD
文件：	总15页 (文件大小：246K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISPLSI3256E [LATTICE]

相关型号：

ISPLSI3256E-100LB320

ISPLSI3256E-100LM

ISPLSI3256E-100LQ

ISPLSI3256E-70LB320

ISPLSI3256E-70LM

ISPLSI3256E-70LQ

ISPLSI3256E-70LQA

ISPLSI3256E100LB320

ISPLSI3256E100LQ

ISPLSI3256E100LQA

ISPLSI3256E70LB320

ISPLSI3256E70LQ