ISPLSI2032-110LT48 [LATTICE]
In-System Programmable High Density PLD; 在系统可编程高密度PLD型号: | ISPLSI2032-110LT48 |
厂家: | LATTICE SEMICONDUCTOR |
描述: | In-System Programmable High Density PLD |
文件: | 总15页 (文件大小:145K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
ispLSI 2032/A
In-System Programmable High Density PLD
Features
Functional Block Diagram
• ENHANCEMENTS
— ispLSI 2032A is Fully Form and Function Compatible
to the ispLSI 2032, with Identical Timing
Specifcations and Packaging
— ispLSI 2032A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
Global Routing Pool
A0
A1
A2
A7
A6
A5
A4
(GRP)
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
D
D
D
D
Q
Q
Q
Q
Logic
Array
GLB
A3
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 180 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
0139Bisp/2000
Description
The ispLSI 2032 and 2032A are High Density Program-
mable Logic Devices. The devices contain 32 Registers,
32 Universal I/O pins, two Dedicated Input Pins, three
Dedicated Clock Input Pins, one dedicated Global OE
input pin and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2032 and 2032A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2032 and 2032A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. A7
(Figure 1). There are a total of eight GLBs in the ispLSI
2032 and 2032A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/ExclusiveORarray, andfouroutputswhichcan
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright©2002LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
2032_10
1
Specifications ispLSI 2032/A
Functional Block Diagram
Figure 1. ispLSI 2032/A Functional Block Diagram
GOE 0
I/O 31
I/O 0
I/O 1
I/O 30
A0
A7
I/O 29
I/O 28
I/O 2
I/O 3
I/O 27
I/O 26
I/O 4
I/O 5
Global Routing Pool
(GRP)
A1
A6
A5
A4
I/O 6
I/O 25
I/O 24
I/O 7
I/O 23
I/O 22
I/O 21
I/O 20
I/O 8
I/O 9
I/O 10
A2
I/O 11
I/O 12
I/O 13
I/O 19
I/O 18
I/O 17
I/O 16
I/O 14
A3
I/O 15
SDI/IN 0
SDO/IN 1
MODE
ispEN
Y0
*Y1/RESET
SCLK/Y2
Notes:
*Y1 and RESET are multiplexed on the same pin
0139B(1)isp/2000
The devices also have 32 I/O cells, each of which is GLBs. Delays through the GRP have been equalized to
directly connected to an I/O pin. Each I/O cell can be minimize timing skew.
individually programmed to be a combinatorial input,
Clocks in the ispLSI 2032 and 2032A devices are se-
output or bi-directional I/O pin with 3-state control. The
lected using the dedicated clock pins. Three dedicated
signal levels are TTL compatible voltages and the output
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
drivers can source 4 mA or sink 8 mA. Each output can
selected on a GLB basis. The asynchronous or Product
be programmed independently for fast or slow output
TermclockcanbegeneratedinanyGLBforitsownclock.
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
toasetof32universal I/Ocellsby theORP. EachispLSI
2032 and 2032A device contains one Megablock.
The GRP has as its inputs, the outputs from all of the
GLBs andallof theinputs from thebi-directionalI/O cells.
All of these signals are made available to the inputs of the
2
Specifications ispLSI 2032/A
1
Absolute Maximum Ratings
Supply Voltage V ...................................-0.5 to +7.0V
cc
Input Voltage Applied........................ -2.5 to V +1.0V
CC
Off-State Output Voltage Applied ..... -2.5 to V +1.0V
CC
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Commercial
Industrial
MIN.
4.75
4.5
0
MAX.
5.25
5.5
UNITS
V
V
V
V
T = 0°C to + 70°C
A
V
CC
Supply Voltage
T = -40°C to + 85°C
A
Input Low Voltage
Input High Voltage
0.8
V
V
IL
2.0
V +1
cc
IH
Table 2 - 0005/2032
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
PARAMETER
Dedicated Input Capacitance
TYPICAL
UNITS
TEST CONDITIONS
VCC = 5.0V, V = 2.0V
6
7
pf
pf
pf
C1
C2
C3
IN
VCC= 5.0V, VI/O = 2.0V
I/O Capacitance
10
VCC= 5.0V, VY = 2.0V
Clock Capacitance
Table 2-0006/2032
Data Retention Specifications
PARAMETER
Data Retention
MINIMUM
MAXIMUM
UNITS
Years
Cycles
20
–
–
Erase/Reprogram Cycles
10000
Table 2-0008A-isp
3
Specifications ispLSI 2032/A
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
-135, -150, -180 ≤ 1.5 ns
-80, -110 ≤ 3 ns
+ 5V
Input Rise and Fall Time
10% to 90%
R
1
2
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
1.5V
Device
Output
Test
Point
See Figure 2
Table 2-0003/2032
R
C
*
L
3-state levels are measured 0.5V from
steady-state active level.
Output Load Conditions (see Figure 2)
*
C includes Test Fixture and Probe Capacitance.
L
0213A
TEST CONDITION
R1
470Ω
∞
R2
CL
A
B
390Ω
390Ω
390Ω
35pF
35pF
35pF
Active High
Active Low
470Ω
Active High to Z
∞
390Ω
390Ω
5pF
at VOH-0.5V
C
Active Low to Z
at VOL+0.5V
470Ω
5pF
Table 2 - 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
CONDITION
IOL= 8 mA
MIN.
–
TYP. MAX. UNITS
–
–
0.4
–
V
VOL
VOH
IIL
IOH = -4 mA
2.4
–
V
Input or I/O Low Leakage Current 0V ≤ V ≤ V (Max.)
–
-10
10
µA
µA
µA
µA
mA
mA
mA
mA
IN
IL
Input or I/O High Leakage Current 3.5V ≤ V ≤ V
–
–
IIH
IN
CC
ispEN Input Low Leakage Current 0V ≤ V ≤ V
–
–
-150
-150
-200
–
IIL-isp
IIL-PU
IOS1
IN
IL
I/O Active Pull-Up Current
Output Short Circuit Current
0V ≤ V ≤ V
–
–
IN
IL
V = 5V, VOUT = 0.5V
–
–
CC
-180, -150
Others
–
60
40
40
ICC2, 4
IL
IH
Comm.
V = 0.0V, V = 3.0V
Operating Power Supply Current
–
–
fTOGGLE = 1 MHz
–
–
Industrial
Table 2-0007/2032
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using two 16-bit counters.
3. Typical values are at VCC= 5V and T = 25°C.
A
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC
.
4
Specifications ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
TEST4
COND.
-180
-150
-135
DESCRIPTION1
UNITS
2
PARAMETER
#
MIN. MAX. MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Prop. Delay, 4PT Bypass, ORP Bypass
Data Prop. Delay
Clk Frequency with Internal Feedback 3
–
5.0
7.5
–
–
–
5.5
8.0
–
–
–
7.5
10.0
–
ns
ns
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
2
3
4
5
6
7
8
9
–
180
125
200
154
111
167
3.0
–
137
100
167
4.0
–
MHz
MHz
MHz
ns
1
Clk Frequency with Ext. Feedback (tsu2 + tco1
)
–
–
–
–
Clk Frequency, Max. Toggle
–
–
–
–
GLB Reg Setup Time before Clk, 4 PT Bypass 3.0
–
–
–
A
–
GLB Reg. Clk to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clk, 4 PT Bypass
GLB Reg. Setup Time before Clk
–
0.0
4.0
–
4.0
–
4.5
–
4.5
–
ns
0.0
4.5
–
0.0
5.5
–
ns
–
–
–
–
ns
–
10 GLB Reg. Clk to Output Delay
11 GLB Reg. Hold Time after Clk
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
4.5
–
5.0
–
5.5
–
ns
–
0.0
–
0.0
–
0.0
–
ns
A
–
7.0
–
8.0
–
10.0
–
ns
4.0
–
4.5
–
5.0
–
ns
B
C
B
C
–
14 Input to Output Enable
10.0
10.0
5.0
5.0
–
11.0
11.0
5.0
5.0
–
12.0
12.0
6.0
6.0
–
ns
15 Input to Output Disable
–
–
–
ns
16 Global OE Output Enable
–
–
–
ns
17 Global OE Output Disable
–
–
–
ns
18 Ext. Synchronous Clk Pulse Duration, High
19 Ext. Synchronous Clk Pulse Duration, Low
2.5
2.5
3.0
3.0
3.0
3.0
ns
–
–
–
–
ns
twl
Table 2-0030B-180/2032
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
5
Specifications ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
TEST4
COND.
-110
-80
DESCRIPTION1
UNITS
2
PARAMETER
#
MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback3
–
–
10.0
13.0
–
–
–
15.0
18.5
–
ns
ns
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
2
3
4
5
6
7
8
9
111
77.0
125
5.5
–
84.0
57.0
83.0
7.5
–
MHz
MHz
MHz
ns
1
Clock Frequency with External Feedback(tsu2 + tco1
)
–
–
–
Clock Frequency, Max. Toggle
–
–
–
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
A
–
5.5
–
8.0
–
ns
0.0
7.5
–
0.0
9.5
–
ns
–
–
–
ns
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
6.5
–
9.5
–
ns
–
0.0
–
0.0
–
ns
A
–
13.5
–
19.5
–
ns
6.5
–
10.0
–
ns
B
C
B
C
–
14 Input to Output Enable
14.5
14.5
7.0
7.0
–
24.0
24.0
12.0
12.0
–
ns
15 Input to Output Disable
–
–
ns
16 Global OE Output Enable
–
–
ns
17 Global OE Output Disable
–
–
ns
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
4.0
4.0
6.0
6.0
ns
–
–
–
ns
twl
Table 2-0030B-110/2032
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
6
Specifications ispLSI 2032/A
Internal Timing Parameters1
Over Recommended Operating Conditions
-180
MIN. MAX. MIN. MAX. MIN. MAX.
-150
-135
2
PARAMETER
#
DESCRIPTION
UNITS
Inputs
tio
tdin
20 Input Buffer Delay
–
–
0.6
1.1
–
–
0.6
1.3
–
–
1.1
2.4
ns
ns
21 Dedicated Input Delay
GRP
22 GRP Delay
–
0.7
–
0.7
–
1.3
ns
tgrp
GLB
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
–
–
2.3
3.1
3.6
4.1
4.8
0.2
–
–
–
2.6
3.1
4.3
4.6
5.0
0.0
–
–
–
3.6
3.6
5.0
5.1
5.6
0.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
–
–
–
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
–
–
–
–
–
–
28 GLB Register Bypass Delay
–
–
–
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
0.5
1.8
–
0.7
1.8
–
0.3
3.0
–
–
–
–
0.7
1.0
2.8
5.9
0.8
1.2
2.9
6.9
0.7
1.1
4.4
6.4
–
–
–
–
–
–
tptre
–
–
–
tptoe
tptck
ORP
2.5 3.8
2.5 4.1 2.9 5.2
36 ORP Delay
–
–
0.7
0.2
–
–
0.8
0.3
–
–
1.3
0.3
ns
ns
torp
37 ORP Bypass Delay
torpbp
Outputs
tob
tsl
toen
38 Output Buffer Delay
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.2
10.0
3.2
ns
ns
ns
ns
ns
1.2
10.0
2.8
1.3
10.0
2.8
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
3.2
todis
tgoe
2.8
2.8
2.8
2.2
2.2
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.9
1.9
2.1
2.1
2.3 2.3
2.3 2.3
ns
ns
tgy0
1.9
1.9
2.1
2.1
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
–
–
–
6.4
ns
4.1
4.7
Table 2-0036C-180/2032
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Specifications ispLSI 2032/A
Internal Timing Parameters1
Over Recommended Operating Conditions
-110
-80
2
PARAMETER
Inputs
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
20 Input Buffer Delay
–
–
1.7
3.4
–
–
2.2
4.8
ns
ns
t
t
io
21 Dedicated Input Delay
din
GRP
grp
GLB
22 GRP Delay
–
1.7
–
2.6
ns
t
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
–
–
4.9
4.8
6.2
6.8
7.5
0.1
–
–
–
7.2
7.2
8.8
9.2
10.2
0.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
–
–
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
–
–
–
–
28 GLB Register Bypass Delay
–
–
29 GLB Register Setup Time befor Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
0.5
4.0
–
0.1
6.0
–
gsu
–
–
gh
0.6
1.8
5.9
7.1
0.4
2.2
8.8
12.8
gco
–
–
gro
–
–
ptre
–
–
ptoe
ptck
4.0 7.0 5.5 9.5
ORP
36 ORP Delay
–
–
1.5
0.5
–
–
2.1
0.6
ns
ns
t
t
orp
37 ORP Bypass Delay
orpbp
Outputs
38 Output Buffer Delay
–
–
–
–
–
–
–
–
–
–
2.4
10.0
6.4
ns
ns
ns
ns
ns
t
t
t
t
t
ob
1.2
10.0
4.0
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
sl
oen
odis
goe
6.4
4.0
5.6
3.0
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
3.2
3.2
4.6 4.6
4.6 4.6
ns
ns
t
t
gy0
3.2
3.2
gy1/2
Global Reset
45 Global Reset to GLB
–
–
12.8
Table 2-0036C-110/2032
ns
t
gr
9.0
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Specifications ispLSI 2032/A
ispLSI 2032/A Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
Ded. In
#21
I/O Delay
#20
GRP
#22
Reg 4 PT Bypass
GLB Reg Bypass
#28
ORP Bypass
#37
#38,
39
I/O Pin
(Output)
I/O Pin
(Input)
#24
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
Q
#36
#25, 26, 27
RST
#45
#29, 30,
31, 32
Reset
Control
PTs
RE
OE
CK
#33, 34,
35
#40, 41
#43, 44
#42
Y0,1,2
GOE 0
0491/2000
Derivations of tsu, th and tco from the Product Term Clock1
tsu
= Logic + Reg su - Clock (min)
= (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
= (#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
2.1 ns = (0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5)
th
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
1.5 ns = (0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1)
tco
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20+ #22+ #35) + (#31) + (#36 + #38)
7.7 ns = (0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2)
Note: Calculations are based upon timing specifications for the ispLSI 2032/A-180L
Table 2- 0042-16/2032
9
Specifications ispLSI 2032/A
Power Consumption
used. Figure 4 shows the relationship between power
and operating speed.
Power consumption in the ispLSI 2032 and 2032A de-
vices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
Figure 4. Typical Device Power Consumption vs fmax
120
110
ispLSI 2032/A (-150, -180)
100
90
80
70
60
ispLSI 2032/A (-80, -110, -135)
50
40
1
20
40 60
80 100 120 140 160 180
max (MHz)
f
Notes: Configuration of Two 16-bit Counters
Typical Current at 5V, 25° C
I
can be estimated for the ispLSI 2032/A using the following equation:
CC
For 2032/A -150, -180: I (mA) = 30 + (# of PTs 0.46) + (# of nets Max freq 0.012)
*
*
*
CC
For 2032/A -135, -110, -80: I (mA)= 21 + (# of PTs 0.30) + (# of nets Max freq 0.012)
*
*
*
CC
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I
CC
estimate is based on typical conditions (V
= 5.0V, room temperature) and an assumption of two GLB loads
CC
on average exists. These values are for estimates only. Since the value of I
is sensitive to operating conditions
CC
and the program in the device, the actual I
should be verified.
CC
0127A/2032A
10
Specifications ispLSI 2032/A
Pin Description
48-PIN TQFP
44-PIN PLCC
44-PIN TQFP
PIN NUMBERS
PIN NUMBERS
PIN NUMBERS
NAME
DESCRIPTION
9, 10, 11, 13,
14, 15, 16, 17,
20, 21, 22, 23,
25, 26, 27, 28,
33, 34, 35, 37,
38, 39, 40, 41,
44, 45, 46, 47,
I/O 0 - I/O 3
I/O 4 - I/O 7
15, 16, 17, 18,
19, 20, 21, 22,
25, 26, 27, 28,
29, 30, 31, 32,
37, 38, 39, 40,
41, 42, 43, 44,
3, 4, 5, 6,
7, 8, 9, 10
9, 10, 11, 12,
13, 14, 15, 16,
19, 20, 21, 22,
23, 24, 25, 26,
31 32, 33, 34,
35, 36, 37, 38,
41, 42, 43, 44,
Input/Output Pins — These are the general purpose
I/O pins used by the logic array.
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
1, 2, 3,
4
1, 2, 3,
4
40
5
GOE 0
Y0
2
Global Output Enable input pin.
43
5
11
Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
RESET/Y1
35
This pin performs two functions:
29
31
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
7
8
ispEN
13
14
7
8
Input — Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and SCLK
controls become active.
2
SDI/IN 0
Input — This pin performs two functions. When ispEN
is logic low, it functions as an input pin to load
programming data into the device. SDI/IN0 also is used
as one of the two control pins for the isp state machine.
When ispEN is high, it functions as a dedicated input
pin.
32
19
MODE
36
24
30
18
Input — When in ISP Mode, controls operation of ISP
state machine.
2
SDO/IN 1
Output/Input — This pin performs two functions. When
ispEN is logic low, it functions as an output pin to read
serial shift register data. When ispEN is high, it
functions as a dedicated input pin.
2
SCLK/Y2
33
27
29
Input — This pin performs two functions. When
ispEN is logic low, it functions as a clock pin for the
Serial Shift Register. When ispEN is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
GND
VCC
1, 23
12, 34
17, 39
6, 28
18, 42
6, 30
Ground (GND)
V
CC
1
NC
No Connect.
12, 24, 36, 48
Table 2-0002A-08isp/2032
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
11
Specifications ispLSI 2032/A
Pin Configuration
ispLSI 2032/A 44-Pin PLCC Pinout Diagram
6
5
4
3
2
1 44 43 42 41 40
I/O 28
I/O 29
I/O 30
I/O 31
Y0
7
39
38
37
36
35
34
33
32
31
30
29
I/O 18
8
I/O 17
I/O 16
9
10
11
12
13
14
15
16
17
MODE
RESET/Y1
VCC
VCC
ispLSI 2032/A
ispEN
1SDI/IN 0
I/O 0
SCLK/Y21
Top View
I/O 15
I/O 14
I/O 1
I/O 13
I/O 2
I/O 12
18 19 20 21 22 23 24 25 26 27 28
0123B/2032/A
1. Pins have dual function capability.
ispLSI 2032/A 44-Pin TQFP Pinout Diagram
44 43 42 41 40 39 38 37 36 35 34
I/O 28
1
33
I/O 18
I/O 17
I/O 16
2
I/O 29
I/O 30
32
31
3
4
5
6
7
I/O 31
Y0
30
29
28
27
MODE
RESET/Y1
VCC
SCLK/Y21
ispLSI 2032/A
VCC
ispEN
Top View
1SDI/IN 0
I/O 0
8
26
25
24
23
I/O 15
I/O 14
I/O 13
I/O 12
9
I/O 1
10
11
I/O 2
12 13 14 15 16 17 18 19 20 21 22
0851/2032/A
1. Pins have dual function capability.
12
Specifications ispLSI 2032/A
Pin Configuration
ispLSI 2032/A 48-Pin TQFP Pinout Diagram
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
NC1
I/O 28
I/O 29
I/O 30
1
2
I/O 18
I/O 17
I/O 16
MODE
RESET/Y12
VCC
SCLK/Y22
I/O 15
I/O 14
I/O 13
I/O 12
3
4
5
6
7
I/O 31
Y0
32
31
30
29
ispLSI 2032/A
VCC
ispEN
Top View
2SDI/IN 0
I/O 0
8
28
27
26
25
9
I/O 1
10
11
12
I/O 2
1NC
13 14 15 16 17 18 19 20 21 22 23 24
48-Pin TQFP-2032/A
1. NC pins are not to be connected to any active signal, Vcc or GND.
2. Pins have dual function capability.
13
Specifications ispLSI 2032/A
Part Number Description
ispLSI XXXX —XXX X XXX X
Device Family
Grade
Blank = Commercial
I = Industrial
Package
J = PLCC
T44 = TQFP
T48 = TQFP
Power
Device Number
2032
2032A
Speed
180 = 180 MHz
150 = 154 MHz
135 = 137 MHz
110 = 111 MHz
f
max
max
max
max
f
f
f
L = Low
0212A/2032
80 = 84 MHz fmax
ispLSI 2032/A Ordering Information
COMMERCIAL
ORDERING NUMBER
FAMILY
fmax (MHz)
180
180
180
154
154
154
137
137
137
111
111
111
84
tpd (ns)
5.0
5.0
5.0
5.5
5.5
5.5
7.5
7.5
7.5
10
PACKAGE
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
Table 2-0041A/2032A
ispLSI 2032A-180LJ44
ispLSI 2032A-180LT44
ispLSI 2032A-180LT48
ispLSI 2032A-150LJ44
ispLSI 2032A-150LT44
ispLSI 2032A-150LT48
ispLSI 2032A-135LJ44
ispLSI 2032A-135LT44
ispLSI 2032A-135LT48
ispLSI 2032A-110LJ44
ispLSI 2032A-110LT44
ispLSI 2032A-110LT48
ispLSI 2032A-80LJ44
ispLSI 2032A-80LT44
ispLSI 2032A-80LT48
ispLSI
10
10
15
84
15
84
15
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
15
ORDERING NUMBER
ispLSI 2032A-80LJ44I
ispLSI 2032A-80LT44I
ispLSI 2032A-80LT48I
PACKAGE
44-Pin PLCC
44-Pin TQFP
84
84
84
15
15
48-Pin TQFP
Table 2-0041B/2032A
14
Specifications ispLSI 2032/A
COMMERCIAL
FAMILY
fmax (MHz)
180
180
180
154
154
154
137
137
137
111
111
111
84
tpd (ns)
5.0
5.0
5.0
5.5
5.5
5.5
7.5
7.5
7.5
10
ORDERING NUMBER
PACKAGE
ispLSI 2032-180LJ
ispLSI 2032-180LT44
ispLSI 2032-180LT48
ispLSI 2032-150LJ
ispLSI 2032-150LT44
ispLSI 2032-150LT48
ispLSI 2032-135LJ
ispLSI 2032-135LT44
ispLSI 2032-135LT48
ispLSI 2032-110LJ
ispLSI 2032-110LT44
ispLSI 2032-110LT48
ispLSI 2032-80LJ
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
ispLSI
10
10
15
84
15
ispLSI 2032-80LT44
ispLSI 2032-80LT48
84
15
48-Pin TQFP
Table 2-0041A/2032
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
15
ORDERING NUMBER
ispLSI 2032-80LJI
PACKAGE
44-Pin PLCC
44-Pin TQFP
84
84
84
15
ispLSI 2032-80LT44I
ispLSI 2032-80LT48I
15
48-Pin TQFP
Table 2-0041C/2032
15
相关型号:
©2020 ICPDF网 联系我们和版权申明