ISPLSI1032E-70LTI [LATTICE]
High-Density Programmable Logic; 高密度可编程逻辑
| 型号： | ISPLSI1032E-70LTI |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | High-Density Programmable Logic |
| 文件： | 总16页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
®
ispLSI and pLSI 1032E
High-Density Programmable Logic
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
Output Routing Pool
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
D7 D6 D5 D4 D3 D2 D1 D0
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
D
D
D
D
Q
Q
Q
Q
Logic
Array
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
GLB
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
Global Routing Pool (GRP)
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
CLK
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— In-System Programmable (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
0139A(A1)-isp
Description
— Reprogram Soldered Devices for Faster Prototyping
The ispLSI and pLSI 1032E are High Density Program-
mable Logic Devices containing 192 Registers, 64
Universal I/O pins, eight Dedicated Input pins, four Dedi-
cated Clock Input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 1032E features 5-Volt
in-system programmability and in-system diagnostic ca-
pabilities. The ispLSI 1032E device offers non-volatile
reprogrammability of the logic, as well as the intercon-
nects to provide truly reconfigurable systems. It is
architecturally and parametrically compatible to the pLSI
1032E device, but multiplexes four input pins to control
in-system programming. A functional superset of the
ispLSI and pLSI 1032 architecture, the ispLSI and pLSI
1032E devices add two new global output enable pins.
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispEXPERT™ – LOGIC COMPILER AND COMPLETE
ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS
THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
The basic unit of logic on the ispLSI and pLSI 1032E
devices is the Generic Logic Block (GLB). The GLBs are
labeledA0, A1…D7(seeFigure1). Thereareatotalof32
GLBs in the ispLSI and pLSI 1032E devices. Each GLB
has 18 inputs, a programmable AND/OR/Exclusive OR
array, and four outputs which can be configured to be
either combinatorial or registered. Inputs to the GLB
come from the GRP and dedicated inputs. All of the GLB
outputs are brought back into the GRP so that they can
be connected to the inputs of any GLB on the device.
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright©1998LatticeSemiconductorCorp.Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
October 1998
1
1032E_06
Specifications ispLSI and pLSI 1032E
Functional Block Diagram
Figure 1. ispLSI and pLSI 1032E Functional Block Diagram
RESET
Input Bus
Generic
Logic Blocks
(GLBs)
Output Routing Pool (ORP)
GOE 1/IN 5
GOE 0/IN 4
D7
D6
D5
D4
D3
D2
D1
D0
I/O 47
I/O 46
I/O 45
I/O 44
C7
C6
C5
C4
I/O 0
I/O 1
I/O 2
I/O 3
A0
A1
A2
A3
I/O 43
I/O 42
I/O 41
I/O 40
I/O 4
I/O 5
I/O 6
I/O 7
Global
Routing
Pool
I/O 39
I/O 38
I/O 37
I/O 36
C3
C2
C1
C0
I/O 8
I/O 9
(GRP)
A4
A5
A6
A7
I/O 10
I/O 11
I/O 35
I/O 34
I/O 33
I/O 32
I/O 12
I/O 13
I/O 14
I/O 15
*SDI/IN 0
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
B0
B1
B2
B3
B4
B5
B6
B7
*MODE/IN 1
Clock
Distribution
Network
Output Routing Pool (ORP)
Input Bus
Megablock
*ispEN/NC
*ISP Control Functions for ispLSI 1032E Only
The devices also have 64 I/O cells, each of which is The GRP has, as its inputs, the outputs from all of the
directly connected to an I/O pin. Each I/O cell can be GLBs and all of the inputs from the bi-directional I/O cells.
individually programmed to be a combinatorial input, All of these signals are made available to the inputs of the
registered input, latched input, output or bi-directional GLBs. Delays through the GRP have been equalized to
I/O pin with 3-state control. The signal levels are TTL minimize timing skew.
compatible voltages and the output drivers can source 4
Clocks in the ispLSI and pLSI 1032E devices are se-
mA or sink 8 mA. Each output can be programmed
lected using the Clock Distribution Network. Four
independently for fast or slow output slew rate to mini-
dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into
mize overall output switching noise.
the distribution network, and five clock outputs (CLK 0,
Eight GLBs, 16 I/O cells, two dedicated inputs and one CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to
ORP are connected together to make a Megablock (see route clocks to the GLBs and I/O cells. The Clock Distri-
figure 1). The outputs of the eight GLBs are connected to bution Network can also be driven from a special clock
a set of 16 universal I/O cells by the ORP. Each ispLSI GLB (C0 on the ispLSI and pLSI 1032E devices). The
and pLSI 1032E device contains four Megablocks.
logic of this GLB allows the user to create an internal
clock from a combination of internal signals within the
device.
2
Specifications ispLSI and pLSI 1032E
1
Absolute Maximum Ratings
Supply Voltage V .................................. -0.5 to +7.0V
cc
Input Voltage Applied........................ -2.5 to V +1.0V
CC
Off-State Output Voltage Applied ..... -2.5 to V +1.0V
CC
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Commercial
Industrial
MIN.
4.75
4.5
0
MAX.
5.25
5.5
UNITS
V
V
V
V
T
T
= 0°C to + 70°C
A
A
V
CC
Supply Voltage
= -40°C to + 85°C
Input Low Voltage
Input High Voltage
0.8
V
V
IL
2.0
V +1
cc
IH
Table 2-0005/1032E
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
VCC = 5.0V, VPIN = 2.0V
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)
8
pf
C1
15
pf
VCC= 5.0V, VPIN = 2.0V
Y0 Clock Capacitance
C2
Table 2-0006/1032E
Data Retention Specifications
PARAMETER
Data Retention
MINIMUM
20
MAXIMUM
UNITS
Years
–
–
–
ispLSI Erase/Reprogram Cycles
pLSI Erase/Reprogram Cycles
10000
100
Cycles
Cycles
Table 2-0008/1032E
3
Specifications ispLSI and pLSI 1032E
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
-125
≤ 2 ns
≤ 3 ns
Input Rise and Fall Time
10% to 90%
+ 5V
Others
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
1.5V
R
1
Device
Output
Test
Point
See Figure 2
Table 2-0003/1032E
3-state levels are measured 0.5V from
steady-state active level.
R
2
C
L
*
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
470Ω
∞
R2
CL
*C includes Test Fixture and Probe Capacitance.
L
0213a
A
B
390Ω
390Ω
390Ω
35pF
35pF
35pF
Active High
Active Low
470Ω
Active High to Z
at VOH-0.5V
∞
390Ω
5pF
C
Active Low to Z
at VOL+0.5V
470Ω
390Ω
5pF
Table 2-0004/1032E
DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
CONDITION
IOL= 8 mA
MIN.
–
TYP. MAX. UNITS
–
–
0.4
–
V
V
V
OL
IOH = -4 mA
2.4
–
V
OH
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
0V ≤ V ≤ V (Max.)
–
-10
10
µA
µA
µA
µA
mA
mA
mA
I
I
I
I
I
IL
IH
IN
IL
3.5V ≤ V ≤ V
–
–
IN
CC
0V ≤ V ≤ V
–
–
-150
-150
-200
–
IL-isp
IL-PU
OS1
IN
IL
0V ≤ V ≤ V
–
–
IN
IL
Output Short Circuit Current
V = 5V, VOUT = 0.5V
–
–
CC
–
190
190
V = 0.5V, V = 3.0V
Commercial
Industrial
CC2, 4
IL
IH
Operating Power Supply Current
I
–
–
fCLOCK = 1 MHz
Table 2-0007/1032E
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at VCC= 5V and T = 25°C.
A
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC
.
4
Specifications ispLSI and pLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
TEST 4
COND.
-125
-100
DESCRIPTION1
UNITS
2
PARAMETER
#
MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback 3
–
–
7.5
10.0
–
–
10.0
12.5
–
ns
ns
t
pd1
2
3
4
5
6
7
8
9
–
t
f
f
f
t
t
pd2
125
91.0
167
5.0
–
100
71.0
125
7.0
–
MHz
MHz
MHz
ns
max (Int.)
max (Ext.)
max (Tog.)
su1
1
Clock Frequency with External Feedback
(
)
–
–
tsu2 + tco1
1
–
Clock Frequency, Max. Toggle
(
)
–
–
twh + tw1
–
GLB Reg. Setup Time before Clock,4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
A
5.0
6.0
ns
co1
–
–
0.0
6.0
–
–
–
0.0
8.0
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
h1
su2
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
6.0
–
7.0
–
co2
–
0.0
–
0.0
–
h2
A
–
10.0
–
13.5
–
r1
5.0
–
6.5
–
rw1
B
C
B
C
–
14 Input to Output Enable
12.0
12.0
7.0
7.0
–
15.0
15.0
9.0
9.0
–
ptoeen
ptoedis
goeen
goedis
wh
15 Input to Output Disable
–
–
16 Global OE Output Enable
–
–
17 Global OE Output Disable
–
–
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
3.0
3.0
3.0
4.0
4.0
3.5
–
–
–
wl
–
20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
–
–
su3
–
0.0
–
0.0
–
ns
th3
Table 2-0030A/1032E
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
5
Specifications ispLSI and pLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
TEST 4
COND.
-90
-80
-70
DESCRIPTION1
UNITS
2
PARAMETER
#
MIN. MAX. MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback 3
–
–
10.0
12.5
–
–
–
12.0
15.0
–
–
15.0
17.5
–
ns
ns
t
pd1
2
3
4
5
6
7
8
9
–
t
f
f
f
t
t
pd2
90.0
69.0
125
7.5
–
80.0
61.0
111
8.5
–
70.0
56.0
100
9.0
–
MHz
MHz
MHz
ns
max (Int.)
max (Ext.)
max (Tog.)
su1
1
Clock Frequency with External Feedback
(
)
–
–
–
tsu2 + tco1
1
–
Clock Frequency, Max. Toggle
(
)
–
–
–
twh + tw1
–
GLB Reg. Setup Time before Clock,4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
–
A
6.0
6.5
7.0
ns
co1
–
–
0.0
8.5
–
–
–
0.0
10.0
–
–
–
0.0
11.0
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
h1
su2
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
7.0
–
7.5
–
8.0
–
co2
–
0.0
–
0.0
–
0.0
–
h2
A
–
13.5
–
14.0
–
15.0
–
r1
6.5
–
8.0
–
10.0
–
rw1
B
C
B
C
–
14 Input to Output Enable
15.0
15.0
9.0
9.0
–
16.5
16.5
10.0
10.0
–
18.0
18.0
12.0
12.0
–
ptoeen
ptoedis
goeen
goedis
wh
15 Input to Output Disable
–
–
–
16 Global OE Output Enable
–
–
–
17 Global OE Output Disable
–
–
–
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
4.0
4.0
4.5
4.5
3.5
5.0
5.0
4.0
–
–
–
–
wl
–
20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.5
21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0
–
–
–
su3
–
–
0.0
–
0.0
–
ns
th3
Table 2-0030B/1032E
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
6
Specifications ispLSI and pLSI 1032E
1
Internal Timing Parameters
-125
MIN. MAX. MIN. MAX.
-100
2
PARAM.
#
DESCRIPTION
UNITS
Inputs
22 I/O Register Bypass
23 I/O Latch Delay
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
t
t
t
t
t
t
t
iobp
iolat
iosu
ioh
0.3
1.9
–
0.3
2.3
–
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
3.0
0.0
–
3.5
0.0
–
–
–
ioco
ior
4.6
4.6
2.3
5.0
5.0
2.7
–
–
–
–
din
GRP
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 32 GLB Loads
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
t
t
t
grp1
grp4
grp8
1.8
2.0
2.3
2.8
3.8
1.9
2.4
2.4
3.0
4.2
tgrp16
tgrp32
GLB
34 4 Prod.Term Bypass Path Delay (Combinatorial)
35 4 Prod. Term Bypass Path Delay (Registered)
36 1 Prod.Term/XOR Path Delay
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
3.9
4.0
3.6
5.0
5.0
0.4
–
5.3
5.3
4.6
5.8
6.3
1.0
–
t
t
t
t
t
t
t
t
t
t
t
t
–
–
37 20 Prod. Term/XOR Path Delay
38 XOR Adjacent Path Delay 3
–
–
–
–
39 GLB Register Bypass Delay
–
–
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
42 GLB Register Clock to Output Delay
43 GLB Register Reset to Output Delay
44 GLB Prod.Term Reset to Register Delay
45 GLB Prod. Term Output Enable to I/O Cell Delay
46 GLB Prod. Term Clock Delay
0.1
4.5
–
0.5
5.8
–
gsu
gh
–
–
gco
2.3
4.9
3.9
5.4
4.0
2.5
6.2
4.5
7.2
4.7
–
–
gro
–
–
ptre
–
–
ptoe
ptck
2.9
3.5
ORP
47 ORP Delay
ns
ns
–
–
–
–
t
orp
1.0
0.0
1.0
0.0
48 ORP Bypass Delay
torpbp
Table 2-0036A/1032E
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Specifications ispLSI and pLSI 1032E
1
Internal Timing Parameters
-80
-70
-90
2
PARAM.
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
–
–
22 I/O Register Bypass
23 I/O Latch Delay
–
–
ns
ns
ns
ns
ns
ns
ns
0.3
2.3
–
t
t
t
t
t
t
t
iobp
iolat
iosu
ioh
0.3
2.7
–
–
–
0.3
3.3
–
3.5
0.0
–
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
3.5
0.0
–
4.0
0.0
–
–
–
–
5.0
5.0
2.6
ioco
ior
5.4
5.4
2.8
6.1
6.0
2.8
–
–
–
–
–
din
–
GRP
–
–
–
–
–
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 32 GLB Loads
–
–
–
–
–
ns
ns
ns
ns
ns
2.1
2.3
2.6
3.2
4.4
t
t
t
grp1
grp4
grp8
2.2
2.5
2.8
3.5
4.8
–
–
–
–
–
2.5
2.5
3.2
4.0
5.6
t
grp16
t
grp32
GLB
–
–
34 4 Prod.Term Bypass Path Delay (Combinatorial)
35 4 Prod. Term Bypass Path Delay (Registered)
36 1 Prod.Term/XOR Path Delay
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.7
6.1
5.6
6.8
7.1
0.4
–
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
7.1
6.7
6.6
7.8
8.2
1.3
–
–
–
8.8
7.2
8.3
8.7
9.2
1.6
–
t
t
t
t
t
t
t
t
t
t
t
t
–
–
–
–
37 20 Prod. Term/XOR Path Delay
38 XOR Adjacent Path Delay 3
–
–
–
–
–
–
–
39 GLB Register Bypass Delay
–
0.2
6.8
–
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
42 GLB Register Clock to Output Delay
43 GLB Register Reset to Output Delay
44 GLB Prod.Term Reset to Register Delay
45 GLB Prod. Term Output Enable to I/O Cell Delay
46 GLB Prod. Term Clock Delay
0.5
7.9
–
gsu
0.5
8.8
–
–
gh
–
–
2.9
6.3
5.1
7.1
5.3
gco
2.9
6.4
5.5
8.0
2.9
6.8
5.8
9.0
6.2
–
–
gro
–
–
–
ptre
–
–
–
ptoe
ptck
–
4.1
4.5
5.8 4.8
ORP
–
–
47 ORP Delay
–
–
ns
ns
1.0
0.0
t
t
orp
1.0
0.0
–
–
1.0
0.0
48 ORP Bypass Delay
orpbp
Table 2-0036B/1032E
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Specifications ispLSI and pLSI 1032E
1
Internal Timing Parameters
-125
MIN. MAX. MIN. MAX.
-100
PARAM.
#
DESCRIPTION
UNITS
Outputs
1.3
9.9
4.3
4.3
2.7
2.0
10.0
5.1
–
–
–
–
–
–
–
–
–
–
49 Output Buffer Delay
ns
ns
ns
ns
ns
t
t
t
t
t
ob
50 Output Buffer Delay, Slew Limited Adder
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
sl
oen
odis
goe
5.1
3.9
Clocks
1.4
1.4
1.8
0.0
1.8
1.5
1.5
1.8
0.0
1.8
1.4
1.4
0.8
0.0
0.8
1.5
1.5
0.8
0.0
0.8
54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk)
55 Clk Delay, Y1 or Y2 to Global GLB Clk Line
56 Clk Delay, Clock GLB to Global GLB Clk Line
57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line
58 Clk Delay, Clk GLB to I/O Cell Global Clk Line
ns
ns
ns
ns
ns
t
t
t
t
t
gy0
gy1/2
gcp
ioy2/3
iocp
Global Reset
2.8
4.3
–
–
59 Global Reset to GLB and I/O Registers
ns
tgr
Table 2-0037A/1032E
1. Internal Timing Parameters are not tested and are for reference only.
9
Specifications ispLSI and pLSI 1032E
1
Internal Timing Parameters
-80
-70
-90
PARAM.
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Outputs
1.7
10.0
5.3
2.1
10.0
5.7
–
–
–
–
–
2.6
10.0
6.2
49 Output Buffer Delay
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
t
t
t
t
t
ob
50 Output Buffer Delay, Slew Limited Adder
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
sl
oen
odis
goe
5.3
5.7
6.2
3.7
4.3
5.8
Clocks
1.4
2.9
1.8
0.0
1.8
1.5
3.1
1.8
0.0
1.8
1.5 1.5
1.5 1.5
0.8 1.8
0.0 0.0
0.8 1.8
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
56 Clock Delay, Clock GLB to Global GLB Clock Line
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
1.4
2.4
0.8
0.0
0.8
1.5
2.6
0.8
0.0
0.8
ns
ns
ns
ns
ns
t
t
t
t
t
gy0
gy1/2
gcp
ioy2/3
iocp
Global Reset
4.5
4.5
–
4.6
59 Global Reset to GLB and I/O Registers
–
–
ns
tgr
Table 2-0037B/1032E
1. Internal Timing Parameters are not tested and are for reference only.
10
Specifications ispLSI and pLSI 1032E
ispLSI and pLSI 1032E Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
#34
Ded. In
Comb 4 PT Bypass
#28
I/O Reg Bypass
#22
GRP4
#30
Reg 4 PT Bypass
#35
GLB Reg Bypass
#39
ORP Bypass
#48
#49, 50
I/O Pin
(Input)
I/O Pin
(Output)
Input
Register
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
GRP Loading
Delay
Q
D
#51, 52
RST
D
Q
#47
#36 - 38
#59
#29, 31 - 33
#59
#23 - 27
RST
Reset
#40 - 43
Clock
Control
PTs
RE
OE
CK
Distribution
0491
Y1,2,3
#55 - 58
#44 - 46
#54
#53
Y0
GOE 0,1
Derivations of tsu, th and tco from the Product Term Clock1
tsu
th
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))
= (#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
2.2 ns = (0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
= Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
3.5 ns
= (0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
tco
= Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#22 + #30 + #46) + (#42) + (#47 + #49)
10.9 ns = (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
1
Derivations of tsu, th and tco from the Clock GLB
tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))
= (#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
2.9 ns = (0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8)
th
= Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
= (#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
= (1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
2.7 ns
tco
= Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#54 + #42 + #56) + (#42) + (#47 + #49)
5.5 ns = (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032E-125.
Table 2-0042a/1032E
11
Specifications ispLSI and pLSI 1032E
Maximum GRP Delay vs GLB Loads
6.0
ispLSI and pLSI 1032E-70
5.0
4.0
ispLSI and pLSI 1032E-80
ispLSI and pLSI 1032E-90/100
ispLSI and pLSI 1032E-125
3.0
2.0
1.0
1
4
8
16
32
GLB Load
GRP/GLB/1032E
Power Consumption
Power consumption in the ispLSI and pLSI 1032E device used. Figure 3 shows the relationship between power
depends on two primary factors: the speed at which the and operating speed.
device is operating, and the number of product terms
Figure 3. Typical Device Power Consumption vs fmax
350
ispLSI and pLSI 1032E
300
250
200
150
100
40
20
60
80
125
150
0
100
f
max (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
I CC can be estimated for the ispLSI and pLSI 1032E using the following equation:
I CC(mA) = 15 + (# of PTs 0.59) + (# of nets Max freq 0.0078)
*
*
*
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (V
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.
= 5.0V, room temperature) and an assumption of four GLB
CC
0127/1032E
12
Specifications ispLSI and pLSI 1032E
Pin Description
PLCC PIN
NUMBERS
TQFP PIN
NUMBERS
NAME
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic
array.
26, 27, 28, 29,
30, 31, 32, 33,
34, 35, 36, 37,
38, 39, 40, 41,
45, 46, 47, 48,
49, 50, 51, 52,
53, 54, 55, 56,
57, 58, 59, 60,
68, 69, 70, 71,
72, 73, 74, 75,
76, 77, 78, 79,
80, 81, 82, 83,
I/O 0 - I/O 3
I/O 4 - I/O 7
17, 18, 19, 20,
21, 22, 23, 28,
29, 30, 31, 32,
33, 34, 35, 36,
40, 41, 42, 43,
44, 45, 46, 47,
48, 53, 54, 55,
56, 57, 58, 59,
67, 68, 69, 70,
71, 72, 73, 78,
79, 80, 81, 82,
83, 84, 85, 86,
90, 91, 92, 93,
94, 95, 96, 97,
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
3,
7,
4,
8,
5, 6,
9, 10,
11, 12, 13, 14,
15, 16, 17, 18
98,
6,
3,
7,
4, 5,
8,
9
GOE 0/IN 43
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
67
66
GOE 1/IN 53
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
84
87
2,
19
Dedicated input pins to the device.
89, 10
14
IN 6, IN 7
ispEN/NC1,2
23
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK options become active.
SDI/IN 02
25
Input - This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. SDI/IN 0 is also
used as one of the two control pins for the isp state machine. It is a
dedicated input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it functions
as pin to control the operation of the isp state machine. It is a dedicated
input pin when ispEN is logic high.
16
MODE/IN 12
SDO/IN 22
SCLK/IN 32
42
44
61
37
39
60
Output/Input - This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it functions
as a clock pin for the Serial Shift Register. It is a dedicated input pin when
ispEN is logic high.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the
device.
RESET
Y0
24
20
66
15
11
65
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB on the device.
Y1
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB and/or any I/O cell on the
device.
Y2
Y3
63
62
62
61
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any I/O cell on the device.
Ground (GND)
Vcc
1, 22, 43, 64
21, 65
GND
VCC
13, 38, 63, 88
12, 64
1
NC
1, 2,
24, 25, No connect.
26, 27, 49, 50,
51, 52, 74, 75,
76, 77, 99, 100
Table 2-0002A/1032E
1. NC pins are not to be connected to any ative signals, Vcc or GND.
2. Pins have dual function capability for ispLSI 1032E only.
3. Pins have dual function capability which is software selectable.
13
Specifications ispLSI and pLSI 1032E
Pin Configurations
ispLSI and pLSI 1032E 84-Pin PLCC Pinout Diagram
11 10 9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 62
I/O 63
I/O 33
I/O 32
GOE 0/IN 43
Y1
IN 7
Y0
VCC
VCC
ispLSI 1032E
GND
1,2ispEN/NC
GND
Y2
pLSI 1032E
RESET
Y3
Top View
2SDI/IN 0
I/O 0
SCLK/IN 32
I/O 31
I/O 1
I/O 30
I/O 2
I/O 29
I/O 3
I/O 4
I/O 5
I/O 6
I/O 28
I/O 27
I/O 26
I/O 25
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
1. NC pins are not to be connected to any active signals, Vcc or GND.
2. Pins have dual function capability for ispLSI 1032E only (except pin 23, which is ispEN only).
3. Pins have dual function capability which is software selectable.
0123-32-isp
14
Specifications ispLSI and pLSI 1032E
Pin Configurations
ispLSI 1032E 100-Pin TQFP Pinout Diagram
NC
NC
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
IN 7
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
GOE 0/IN 42
Y1
VCC
GND
Y2
Y3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Y0
VCC
ispLSI 1032E
GND
ispEN
RESET
1SDI/IN 0
I/O 0
Top View
SCLK/IN 31
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
NC
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
NC
NC
NC
1. Pins have dual function capability.
2. Pins have dual function capability which is software selectable.
0766A-32E-isp
15
Specifications ispLSI and pLSI 1032E
Part Number Description
(is)pLSI
–
1032E XXX
X
X
X
Device Family
Grade
Blank = Commercial
I = Industrial
Package
Device Number
J = PLCC
T = TQFP
Speed
Power
L = Low
125 = 125 MHz
100 = 100 MHz
f
f
max
max
0212/1032E
90 = 90 MHz
80 = 80 MHz
70 = 70 MHz
f
f
f
max
max
max
ispLSI and pLSI 1032E Ordering Information
COMMERCIAL
FAMILY
fmax (MHz)
tpd (ns)
7.5
7.5
10
ORDERING NUMBER
ispLSI 1032E-125LJ
ispLSI 1032E-125LT
ispLSI 1032E-100LJ
ispLSI 1032E-100LT
ispLSI 1032E-90LJ*
ispLSI 1032E-90LT*
ispLSI 1032E-80LJ*
PACKAGE
84-Pin PLCC
100-Pin TQFP
84-Pin PLCC
100-Pin TQFP
84-Pin PLCC
100-Pin TQFP
84-Pin PLCC
125
125
100
100
90
10
ispLSI
10
90
10
80
12
80
70
12
15
15
7.5
ispLSI 1032E-80LT*
ispLSI 1032E-70LJ
ispLSI 1032E-70LT
pLSI 1032E-125LJ
pLSI 1032E-100LJ
pLSI 1032E-90LJ*
pLSI 1032E-80LJ*
pLSI 1032E-70LJ
100-Pin TQFP
84-Pin PLCC
100-Pin TQFP
84-Pin PLCC
84-Pin PLCC
84-Pin PLCC
84-Pin PLCC
84-Pin PLCC
70
125
100
90
10
10
12
15
pLSI
80
70
Table 2-0041A/1032E
*Use ispLSI 1032E-100 for all new designs.
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
15
ORDERING NUMBER
ispLSI 1032E-70LJI
ispLSI 1032E-70LTI
PACKAGE
84-Pin PLCC
100-Pin TQFP
70
70
15
Table 2-0041B/1032E
16
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