ISPLSI1032-90 [LATTICE]
In-System Programmable High Density PLD; 在系统可编程高密度PLD
| 型号： | ISPLSI1032-90 |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | In-System Programmable High Density PLD |
| 文件： | 总16页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ispLSI 1032
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
Output Routing Pool
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
D7 D6 D5 D4 D3 D2 D1 D0
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 90 MHz Maximum Operating Frequency
C7
C6
C5
C4
C3
C2
C1
C0
A0
A1
A2
A3
A4
A5
A6
A7
D
D
D
D
Q
Q
Q
Q
Logic
Array
GLB
—— tfpmdax= =1260nsMPHrzofpoargIantdiounstDrieallaaynd Military/883 Devices
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
• IN-SYSTEM PROGRAMMABLE
CLK
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Description
The ispLSI 1032 is a High-Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1032 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
thefirstdevicewhichoffersnon-volatilereprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
The basic unit of logic on the ispLSI 1032 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright©1999LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
March 1999
1
1032_07
Specifications ispLSI 1032
Functional Block Diagram
Figure 1. ispLSI 1032 Functional Block Diagram
I/O I/O I/OI/O
63 62 61 60
I/O I/OI/OI/O
59 58 57 56
I/O I/O I/O I/O
55 54 53 52
I/O I/O I/O I/O
51 50 49 48
IN IN
7
6
RESET
Input Bus
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
IN 5
IN 4
D7
D6
D5
D4
D3
D2
D1
D0
I/O 47
I/O 46
I/O 45
I/O 44
C7
C6
C5
C4
I/O 0
I/O 1
I/O 2
I/O 3
A0
A1
A2
A3
I/O 43
I/O 42
I/O 41
I/O 4
I/O 5
I/O 6
I/O 7
I/O 40
Global
Routing
Pool
I/O 39
I/O 38
I/O 37
I/O 36
C3
C2
C1
C0
(GRP)
I/O 8
A4
A5
A6
A7
I/O 9
I/O 10
I/O 11
I/O 35
I/O 34
I/O 33
I/O 32
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
CLK 0
B0
B1
B2
B3
B4
B5
B6
B7
MODE/IN 1
CLK 1
CLK 2
Clock
Distribution
Network
IOCLK 0
IOCLK 1
Output Routing Pool (ORP)
Input Bus
Megablock
ispEN
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
Y
0
Y
1
Y
2
Y
3
SDO/IN 2
SCLK/IN 3
0139(1)-32-isp
The device also has 64 I/O cells, each of which is directly TheGRPhasasitsinputstheoutputsfromalloftheGLBs
connected to an I/O pin. Each I/O cell can be individually and all of the inputs from the bi-directional I/O cells. All of
programmed to be a combinatorial input, registered in- these signals are made available to the inputs of the
put, latched input, output or bi-directional I/O pin with GLBs. Delays through the GRP have been equalized to
3-state control. Additionally, all outputs are polarity se- minimize timing skew.
lectable, active high or active low. The signal levels are
Clocks in the ispLSI 1032 device are selected using the
TTL compatible voltages and the output drivers can
Clock Distribution Network. Four dedicated clock pins
source 4 mA or sink 8 mA.
(Y0, Y1, Y2 and Y3) are brought into the distribution
Eight GLBs, 16 I/O cells, two dedicated inputs and one network, and five clock outputs (CLK 0, CLK 1, CLK 2,
ORP are connected together to make a Megablock (see IOCLK 0 and IOCLK 1) are provided to route clocks to the
figure 1). The outputs of the eight GLBs are connected to GLBs and I/O cells. The Clock Distribution Network can
a set of 16 universal I/O cells by the ORP. The I/O cells alsobedrivenfromaspecialclockGLB (C0ontheispLSI
within the Megablock also share a common Output 1032 device). The logic of this GLB allows the user to
Enable(OE)signal. TheispLSI1032devicecontainsfour create an internal clock from a combination of internal
of these Megablocks.
signals within the device.
2
Specifications ispLSI 1032
1
Absolute Maximum Ratings
Supply Voltage V .................................. -0.5 to +7.0V
cc
Input Voltage Applied........................ -2.5 to V +1.0V
CC
Off-State Output Voltage Applied ..... -2.5 to V +1.0V
CC
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
MIN.
MAX.
5.25
5.5
UNITS
Commercial TA = 0°C to +70°C
4.75
4.5
4.5
0
Supply Voltage
V
V
V
CC
Industrial
TA = -40°C to +85°C
TC = -55°C to +125°C
Military/883
5.5
Input Low Voltage
Input High Voltage
V
V
IL
0.8
IH
V
2.0
Vcc + 1
Table 2- 0005Aisp w/mil.eps
Capacitance (TA=25oC, f=1.0 MHz)
1
SYMBOL PARAMETER
MAXIMUM
UNITS
TEST CONDITIONS
C1
Commercial/Industrial
Military
8
pf
VCC=5.0V, VIN=2.0V
Dedicated Input Capacitance
10
10
pf
pf
VCC=5.0V, VIN=2.0V
C2
I/O and Clock Capacitance
VCC=5.0V, VI/O, VY=2.0V
Table 2- 0006
1. Guaranteed but not 100% tested.
Data Retention Specifications
PARAMETER
Data Retention
MINIMUM
20
MAXIMUM
UNITS
Years
Cycles
—
—
Erase/Reprogram Cycles
10000
Table 2- 0008B
3
Specifications ispLSI 1032
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
≤ 3ns 10% to 90%
1.5V
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
+ 5V
1.5V
R
1
See figure 2
Device
Output
Test
Point
3-state levels are measured 0.5V from steady-state
active level.
Table 2- 0003
R
2
C *
L
Output Load Conditions (see figure 2)
*
C includes Test Fixture and Probe Capacitance.
L
Test Condition
R1
R2
CL
A
470Ω
390Ω
390Ω
390Ω
390Ω
35pF
35pF
35pF
5pF
B
Active High
Active Low
∞
470Ω
Active High to Z
at VOH - 0.5V
∞
C
Active Low to Z
470Ω
390Ω
5pF
at VOL + 0.5V
DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL
PARAMETER
CONDITION
MIN. TYP.
MAX.
UNITS
V
Output Low Voltage
Output High Voltage
–
2.4
–
–
–
0.4
–
IOL =8 mA
V
V
OL
V
IOH =-4 mA
OH
µA
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
isp Input Low Leakage Current
I/O Active Pull-Up Current
–
-10
10
0V ≤ VIN ≤ VIL (MAX.)
3.5V ≤ VIN ≤ VCC
I
I
I
I
I
IL
µA
–
–
IH
µA
–
–
-150
-150
-200
190
220
0V ≤ VIN ≤ VIL (MAX.)
0V ≤ VIN ≤ VIL
IL-isp
IL-PU
µA
–
–
mA
mA
mA
1
Output Short Circuit Current
–
–
VCC = 5V, VOUT = 0.5V
VIL = 0.5V, VIH = 3.0V Commercial
OS
2,4
Operating Power Supply Current
–
130
135
I
CC
–
fTOGGLE = 1 MHz
Industrial/Military
Table 2- 0007A-32-isp
1. One output at a time for a maximum duration of one second.
2. Measured using eight 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25oC.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
ICC.
4
Specifications ispLSI 1032
External Timing Parameters
Over Recommended Operating Conditions
-90
-80
-60
5
2
1
TEST
PARAMETER
#
DESCRIPTION
UNITS
COND.
MIN. MAX. MIN. MAX. MIN. MAX.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
1
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
–
–
12
17
–
–
–
15
20
–
–
–
20
25
–
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
ns
ns
2
3
4
5
6
7
8
9
pd2
3
Clock Frequency with Internal Feedback
90.9
58.8
125
6
80
50
100
7
60
38
83
9
max (Int.)
max (Ext.)
max (Tog.)
su1
MHz
MHz
MHz
ns
1
Clock Frequency with External Feedback
–
–
–
(
)
tsu2 + tco1
4
Clock Frequency, Max Toggle
–
–
–
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg. Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
–
–
–
–
8
–
10
–
–
13
–
co1
ns
0
–
0
0
h1
ns
9
–
10
–
–
13
–
–
su2
ns
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
–
10
–
12
–
16
–
co2
ns
0
0
0
h2
ns
–
15
–
–
17
–
–
22.5
–
r1
ns
10
–
10
–
13
–
rw1
ns
14 Input to Output Enable
15
15
–
18
18
–
24
24
–
en
ns
15 Input to Output Disable
–
–
–
dis
ns
16 Ext. Sync. Clock Pulse Duration, High
17 Ext. Sync. Clock Pulse Duration, Low
4
5
6
wh
ns
4
–
5
–
6
–
wl
ns
18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
2
–
2
–
2.5
8.5
–
su5
ns
6.5
–
6.5
–
–
h5
ns
Table 2-0030-32/90,80,60C
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
5
Specifications ispLSI 1032
1
Internal Timing Parameters
-90
-80
-60
2
PARAMETER
DESCRIPTION
UNITS
#
MIN. MAX. MIN. MAX.
MIN. MAX.
Inputs
–
–
1.6
2.4
–
–
–
2.0
3.0
–
t
t
t
t
t
t
t
iobp
iolat
iosu
ioh
I/O Register Bypass
–
–
2.7
4.0
–
20
21
22
23
24
25
26
ns
ns
ns
ns
ns
ns
ns
I/O Latch Delay
4.8
2.1
–
5.5
1.0
–
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
7.3
1.3
–
–
–
–
2.4
2.8
3.2
3.0
2.5
4.0
ioco
ior
4.0
3.3
5.3
–
–
–
–
–
din
–
GRP
–
–
–
–
–
–
1.2
1.6
2.4
3.0
3.6
6.4
–
–
–
–
–
–
1.5
2.0
3.0
3.8
4.5
8.0
t
t
t
t
t
t
grp1
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 32 GLB Loads
–
–
–
–
–
–
2.0
2.7
4.0
5.0
6.0
10.6
27
28
29
30
31
32
ns
ns
ns
ns
ns
ns
grp4
grp8
grp12
grp16
grp32
GLB
–
–
5.2
5.7
7.0
8.2
0.8
–
–
–
6.5
7.0
8.0
9.5
1.0
–
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
t
t
t
t
t
t
t
t
t
t
t
t
4ptbp
1ptxor
20ptxor
xoradj
gbp
33
34
35
36
37
38
39
40
41
42
43
44
–
–
8.6
9.3
10.6
12.7
1.3
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
3
–
–
XOR Adjacent Path Delay
–
–
–
GLB Register Bypass Delay
–
1.2
3.6
–
1.0
4.5
–
gsu
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
1.3
6.0
–
–
–
gh
–
1.6
2.0
8.0
7.8
2.0
2.5
10.0
9.0
gco
2.7
3.3
13.3
12.0
–
–
gr
–
–
–
ptre
–
–
–
ptoe
ptck
–
2.8 6.0 3.5 7.5
4.6 9.9
ORP
–
–
2.4
0.4
–
–
2.5
0.5
t
orp
ORP Delay
–
–
3.3
0.7
45
46
ns
ns
ORP Bypass Delay
torpbp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
Specifications ispLSI 1032
1
Internal Timing Parameters
-90
-80
-60
2
PARAMETER
DESCRIPTION
UNITS
#
MIN. MAX.
MIN. MAX. MIN. MAX.
Outputs
–
–
–
2.4
4.0
4.0
t
t
t
ob
Output Buffer Delay
–
–
–
3.0
5.0
5.0
–
–
–
4.0
6.7
6.7
47
48
49
ns
ns
ns
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
oen
odis
Clocks
3.6 3.6
2.8 4.4
0.8 4.0
2.8 4.4
0.8 4.0
t
t
t
t
t
gy0
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
4.5 4.5 6.0 6.0
3.5 5.5 4.6 7.3
1.0 5.0 1.3 6.6
3.5 5.5 4.6 7.3
1.0 5.0 1.3 6.6
50
51
52
53
54
ns
ns
ns
ns
ns
gy1/2
gcp
ioy2/3
iocp
Global Reset
–
8.2
tgr
Global Reset to GLB and I/O Registers
–
9.0
–
12.0
55
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
7
Specifications ispLSI 1032
ispLSI 1032 Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
#26
I/O Reg Bypass
GRP 4
#28
4 PT Bypass
#33
GLB Reg Bypass
#37
ORP Bypass
#46
#47
I/O Pin
#20
I/O Pin
(Output)
#48, 49
(Input)
Input
Register
GRP
Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
Q
D
RST
D
Q
#45
#34, 35, 36
#55
#27, 29,
30, 31, 32
#55
#21 - 25
RST
#38, 39,
40, 41
Reset
Clock
Control
PTs
RE
OE
CK
Distribution
Y1,2,3
Y0
#51, 52,
53, 54
#42, 43,
44
#50
1
Derivations of tsu, th and tco from the Product Term Clock
tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
= (#20 + #28 + #35) + (#38) - (#20 + #28 + #44)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5)
th
= Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#20 + #28 + #44) + (#39) - (#20 + #28 + #35)
4.0 ns = (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0)
tco
= Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #28 + #44) + (#40) + (#45 + #47)
19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0)
1
Derivations of tsu, th and tco from the Clock GLB
tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))
= (#20 + #28 + #35) + (#38) - (#50 + #40 + #52)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0)
th
= Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#50 + #40 + #52) + (#39) - (#20 + #28 + #35)
4.0 ns = (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0)
tco
= Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#50 + #40 + #52) + (#40) + (#45 + #47)
19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0)
1. Calculations are based upon timing specifications for the ispLSI 1032-80.
8
Specifications ispLSI 1032
Maximum GRP Delay vs GLB Loads
ispLSI 1032-60
6
5
4
3
2
1
ispLSI 1032-80
ispLSI 1032-90
0
4
8
12
16
GLB Loads
0126A-80-32-isp
Power Consumption
Power consumption in the ispLSI 1032 device depends ure 3 shows the relationship between power and operat-
on two primary factors: the speed at which the device is ing speed.
operating, and the number of Product Terms used. Fig-
Figure 3. Typical Device Power Consumption vs fmax
250
ispLSI 1032
200
150
100
50
0
10
20 30
40 50 60 70 80
fmax (MHz)
Notes: Configuration of eight 16-bit Counters
Typical Current at 5V, 25ßC
I
I
can be estimated for the ispLSI 1032 using the following equation:
= 52 + (# of PTs * 0.30) + (# of nets * Max. freq * 0.009) where:
CC
CC
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The I
estimate is based on typical conditions (V
= 5.0V, room temperature) and an assumption of 2 GLB loads on
CC
CC
average exists. These values are for estimates only. Since the value of I
program in the device, the actual I
is sensitive to operating conditions and the
CC
should be verified.
CC
0127A-32-80-isp
9
Specifications ispLSI 1032
Pin Description
Name
PLCC Pin Numbers
Description
Input/OutputPins-ThesearethegeneralpurposeI/Opinsusedbythe
logic array.
I/O 0 - I/O 3
I/O 4 - I/O 7
26,
30,
34,
38,
45,
49,
53,
57,
68,
72,
76,
80,
3,
27,
31,
35,
39,
46,
50,
54,
58,
69,
73,
77,
81,
4,
28,
32,
36,
40,
47,
51,
55,
59,
70,
74,
78,
82,
5,
29,
33,
37,
41,
48,
52,
56,
60,
71,
75,
79,
83,
6,
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
7,
11,
15,
8,
12,
16,
9,
13,
17,
10,
14,
18
Dedicated input pins to the device.
IN 4 - IN 7
ispEN
67,
23
84,
2,
19
Input —Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
1
SDI/IN 0
25
Input—Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
1
MODE/IN 1
42
44
61
Input—Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
1
SDO/IN 2
Input/Output —This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
1
SCLK/IN 3
Input —This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
RESET
Y0
24
20
66
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Y1
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Y2
Y3
63
62
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
GND
1,
21,
22,
65
43,
64
Ground (GND)
VCC
VCC
1. Pins have dual function capability
10
Specifications ispLSI 1032
Pin Description
Name
Description
TQFP Pin Numbers
I/O 0 - I/O 3
I/O 4 - I/O 7
17,
21,
29,
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
6,
18,
22,
30,
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
3,
19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
20,
28,
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
Input/OutputPins-ThesearethegeneralpurposeI/Opinsusedbythe
logic array.
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
7,
8,
9
Dedicated input pins to the device.
IN 4 - IN 7
ispEN
66,
14
87,
89,
10
Input —Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
1
SDI/IN 0
16
Input—Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
1
MODE/IN 1
37
39
60
1,
Input—Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
1
SDO/IN 2
Input/Output —This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
1
SCLK/IN 3
Input —This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
2
No Connect
NC
2,
24,
25,
26,
51,
76,
27,
52,
77,
49,
74,
99,
50,
75
100
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
RESET
Y0
15
11
65
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Y1
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Y2
62
61
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Y3
GND
13,
12,
38,
64
63,
88
Ground (GND)
VCC
V
CC
1. Pins have dual function capability
2. NC pins are not to be connected to any active signals, Vcc or GND.
11
Specifications ispLSI 1032
Pin Description
Name
CPGA Pin Numbers
Description
Input/OutputPins-ThesearethegeneralpurposeI/Opinsusedbythe
logic array.
I/O 0 - I/O 3
I/O 4 - I/O 7
F1,
K1, J2,
K3, L2,
L4,
L7,
K8, L9,
L11, K10, J10, K11,
J11, H10, H11, F10,
E9, D11, D10, C11,
B11, C10, A11, B10,
B9, A10, A9, B8,
A8, B6, B7, A7,
A5, B5, C5, A4,
B4, A3, A2, B3,
A1, B2, C2, B1,
C1, D2, D1, E3
H1, H2, J1,
L1,
L3,
K2,
K4,
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
J5,
K5, L5,
K7, L6,
L8,
L10, K9,
Dedicated input pins to the device.
IN 4 - IN 7
ispEN
E10, C7, A6, E2
G3
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
SDI/IN 01
G2
Input– Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
MODE/IN 11
SDO/IN 21
SCLK/IN 31
K6
Input– Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
J7
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
G10
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
RESET
Y0
G1
E1
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Y1
E11
Y2
G9
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Y3
G11
G3
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
NC2
No Connect
GND
C6, F3,
F2, F11
F9,
J6
Ground (GND)
VCC
V
CC
Table 2-0002-32/883
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, Vcc or GND.
12
Specifications ispLSI 1032
Pin Configuration
ispLSI 1032 84-Pin PLCC Pinout Diagram
11 10
9
8
7
6
5
4
3
2
1
84 83 82 81 80 79 78 77 76 75
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
IN 7
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
IN 4
Y0
Y1
VCC
VCC
ispLSI 1032
GND
GND
Top View
ispEN
RESET
*SDI/IN 0
I/O 0
Y2
Y3
IN 3/SCLK*
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
*Pins have dual function capability.
0123-32-isp
13
Specifications ispLSI 1032
Pin Configuration
ispLSI 1032 100-pin TQFP Pinout Diagram
1
1
1
1
NC
NC
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
IN 7
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
IN 4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Y0
Y1
ispLSI 1032
VCC
GND
ispEN
RESET
SDI/IN 0
I/O 0
VCC
GND
Top View
Y2
Y3
2
2
IN 3/SCLK
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
1
1
NC
NC
1
1
NC
NC
1. NC pins are not to be connected to any active signal, Vcc or GND.
2. Pins have dual function capability.
0766A-32-isp
14
Specifications ispLSI 1032
Pin Configuration
ispLSI 1032/883 84-Pin CPGA Pinout Diagram
PIN A1
11
10
9
8
7
6
5
4
3
2
1
A
I/O38
I/O41
I/O42
I/O44
I/O47
IN6
I/O48
I/O51
I/O53
I/O54
I/O56
I/O36
I/O35
I/O39
I/O37
I/O40
I/O43
I/O46
IN5
I/O45
I/O49
I/O50
I/O52
I/O55
I/O57
I/O58
I/O61
I/O59
I/O60
I/O62
B
C
D
E
F
GND
INDEX
I/O33
Y1
I/O34
IN4
I/O32
I/O63
GND
IN7
Y0
ispLSI 1032/883
Vcc
Y3
I/O31
GND
Vcc
I/O0
Bottom View
*SDI/
IN0
*SCLK/
IN3
G
H
ispEN
Y2
RESET
I/O30
I/O29
I/O2
I/O5
I/O7
I/O1
I/O3
I/O4
*SDO/
IN2
GND
I/O28
I/O27
I/O24
I/O26
I/O25
I/O22
I/O13
I/O14
I/O15
J
K
L
*MODE/
IN1
I/O23
I/O21
I/O20
I/O19
I/O17
I/O11
I/O12
I/O8
I/O16
I/O18
I/O10
I/O9
I/O6
*Pins have dual function capability.
0488A-32-isp/883
15
Specifications ispLSI 1032
Part Number Description
—
1032
XX
X
X
X
ispLSI
Device Family
Device Number
Speed
Grade
Blank = Commercial
I = Industrial
/883 = 883 Military Process
Package
J = PLCC
T = TQFP
G = CPGA
90 = 90 MHz
80 = 80 MHz
60 = 60 MHz
fmax
f
f
max
max
Power
L = Low
0212-80B-isp1032
Ordering Information
COMMERCIAL
pd (ns)
Family
f
max (MHz)
t
Ordering Number
ispLSI 1032-90LJ
ispLSI 1032-90LT
ispLSI 1032-80LJ
ispLSI 1032-80LT
ispLSI 1032-60LJ
ispLSI 1032-60LT
Package
90
90
80
80
60
60
12
12
15
15
20
20
84-Pin PLCC
100-Pin TQFP
84-Pin PLCC
100-Pin TQFP
84-Pin PLCC
100-Pin TQFP
ispLSI
INDUSTRIAL
Family
ispLSI
f
max (MHz)
t
pd (ns)
Ordering Number
ispLSI 1032-60LJI
ispLSI 1032-60LTI
Package
60
60
20
84-Pin PLCC
100-Pin TQFP
20
MILITARY/883
Family
ispLSI
f
max (MHz)
t
pd (ns)
Ordering Number
SMD Number
Package
60
20
ispLSI 1032-60LG/883
5962-9308501MXC 84-Pin CPGA
Note: Lattice Semiconductor recognizes the trend in military device procurement towards
Table 2- 0041A-32-isp
using SMD compliant devices, as such, ordering by this number is recommended.
16
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