ICE40HX8K-BG121TR [LATTICE]
iCE40 LP/HX Family;型号: | ICE40HX8K-BG121TR |
厂家: | LATTICE SEMICONDUCTOR |
描述: | iCE40 LP/HX Family |
文件: | 总52页 (文件大小:1366K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
iCE40 LP/HX Family
Data Sheet
FPGA-DS-02029-3.5
September 2018
iCE40 LP/HX Family
Data Sheet
Contents
Acronyms in This Document.................................................................................................................................................5
1. General Description......................................................................................................................................................6
1.1.
Features...............................................................................................................................................................6
2. Product Family..............................................................................................................................................................7
3. Architecture..................................................................................................................................................................8
3.1.
Architecture Overview ........................................................................................................................................8
3.1.1. PLB Blocks .......................................................................................................................................................9
3.1.2. Routing..........................................................................................................................................................10
3.1.3. Clock/Control Distribution Network .............................................................................................................10
3.1.4. sysCLOCK Phase Locked Loops (PLLs) ...........................................................................................................11
3.1.5. sysMEM Embedded Block RAM Memory .....................................................................................................12
3.1.6. sysI/O ............................................................................................................................................................14
3.1.7. sysI/O Buffer .................................................................................................................................................17
3.1.8. Non-Volatile Configuration Memory ............................................................................................................18
3.1.9. Power On Reset ............................................................................................................................................18
3.2.
Programming and Configuration.......................................................................................................................18
3.2.1. Power Saving Options ...................................................................................................................................18
4. DC and Switching Characteristics................................................................................................................................19
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
Absolute Maximum Ratings ..............................................................................................................................19
Recommended Operating Conditions...............................................................................................................19
Power Supply Ramp Rates.................................................................................................................................20
Power-On-Reset Voltage Levels ........................................................................................................................20
ESD Performance...............................................................................................................................................20
DC Electrical Characteristics..............................................................................................................................21
Static Supply Current – LP Devices....................................................................................................................21
Static Supply Current – HX Devices ...................................................................................................................22
Programming NVCM Supply Current – LP Devices............................................................................................22
4.10. Programming NVCM Supply Current – HX Devices ...........................................................................................23
4.11. Peak Startup Supply Current – LP Devices ........................................................................................................23
4.12. Peak Startup Supply Current – HX Devices........................................................................................................24
4.13. sysI/O Recommended Operating Conditions....................................................................................................24
4.14. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................24
4.15. sysI/O Differential Electrical Characteristics .....................................................................................................25
4.15.1.
4.15.2.
LVDS25......................................................................................................................................................25
subLVDS....................................................................................................................................................25
4.16. LVDS25E Emulation ...........................................................................................................................................26
4.17. SubLVDS Emulation ...........................................................................................................................................27
4.18. Typical Building Block Function Performance – LP Devices* ............................................................................28
4.18.1.
4.18.2.
Pin-to-Pin Performance (LVCMOS25) – LP Devices ..................................................................................28
Register-to-Register Performance – LP Devices .......................................................................................28
4.19. Typical Building Block Function Performance – HX Devices*............................................................................28
4.19.1.
4.19.2.
Pin-to-Pin Performance (LVCMOS25) – HX Devices .................................................................................28
Register-to-Register Performance – HX Devices ......................................................................................29
4.20. Derating Logic Timing........................................................................................................................................29
4.21. Maximum sysI/O Buffer Performance...............................................................................................................29
4.22. Timing Adders ...................................................................................................................................................30
4.23. External Switching Characteristics – LP Devices................................................................................................31
4.24. External Switching Characteristics – HX Devices...............................................................................................33
4.25. sysClock PLL Timing ...........................................................................................................................................34
4.26. SPI Master or NVCM Configuration Time..........................................................................................................35
4.27. sysCONFIG Port Timing Specifications...............................................................................................................36
4.28. Switching Test Conditions .................................................................................................................................37
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
5. Pinout Information .....................................................................................................................................................38
5.1.
Signal Descriptions ............................................................................................................................................38
5.1.1. General Purpose ...........................................................................................................................................38
5.1.2. PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)......38
5.1.3. Programming and Configuration ..................................................................................................................38
5.2.
5.3.
Pin Information Summary.................................................................................................................................40
iCE40 LP/HX Part Number Description..............................................................................................................43
5.3.1. Ultra Low Power (LP) Devices .......................................................................................................................43
5.3.2. High Performance (HX) Devices....................................................................................................................43
5.4.
5.5.
Ordering Information........................................................................................................................................44
Ordering Part Numbers.....................................................................................................................................44
5.5.1. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging ...............................................44
5.5.2. High-Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging.............................................45
Supplemental Information .................................................................................................................................................46
Technical Support...............................................................................................................................................................47
Revision History..................................................................................................................................................................48
Figures
Figure 3.1. iCE40LP/HX1K Device, Top View.........................................................................................................................8
Figure 3.2. PLB Block Diagram ..............................................................................................................................................9
Figure 3.3. PLL Diagram ......................................................................................................................................................11
Figure 3.4. sysMEM Memory Primitives.............................................................................................................................13
Figure 3.5. I/O Bank and Programmable I/O Cell ...............................................................................................................15
Figure 3.6. iCE I/O Register Block Diagram.........................................................................................................................16
Figure 4.1. LVDS25E Using External Resistors.....................................................................................................................26
Figure 4.2. subLVDSE DC Conditions...................................................................................................................................27
Figure 4.3. Output Test Load, LVCMOS Standards .............................................................................................................37
Figure 5.1. Low Power (LP) Devices....................................................................................................................................43
Figure 5.2. High Performance (HX) Devices........................................................................................................................43
Figure 5.3. High Performance (HX) Devices........................................................................................................................44
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
3
iCE40 LP/HX Family
Data Sheet
Tables
Table 2.1. iCE40 LP/HX Family Selection Guide ....................................................................................................................7
Table 3.1. Logic Cell Signal Descriptions .............................................................................................................................10
Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks....................................................................10
Table 3.3. PLL Signal Descriptions.......................................................................................................................................12
Table 3.4. sysMEM Block Configurations*..........................................................................................................................13
Table 3.5. EBR Signal Descriptions......................................................................................................................................14
Table 3.6. PIO Signal List.....................................................................................................................................................16
Table 3.7. Supported Input Standards................................................................................................................................17
Table 3.8. Supported Output Standards.............................................................................................................................17
Table 3.9. Power Saving Features Description....................................................................................................................18
Table 4.1. Absolute Maximum Ratings* .............................................................................................................................19
Table 4.2. Recommended Operating Conditions1 ..............................................................................................................19
Table 4.3. Power Supply Ramp Rates* ...............................................................................................................................20
Table 4.4. Power-On-Reset Voltage Levels*.......................................................................................................................20
Table 4.5. DC Electrical Characteristics...............................................................................................................................21
Table 4.6. Supply Current– LP Devices1, 2, 3, 4.......................................................................................................................21
Table 4.7. Supply Current– HX Devices1, 2, 3, 4 ......................................................................................................................22
Table 4.8. Programming NVCM Supply Current – LP Devices1, 2, 3, 4....................................................................................22
Table 4.9. Programming NVCM Supply Current – HX Devices1, 2, 3, 4 ...................................................................................23
Table 4.10. Peak Startup Supply Current – LP Devices .......................................................................................................23
Table 4.11. Peak Startup Supply Current – HX Devices ......................................................................................................24
Table 4.12. sysI/O Recommended Operating Conditions...................................................................................................24
Table 4.13. sysI/O Single-Ended DC Electrical Characteristics............................................................................................24
Table 4.14. LVDS25 .............................................................................................................................................................25
Table 4.15. subLVDS............................................................................................................................................................25
Table 4.16. LVDS25E DC Conditions....................................................................................................................................26
Table 4.17. subLVDSE DC Conditions..................................................................................................................................27
Table 4.18. Pin-to-Pin Performance (LVCMOS25) – LP Devices..........................................................................................28
Table 4.19. Register-to-Register Performance – LP Devices...............................................................................................28
Table 4.20. Pin-to-Pin Performance (LVCMOS25) – HX Devices.........................................................................................28
Table 4.21. Register-to-Register Performance – HX Devices..............................................................................................29
Table 4.22. Register-to-Register Performance1 ..................................................................................................................29
Table 4.23. Timing Adders – LP Devices*............................................................................................................................30
Table 4.24. Timing Adders – HX Devices*...........................................................................................................................30
Table 4.25. External Switching Characteristics – LP Devices1, 2...........................................................................................31
Table 4.26. External Switching Characteristics – HX Devices1, 2 ..........................................................................................33
Table 4.27. sysClock PLL Timing..........................................................................................................................................34
Table 4.28. SPI Master or NVCM Configuration Time1, 2 .....................................................................................................35
Table 4.29. sysCONFIG Port Timing Specifications1 ............................................................................................................36
Table 4.30. Test Fixture Required Components, Non-Terminated Interfaces....................................................................37
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
DFF
D-style Flip-Flop
DSP
Digital Signal Processor
EBR
Embedded Block RAM
HFOSC
I2C
High Frequency Oscillator
Inter-Integrated Circuit
LFOSC
LUT
Low Frequency Oscillator
Look Up Table
LVCMOS
NVCM
PFU
Low-Voltage Complementary Metal Oxide Semiconductor
Non Volatile Configuration Memory
Programmable Functional Unit
Programmable Logic Blocks
Phase Locked Loops
PLB
PLL
SPI
Serial Peripheral Interface
Wafer Level Chip Scale Packaging
WLCSP
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
5
iCE40 LP/HX Family
Data Sheet
1.1. Features
1. General Description
Flexible Logic Architecture
The iCE40™ LP/HX family of ultra-low power, non-volatile
FPGAs has five devices with densities ranging from 384 to
7,680 Look-Up Tables (LUTs). In addition to LUT-based, low-
cost programmable logic, these devices feature Embedded
Block RAM (EBR), Non-volatile Configuration Memory
(NVCM) and Phase Locked Loops (PLLs). These features
allow the devices to be used in low-cost, high-volume
consumer and system applications. Select packages offer
High-Current drivers that are ideal to drive three white
LEDs, or one RGB LED.
Five devices with 384 to 7,680 LUT4s and 10
to 206 I/Os
Ultra-low Power Devices
Advanced 40 nm low power process
As low as 21 µA standby power
Programmable low swing differential I/Os
Embedded and Distributed Memory
Up to 128 kb sysMEM™ Embedded Block RAM
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
High Current LED Drivers
The iCE40 LP/HX devices are fabricated on a 40 nm CMOS
low power process. The device architecture has several
features such as programmable low-swing differential I/Os
and the ability to turn off on-chip PLLs dynamically. These
features help manage static and dynamic power
consumption, resulting in low static power for all members
of the family. The iCE40 LP/HX devices are available in two
versions – ultra low power (LP) and high performance (HX)
devices.
Three High Current Drivers used for three
different LEDs or one RGB LED
High Performance, Flexible I/O Buffer
Programmable sysI/O™ buffer supports wide
range of interfaces:
LVCMOS 3.3/2.5/1.8
LVDS25E, subLVDS
Schmitt trigger inputs, to 200 mV typical
hysteresis
The iCE40 LP/HX FPGAs are available in a broad range of
advanced halogen-free packages ranging from the space
saving 1.40 mm x 1.48 mm WLCSP to the PCB-friendly 20
mm x 20 mm TQFP. Table 2.1 shows the LUT densities,
package and I/O options, along with other key parameters.
Programmable pull-up mode
Flexible On-Chip Clocking
Eight low skew global signal resources
Up to two analog PLLs per device
The iCE40 LP/HX devices offer enhanced I/O features such
as pull-up resistors. Pull-up features are controllable on a
per-pin basis.
Flexible Device Configuration
SRAM is configured through:
Standard SPI Interface
Internal Nonvolatile Configuration
Memory (NVCM)
The iCE40 LP/HX devices also provide flexible, reliable and
secure configuration from on-chip NVCM. These devices
can also configure themselves from external SPI Flash or be
configured by an external master such as a CPU.
Broad Range of Package Options
WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA, and
csBGA package options
Small footprint package options
Lattice provides a variety of design tools that allow complex
designs to be efficiently implemented using the iCE40
LP/HX family of devices. Popular logic synthesis tools
provide synthesis library support for iCE40 LP/HX. Lattice
design tools use the synthesis tool output along with the
user-specified preferences and constraints to place and
route the design in the iCE40 LP/HX device. These tools
extract the timing from the routing and back-annotate it
into the design for timing verification.
As small as 1.40 mm x 1.48 mm
Advanced halogen-free packaging
Lattice provides many pre-engineered IP (Intellectual
Property) modules, including a number of reference
designs, licensed free of charge, optimized for the iCE40
LP/HX FPGA family. By using these configurable soft core IP
cores as standardized blocks, users are free to concentrate
on the unique aspects of their design, increasing their
productivity.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
2. Product Family
Table 2.1 lists device information and packages of the iCE40 LP/HX family.
Table 2.1. iCE40 LP/HX Family Selection Guide
Part Number
LP384
LP640
640
8
LP1K
1,280
16
LP4K
3,520
20
LP8K
7,680
32
HX1K
1,280
16
HX4K
3,520
20
HX8K
7,680
32
Logic Cells (LUT + Flip-Flop)
RAM4K Memory Blocks
RAM4K RAM bits
384
0
0
32K
0
64K
11
80K
22
128K
22
64K
11
80K
2
128K
2
Phase-Locked Loops (PLLs)
Maximum Programmable I/O Pins
Maximum Differential Input Pairs
High Current LED Drivers
Package
0
63
8
25
3
95
167
20
178
23
95
95
206
26
12
11
12
0
3
3
0
0
0
0
0
Code
Programmable I/O: Max Input (LVDS25)
16 WLCSP
(1.40 mm x 1.48 mm, 0.35 mm)
SWG16
10(0)1
—
10(0)1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32 QFN
(5 mm x 5 mm, 0.5 mm)
SG32
21(3)
25(3)
37(6)
—
—
36 ucBGA
(2.5 mm x 2.5 mm, 0.4 mm)
CM36
CM49
CM81
—
25(3)1
35(5)1
63(8)
—
—
49 ucBGA
(3 mm x 3 mm, 0.4 mm)
—
—
—
81 ucBGA
(4 mm x 4 mm, 0.4 mm)
—
63(9)2
63(9)2
81 csBGA
(5 mm x 5 mm, 0.5 mm)
CB81
—
—
—
—
62(9)1
67(7)1
—
—
—
—
—
—
—
—
84 QFN
QN84
(7 mm x 7 mm, 0.5 mm)
100 VQFP
(14 mm x 14 mm, 0.5 mm)
VQ100
CM121
CB121
BG121
CB132
TQ144
CM225
CT256
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
95(12)
92(12)
—
—
93(13)
—
—
93(13)
—
72(9)1
—
—
—
—
—
121 ucBGA
(5 mm x 5 mm, 0.4 mm)
121 csBGA
(6 mm x 6 mm, 0.5 mm)
—
—
—
121 caBGA
(9 mm x 9 mm, 0.8 mm)
—
—
—
93(13)
95(12)
93(13)
95(12)
—
132 csBGA
(8 mm x 8 mm, 0.5 mm)
—
—
—
95(11)
144 TQFP
(20 mm x 20 mm, 0.5 mm)
—
—
—
96(12) 107(14)
225 ucBGA
(7 mm x 7 mm, 0.4 mm)
—
178(23) 178(23)
—
—
—
—
178(23)
206(26)
256-ball caBGA
—
—
—
(14 mm x 14 mm, 0.8 mm)
Notes:
1. No PLL available on the 16 WLCSP, 36 ucBGA, 81 csBGA, 84 QFN, and 100 VQFP packages.
2. Only one PLL available on the 81 ucBGA package.
3. High Current I/Os only available on the 16 WLCSP package.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
7
iCE40 LP/HX Family
Data Sheet
3. Architecture
3.1. Architecture Overview
The iCE40 LP/HX family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs,
Nonvolatile Programmable Configuration Memory (NVCM) and blocks of sysMEM Embedded Block RAM (EBR)
surrounded by Programmable I/O (PIO). Figure 3.1 shows the block diagram of the iCE40LP/HX1K device.
Programmable
Logic Block (PLB)
I/O Bank 0
Programmable Interconnect
NVCM
PLL
SPI
I/O Bank 2
Bank
Carry Logic
Non-volatile
Configuration Memory
(NVCM)
Phase-Locked
Loop
4-Input Look-up
Table (LUT4)
Flip-flop with Enable
and Reset Controls
Figure 3.1. iCE40LP/HX1K Device, Top View
The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with
rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the periphery of the
device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs
utilize a flexible I/O buffer referred to as a sysI/O buffer that supports operation with a variety of interface standards.
The blocks are connected with many vertical and horizontal routing channel resources. The place and route software
tool automatically allocates these routing resources.
In the iCE40 LP/HX family, there are up to four independent sysI/O banks. Note on some packages VCCIO banks are tied
together. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
document. The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM,
ROM or FIFO.
The iCE40 LP/HX architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have
multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the
clocks.
Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40 LP/HX
includes on-chip, Nonvolatile Configuration Memory (NVCM).
3.1.1. PLB Blocks
The core of the iCE40 LP/HX device consists of Programmable Logic Blocks (PLB) which can be programmed to perform
logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 3.2. Each LC
contains one LUT and one register.
Figure 3.2. PLB Block Diagram
Logic Cells
Each Logic Cell includes three primary logic elements shown in Figure 3.2.
A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to four
inputs. Similarly, the LUT4 element behaves as a 16 x 1 Read-Only Memory (ROM). Combine and cascade multiple
LUT4s to create wider logic functions.
A D-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions.
Each DFF also connects to a global reset signal that is automatically asserted immediately following device
configuration.
Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters,
comparators, binary counters and some wide, cascaded logic functions.
Table 3.1 lists the logic cell signals.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
9
iCE40 LP/HX Family
Data Sheet
Table 3.1. Logic Cell Signal Descriptions
Function
Type
Signal Name
I0, I1, I2, I3
Enable
Description
Input
Data signal
Control signal
Control signal
Inputs to LUT4
Input
Clock enable shared by all LCs in the PLB
Input
Set/Reset*
Asynchronous or synchronous local set/reset shared by
all LCs in the PLB.
Input
Control signal
Clock
Clock one of the eight Global Buffers, or from the
general-purpose interconnects fabric shared by all LCs
in the PLB.
Input
Output
Output
Inter-PLB signal
Data signals
FCIN
O
Fast carry in
LUT4 or registered output
Fast carry out
Inter-PFU signal
FCOUT
*Note: If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration.
3.1.2. Routing
There are many resources provided in the iCE40 LP/HX devices to route signals individually with related control signals.
The routing resources consist of switching circuitry, buffers, and metal interconnect (routing) segments.
The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4
(spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4, and x12 connections provide fast and efficient
connections in the diagonal, horizontal and vertical directions.
The design tool takes the output of the synthesis tool and places and routes the design.
3.1.3. Clock/Control Distribution Network
Each iCE40 LP/HX device has eight global inputs, two pins on each side of the device. Note that not all GBINs are
available in all packages.
These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are
identified as GBIN[7:0] and the global buffers are identified as-GBUF[7:0]. These eight inputs may be used as general
purpose I/O if they are not used to drive the clock nets. Global buffer GBUF7 in I/O Bank 3 also provides an optional
direct LVDS25 or subLVDS differential clock input.
Table 3.2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally
connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global
buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clock-
enable input.
Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks
Global Buffer
LUT Inputs
Clock
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Reset
Yes
—
Clock Enable
GBUF0
—
Yes
—
GBUF1
GBUF2
Yes
—
GBUF3
Yes
—
Yes, any 4 of 8 GBUF
Inputs
GBUF4
Yes
—
GBUF5
Yes
—
GBUF6
Yes
—
GBUF7
Yes
The maximum frequency for the global buffers are listed in the External Switching Characteristics tables in this
document.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
3.1.3.1. Global Hi-Z Control
The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 LP/HX device. This GHIZ signal is
automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance state.
3.1.3.2. Global Reset Control
The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 LP/HX device. The global reset signal is
automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For
PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application.
3.1.4. sysCLOCK Phase Locked Loops (PLLs)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 LP/HX devices have one sysCLOCK PLL.
REFERENCECLK is the reference frequency input to the PLL and its source can come from an external I/O pin, the
internal Oscillator Generators from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come
from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus
synthesize a higher frequency clock output.
The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output. The
output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to drive the
iCE40 LP/HX global clock network directly or general purpose routing resources can be used.
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A
block diagram of the PLL is shown in Figure 3.3.
The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock which
will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be either
programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase
adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied.
There is an additional feature in the iCE40 LP/HX PLL. There are two FPGA controlled inputs, SCLK and SDI, that allows
the user logic to serially shift in data thru SDI, clocked by SCLK clock. The data shifted in would change the configuration
settings of the PLL. This feature allows the PLL to be time multiplexed for different functions, with different clock rates.
After the data is shifted in, you would simply pulse the RESET input of the PLL block, and the PLL will re-lock with the
new settings. For more details, refer to iCE40 sysCLOCK PLL Design and Usage Guide (TN1251).
RESET
BYPASS
BYPASS
GNDPLL VCC PLL
Phase
Detector
DIVQ
DIVR
RANGE
Low-Pass
Filter
Voltage
Controlled
Oscillator
(VCO)
REFERENCECLK
VCO
Input
Divider
Divider
SIMPLE
SCLK
SDI
DIVF
PLLOUTCORE
Feedback
Fine Delay
Adjustment
Output Port
Divider
Fine Delay
Adjustment
Feedback
Phase
Shifter
PLLOUTGLOBAL
Feedback_Path
LOCK
DYNAMICDELAY[7:0]
EXTFEEDBACK
EXTERNAL
LATCHINPUTVALUE
Low Powermode
Figure 3.3. PLL Diagram
Table 3.3 provides signal descriptions of the PLL block.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
11
iCE40 LP/HX Family
Data Sheet
Table 3.3. PLL Signal Descriptions
Signal Name
REFERENCECLK
BYPASS
Direction
Description
Input
Input
Input reference clock
The BYPASS control selects which clock signal connects to the PLLOUT output.
0 – PLL generated signal
1 – REFERENCECLK
EXTFEEDBACK
Input
Input
External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set
to EXTERNAL.
DYNAMICDELAY[7:0]
LATCHINPUTVALUE
PLLOUTGLOBAL
PLLOUTCORE
Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE
is set to DYNAMIC.
Input
When enabled, puts the PLL into low-power mode; PLL output is held static at the
last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to 1 to enable.
Output
Output
Output from the Phase-Locked Loop (PLL). Drives a global clock network on the
FPGA. The port has optimal connections to global clock buffers GBUF4 and GBUF5.
Output clock generated by the PLL, drives regular FPGA routing. The frequency
generated on this output is the same as the frequency of the clock signal generated
on the PLLOUTLGOBAL port.
LOCK
Output
When High, indicates that the PLL output is phase aligned or locked to the input
reference clock.
RESET
SCLK
SDI
Input
Input
Input
Active low reset.
Input, Serial Clock used for re-programming PLL settings.
Input, Serial Data used for re-programming PLL settings.
3.1.5. sysMEM Embedded Block RAM Memory
Larger iCE40 LP/HX device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each
4 kbit in size. This memory can be used for a wide variety of purposes including data buffering and FIFO.
3.1.5.1. sysMEM Memory Block
The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic resources.
Each block can be used in a variety of depths and widths as listed in Table 3.4.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
Table 3.4. sysMEM Block Configurations*
Block RAM
Block RAM
WADDR Port
Size (Bits)
WDATA Port
Size (Bits)
RADDR Port
Size (Bits)
RDATA Port
Size (Bits)
MASK Port
Size (Bits)
Configuration
Configuration
and Size
SB_RAM256x16
SB_RAM256x16NR
SB_RAM256x16NW
SB_RAM256x16NRNW
256 x 16 (4 k)
8 [7:0]
9 [8:0]
16 [15:0]
8 [7:0]
4 [3:0]
2 [1:0]
8 [7:0]
9 [8:0]
16 [15:0]
8 [7:0]
4 [3:0]
2 [1:0]
16 [15:0]
SB_RAM512x8
SB_RAM512x8NR
512 x 8 (4 k)
No Mask Port
No Mask Port
No Mask Port
SB_RAM512x8NW
SB_RAM512x8NRNW
SB_RAM1024x4
SB_RAM1024x4NR
1024 x 4 (4 k)
10 [9:0]
11 [10:0]
10 [9:0]
11 [10:0]
SB_RAM1024x4NW
SB_RAM1024x4NRNW
SB_RAM2048x2
SB_RAM2048x2NR
SB_RAM2048x2NW
2048 x 2 (4 k)
SB_RAM2048x2NRNW
*Note: For iCE40 LP/HX EBR primitives with a negative-edged Read or Write clock, the base primitive name is appended with a ‘N’
and a ‘R’ or W depending on the clock that is affected.
3.1.5.2. RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block
can also be utilized as a ROM.
Note that the sysMEM Embedded Block RAM Memory address 0 cannot be initialized.
3.1.5.3. Memory Cascading
Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks.
3.1.5.4. RAM4k Block
Figure 3.4 shows the 256 x 16 memory configurations and their input/output names. In all the sysMEM RAM modes,
the input data and addresses for the ports are registered at the input of the memory array.
Write Port
Read Port
WDATA[15:0]
MASK[15:0]
RDATA[15:0]
RADDR[7:0]
WADDR[7:0]
RAM4K
RAM Block
(256 x 16)
WE
WCLKE
WCLK
RE
RCLKE
RCLK
Figure 3.4. sysMEM Memory Primitives
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
13
iCE40 LP/HX Family
Data Sheet
Table 3.5 lists the EBR signals.
Table 3.5. EBR Signal Descriptions
Signal Name
WDATA[15:0]
MASK[15:0]
Direction
Description
Input
Write Data input.
Input
Masks write operations for individual data bit-lines.
0 – Write bit
1 – Do not write bit
WADDR[7:0]
WE
Input
Input
Input
Input
Output
Input
Input
Input
Input
Write Address input. Selects one of 256 possible RAM locations.
Write Enable input.
WCLKE
WCLK
Write Clock Enable input.
Write Clock input. Default rising-edge, but with falling-edge option.
Read Data output.
RDATA[15:0]
RADDR[7:0]
RE
Read Address input. Selects one of 256 possible RAM locations.
Read Enable input.
RCLKE
Read Clock Enable input.
RCLK
Read Clock input. Default rising-edge, but with falling-edge option.
For further information on the sysMEM EBR block, refer to Memory Usage Guide for iCE40 Devices (TN1250).
3.1.6. sysI/O
Buffer Banks
iCE40 LP/HX devices have up to four I/O banks with independent VCCIO rails with an additional configuration bank VCC_SPI
for the SPI I/Os.
Programmable I/O (PIO)
The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective
sysI/O buffers and pads. The PIOs are placed on the top and bottom of the devices.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
VCCIO
I/O Bank 0, 1, 2, or 3
Voltage Supply
0 = Hi-Z
1 = Output
Enabled
Enabled 1ꢀ
Disabled 0ꢀ
P ull-up
OE
VCCIO_0
VCC
Internal Core
P ull-up
Enable
OUTCLK
I/O Bank 0
General-Purpose I/O
OUT
PIO
PAD
Latch inhibits
switching for
lowest power
OUTCLK
iCEGATE
HOLD
HD
IN
GBIN pins optionally
connect directly to an
associated GBUF global
buffer
INCLK
I/O Bank 2
General-Purpose I/O
SPI
Bank
Programmable Input/Output
= Statically defined by configuration program
VCC_SPI
VCCIO_2
Figure 3.5. I/O Bank and Programmable I/O Cell
The PIO contains three blocks: an input register block, output register block iCEgate™ and tri-state register block. To
save power, the optional iCEgate latch can selectively freeze the state of individual, non-registered inputs within an I/O
bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of modes along with the
necessary clock and selection logic.
Input Register Block
The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface
signals before they are passed to the device core. In Generic DDR mode, two registers are used to sample the data on
the positive and negative edges of the system clock signal, creating two data streams.
Output Register Block
The output register block can optionally register signals from the core of the device before they are passed to the
sysI/O buffers. In Generic DDR mode, two registers are used to capture the data on the positive and negative edge of
the system clock and then muxed creating one data stream.
Figure 3.6 shows the input/output register block for the PIOs.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
15
iCE40 LP/HX Family
Data Sheet
CLOCK_ENABLE
PIO Pair
OUTPUT_CLK
INPUT_CLK
(1,0)
LATCH_INPUT_VALUE
D_IN_1
D_IN_0
Pad
D_OUT_1
D_OUT_0
(1,0)
0
1
OUTPUT_ENABLE
(1,0)
LATCH_INPUT_VALUE
D_IN_1
D_IN_0
Pad
D_OUT_1
D_OUT_0
(1,0)
0
1
OUTPUT_ENABLE
= Statically defined by configuration program.
Figure 3.6. iCE I/O Register Block Diagram
Table 3.6. PIO Signal List
Pin Name
I/O Type
Input
Description
OUTPUT_CLK
Output register clock
Clock enable
CLOCK_ENABLE
INPUT_CLK
Input
Input
Input register clock
Output enable
OUTPUT_ENABLE
D_OUT_0/1
Input
Input
Data from the core
Data to the core
D_IN_0/1
Output
Input
LATCH_INPUT_VALUE
Latches/holds the Input Value
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
3.1.7. sysI/O Buffer
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of
standards that are found in today’s systems including LVCMOS and LVDS25.
High Current LED Drivers combine three sysI/O buffers together. This allows for programmable drive strength. This also
allows for high current drivers that are ideal to drive three white LEDs, or one RGB LED. Each bank is capable of
supporting multiple I/O standards including single-ended LVCMOS buffers and differential LVDS25E output buffers.
Bank 3 additionally supports differential LVDS25 input buffers. Each sysI/O bank has its own dedicated power supply.
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO_2, VPP_2V5, and VCC_SPI have reached the level
defined in Table 4.4. After the POR signal is deactivated, the FPGA core logic becomes active. It is your responsibility to
ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O
banks that are critical to the application. The default configuration of the I/O pins in a device prior to configuration is
tri-stated with a weak pull-up to VCCIO. The I/O pins will maintain the pre-configuration state until VCC and VCCIO (for I/O
banks containing configuration I/Os) have reached levels, at which time the I/Os will take on the software user-
configured settings only after a proper download/configuration. Unused I/Os are automatically blocked and the pull-up
termination is disabled.
Supported Standards
The iCE40 LP/HX sysI/O buffer supports both single-ended input/output standards, and used as differential
comparators. The buffer supports the LVCMOS 1.8 V, 2.5 V, and 3.3 V standards. The buffer has individually
configurable options for bus maintenance (weak pull-up or none).
Table 3.7 and Table 3.8 show the I/O standards (together with their supply and reference voltages) supported by the
iCE40 LP/HX devices.
Table 3.7. Supported Input Standards
VCCIO (Typical)
I/O Standard
3.3 V
2.5 V
1.8 V
Single-Ended Interfaces
LVCMOS33
Yes
—
—
Yes
—
—
—
LVCMOS25
LVCMOS18
—
Yes
Differential Interfaces
LVDS25*
—
—
Yes
—
SubLVDS*
—
Yes
*Note: Bank 3 only.
Table 3.8. Supported Output Standards
I/O Standard
VCCIO (Typical)
Single-Ended Interfaces
LVCMOS33
3.3 V
2.5 V
1.8 V
LVCMOS25
LVCMOS18
Differential Interfaces
LVDS25*
—
—
SubLVDS*
*Note: These interfaces can be emulated with external resistors in all devices.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
17
iCE40 LP/HX Family
Data Sheet
3.1.8. Non-Volatile Configuration Memory
All iCE40 LP/HX devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure the
device.
For more information on the NVCM, refer to iCE40 Programming and Configuration (FPGA-TN-02001).
3.1.9. Power On Reset
iCE40 LP/HX devices have power-on reset circuitry to monitor VCC, VCCIO_2, VPP_2V5, and VCC_SPI voltage levels during
power-up and operation. At power-up, the POR circuitry monitors VCC, VCCIO_2, VPP_2V5, and VCC_SPI (controls
configuration) voltage levels. It then triggers download from the on-chip NVCM or external Flash memory after
reaching the power-up levels specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics
section of this data sheet. Before and during configuration, the I/Os are held in tri-state. I/Os are released to user
functionality once the device has finished configuration.
3.2. Programming and Configuration
This section describes the programming and configuration of the iCE40 LP/HX family.
Device Programming
The NVCM memory can be programmed through the SPI port.
Device Configuration
There are various ways to configure the Configuration RAM (CRAM) including:
Internal NVCM Download
From an SPI Flash (Master SPI mode)
System microprocessor to drive a Serial Slave SPI port (SSPI mode)
The image to configure the CRAM can be selected by the user on power up (Cold Boot) or once powered up (Warm
Boot).
For more details on configuring the iCE40 LP/HX device, refer to iCE40 Programming and Configuration (FPGA-TN-
02001).
3.2.1. Power Saving Options
iCE40 LP/HX devices are available in two options for maximum flexibility: LP and HX devices. The LP devices have ultra
low static and dynamic power consumption. HX devices are designed to provide high performance. Both the LP and
the HX devices operate at 1.2 V VCC.
iCE40 LP/HX devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic power
requirements of their applications. While these features are available in both device types, these features are mainly
intended for use with iCE40 LP devices to manage power consumption.
Table 3.9. Power Saving Features Description
Device Subsystem
Feature Description
PLL
When LATCHINPUTVALUE is enabled, puts the PLL into low-power mode; PLL output held static at last
input clock value.
iCEGate
To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered
inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-
enable control.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
4. DC and Switching Characteristics
4.1. Absolute Maximum Ratings
Table 4.1. Absolute Maximum Ratings*
Parameter
Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–65
Max
1.42
3.60
3.60
1.42
3.60
3.60
150
Unit
V
Supply Voltage VCC
Output Supply Voltage VCCIO
V
NVCM Supply Voltage VPP_2V5
PLL Supply Voltage VCCPLL
I/O Tri-state Voltage Applied
Dedicated Input Voltage Applied
Storage Temperature (Ambient)
Junction Temperature (TJ)
*Notes:
V
V
V
V
°C
°C
–55
125
Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied.
Compliance with the Thermal Management document is required.
All voltages referenced to GND.
I/Os can support a 200 mV Overshoot above the Recommended Operating Conditions VCCIO (Max) and -200 mV Undershoot
below VIL (Min). Overshoot and Undershoot is permitted for 25% duty cycle but must not exceed 1.6 ns.
4.2. Recommended Operating Conditions
Table 4.2. Recommended Operating Conditions1
Symbol
Parameter
Min
1.14
1.71
Max
1.26
3.46
Unit
V
1
VCC
Core Supply Voltage
Slave SPI Configuration
V
VPP_2V5 NVCM Programming
and Operating Supply
Voltage
Master SPI Configuration
Configuration from NVCM
NVCM Programming
2.30
2.30
2.30
N/A
1.14
1.71
1.71
–40
3.46
3.46
3.00
N/A
1.26
3.46
3.46
100
V
V
V
VPP_2V5
4
VPP_FAST
Optional fast NVCM programming supply. Leave unconnected.
PLL Supply Voltage
V
V
5,6
VCCPLL
VCCIO0-3
I/O Driver Supply Voltage
VCC_SPI
Junction Temperature, Industrial Operation
Junction Temperature NVCM Programming
V
1,2,3
VCCIO
V
°C
°C
tJIND
tPROG
10.00
30.00
Notes:
1. Like power supplies must be tied together. For example, if VCCIO and VCC_SPI are both the same voltage, they must also be the
same supply.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
4. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and
CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
5. No PLL available on the iCE40LP384 and iCE40LP640 device.
6. VCCPLL is tied to VCC internally in packages without PLL pins.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
19
iCE40 LP/HX Family
Data Sheet
4.3. Power Supply Ramp Rates
Table 4.3. Power Supply Ramp Rates*
Symbol
Parameter
Min
Max
Unit
All configuration modes. No power
supply sequencing.
0.40
10
V/ms
Configuring from Slave SPI. No power
supply sequencing,
0.01
0.01
0.01
10
10
10
V/ms
V/ms
V/ms
Power supply ramp rates for all
power supplies
tRAMP
Configuring from NVCM. VCC and VPP_2V5
to be powered 0.25 ms before VCC_SPI
Configuring from MSPI. VCC and VPP_SPI to
be powered 0.25 ms before VPP_2V5
.
.
Notes:
Assumes monotonic ramp rates.
iCE40LP384 requires VCC to be greater than 0.7 V when VCCIO and VCC_SPI are above GND.
4.4. Power-On-Reset Voltage Levels
Table 4.4. Power-On-Reset Voltage Levels*
Symbol
Device
Parameter
Min
Max
Unit
VPORUP iCE40LP384
Power-On-Reset ramp-up trip point (band gap
based circuit monitoring VCC, VCCIO_2, VCC_SPI
and VPP_2V5)
0.67
0.99
VCC
V
0.70
0.70
0.70
0.55
0.86
0.86
0.86
—
1.59
1.59
1.59
0.75
1.29
1.29
1.33
0.64
1.59
1.59
1.59
0.75
1.29
1.29
1.33
VCCIO_2
VCC_SPI
VPP_2V5
VCC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
iCE40LP640,
Power-On-Reset ramp-up trip point (band gap
based circuit monitoring VCC, VCCIO_2, VCC_SPI
and VPP_2V5)
iCE40LP/HX1K,
iCE40LP/HX4K,
iCE40LP/HX8K
VCCIO_2
VCC_SPI
VPP_2V5
VCC
VPORDN iCE40LP384
Power-On-Reset ramp-down trip point (band gap
based circuit monitoring VCC, VCCIO_2, VCC_SPI
and VPP_2V5)
—
VCCIO_2
VCC_SPI
VPP_2V5
VCC
—
—
iCE40LP640,
Power-On-Reset ramp-down trip point (band gap
based circuit monitoring VCC, VCCIO_2, VCC_SPI
and VPP_2V5)
—
iCE40LP/HX1K,
iCE40LP/HX4K,
iCE40LP/HX8K
—
VCCIO_2
VCC_SPI
VPP_2V5
—
—
*Note: These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages
specified under recommended operating conditions.
4.5. ESD Performance
Please refer to the iCE40 Product Family Qualification Summary for complete qualification data, including ESD performance.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
4.6. DC Electrical Characteristics
Over recommended operating conditions.
Table 4.5. DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Condition
0 V < VIN < VCCIO + 0.2 V
1, 3, 4, 5, 6, 7
Input or I/O Leakage
I/O Capacitance2
—
—
±10
µA
IIL, IIH
VCCIO = 3.3 V, 2.5 V, 1.8 V
6, 7
C1
—
—
6
6
—
—
pf
pf
VCC = Typ, VIO = 0 to VCCIO + 0.2 V
Global Input Buffer
Capacitance2
VCCIO = 3.3 V, 2.5 V, 1.8 V
6, 7
C2
VCC = Typ, VIO = 0 to VCCIO + 0.2 V
V
Input Hysteresis
VCCIO = 1.8 V, 2.5 V, 3.3 V
—
−3
200
—
—
mV
µA
µA
µA
HYST
Internal PIO Pull-up
−31
−72
−128
VCCIO = 1.8 V, 0 ≤ VIN ≤ 0.65 * VCCIO
VCCIO = 2.5 V, 0 ≤ VIN ≤ 0.65 * VCCIO
VCCIO = 3.3 V, 0 ≤ VIN ≤ 0.65 * VCCIO
6, 7
−8
—
IPU
−11
—
Notes:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is
not measured with the output driver active. Internal pull-up resistors are disabled.
2. TJ 25 oC, f = 1.0 MHz.
3. Refer to VIL and VIH in the sysI/O Single-Ended DC Electrical Characteristics table.
4. Only applies to I/Os in the SPI bank following configuration.
5. Some products are clamped to a diode when VIN is larger than VCCIO
.
6. High current I/Os has three sysI/O buffers connected together.
7. The iCE40LP640 and iCE40LP1K SWG16 package has CDONE and a sysI/O buffer are connected together.
4.7. Static Supply Current – LP Devices
Table 4.6. Supply Current– LP Devices1, 2, 3, 4
4
Symbol
Parameter
Device
Typ VCC
21
Unit
µA
µA
µA
µA
µA
µA
µA
iCE40LP384
iCE40LP640
iCE40LP1K
iCE40LP4K
iCE40LP8K
All devices
All devices
100
100
250
250
0.5
ICC
Core Power Supply
5, 6
ICCPLL
PLL Power Supply
IPP_2V5
NVCM Power Supply
1.0
Bank Power Supply4
VCCIO = 2.5 V
ICCIO, ICC_SPI
Notes:
All devices
3.5
µA
1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and
held at VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified
with master SPI configuration mode. Other modes may be up to 25% higher.
2. Frequency = 0 MHz.
3. TJ = 25 °C, power supplies at nominal voltage.
4. Does not include pull-up.
5. No PLL available on the iCE40LP384 and iCE40LP640 device.
6. VCCPLL is tied to VCC internally in packages without PLL pins.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
21
iCE40 LP/HX Family
Data Sheet
4.8. Static Supply Current – HX Devices
Table 4.7. Supply Current– HX Devices1, 2, 3, 4
4
Symbol
Parameter
Device
Typ VCC
296
Unit
µA
µA
µA
µA
µA
iCE40HX1K
iCE40HX4K
iCE40HX8K
All devices
All devices
ICC
Core Power Supply
1140
1140
0.5
5
ICCPLL
PLL Power Supply
IPP_2V5
NVCM Power Supply
1.0
Bank Power Supply4
VCCIO = 2.5 V
ICCIO, ICC_SPI
Notes:
All devices
3.5
µA
1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and
held at VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified
with master SPI configuration mode. Other modes may be up to 25% higher.
2. Frequency = 0 MHz.
3. TJ = 25 °C, power supplies at nominal voltage.
4. Does not include pull-up.
5. VCCPLL is tied to VCC internally in packages without PLL pins.
4.9. Programming NVCM Supply Current – LP Devices
Table 4.8. Programming NVCM Supply Current – LP Devices1, 2, 3, 4
5
Symbol
Parameter
Device
Typ VCC
60
Unit
µA
iCE40LP384
iCE40LP640
iCE40LP1K
iCE40LP4K
iCE40LP8K
All devices
All devices
All devices
iCE40LP384
120
120
350
350
0.5
µA
µA
ICC
Core Power Supply
µA
µA
µA
6, 7
ICCPLL
PLL Power Supply
2.5
mA
mA
µA
IPP_2V5
NVCM Power Supply
Bank Power Supply4
3.5
8
ICCIO , ICC_SPI
60
Notes:
1. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated.
2. Typical user pattern.
3. SPI programming is at 8 MHz.
4. TJ = 25 °C, power supplies at nominal voltage.
5. Per bank. VCCIO = 2.5 V. Does not include pull-up.
6. No PLL available on the iCE40LP384 and iCE40LP640 devices.
7. VCCPLL is tied to VCC internally in packages without PLLs pins.
8. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and
CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
4.10. Programming NVCM Supply Current – HX Devices
Table 4.9. Programming NVCM Supply Current – HX Devices1, 2, 3, 4
Symbol
Parameter
Device
Typ. VCC5
278
Units
µA
iCE40HX1K
iCE40HX4K
iCE40HX8K
All devices
All devices
All devices
ICC
Core Power Supply
1174
1174
0.5
µA
µA
ICCPLL6, 7
IPP_2V5
ICCIO7, ICC_SPI
PLL Power Supply
µA
NVCM Power Supply
Bank Power Supply5
2.5
mA
mA
3.5
Notes:
1. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated.
2. Typical user pattern.
3. SPI programming is at 8 MHz.
4. TJ = 25 °C, power supplies at nominal voltage.
5. Per bank. VCCIO = 2.5 V. Does not include pull-up.
6. VCCPLL is tied to VCC internally in packages without PLL pins.
7. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications.
4.11. Peak Startup Supply Current – LP Devices
Table 4.10. Peak Startup Supply Current – LP Devices
Symbol
Parameter
Device
Max
7.7
6.4
6.4
15.7
15.7
1.5
1.5
8.0
8.0
3.0
7.7
7.7
4.2
4.2
5.7
8.1
8.1
8.4
3.3
3.3
8.2
8.2
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
iCE40LP384
iCE40LP640
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP1K
iCE40LP640
iCE40LP4K
iCE40LP8K
iCE40LP384
iCE40LP640
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP384
iCE40LP640
iCE40LP1K
iCE40LP384
iCE40LP640
iCE40LP1K
iCE40LP4K
iCE40LP8K
ICCPEAK
Core Power Supply
1, 2, 4
ICCPLLPEAK
PLL Power Supply
IPP_2V5PEAK
NVCM Power Supply
NVCM Programming
Supply
3
IPP_FASTPEAK
ICCIOPEAK5, ICC_SPIPEAK
Bank Power Supply
Notes:
1. No PLL available on the iCE40LP384 and iCE40LP640 device.
2. VCCPLL is tied to VCC internally in packages without PLLs pins.
3. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and
CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
4. While no PLL is available in the iCE40LP640 the ICCPLLPEAK is additive to ICCPEAK
.
5. iCE40LP384 requires VCC to be greater than 0.7 V when VCCIO and VCC_SPI are above GND.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
23
iCE40 LP/HX Family
Data Sheet
4.12. Peak Startup Supply Current – HX Devices
Table 4.11. Peak Startup Supply Current – HX Devices
Symbol
Parameter
Device
Max
6.9
22.3
22.3
1.8
6.4
6.4
2.8
4.1
4.1
6.8
6.8
6.8
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
ICCPEAK
Core Power Supply
ICCPLLPEAK
*
PLL Power Supply
NVCM Power Supply
Bank Power Supply
IPP_2V5PEAK
ICCIOPEAK, ICC_SPIPEAK
*Note: VCCPLL is tied to VCC internally in packages without PLLs pins.
4.13. sysI/O Recommended Operating Conditions
Table 4.12. sysI/O Recommended Operating Conditions
VCCIO (V)
Typ.
3.3
Input/Output Standard
Min.
Max.
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
LVDS25E1, 2
subLVDSE1, 2
Notes:
3.14
2.37
1.71
2.37
1.71
3.46
2.62
1.89
2.62
1.89
2.5
1.8
2.5
1.8
1. Inputs on-chip. Outputs are implemented with the addition of external resistors.
2. Does not apply to Configuration Bank VCC_SPI
.
4.14. sysI/O Single-Ended DC Electrical Characteristics
Table 4.13. sysI/O Single-Ended DC Electrical Characteristics
1
VIL
VIH
Input/Output
Standard
VOL Max.
(V)
VOH Min.
IOL Max.
IOH Max.
(mA)
(V)
(mA)
8, 162, 242
0.1
Min. (V)
Max. (V)
Min. (V)
Max. (V)
–8, –162,
0.4
0.2
0.4
0.2
0.4
0.2
VCCIO – 0.4
VCCIO – 0.2
VCCIO – 0.4
VCCIO – 0.2
VCCIO – 0.4
VCCIO – 0.2
–242
LVCMOS 3.3
LVCMOS 2.5
0.8
2.0
VCCIO + 0.2 V
–0.3
–0.1
–6, –122,
6, 122, 182
–182
0.7
1.7
VCCIO + 0.2 V
VCCIO + 0.2 V
–0.3
–0.3
0.1
–0.1
–4, –82, –
4, 82, 122
0.1
122
LVCMOS 1.8
0.35VCCIO
0.65VCCIO
–0.1
Notes:
1. Some products are clamped to a diode when VIN is larger than VCCIO.
2. Only for High Drive LED outputs.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
4.15. sysI/O Differential Electrical Characteristics
The LVDS25E/subLVDSE differential output buffers are available on all banks but the LVDS/subLVDS input buffers are
only available on Bank 3 of iCE40 LP/HX devices.
4.15.1. LVDS25
Over recommended operating conditions.
Table 4.14. LVDS25
Parameter
Symbol
Test
Conditions
Parameter Description
Min.
Typ.
Max.
Units
VINP, VINM
Input Voltage
VCCIO* = 2.5
0
—
2.5
V
VTHD
Differential Input Threshold
—
250
350
450
mV
Input Common Mode
Voltage
VCM
VCCIO* = 2.5
Power on
(VCCIO/2) - 0.3
VCCIO/2
(VCCIO/2) + 0.3
±10
V
IIN
Input Current
—
—
µA
*Note: Typical
4.15.2. subLVDS
Over recommended operating conditions.
Table 4.15. subLVDS
Parameter
Symbol
Test
Conditions
Parameter Description
Min.
Typ.
Max.
Units
VINP, VINM
VTHD
Input Voltage
VCCIO* = 2.5
0
—
1.8
V
Differential Input Threshold
—
100
150
200
mV
Input Common Mode
Voltage
(VCCIO/2) -
0.25
(VCCIO/2) +
0.25
VCM
VCCIO* = 2.5
Power on
VCCIO/2
V
IIN
Input Current
—
—
±10
µA
*Note: Typical
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
25
iCE40 LP/HX Family
Data Sheet
4.16. LVDS25E Emulation
iCE40 LP/HX devices can support LVDSE outputs via emulation on all banks. The output is emulated using
complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme
shown in Figure 4.1. LVDS25E Using External Resistors is one possible solution for LVDS25E standard implementation.
Resistor values in Figure 4.1. LVDS25E Using External Resistors are industry standard values for 1% resistors.
VCCIO
R
R
OD
R
OCM
Differential
Output Pair
Figure 4.1. LVDS25E Using External Resistors
Over recommended operating conditions.
Table 4.16. LVDS25E DC Conditions
Parameter
ZOUT
RS
Description
Typ.
Units
Ω
Output impedance
Driver series resistor
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
Output differential voltage
Output common mode voltage
Back impedance
20
150
Ω
RP
140
Ω
RT
100
Ω
VOH
1.43
1.07
0.30
1.25
100.5
6.03
V
VOL
V
VOD
V
VCM
ZBACK
IDC
V
Ω
DC output current
mA
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
4.17. SubLVDS Emulation
The iCE40 LP/HX family supports the differential subLVDS standard. The output standard is emulated using
complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all banks of the devices. The
subLVDS input standard is supported by the LVDS25 differential input buffer. The scheme shown in Figure 4.2 is one
possible solution for subLVDSE output standard implementation. Use LVDS25E mode with suggested resistors for
subLVDSE operation. Resistor values in Figure 4.2 are industry standard values for 1% resistors.
VCCIO
R
R
OD
R
OCM
Differential
Output Pair
Figure 4.2. subLVDSE DC Conditions
Over recommended operating conditions.
Table 4.17. subLVDSE DC Conditions
Parameter
ZOUT
RS
Description
Typ.
20
Units
Ω
Output impedance
Driver series resistor
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
270
120
100
1.43
1.07
0.35
0.9
Ω
RP
Ω
RT
Ω
VOH
V
VOL
V
VOD
Output differential voltage
Output common mode voltage
Back impedance
V
VCM
ZBACK
IDC
V
100.5
2.8
Ω
DC output current
mA
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
27
iCE40 LP/HX Family
Data Sheet
4.18. Typical Building Block Function Performance – LP Devices*
4.18.1. Pin-to-Pin Performance (LVCMOS25) – LP Devices
Table 4.18. Pin-to-Pin Performance (LVCMOS25) – LP Devices
Function
Timing
Units
Basic Functions
16-bit decoder
4:1 MUX
11.0
12.0
13.0
ns
ns
ns
16:1 MUX
4.18.2. Register-to-Register Performance – LP Devices
Table 4.19. Register-to-Register Performance – LP Devices
Function
Timing
Units
Basic Functions
16:1 MUX
190
160
175
MHz
MHz
MHz
16-bit adder
16-bit counter
Embedded Memory Functions
256 x 16 Pseudo-Dual Port RAM
*Notes:
240
MHz
The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with device and tool
version. The tool uses internal parameters that have been characterized but are not tested on every device.
Using a VCC of 1.14 V at Junction Temp 85 °C.
4.19. Typical Building Block Function Performance – HX Devices*
4.19.1. Pin-to-Pin Performance (LVCMOS25) – HX Devices
Table 4.20. Pin-to-Pin Performance (LVCMOS25) – HX Devices
Function
Timing
Units
Basic Functions
16-bit decoder
4:1 MUX
10.0
9.0
ns
ns
ns
16:1 MUX
9.5
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
4.19.2. Register-to-Register Performance – HX Devices
Table 4.21. Register-to-Register Performance – HX Devices
Function
Timing
Units
Basic Functions
16:1 MUX
305
220
255
105
MHz
MHz
MHz
MHz
16-bit adder
16-bit counter
64-bit counter
Embedded Memory Functions
256 x 16 Pseudo-Dual Port RAM
Notes:
403
MHz
The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with device and tool
version. The tool uses internal parameters that have been characterized but are not tested on every device.
Using a VCC of 1.14 V at Junction Temp 85 °C.
4.20. Derating Logic Timing
Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in
the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a
particular temperature and voltage.
4.21. Maximum sysI/O Buffer Performance
Table 4.22. Register-to-Register Performance1
I/O Standard
Max. Speed
Units
Inputs
LVDS252
400
400
250
250
250
MHz
MHz
MHz
MHz
MHz
subLVDS182
LVCMOS33
LVCMOS25
LVCMOS18
Outputs
LVDS25E
250
155
250
250
155
MHz
MHz
MHz
MHz
MHz
subLVDS18E
LVCMOS33
LVCMOS25
LVCMOS18
Notes:
1. Measured with a toggling pattern.
2. Supported in Bank 3 only.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
29
iCE40 LP/HX Family
Data Sheet
4.22. Timing Adders
Over recommended operating conditions.
Table 4.23. Timing Adders – LP Devices*
Input Adjusters
LVDS25
LVDS, VCCIO = 2.5 V
–0.18
0.82
0.18
0.00
0.19
ns
ns
ns
ns
ns
subLVDS
subLVDS, VCCIO = 1.8 V
LVCMOS, VCCIO = 3.3 V
LVCMOS, VCCIO = 2.5 V
LVCMOS, VCCIO = 1.8 V
LVCMOS33
LVCMOS25
LVCMOS18
Output Adjusters
LVDS25E
LVDS, Emulated, VCCIO = 2.5 V
subLVDS, Emulated, VCCIO = 1.8 V
LVCMOS, VCCIO = 3.3 V
0.00
1.32
–0.12
0.00
1.32
ns
ns
ns
ns
ns
subLVDSE
LVCMOS33
LVCMOS25
LVCMOS18
*Notes:
LVCMOS, VCCIO = 2.5 V
LVCMOS, VCCIO = 1.8 V
Timing adders are relative to LVCMOS25 and characterized but not tested on every device.
LVCMOS timing measured with the load specified in the Switching Test Condition table.
All other standards tested according to the appropriate specifications.
Commercial timing numbers are shown.
Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details.
Over recommended operating conditions.
Table 4.24. Timing Adders – HX Devices*
Input Adjusters
LVDS25
LVDS, VCCIO = 2.5 V
0.13
1.03
0.16
0.00
0.23
ns
ns
ns
ns
ns
subLVDS
subLVDS, VCCIO = 1.8 V
LVCMOS, VCCIO = 3.3 V
LVCMOS, VCCIO = 2.5 V
LVCMOS, VCCIO = 1.8 V
LVCMOS33
LVCMOS25
LVCMOS18
Output Adjusters
LVDS25E
LVDS, Emulated, VCCIO = 2.5 V
subLVDS, Emulated, VCCIO = 1.8 V
LVCMOS, VCCIO = 3.3 V
0.00
1.76
0.17
0.00
1.76
ns
ns
ns
ns
ns
subLVDSE
LVCMOS33
LVCMOS25
LVCMOS18
*Notes:
LVCMOS, VCCIO = 2.5 V
LVCMOS, VCCIO = 1.8 V
Timing adders are relative to LVCMOS25 and characterized but not tested on every device.
LVCMOS timing measured with the load specified in the Switching Test Condition table.
All other standards tested according to the appropriate specifications.
Commercial timing numbers are shown.
Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
4.23. External Switching Characteristics – LP Devices
Over recommended operating conditions.
Table 4.25. External Switching Characteristics – LP Devices1, 2
Parameter
Clock
Description
Device
Min.
Max.
Units
Global Clocks
fMAX_GBUF
tW_GBUF
Frequency for Global Buffer Clock network
Clock Pulse Width for Global Buffer
All iCE40 LP devices
All iCE40 LP devices
iCE40LP384
—
0.92
—
275
—
MHz
ns
370
230
230
340
340
ps
iCE40LP640
—
ps
tSKEW_GBUF
Global Buffer Clock Skew Within a Device
iCE40LP1K
—
ps
iCE40LP4K
—
ps
iCE40LP8K
—
ps
Pin-LUT-Pin Propagation Delay
tPD Best case propagation delay through one LUT-4 All iCE40 LP devices
General I/O Pin Parameters (Using Global Buffer Clock without PLL)3
—
9.36
ns
iCE40LP384
iCE40LP640
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP384
iCE40LP640
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP384
iCE40LP640
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP384
iCE40LP640
iCE40LP1K
iCE40LP4K
iCE40LP8K
—
—
300
200
200
280
280
6.33
5.91
5.91
6.58
6.58
—
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSKEW_IO
Data bus skew across a bank of IOs
Clock to Output - PIO Output Register
—
—
—
—
—
tCO
—
—
—
–0.08
–0.33
–0.33
–0.63
–0.63
1.99
2.81
2.81
3.48
3.48
—
tSU
Clock to Data Setup - PIO Input Register
Clock to Data Hold - PIO Input Register
—
—
—
—
—
tH
—
—
—
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
31
iCE40 LP/HX Family
Data Sheet
Parameter
Description
Device
Min.
Max.
Units
General I/O Pin Parameters (Using Global Buffer Clock with PLL)3
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP1K
iCE40LP4K
iCE40LP8K
iCE40LP1K
iCE40LP4K
iCE40LP8K
—
—
2.20
2.30
2.30
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCOPLL
Clock to Output - PIO Output Register
Clock to Data Setup - PIO Input Register
Clock to Data Hold - PIO Input Register
—
5.23
6.13
6.13
–0.90
–0.80
–0.80
tSUPLL
—
—
—
tHPLL
—
—
Notes:
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 °C and 1.14 V.
Other operating conditions can be extracted from the iCECube2 software.
2. General I/O timing numbers based on LVCMOS 2.5, 0 pf load.
3. Supported on devices with a PLL.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
4.24. External Switching Characteristics – HX Devices
Over recommended operating conditions.
Table 4.26. External Switching Characteristics – HX Devices1, 2
Parameter
Clock
Description
Device
Min.
Max.
Units
Global Clocks
fMAX_GBUF
tW_GBUF
Frequency for Global Buffer Clock network
Clock Pulse Width for Global Buffer
All iCE40 HX devices
All iCE40 HX devices
iCE40HX1K
—
0.88
—
275
—
MHz
ns
727
300
300
ps
tSKEW_GBUF
Global Buffer Clock Skew Within a Device
iCE40HX4K
—
ps
iCE40HX8K
—
ps
Pin-LUT-Pin Propagation Delay
tPD Best case propagation delay through one LUT-4 All iCE40 HX devices
General I/O Pin Parameters (Using Global Buffer Clock without PLL)
—
7.30
ns
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
—
—
696
290
290
5.00
5.41
5.41
—
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSKEW_IO
Data bus skew across a bank of IOs
Clock to Output - PIO Output Register
—
—
tCO
—
—
–0.23
–0.43
–0.43
1.92
2.38
2.38
tSU
Clock to Data Setup - PIO Input Register
—
—
—
tH
Clock to Data Hold - PIO Input Register
—
—
General I/O Pin Parameters (Using Global Buffer Clock with PLL)3
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
—
—
2.96
2.51
2.51
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCOPLL
Clock to Output - PIO Output Register
Clock to Data Setup - PIO Input Register
Clock to Data Hold - PIO Input Register
—
3.10
4.16
4.16
–0.60
–0.53
–0.53
tSUPLL
—
—
—
tHPLL
—
—
Notes:
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 °C and 1.14
V. Other operating conditions, including industrial, can be extracted from the iCECube2 software.
2. General I/O timing numbers based on LVCMOS 2.5, 0pf load.
3. Supported on devices with a PLL.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
33
iCE40 LP/HX Family
Data Sheet
4.25. sysClock PLL Timing
Over recommended operating conditions.
Table 4.27. sysClock PLL Timing
Parameter
Descriptions
Conditions
Min.
Max.
Units
Input Clock Frequency
(REFERENCECLK, EXTFEEDBACK)
fIN
—
10
133
MHz
fOUT
fVCO
Output Clock Frequency (PLLOUT)
PLL VCO Frequency
—
—
16
275
MHz
MHz
533
1066
AC Characteristics
fOUT < 175 MHz
40
35
50
65
%
tDT
tPH
Output Clock Duty Cycle
175 MHz < fOUT < 275
MHz
"%
Output Phase Accuracy
—
—
—
—
—
—
—
—
1.3
—
—
—
—
147
—
—
10
10
+/–12
450
0.05
750
0.10
275
0.05
—
deg
ps p-p
UIPP
ps p-p
UIPP
ps p-p
UIPP
ns
fOUT <= 100 MHz
Output Clock Period Jitter
fOUT > 100 MHz
fOUT <= 100 MHz
1, 5
tOPJIT
Output Clock Cycle-to-cycle Jitter
Output Clock Phase Jitter
fOUT > 100 MHz
fPFD <= 25 MHz
fPFD > 25 MHz
tW
Output Clock Pulse Width
PLL Lock-in Time
At 90% or 10%
2, 3
tLOCK
—
50
us
tUNLOCK
PLL Unlock Time
—
50
ns
1000
0.02
195
500
100
—
ps p-p
UIPP
ps
fPFD 20 MHz
4
tIPJIT
Input Clock Period Jitter
fPFD < 20 MHz
tFDTAP
Fine Delay adjustment, per Tap
LATCHINPUTVALUE LOW to PLL Stable
LATCHINPUTVALUE Pulse Width
RESET Pulse Width
—
—
—
—
—
—
3
tSTABLE
ns
3
tSTABLE_PW
ns
tRST
ns
tRSTREC
RESET Recovery Time
—
us
VCO
Cycles
tDYNAMIC_WD
DYNAMICDELAY Pulse Width
100
—
iCE40 LP
iCE40 HX
1.18
1.73
4.68
4.07
ns
ns
tPDBYPASS
Propagation delay with the PLL in bypass mode
Notes:
1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is
taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed.
4. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed
in this table.
5. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
4.26. SPI Master or NVCM Configuration Time
Table 4.28. SPI Master or NVCM Configuration Time1, 2
Symbol
Parameter
Condition
Typ.
25
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
iCE40LP384 - Low Frequency (Default)
iCE40LP384 - Medium Frequency
iCE40LP384 - High Frequency
15
11
iCE40LP640 - Low Frequency (Default)
iCE40LP640 - Medium Frequency
iCE40LP640 - High Frequency
53
25
13
iCE40LP/HX1K - Low Frequency (Default)
iCE40LP/HX1K - Medium Frequency
iCE40LP/HX1K - High Frequency
iCE40LP/HX4K - Low Frequency (Default)
iCE40LP/HX4K - Medium Frequency
iCE40LP/HX4K - High Frequency
iCE40LP/HX8K - Low Frequency (Default)
iCE40LP/HX8K - Medium Frequency
iCE40LP/HX8K - High Frequency
53
POR/CRESET_B to
Device I/O Active
tCONFIG
25
13
230
110
70
230
110
70
Notes:
1. Assumes sysMEM Block is initialized to an all zero pattern if they are used.
2. The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
35
iCE40 LP/HX Family
Data Sheet
4.27. sysCONFIG Port Timing Specifications
Table 4.29. sysCONFIG Port Timing Specifications1
Symbol
All Configuration Modes
Minimum CRESET_B Low
Parameter
Min
200
49
Typ
Max
Unit
pulse width required to
restart configuration, from
falling edge to rising edge
tCRESET_B
—
—
ns
—
—
Number of configuration
clock cycles after CDONE goes
High before the PIO pins are
activated
Clock
Cycles
tDONE_IO
—
—
Slave SPI
iCE40LP384
600
800
1200
1200
1
—
—
—
—
—
15
15
15
15
—
—
—
—
25
—
—
—
—
us
us
Minimum time from a rising
edge on CRESET_B until the
first SPI write operation, first
SPI_SCK. During this time, the
iCE40 device is clearing its
internal configuration
iCE40LP640, iCE40LP/HX1K
iCE40LP/HX4K
tCR_SCK
us
iCE40LP/HX8K
us
memory.
Write
MHz
MHz
MHz
MHz
MHz
Minimum time from a rising
edge on CRESET_B until the
first SPI write operation, first
SPI_SCK. During this time, the
iCE40 LP/HX device is clearing
its internal configuration
memory.
Read iCE40LP3842
Read iCE40LP640, iCE40LP/HX1K2
Read iCE40LP/HX4K2
Read iCE40LP/HX8K2
—
—
tCR_SCK
—
—
—
—
—
—
—
20
20
12
12
13
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
tCCLKH
tCCLKL
tSTSU
tSTH
CCLK clock pulse width high
CCLK clock pulse width low
CCLK setup time
—
—
CCLK hold time
CCLK falling edge to valid
output
tSTCO
Master SPI
0
MHz
MHz
MHz
MHz
us
Off
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7.5
24
40
—
—
—
—
—
—
—
—
—
—
Low Frequency (Default)
fMCLK
MCLK clock frequency
Medium Frequency3
High Frequency3
—
600
600
600
800
800
800
800
800
800
1200
iCE40LP384 - Low Frequency (Default)
iCE40LP384 - Medium Frequency
iCE40LP384 - High Frequency
iCE40LP640, iCE40LP/HX1K - Low
iCE40LP640, iCE40LP/HX1K - Medium
iCE40LP640, iCE40LP/HX1K - High
iCE40LP/HX1K -Low Frequency (Default)
iCE40LP/HX1K - Medium Frequency
iCE40LP/HX1K - High Frequency
iCE40LP/HX4K - Low Frequency (Default)
us
us
us
us
CRESET_B high to first MCLK
edge
tMCLK
us
us
us
us
us
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
Symbol
Parameter
Min
1200
1200
1200
1200
1200
Typ
—
—
—
—
—
Max
—
—
—
—
Unit
us
iCE40LP/HX4K - Medium Frequency
iCE40LP/HX4K - high frequency
us
us
iCE40LP/HX8K - Low Frequency (Default)
iCE40LP/HX8K - Medium Frequency
iCE40LP/HX8K - High Frequency
us
us
—
Notes:
1. Does not apply for NVCM.
2. Supported only with 1.2 V VCC and at 25 °C.
3. Extended range fMAX Write operations support up to 53 MHz only with 1.2 V VCC and at 25 °C.
4.28. Switching Test Conditions
Figure 4.3 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are listed in Table 4.30.
VT
R1
Test Point
DUT
CL
Figure 4.3. Output Test Load, LVCMOS Standards
Table 4.30. Test Fixture Required Components, Non-Terminated Interfaces*
Test Condition
R
C
Timing Reference
LVCMOS 3.3 = 1.5 V
LVCMOS 2.5 = VCCIO/2
LVCMOS 1.8 = VCCIO/2
1.5 V
V
T
—
1
L
—
LVCMOS settings (L ≥ H, H ≥ L)
∞
0 pF
0 pF
—
LVCMOS 3.3 (Z ≥ H)
LVCMOS 3.3 (Z ≥ L)
Other LVCMOS (Z ≥ H)
Other LVCMOS (Z ≥ L)
LVCMOS (H ≥ Z)
VOL
VOH
VOL
VOH
VOL
VOH
1.5 V
VCCIO/2
188
VCCIO/2
VOH – 0.15 V
LVCMOS (L ≥ Z)
VOL – 0.15 V
*Note: Output test conditions for all other interfaces are determined by the respective standards.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
37
iCE40 LP/HX Family
Data Sheet
5. Pinout Information
5.1. Signal Descriptions
5.1.1. General Purpose
Signal Name
I/O
Description
IO[Bank]_[Row/Column
Number][A/B]
I/O
[Bank] indicates the bank of the device on which the pad is located.
[Number] indicates IO number on the device.
IO[Bank]_[Row/Column
Number][A/B]
[Bank] indicates the bank of the device on which the pad is located.
[Number] indicates IO number on the device.
[A/B] indicates the differential I/O. 'A' = negative input. 'B' = positive input.
I/O
I/O
HCIO[Bank]_[Number]
High Current IO. [Bank] indicates the bank of the device on which the pad is
located. [Number] indicates IO number.
NC
—
—
No connect
GND
GND – Ground. Dedicated pins. It is recommended that all GNDs are tied
together.
VCC
—
—
VCC – The power supply pins for core logic. Dedicated pins. It is
recommended that all VCCs are tied to the same supply.
VCCIO_x
VCCIO – The power supply pins for I/O Bank x. Dedicated pins. All VCCIOs
located in the same bank are tied to the same supply.
5.1.2. PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or
clock pins)
Signal Name
I/O
Description
PLL VCC – Power. Dedicated pins. The PLL requires a separate power and
ground that is quiet and stable to reduce the output clock jitter of the PLL.
VCCPLLx
—
PLL GND – Ground. Dedicated pins. The sysCLOCK PLL has the DC ground
connection made on the FPGA, so the external PLL ground connection
(GNDPLL) must NOT be connected to the board’s ground.
GNDPLLx
GBINx
—
—
Global pads. Two per side.
5.1.3. Programming and Configuration
Signal Name
I/O
Description
Dual function pins. I/Os when not used as CBSEL. Optional ColdBoot
configuration Select input, if ColdBoot mode is enabled.
CBSEL[0:1]
I/O
Configuration Reset, active Low. Dedicated input. No internal pull-up
resistor. Either actively drive externally or connect a 10 kΩ pull-up resistor
to VCCIO_2.
CRESET_B
CDONE
I
Configuration Done. Includes a permanent weak pull-up resistor to
VCCIO_2. If driving external devices with CDONE output, an external pull-
up resistor to VCCIO_2 may be required. Refer to the iCE40 Programming
and Configuration (FPGA-TN-02001) for more details. Following device
configuration the iCE40LP640 and iCE40LP1K in the SWG16 package CDONE
pin can be used as a user output.
I/O
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
Signal Name
I/O
Description
SPI interface voltage supply input. Must have a valid voltage even if
configuring from NVCM.
VCC_SPI
—
Input Configuration Clock for configuring an FPGA in Slave SPI mode.
Output Configuration Clock for configuring an FPGA configuration modes.
SPI_SCK
SPI_SS
I/O
I/O
SPI Slave Select. Active Low. Includes an internal weak pull-up resistor to
VCC_SPI during configuration. During configuration, the logic level sampled
on this pin determines the configuration mode used by the iCE40 LP/HX
device. An input when sampled at the start of configuration. An input when
in SPI Peripheral configuration mode (SPI_SS = Low). An output when in
Master SPI Flash configuration mode.
SPI_SI
I/O
I/O
Slave SPI serial data input and master SPI serial data output
Slave SPI serial data output and master SPI serial data input
SPI_SO
Optional fast NVCM programming supply. VPP_FAST, used only for fast
production programming, must be left floating or unconnected in
applications, except CM36 and CM49 packages MUST have the VPP_FAST
ball connected to VCCIO_0 ball externally.
VPP_FAST
VPP_2V5
—
—
VPP_2V5 NVCM programming and operating supply
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
39
iCE40 LP/HX Family
Data Sheet
5.2. Pin Information Summary
iCE40LP384
SG32 CM362 CM492
iCE40LP640
SWG16
iCE40LP1K
SWG16 CM361, CM491, CM81 CB81 QN84 CM121 CB121
General Purpose I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Configuration
Total General Purpose
Single
6
5
0
6
4
4
7
4
6
4
10
7
4
12
4
37
3
0
1
2
4
3
0
1
2
4
4
7
4
6
4
10
7
4
10
4
35
17
15
11
16
4
17
16
8
17
4
17
17
11
18
4
24
25
18
24
4
24
21
19
24
4
21
25
10
10
25
63
62
67
95
92
High Current Outputs per Bank
Bank 0
Bank 1
Bank 2
Bank 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
3
3
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Total Current Outputs
Differential Inputs per Bank
Bank 0
Bank 1
Bank 2
Bank 3
0
0
0
3
3
0
0
0
3
3
0
0
0
6
6
0
0
0
1
1
0
0
0
1
1
0
0
0
3
3
0
0
0
5
5
0
0
0
8
8
0
0
0
9
9
0
0
0
7
7
0
0
0
12
12
0
0
0
12
12
Total Differential Inputs
Dedicated Inputs per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Configuration
Total Dedicated Inputs
Vccio Pins
Bank 0
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
1
0
0
1
0
0
1
0
0
1
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
2
2
1
1
Bank 1
Bank 2
1
1
1
1
1
1
1
1
1
1
2
1
Bank 3
1
0
0
0
0
0
0
1
1
1
2
2
VCC
1
1
2
1
1
1
2
3
3
4
4
4
VCC_SPI
1
1
1
0
0
1
1
1
1
1
1
1
VPP_2V5
VPP_FAST
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
3
VCCPLL
0
0
0
0
0
0
1
1
0
0
1
1
GND
NC
2
0
3
0
3
0
2
0
2
0
3
0
4
0
5
0
8
0
4
0
8
0
11
3
Total Count of Bonded
Pins
32
36
49
16
16
36
49
81
81
84
121
121
Notes:
1. VCCIO0 and VCCIO1 are connected together.
2. VCCIO2 and VCCIO3 are connected together.
3. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and
CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
iCE40LP4K
CM121
iCE40LP8K
CM121
iCE40HX1K
CB132
CM81
CM225
CM81
CM225
VQ100
TQ144
General Purpose I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Configuration
Total General
Purpose
17
15
9
18
4
23
21
19
26
4
46
42
40
46
4
17
15
9
18
4
23
21
19
26
4
46
42
40
46
4
19
19
12
18
4
24
25
20
22
4
23
25
20
24
4
63
93
178
63
93
178
72
95
96
High Current Outputs per Bank
Bank 0
Bank 1
Bank 2
Bank 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Total Differential
Differential Inputs per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Total Differential
Dedicated Inputs per Bank
Bank 0
Bank 1
Bank 2
0
0
0
9
9
0
0
0
13
13
0
0
0
23
23
0
0
0
9
9
0
0
0
13
13
0
0
0
23
23
0
0
0
9
9
0
0
0
11
11
0
0
0
12
12
0
0
2
0
0
2
0
0
2
0
0
2
0
1
2
0
0
3
0
0
2
0
0
2
0
0
2
0
0
2
0
1
2
0
0
3
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
Bank 3
Configuration
Total Dedicated
Vccio Pins
Bank 0
1
1
1
1
3
3
1
1
1
1
3
3
2
2
2
2
2
2
Bank 1
Bank 2
1
1
3
1
1
3
2
2
2
Bank 3
1
2
4
1
2
4
3
3
2
VCC
3
4
8
3
4
8
4
5
4
VCC_SPI
1
1
1
1
1
1
1
1
1
VPP_2V5
1
1
1
1
1
1
1
1
1
VPP_FAST
VCCPLL
GND
NC
Total Count of
Bonded Pins
*
1
1
5
0
1
2
12
0
121
1
2
18
0
225
1
1
5
0
1
2
12
0
121
1
2
18
0
225
1
0
10
0
100
1
1
14
2
132
1
1
10
19
144
81
81
*Note: 1VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
41
iCE40 LP/HX Family
Data Sheet
iCE40HX4K
CB132
iCE40HX8K
BG121
TQ144
BG121
CB132
CM225
CT256
General Purpose I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
23
21
19
26
4
24
25
18
24
4
27
29
19
28
4
23
21
19
26
4
24
25
18
24
4
46
42
40
46
4
52
52
46
52
4
Configuration
Total General Purpose Single Ended
I/O
93
95
107
93
95
178
206
High Current Outputs per Bank
Bank 0
Bank 1
Bank 2
Bank 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Total Differential Inputs
Differential Inputs per Bank
Bank 0
Bank 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
0
0
0
0
0
0
0
Bank 3
Total Differential Inputs
13
13
12
12
14
14
13
13
12
12
23
23
26
26
Dedicated Inputs per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Configuration
Total Dedicated Inputs
Vccio Pins
Bank 0
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
2
1
1
2
2
2
2
1
1
2
2
3
3
4
4
Bank 1
Bank 2
1
2
2
1
2
3
4
Bank 3
2
3
2
2
3
4
4
VCC
4
5
4
4
5
8
6
VCC_SPI
1
1
1
1
1
1
1
VPP_2V5
1
1
1
1
1
1
1
VPP_FAST
VCCPLL
GND
NC
*
1
2
12
0
1
2
15
0
1
2
11
6
1
2
12
0
1
2
15
0
1
2
18
0
1
2
20
0
Total Count of Bonded Pins
121
132
144
121
132
225
256
*Note: VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
5.3. iCE40 LP/HX Part Number Description
5.3.1. Ultra Low Power (LP) Devices
ICE40LPXXX – XXXXXXX
Device Family
Shipping Method
TR = Tape and Reel
iCE40 FPGA
TR50 = Tape and Reel 50 units
TR1K = Tape and Reel 1,000 units
Series
LP = Low Power Series
Package
Logic Cells
SWG16 = 16-Ball WLCSP (0.35 mm Pitch)
CM36 = 36-Ball ucBGA (0.4 mm Pitch)
CM49 = 49-Ball ucBGA (0.4 mm Pitch)
CM81 = 81-Ball ucBGA (0.4 mm Pitch)
CB81 = 81-Ball csBGA (0.5 mm Pitch)
CM121 = 121-Ball ucBGA (0.4 mm Pitch)
CB121 = 121-Ball csBGA (0.5 mm Pitch)
CM225 = 225-Ball ucBGA (0.4 mm Pitch)
SG32 = 32-Pin QFN (0.5 mm Pitch)
QN84 = 84-Pin QFN (0.5 mm Pitch)
384 = 384 Logic Cells
640 = 640 Logic Cells
1K = 1,280 Logic Cells
4K = 3,520 Logic Cells
8K = 7,680 Logic Cells
Figure 5.1. Low Power (LP) Devices
5.3.2. High Performance (HX) Devices
ICE40HXXX – XXXXXXX
Device Family
Shipping Method
TR = Tape and Reel
iCE40 Mobile FPGA
Series
HX = High Performance Series
Package
Logic Cells
CB132 = 132-Ball csBGA (0.5 mm Pitch)
CM225 = 225-Ball ucBGA (0.4 mm Pitch)
CT256 = 256-Ball caBGA (0.8 mm Pitch)
TQ144 = 144-Pin TQFP (0.5 mm Pitch)
VQ100 = 100-Pin VQFP (0.5 mm Pitch)
BG121 = 121-Ball caBGA (0.8 mm Pitch)
1K = 1,280 Logic Cells
4K = 3,520 Logic Cells
8K = 7,680 Logic Cells
Figure 5.2. High Performance (HX) Devices
Note: All parts shipped in trays unless noted.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
43
iCE40 LP/HX Family
Data Sheet
5.4. Ordering Information
iCE40 LP/HX devices have top-side markings as shown below:
Industrial
ꢁ
iCE40HX8K
CM225
Datecode
Figure 5.3. High Performance (HX) Devices
Note: Markings are abbreviated for small packages.
5.5. Ordering Part Numbers
5.5.1. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging
Part Number
LUTs
Supply Voltage
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
Package
Leads
36
36
36
49
49
49
32
32
32
16
16
16
16
16
16
36
36
36
49
49
49
81
81
81
81
81
81
121
Temperature
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
ICE40LP384-CM36
384
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free QFN
ICE40LP384-CM36TR
ICE40LP384-CM36TR1K
ICE40LP384-CM49
384
384
384
ICE40LP384-CM49TR
ICE40LP384-CM49TR1K
ICE40LP384-SG32
384
384
384
ICE40LP384-SG32TR
ICE40LP384-SG32TR1K
ICE40LP640-SWG16TR
ICE40LP640-SWG16TR50
ICE40LP640-SWG16TR1K
ICE40LP1K-SWG16TR
ICE40LP1K-SWG16TR50
ICE40LP1K-SWG16TR1K
ICE40LP1K-CM36
384
Halogen-Free QFN
384
Halogen-Free QFN
640
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free WLCSP
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free csBGA
Halogen-Free csBGA
Halogen-Free csBGA
Halogen-Free ucBGA
640
640
1280
1280
1280
1280
1280
1280
1280
1280
1280
1280
1280
1280
1280
1280
1280
1280
ICE40LP1K-CM36TR
ICE40LP1K-CM36TR1K
ICE40LP1K-CM49
ICE40LP1K-CM49TR
ICE40LP1K-CM49TR1K
ICE40LP1K-CM81
ICE40LP1K-CM81TR
ICE40LP1K-CM81TR1K
ICE40LP1K-CB81
ICE40LP1K-CB81TR
ICE40LP1K-CB81TR1K
ICE40LP1K-CM121
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
Part Number
LUTs
1280
1280
1280
1280
3520
3520
3520
3520
3520
3520
3520
7680
7680
7680
7680
7680
7680
7680
Supply Voltage
1.2 V
Package
Leads
121
121
121
84
Temperature
IND
ICE40LP1K-CM121TR
ICE40LP1K-CM121TR1K
ICE40LP1K-CB121
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free csBGA
Halogen-Free QFN
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
Halogen-Free ucBGA
1.2 V
IND
1.2 V
IND
ICE40LP1K-QN84
1.2 V
IND
ICE40LP4K-CM81
1.2 V
81
IND
ICE40LP4K-CM81TR
ICE40LP4K-CM81TR1K
ICE40LP4K-CM121
ICE40LP4K-CM121TR
ICE40LP4K-CM121TR1K
ICE40LP4K-CM225
ICE40LP8K-CM81
1.2 V
81
IND
1.2 V
81
IND
1.2 V
121
121
121
225
81
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
ICE40LP8K-CM81TR
ICE40LP8K-CM81TR1K
ICE40LP8K-CM121
ICE40LP8K-CM121TR
ICE40LP8K-CM121TR1K
ICE40LP8K-CM225
1.2 V
81
IND
1.2 V
81
IND
1.2 V
121
121
121
225
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
5.5.2. High-Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging
Part Number
LUTs
1280
1280
1280
3520
3520
3520
3520
7680
7680
7680
7680
7680
Supply Voltage
Package
Leads
132
100
144
121
121
132
144
121
121
132
225
256
Temperature
IND
ICE40HX1K-CB132
ICE40HX1K-VQ100
ICE40HX1K-TQ144
ICE40HX4K-BG121
ICE40HX4K-BG121TR
ICE40HX4K-CB132
ICE40HX4K-TQ144
ICE40HX8K-BG121
ICE40HX8K-BG121TR
ICE40HX8K-CB132
ICE40HX8K-CM225
ICE40HX8K-CT256
1.2 V
Halogen-Free csBGA
Halogen-Free VQFP
Halogen-Free TQFP
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free csBGA
Halogen-Free TQFP
Halogen-Free caBGA
Halogen-Free caBGA
Halogen-Free csBGA
Halogen-Free ucBGA
Halogen-Free caBGA
1.2 V
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
1.2 V
IND
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
45
iCE40 LP/HX Family
Data Sheet
Supplemental Information
For Further Information
A variety of technical documents for the iCE40 LP/HX family are available on the Lattice web site.
iCE40 Programming and Configuration (FPGA-TN-02001)
Memory Usage Guide for iCE40 Devices (TN1250)
iCE40 sysCLOCK PLL Design and Usage Guide (TN1251)
iCE40 Hardware Checklist (TN1252)
Using Differential I/O LVDS Sub-LVDS in iCE40 Devices (TN1253)
PCB Layout Recommendations for BGA Packages (FPGA-TN-02010)
iCE40 LED Driver Usage Guide (TN1288)
iCE40 Pinout Files
Thermal Management
Lattice design tools
IBIS
Package Diagrams
Schematic Symbols
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
Technical Support
For assistance, submit a technical support case at www.latticesemi.com/techsupport.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
47
iCE40 LP/HX Family
Data Sheet
Revision History
Revision 3.5, September 2018
Section
Change Summary
All
Changed document number from DS1040 to FPGA-DS-02029.
Updated document template.
Pinout Information
Changed signal name from SPI_SS_B to SPI_SS in Signal Descriptions table.
Revision 3.4, October 2017
Section
Change Summary
Pin Information
Modified the dedicated inputs for Bank 1 of iCE40HX1K (CB132, TQ144), iCE40HX4K (CB132,
TQ144) and iCE40HX8K (CB132, CM225, CT256).
Revision 3.3, March 2017
Section
Change Summary
Introduction
Updated Features section. Added 121-ball caBGA package for ICE40 HX4K/8K to Table 1-1,
iCE40 LP/HX Family Selection Guide.
Architecture
Updated PLB Blocks section. Changed “subtracters” to “subtractors” in the Carry Logic
description.
Updated Clock/Control Distribution Network section. Switched the Clock Enable and the
Reset headings in Table 2-2, Global Buffer (GBUF) Connections to Programmable Logic
Blocks.
Pinout Information
Updated Pin Information Summary section. Added BG121information under iCE40HX4K and
iCE40HX8K.
Ordering Information
Updated iCE40 LP/HX Part Number Description section. Added Shipping Method and BG121
package under High Performance (HX) Devices.
Updated Ordering Information section. Added part numbers for BG121 under High-
Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging.
Supplemental Information
Corrected reference to “Package Diagrams Data Sheet”.
Revision 3.2, October 2015
Section
Change Summary
Introduction
Updated Features section. Added footnote to 16 WLCSP Programmable I/O: Max Inputs
(LVDS25) in Table 1-1, iCE40 LP/HX Family Selection Guide.
DC and Switching Characteristics
Updated sysCLOCK PLL Timing section. Changed tDT conditions.
Updated Programming NVCM Supply Current – LP Devices section. Changed IPP_2V5 and
ICCIO, ICC_SPI units.
Revision 3.1, March 2015
Section
Change Summary
DC and Switching Characteristics
Updated sysI/O Single-Ended DC Electrical Characteristics section. Changed LVCMOS 3.3 and
LVCMOS 2. 5 VOH Min. (V) from 0.5 to 0.4.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
Revision 3.0, July 2014
Section
Change Summary
DC and Switching Characteristics
Revised and/or added Typ. VCC data in the following sections.
Static Supply Current – LP Devices
Static Supply Current – HX Devices
Programming NVCM Supply Current – LP Devices
Programming NVCM Supply Current – HX Devices
In each section table, the footnote indicating Advanced device status was removed.
Pinout Information
Updated Pin Information Summary section. Added footnote 1 to CM49 under iCE40LP1K.
Revision 02.9, April 2014
Section
Change Summary
Ordering Information
Changed “i” to “I” in part number description and ordering part numbers.
Added part numbers to the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS)
Packaging table.
Revision 02.8, February 2014
Section
Change Summary
DC and Switching Characteristics
Updated Features section.
Corrected standby power units.
Included High Current LED Drivers.
Updated Table 1-1, iCE40 LP/HX Family Selection Guide.
Removed LP384 Programmable I/O for 81 ucBGA package.
Architecture
Updated Supported Standards section. Added information on High Current LED drivers.
Corrected typos.
DC and Switching Characteristics
Added footnote to the Peak Startup Supply Current – LP Devices table.
Updated part number description in the Ultra Low Power (LP) Devices section.
Ordering Information
Added part numbers to the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS)
Packaging table.
Revision 02.7, October 2013
Section
Change Summary
Introduction
Updated Features list and iCE40 LP/HX Family Selection Guide table.
Revised iCE40-1K device to iCE40LP/HX1K device.
Added iCE40LP640 device information.
Architecture
DC and Switching Characteristics
Pinout Information
Ordering Information
Added iCE40LP640 and iCE40LP1K information.
Added iCE40LP640 and iCE40LP1K information.
Revision 02.6, September 2013
Section
Change Summary
DC and Switching Characteristics
Updated Absolute Maximum Ratings section.
Updated sysCLOCK PLL Timing – Preliminary table.
Updated Pin Information Summary table.
Pinout Information
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
49
iCE40 LP/HX Family
Data Sheet
Revision 02.5, August 2013
Section
Change Summary
Introduction
Updated the iCE40 LP/HX Family Selection Guide table.
Updated the following tables:
DC and Switching Characteristics
Absolute Maximum Ratings
Power-On-Reset Voltage Levels
Static Supply Current – LP Devices
Static Supply Current – HX Devices
Programming NVCM Supply Current – LP Devices
Programming NVCM Supply Current – HX Devices
Peak Startup Supply Current – LP Devices
sysI/O Recommended Operating Conditions
Typical Building Block Function Performance – HX Devices
External Switching Characteristics – HX Devices
sysCLOCK PLL Timing – Preliminary
SPI Master or NVCM Configuration Time
Pinout Information
Updated the Pin Information Summary table.
Revision 02.4, July 2013
Section
Change Summary
Introduction
Updated the iCE40 LP/HX Family Selection Guide table.
Updated the sysCONFIG Port Timing Specifications table.
Updated footnote in DC Electrical Characteristics table.
GDDR tables removed. Support to be provided in a technical note.
Updated the Pin Information Summary table.
Updated the top-side markings figure.
DC and Switching Characteristics
Pinout Information
Ordering Information
Updated the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging
table.
Revision 02.3, May 2013
Section
Change Summary
DC and Switching Characteristics
Added new data from Characterization.
Revision 02.2, April 2013
Section
Change Summary
Introduction
Added the LP8K 81 ucBGA.
Corrected typos.
Architecture
DC and Switching Characteristics
Pinout Information
Ordering Information
Corrected typos.
Added 7:1 LVDS waveforms.
Corrected typos in signal descriptions.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
50
FPGA-DS-02029-3.5
iCE40 LP/HX Family
Data Sheet
Revision 02.1, March 2013
Section
Change Summary
DC and Switching Characteristics
Recommended operating conditions added requirement for Master SPI.
Updated Recommended Operating Conditions for VPP_2V5.
Updated Power-On-Reset Voltage Levels and sequence requirements.
Updated Static Supply Current conditions.
Changed unit for tSKEW_IO from ns to ps.
Updated range of CCLK fMAX.
Ordering Information
Updated ordering information to include tape and reel part numbers.
Revision 02.0, September 2012
Section
Change Summary
All
Merged SiliconBlue iCE40 LP and HX data sheets and updated to Lattice format.
Revision 01.31, September 2012
Section
Change Summary
Introduction
Updated Table 1.
Revision 01.3, September 2012
Section
Change Summary
All
Production release.
—
Updated notes on Table 3: Recommended Operating Conditions.
Updated values in Table 4, Table 5, Table 12, Table 13 and Table 17.
—
Revision 01.21, September 2012
Section
Change Summary
—
Updated Figure 3 and Figure 4 to specify iCE40.
Revision 01.2, August 2012
Section
Change Summary
—
Updated company name.
Revision 01.1, July 2011
Section
Change Summary
—
Moved package specifications to iCE40 pinout Excel files.
Updated Table 1 maximum I/Os.
Revision 01.01, July 2011
Section
Change Summary
—
Added 640, 1K and 4K to Table 13 configuration times. Updated Table 1 maximum I/Os.
Revision 01.0, July 2011
Section
Change Summary
—
Initial release.
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02029-3.5
51
7th Floor, 111 SW 5th Avenue
Portland, OR 97204, USA
T 503.268.8000
www.latticesemi.com
相关型号:
©2020 ICPDF网 联系我们和版权申明