GAL16V8B-15LJI [LATTICE]
High Performance E2CMOS PLD Generic Array Logic; 高性能E2CMOS PLD通用阵列逻辑
| 型号： | GAL16V8B-15LJI |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | High Performance E2CMOS PLD Generic Array Logic |
| 文件： | 总23页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GAL16V8
High Performance E2CMOS PLD
Generic Array Logic™
FUNCTIONAL BLOCK DIAGRAM
FEATURES
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
I/CLK
CLK
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
8
8
OLMC
I
I
I
I
I
I
I
I
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/Guaranteed 100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
8
8
8
8
8
8
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 20-pin PAL® Devices with Full Func-
tion/Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
I/O/Q
I/OE
OE
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
PIN CONFIGURATION
The GAL16V8C, at 5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
DIP
1
20
Vcc
I/CLK
PLCC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
I
I
I
I/CLK Vcc I/O/Q
20
I
I
2
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL16V8 are the PAL architectures
listed in the table of the macrocell description section. GAL16V8
devices are capable of emulating any of these PAL architectures
with full function/fuse map/parametric compatibility.
GAL
18
I/O/Q
4
6
I
16V8
I/O/Q
I/O/Q
I
GAL16V8
Top View
5
I
I
16
I
15
I/O/Q
I/O/Q
I
I
I
14
I
8
9
I
11
13
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor guarantees 100% field programmability
and functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are guaranteed.
GND I/OE I/O/Q I/O/Q
I
10
11
GND
2
Copyright © 1996 Lattice Semiconductor Corporation. E CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, L with Lattice Semiconductor Corp. and L (Stylized) are registered
trademarks of Lattice Semiconductor Corporation (LSC). The LSC Logo, Generic Array Logic, In-System Programmability, In-System Programmable, ISP, ispATE, ispCODE, ispDOWNLOAD,
ispGDS, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice
Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
1996 Data Book
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.lattice.com
Specifications GAL16V8
GAL16V8 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)
Ordering #
Package
5
3
4
115
115
20-Pin Plastic DIP
GAL16V8C-5LP
GAL16V8C-5LJ
GAL16V8C-7LP
GAL16V8C-7LJ
GAL16V8B-7LP
GAL16V8B-7LJ
GAL16V8B-10LP
20-Lead PLCC
7.5
7
5
20-Pin Plastic DIP
20-Lead PLCC
115
115
115
115
115
20-Pin Plastic DIP
20-Lead PLCC
10
15
10
12
7
20-Pin Plastic DIP
115
55
GAL16V8B-10LJ
GAL16V8B-15QP
GAL16V8B-15QJ
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
10
55
90
GAL16V8B-15LP
20-Pin Plastic DIP
90
55
55
GAL16V8B-15LJ
GAL16V8B-25QP
GAL16V8B-25QJ
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
25
15
12
90
90
GAL16V8B-25LP
GAL16V8B-25LJ
20-Pin Plastic DIP
20-Lead PLCC
Industrial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)
Ordering #
Package
7.5
10
15
20
25
7
5
130
130
130
130
130
130
65
GAL16V8C-7LPI
GAL16V8C-7LJI
GAL16V8B-10LPI
GAL16V8B-10LJI
GAL16V8B-15LPI
GAL16V8B-15LJI
GAL16V8B-20QPI
GAL16V8B-20QJI
GAL16V8B-25QPI
GAL16V8B-25QJI
20-Pin Plastic DIP
20-Lead PLCC
10
12
13
15
7
20-Pin Plastic DIP
20-Lead PLCC
10
11
12
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
65
65
20-Pin Plastic DIP
20-Lead PLCC
65
130
130
GAL16V8B-25LPI
GAL16V8B-25LJI
20-Pin Plastic DIP
20-Lead PLCC
PART NUMBER DESCRIPTION
_
XXXXXXXX XX
X
X X
GAL16V8C Device Name
GAL16V8B
Grade
Blank = Commercial
I = Industrial
Speed (ns)
L = Low Power Power
Package P = Plastic DIP
Q = Quarter Power
J = PLCC
1996 Data Book
3-66
Specifications GAL16V8
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is ac-
complished by development software/hardware and is completely
transparent to the user.
PAL Architectures
Emulated by GAL16V8
GAL16V8
Global OLMC Mode
16R8
16R6
16R4
16RP8
16RP6
16RP4
Registered
Registered
Registered
Registered
Registered
Registered
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes are illustrated in the following pages. Two global bits, SYN
and AC0, control the mode configuration for all macrocells. The
XOR bit of each macrocell controls the polarity of the output in any
of the three modes, while the AC1 bit of each of the macrocells
controls the input/output configuration. These two global and 16
individual architecture bits define all possible configurations in a
GAL16V8 . The information given on these architecture bits is
only to give a better understanding of the device. Compiler soft-
ware will transparently set these architecture bits from the pin
definitions, so the user should not need to directly manipulate
these architecture bits.
16L8
16H8
16P8
Complex
Complex
Complex
10L8
12L6
14L4
16L2
10H8
12H6
14H4
16H2
10P8
12P6
14P4
16P2
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
The following is a list of the PAL architectures that the GAL16V8
can emulate. It also shows the OLMC mode under which the
GAL16V8 emulates the PAL architecture.
COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OLMC
modes as different device types. These device types are listed
in the table below. Most compilers have the ability to automati-
cally select the device type, generally based on the register usage
and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. The different device types listed in the table
can be used to override the automatic device selection by the
software. For further details, refer to the compiler software
manuals.
In registered mode pin 1 and pin 11 are permanently configured
as clock and output enable, respectively. These pins cannot be
configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.
Registered
Complex
Simple
Auto Mode Select
ABEL
CUPL
LOG/iC
OrCAD-PLD
PLDesigner
TANGO-PLD
P16V8R
G16V8MS
GAL16V8_R
"Registered"1
P16V8R2
P16V8C
G16V8MA
GAL16V8_C7
"Complex"1
P16V8C2
P16V8AS
G16V8AS
GAL16V8_C8
"Simple"1
P16V8
G16V8
GAL16V8
GAL16V8A
P16V8A
G16V8
P16V8C2
G16V8R
G16V8C
G16V8AS3
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
1996 Data Book
3-67
Specifications GAL16V8
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
mode. Dedicated input or output functions can be implemented
as subsets of the I/O function.
Architecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations
of polarity, I/O and register placement.
Registered outputs have eight product terms per output. I/O's
have seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/O's are possible in this
CLK
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.
D
Q
Q
XOR
OE
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
1996 Data Book
3-68
Specifications GAL16V8
REGISTERED MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
2128
PTD
28
0
4
8
12
16
20
24
0000
0224
OLMC
19
18
17
16
15
14
13
XOR-2048
AC1-2120
2
3
4
5
6
7
8
9
0256
0480
OLMC
XOR-2049
AC1-2121
0512
0736
OLMC
XOR-2050
AC1-2122
0768
0992
OLMC
XOR-2051
AC1-2123
1024
1248
OLMC
XOR-2052
AC1-2124
1280
1504
OLMC
XOR-2053
AC1-2125
1536
1760
OLMC
XOR-2054
AC1-2126
1792
2016
OLMC
12
11
XOR-2055
AC1-2127
OE
2191
SYN-2192
AC0-2193
1996 Data Book
3-69
Specifications GAL16V8
COMPLEX MODE
In the Complex mode, macrocells are configured as output only
or I/O functions.
pability. Designs requiring eight I/O's can be implemented in the
Registered mode.
Architecture configurations available in this mode are similar to
the common 16L8 and 16P8 devices with programmable polarity
in each macrocell.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
11 are always available as data inputs into theAND array.
Up to six I/O's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the I/O function. The
two outer most macrocells (pins 12 & 19) do not have input ca-
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
XOR
- Pin 13 through Pin 18 are configured to this function.
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
XOR
- Pin 12 and Pin 19 are configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
1996 Data Book
3-70
Specifications GAL16V8
COMPLEX MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
2128
PTD
0
4
8
12
16
20
24
28
0000
0224
OLMC
XOR-2048
AC1-2120
19
2
3
4
0256
0480
OLMC
XOR-2049
AC1-2121
18
0512
0736
OLMC
XOR-2050
AC1-2122
17
0768
0992
OLMC
16
XOR-2051
AC1-2123
5
6
7
8
1024
1248
OLMC
15
XOR-2052
AC1-2124
1280
1504
OLMC
14
XOR-2053
AC1-2125
1536
1760
OLMC
XOR-2054
AC1-2126
13
1792
2016
OLMC
12
XOR-2055
AC1-2127
9
11
2191
SYN-2192
AC0-2193
1996 Data Book
3-71
Specifications GAL16V8
SIMPLE MODE
In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.
Pins 1 and 11 are always available as data inputs into the AND
array. The center two macrocells (pins 15 & 16) cannot be used
as input or I/O pins, and are only available as dedicated outputs.
Architecture configurations available in this mode are similar to
the common 10L8 and 12P6 devices with many permutations of
generic output polarity or input choices.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.
All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro-
grammable polarity.
Combinatorial Output with Feedback Configuration
for Simple Mode
Vcc
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
XOR
Combinatorial Output Configuration for Simple Mode
Vcc
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- Pins 15 & 16 are permanently configured to this
function.
XOR
Dedicated Input Configuration for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
1996 Data Book
3-72
Specifications GAL16V8
SIMPLE MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
2128
0
4
8
12
16
20
24
28
PTD
0000
0224
OLMC
19
18
17
16
15
14
13
XOR-2048
AC1-2120
2
3
0256
0480
OLMC
XOR-2049
AC1-2121
0512
0736
OLMC
XOR-2050
AC1-2122
4
5
6
0768
0992
OLMC
XOR-2051
AC1-2123
1024
1248
OLMC
XOR-2052
AC1-2124
1280
1504
OLMC
XOR-2053
AC1-2125
7
8
1536
1760
OLMC
XOR-2054
AC1-2126
1792
2016
OLMC
XOR-2055
AC1-2127
12
11
9
2191
SYN-2192
AC0-2193
1996 Data Book
3-73
SpecificationsGAL16V8C
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING COND.
Commercial Devices:
Ambient Temperature (TA) ...............................0 to 75°C
Supply voltage (VCC)
Supply voltage VCC ....................................... –0.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied .......... –2.5 to VCC +1.0V
Storage Temperature.................................–65 to 150°C
Ambient Temperature with
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient Temperature (TA) ...........................–40 to 85°C
Supply voltage (VCC)
Power Applied ........................................–55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
with Respect to Ground ..................... +4.50 to +5.50V
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.3
MAX. UNITS
VIL
VIH
IIL1
Input Low Voltage
Vss – 0.5
2.0
—
—
—
—
—
—
—
—
—
—
0.8
Vcc+1
–100
10
V
V
Input High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
Output Low Voltage
0V ≤ VIN ≤ VIL (MAX.)
3.5V ≤ VIN ≤ VCC
µA
µA
V
IIH
—
VOL
VOH
IOL
IOL = MAX. Vin = VIL or VIH
IOH = MAX. Vin = VIL or VIH
—
0.5
Output High Voltage
2.4
—
—
V
Low Level Output Current
High Level Output Current
Output Short Circuit Current
16
mA
mA
mA
IOH
IOS2
—
–3.2
–150
VCC = 5V VOUT = 0.5V TA= 25°C
–30
COMMERCIAL
ICC
Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V
L -5/-7
L -7
—
—
75
75
115
130
mA
mA
ftoggle = 15MHz Outputs Open
INDUSTRIAL
ICC
Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
1996 Data Book
3-74
SpecificationsGAL16V8C
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
COM
-5
COM
-7
IND
-7
TEST
COND1.
DESCRIPTION
PARAMETER
UNITS
MIN. MAX.
MIN. MAX.
MIN. MAX.
tpd
A
Input or I/O to
Comb. Output
8 outputs switching
1 output switching
1
5
3
7.5
7
1
7.5
—
ns
ns
—
—
—
—
tco
tcf2
tsu
th
A
Clock to Output Delay
1
—
3
4
3
2
—
7
5
3
1
—
7
5
3
ns
ns
ns
—
—
Clock to Feedback Delay
Setup Time, Input or Feedback before Clock↑
Hold Time, Input or Feedback after Clock↑
—
—
—
—
—
A
0
0
—
—
0
—
—
ns
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
142.8 —
83.3
83.3
MHz
fmax3
A
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
166
166
—
—
100
100
—
—
100
100
—
—
MHz
MHz
Maximum Clock Frequency with
No Feedback
twh
twl
—
—
Clock Pulse Duration, High
Clock Pulse Duration, Low
3
3
—
—
5
5
—
—
5
5
—
—
ns
ns
ten
B
B
Input or I/O to Output Enabled
OE to Output Enabled
1
1
6
6
3
2
9
6
1
1
9
6
ns
ns
tdis
C
C
Input or I/O to Output Disabled
OE to Output Disabled
1
1
5
5
2
9
6
1
1
9
6
ns
ns
1.5
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section. Characterized initially and after any design or process changes that may affect these
parameters.
CAPACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
Input Capacitance
I/O Capacitance
MAXIMUM*
UNITS
pF
TEST CONDITIONS
VCC = 5.0V, VI = 2.0V
VCC = 5.0V, VI/O = 2.0V
CI
8
8
CI/O
pF
*Guaranteed but not 100% tested.
1996 Data Book
3-75
SpecificationsGAL16V8B
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING COND.
Commercial Devices:
Ambient Temperature (TA) ...............................0 to 75°C
Supply voltage (VCC)
Supply voltage VCC ....................................... –0.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied .......... –2.5 to VCC +1.0V
Storage Temperature.................................–65 to 150°C
Ambient Temperature with
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient Temperature (TA) ...........................–40 to 85°C
Supply voltage (VCC)
Power Applied ........................................–55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
with Respect to Ground ..................... +4.50 to +5.50V
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.3
MAX. UNITS
VIL
VIH
IIL1
Input Low Voltage
Vss – 0.5
2.0
—
—
—
—
—
—
—
—
—
—
0.8
Vcc+1
–100
10
V
V
Input High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
Output Low Voltage
0V ≤ VIN ≤ VIL (MAX.)
3.5V ≤ VIN ≤ VCC
µA
µA
V
IIH
—
VOL
VOH
IOL
IOL = MAX. Vin = VIL or VIH
IOH = MAX. Vin = VIL or VIH
—
0.5
Output High Voltage
2.4
—
—
V
Low Level Output Current
High Level Output Current
Output Short Circuit Current
24
mA
mA
mA
IOH
IOS2
—
–3.2
–150
VCC = 5V VOUT = 0.5V TA= 25°C
–30
COMMERCIAL
ICC
Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V
L -7/-10
—
—
75
75
115
90
mA
mA
ftoggle = 15MHz Outputs Open
L -15/-25
Q -15/-25
—
45
55
mA
INDUSTRIAL
ICC
Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V
L -10/-15/-25
Q -20/-25
—
—
75
45
130
65
mA
mA
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
1996 Data Book
3-76
SpecificationsGAL16V8B
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
COM
-7
COM / IND COM / IND
IND
-20
COM / IND
-25
-10
-15
TEST
COND1.
DESCRIPTION
PARAM.
UNITS
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
MIN. MAX.
tpd
A
Input or I/O to
Comb. Output
8 outputs switching
1 output switching
3
7.5
7
3
10
—
3
15
—
3
20
—
3
25
—
ns
ns
—
—
—
—
—
tco
tcf2
tsu
th
A
Clock to Output Delay
2
—
7
5
3
2
7
6
2
10
8
2
11
9
2
12
10
—
ns
ns
ns
—
—
Clock to Feedback Delay
—
10
—
12
—
13
—
15
Setup Time, Input or Fdbk before Clk↑
Hold Time, Input or Fdbk after Clk↑
—
—
—
—
—
A
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
ns
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
83.3
58.8
45.5
41.6
37
MHz
fmax3
A
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
100
100
—
—
62.5
62.5
—
—
50
—
—
45.4
50
—
—
40
—
—
MHz
MHz
Maximum Clock Frequency with
No Feedback
62.5
41.6
twh
twl
—
—
Clock Pulse Duration, High
Clock Pulse Duration, Low
5
5
—
—
8
8
—
—
8
8
—
—
10
10
—
—
12
12
—
—
ns
ns
ten
B
B
Input or I/O to Output Enabled
OE to Output Enabled
3
2
9
6
3
2
10
10
—
—
15
15
—
—
20
18
—
—
25
20
ns
ns
tdis
C
C
Input or I/O to Output Disabled
OE to Output Disabled
2
9
6
2
10
—
—
15
15
—
—
20
18
—
—
25
20
ns
ns
1.5
1.5 10
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.
CAPACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
Input Capacitance
I/O Capacitance
MAXIMUM*
UNITS
TEST CONDITIONS
VCC = 5.0V, VI = 2.0V
VCC = 5.0V, VI/O = 2.0V
CI
8
8
pF
pF
CI/O
*Guaranteed but not 100% tested.
1996 Data Book
3-77
Specifications GAL16V8
SWITCHING WAVEFORMS
INPUT or
I/O FEEDBACK
VALID INPUT
su
h
t
t
CLK
INPUT or
I/O FEEDBACK
VALID INPUT
tco
REGISTERED
OUTPUT
tpd
COMBINATIONAL
OUTPUT
1/fmax
(external fdbk)
Combinatorial Output
Registered Output
INPUT or
I/O FEEDBACK
OE
dis
en
t
t
dis
t
en
t
COMBINATIONAL
OUTPUT
REGISTERED
OUTPUT
Input or I/O to Output Enable/Disable
OE to Output Enable/Disable
wh
wl
t
t
CLK
1/ max (internal fdbk)
f
CLK
cf
t
su
t
1/ max
(w/o fb)
f
REGISTERED
FEEDBACK
Clock Width
fmax with Feedback
1996 Data Book
3-78
Specifications GAL16V8
fmax DESCRIPTIONS
CLK
CLK
LOGIC
ARRAY
REGISTER
LOGIC
ARRAY
REGISTER
t
su
tco
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
t
cf
pd
tsu and tco.
t
CLK
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC
REGISTER
ARRAY
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
t
su + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
SWITCHING TEST CONDITIONS
+5V
Input Pulse Levels
Input Rise and
Fall Times
GND to 3.0V
2 – 3ns 10% – 90%
1.5ns 10% – 90%
1.5V
R
1
GAL16V8B
GAL16V8C
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
C L*
See Figure
R
2
3-state levels are measured 0.5V from steady-state active
level.
*CL INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
GAL16V8B Output Load Conditions (see figure)
GAL16V8C Output Load Conditions (see figure)
Test Condition
R1
R2
CL
Test Condition
R1
R2
CL
A
B
200Ω
∞
200Ω
∞
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
A
B
200Ω
∞
200Ω
∞
200Ω
200Ω
200Ω
200Ω
200Ω
50pF
50pF
50pF
5pF
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
C
C
200Ω
5pF
200Ω
5pF
1996 Data Book
3-79
Specifications GAL16V8
ELECTRONIC SIGNATURE
OUTPUT REGISTER PRELOAD
An electronic signature is provided in every GAL16V8 device. It
contains 64 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision num-
bers, or inventory control. The signature data is always available
to the user independent of the state of the security cell.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.
NOTE: The electronic signature is included in checksum calcu-
lations. Changing the electronic signature will alter the checksum.
SECURITY CELL
GAL16V8 devices include circuitry that allows each registered
output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing text
vectors perform output register preload automatically.
A security cell is provided in the GAL16V8 devices to prevent un-
authorized copying of the array patterns. Once programmed, this
cell prevents further read access to the functional bits in the de-
vice. This cell can only be erased by re-programming the device,
so the original configuration can never be examined once this cell
is programmed. The Electronic Signature is always available to
the user, regardless of the state of this control cell.
INPUT BUFFERS
GAL16V8 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar
TTL devices.
LATCH-UP PROTECTION
GAL16V8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential of latch-up caused by negative input undershoots.
Additionally, outputs are designed with n-channel pull-ups instead
of the traditional p-channel pull-ups in order to eliminate latch-up
due to output overshoots.
The GAL16V8 input and I/O pins have built-in active pull-ups. As
a result, unused inputs and I/O's will float to a TTL "high" (logi-
cal "1"). Lattice Semiconductor recommends that all unused
inputs and tri-stated I/O pins be connected to another active input,
VCC, or Ground. Doing this will tend to improve noise immunity
and reduce ICC for the device.
DEVICE PROGRAMMING
Typical Input Pull-up Characteristic
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.
0
- 2 0
- 4 0
- 6 0
0
1 . 0
2 . 0
3 . 0
4 . 0
5 . 0
Input Voltage (Volts)
1996 Data Book
3-80
Specifications GAL16V8
POWER-UP RESET
Vcc (min.)
Vcc
t
su
t
wl
CLK
t
pr
Internal Register
Reset to Logic "0"
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Circuitry within the GAL16V8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1µs MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
conditions must be met to guarantee a valid power-up reset of the
device. First, the VCC rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN
PIN
Feedback
Vcc
Active Pull-up
Circuit
Active Pull-up
Circuit
Vcc
Tri-State
Control
Vref
Vcc
Vcc
Vref
ESD
Protection
Circuit
Data
Output
PIN
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Typ. Vref = 3.2V
Typ. Vref = 3.2V
Typical Input
Typical Output
1996 Data Book
3-81
Specifications GAL16V8
GAL 16V8C-5/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
1.2
1.1
1
1.2
1.1
1
1.2
1.1
1
RISE
FALL
PT H->L
PT L->H
PT H->L
PT L->H
0.9
0.8
0.9
0.8
0.9
0.8
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
Normalized Tco vs Temp
Normalized Tsu vs Temp
1.3
1.2
1.1
1
1.3
1.2
1.1
1
1.4
1.3
1.2
1.1
1
PT H->L
PT L->H
RISE
FALL
PT H->L
PT L->H
0.9
0.8
0.7
0.9
0.8
0.7
0.9
0.8
0.7
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
Delta Tco vs # of Outputs
Switching
0
-0.25
-0.5
0
-0.25
-0.5
RISE
FALL
RISE
FALL
-0.75
-1
-0.75
-1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
8
6
4
2
0
8
6
4
2
0
RISE
FALL
RISE
FALL
-2
0
-2
50
100
150
200
250
300
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
1996 Data Book
3-82
Specifications GAL16V8
GAL 16V8C-5/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Voh vs Ioh
Voh vs Ioh
Vol vs Iol
5
4
3
2
1
0
4.25
4
2
1.5
1
3.75
3.5
0.5
0
3.25
0.00
10.00
20.00
30.00
40.00
50.00
0.00
1.00
2.00
3.00
4.00
0.00
20.00
40.00
60.00
80.00
Ioh(mA)
Ioh(mA)
Iol (mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq.
1.20
1.10
1.00
0.90
0.80
1.3
1.2
1.1
1
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.9
0.8
4.50
4.75
5.00
5.25
5.50
-55
-25
0
25
50
75
100 125
0
25
50
75
100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
Input Clamp (Vik)
10
0
5
8
6
4
2
0
10
15
20
25
30
35
40
45
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
-2.00
-1.50
-1.00
-0.50
0.00
Vin (V)
Vik (V)
1996 Data Book
3-83
Specifications GAL16V8
GAL 16V8B-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
1.2
1.1
1
1.2
1.1
1
1.2
1.1
1
RISE
FALL
PT H->L
PT L->H
PT H->L
PT L->H
0.9
0.8
0.9
0.8
0.9
0.8
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
Normalized Tco vs Temp
Normalized Tsu vs Temp
1.3
1.2
1.1
1
1.3
1.2
1.1
1
1.4
1.3
1.2
1.1
1
PT H->L
PT L->H
RISE
FALL
PT H->L
PT L->H
0.9
0.8
0.7
0.9
0.8
0.7
0.9
0.8
0.7
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
Delta Tco vs # of Outputs
Switching
0
-0.5
-1
0
-0.5
-1
RISE
FALL
RISE
FALL
-1.5
-1.5
-2
-2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
10
8
10
8
RISE
FALL
RISE
FALL
6
6
4
4
2
2
0
0
-2
-2
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
1996 Data Book
3-84
Specifications GAL16V8
GAL 16V8B-7/-10: TYPICALAC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Voh vs Ioh
Voh vs Ioh
1
0.75
0.5
5
4
3
2
1
0
4.5
4.25
4
0.25
0
3.75
3.5
0.00
20.00
40.00
60.00
80.00 100.00
0.00 10.00 20.00 30.00 40.00 50.00 60.00
0.00
1.00
2.00
3.00
4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq.
1.20
1.10
1.00
0.90
0.80
1.2
1.30
1.20
1.10
1.00
0.90
0.80
1.1
1
0.9
0.8
4.50
4.75
5.00
5.25
5.50
-55
-25
0
25
50
75
100 125
0
25
50
75
100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
Input Clamp (Vik)
10
0
10
20
30
40
50
60
70
80
90
100
8
6
4
2
0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
-2.00
-1.50
-1.00
-0.50
0.00
Vin (V)
Vik (V)
1996 Data Book
3-85
Specifications GAL16V8
GAL 16V8B-15/-25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
1.2
1.1
1
1.2
1.1
1
1.2
1.1
1
RISE
FALL
PT H->L
PT L->H
PT H->L
PT L->H
0.9
0.8
0.9
0.8
0.9
0.8
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tsu vs Temp
Normalized Tpd vs Temp
Normalized Tco vs Temp
1.4
1.3
1.2
1.1
1
1.3
1.2
1.1
1
1.3
1.2
1.1
1
PT H->L
PT L->H
PT H->L
PT L->H
RISE
FALL
0.9
0.8
0.7
0.9
0.8
0.7
0.9
0.8
0.7
-55
-25
0
25
50
75
100 125
-55
-25
0
25
50
75
100 125
-55
-25
0
25
50
75
100 125
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
Delta Tco vs # of Outputs
Switching
0
-0.5
-1
0
-0.5
-1
RISE
FALL
RISE
FALL
-1.5
-1.5
-2
-2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
12
10
8
12
10
8
RISE
FALL
RISE
FALL
6
6
4
4
2
2
0
0
-2
-2
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
1996 Data Book
3-86
Specifications GAL16V8
GAL 16V8B-15/-25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Voh vs Ioh
Voh vs Ioh
Vol vs Iol
5
4
3
2
1
0
4.25
4
2
1.5
1
3.75
3.5
0.5
0
3.25
0.00 10.00 20.00 30.00 40.00 50.00 60.00
0.00
1.00
2.00
3.00
4.00
0.00
20.00
40.00
60.00
80.00 100.00
Ioh(mA)
Ioh(mA)
Iol (mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq.
1.20
1.10
1.00
0.90
0.80
1.2
1.40
1.30
1.20
1.10
1.00
0.90
0.80
1.1
1
0.9
0.8
4.50
4.75
5.00
5.25
5.50
-55
-25
0
25
50
75
100 125
0
25
50
75
100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Input Clamp (Vik)
Delta Icc vs Vin (1 input)
0
10
20
30
40
50
60
70
80
90
100
12
10
8
6
4
2
0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
-2.00
-1.50
-1.00
-0.50
0.00
Vin (V)
Vik (V)
1996 Data Book
3-87
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