DS1035_技术文档

MachXO2™ Family Data Sheet

DS1035 Version 02.0, January 2013

MachXO2 Family Data Sheet

Introduction

January 2013

Data Sheet DS1035

 Flexible On-Chip Clocking

• Eight primary clocks

Features

 Flexible Logic Architecture

• Six devices with 256 to 6864 LUT4s and 

19 to 335 I/Os

 Ultra Low Power Devices

• Advanced 65 nm low power process

• As low as 19 µW standby power

• Programmable low swing differential I/Os

• Stand-by mode and other power saving options

 Embedded and Distributed Memory

• Up to 240 Kbits sysMEM™ Embedded Block

RAM

• Up to two edge clocks for high-speed I/O 

interfaces (top and bottom sides only)

• Up to two analog PLLs per device with 

fractional-n frequency synthesis

– Wide input frequency range (10 MHz to 

400 MHz)

 Non-volatile, Infinitely Reconfigurable

• Instant-on – powers up in microseconds

• Single-chip, secure solution

• Programmable through JTAG, SPI or I²C

• Supports background programming of non-vola-

tile memory

• Up to 54 Kbits Distributed RAM

• Dedicated FIFO control logic

 On-Chip User Flash Memory

• Up to 256 Kbits of User Flash Memory

• 100,000 write cycles

• Optional dual boot with external SPI memory

 TransFR™ Reconfiguration

• In-field logic update while system operates

 Enhanced System Level Support

• On-chip hardened functions: SPI, I²C, timer/

counter

• Accessible through WISHBONE, SPI, I²C and

JTAG interfaces

• Can be used as soft processor PROM or as

Flash memory

• On-chip oscillator with 5.5% accuracy

• Unique TraceID for system tracking

• One Time Programmable (OTP) mode

• Single power supply with extended operating

range

 Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated gearing logic

• 7:1 Gearing for Display I/Os

• Generic DDR, DDRX2, DDRX4

• Dedicated DDR/DDR2/LPDDR memory with

DQS support

• IEEE Standard 1149.1 boundary scan

• IEEE 1532 compliant in-system programming

 Broad Range of Package Options

• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,

fpBGA, QFN package options

 High Performance, Flexible I/O Buffer

• Programmable sysIO™ buffer supports wide

range of interfaces:

• Small footprint package options

– As small as 2.5x2.5mm

• Density migration supported

– LVCMOS 3.3/2.5/1.8/1.5/1.2

– LVTTL

– PCI

• Advanced halogen-free packaging

– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL

– SSTL 25/18

– HSTL 18

– Schmitt trigger inputs, up to 0.5V hysteresis

• I/Os support hot socketing

• On-chip differential termination

• Programmable pull-up or pull-down mode

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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1-1

DS1035 Introduction_01.6

Introduction

MachXO2 Family Data Sheet

Table 1-1. MachXO2™ Family Selection Guide

XO2-256

XO2-640

XO2-640U¹

XO2-1200

XO2-1200U¹

XO2-2000

XO2-2000U¹

XO2-4000

XO2-7000

LUTs

256

2

0

640

5

18

640

5

64

1280

10

64

1280

10

74

2112

16

74

2112

16

92

4320

34

92

6864

54

240

Distributed RAM (Kbits)

EBR SRAM (Kbits)

Number of EBR SRAM

Blocks (9 Kbits/block)

0

2

7

8

10

96

10

96

26

24

64

80

256

UFM (Kbits)

HC²

HE³

Device Options

ZE⁴

0

1

2

Number of PLLs

Hardened Functions:

2

I C

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

SPI

Timer/Counter

1

Packages

I/Os

25 WLCSP⁵

18

(2.5 x 2.5mm, 0.4mm)

32 QFN⁶

(5 x 5mm, 0.5mm)

21

44

55

64 ucBGA

(4 x 4mm, 0.4mm)

100 TQFP

(14 x 14mm)

78

79

132 csBGA

(8 x 8mm, 0.5mm)

79

104

107

104

111

104

114

150

206

274

278

144 TQFP

(20 x 20mm)

107

114

184 csBGA⁷

(8 x 8mm, 0.5mm)

256 caBGA

(14 x 14mm, 0.8mm)

206

278

334

256 ftBGA

(17 x 17mm, 1.0mm)

206

332 caBGA

(17 x 17mm, 0.8mm)

484 fpBGA

(23 x 23mm, 1.0mm)

278

1. Ultra high I/O device.

2. High performance with regulator – V_CC= 2.5V, 3.3V

3. High performance without regulator – V_CC= 1.2V

4. Low power without regulator – V_CC= 1.2V

5. WLCSP package only available for ZE devices.

6. QFN package only available for HC and ZE devices.

7. 184 csBGA package only available for HE devices.

Introduction

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from

256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature

Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-

engineered source synchronous I/O support, advanced configuration support including dual-boot capability and

hardened versions of commonly used functions such as SPI controller, I²C controller and timer/counter. These fea-

tures allow these devices to be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has sev-

eral features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs

1-2

Introduction

MachXO2 Family Data Sheet

and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low

static power for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE)

devices. The ultra low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. Sim-

ilarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. HC

devices have an internal linear voltage regulator which supports external V supply voltages of 3.3V or 2.5V. ZE

CC

and HE devices only accept 1.2V as the external V supply voltage. With the exception of power supply voltage

CC

all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space

saving 2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the same

package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range

of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati-

bility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-

down and bus-keeper features are controllable on a “per-pin” basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may

be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-

ilar state machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These

devices can also configure themselves from external SPI Flash or be configured by an external master through the

JTAG test access port or through the I²C port. Additionally, MachXO2 devices support dual-boot capability (using

external Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the

MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice

design tools use the synthesis tool output along with the user-specified preferences and constraints to place and

route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into

the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of

reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft

core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increas-

ing their productivity.

1-3

MachXO2 Family Data Sheet

Architecture

January 2013

Data Sheet DS1035

Architecture Overview

The MachXO2 family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The

larger logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM

(EBRs). Figures 2-1 and 2-2 show the block diagrams of the various family members.

Figure 2-1. Top View of the MachXO2-1200 Device

Embedded Function

Block (EFB)

User Flash Memory

(UFM)

sysCLOCK PLL

sysMEM Embedded

Block RAM (EBR)

On-chip Configuration

Flash Memory

Programmable Function Units

with Distributed RAM (PFUs)

PIOs Arranged into

sysIO Banks

Note: MachXO2-256, and MachXO2-640/U are similar to MachXO2-1200. MachXO2-256 has a lower LUT count and no PLL or EBR blocks.

MachXO2-640 has no PLL, a lower LUT count and two EBR blocks. MachXO2-640U has a lower LUT count, one PLL and seven EBR blocks.

Figure 2-2. Top View of the MachXO2-4000 Device

Embedded

Function Block(EFB)

User Flash

Memory (UFM)

sysCLOCK PLL

On-chip Configuration

Flash Memory

sysMEM Embedded

Block RAM (EBR)

PIOs Arranged into

sysIO Banks

Programmable Function Units

with Distributed RAM (PFUs)

Note: MachXO2-1200U, MachXO2-2000/U and MachXO2-7000 are similar to MachXO2-4000. MachXO2-1200U and MachXO2-2000 have a lower LUT count,

one PLL, and eight EBR blocks. MachXO2-2000U has a lower LUT count, two PLLs, and 10 EBR blocks. MachXO2-7000 has a higher LUT count, two PLLs,

and 26 EBR blocks.

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

2-1

DS1035 Architecture_01.5

Architecture

MachXO2 Family Data Sheet

The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimen-

sional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are

located at the periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic,

RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports

operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing

channel resources. The place and route software tool automatically allocates these routing resources.

In the MachXO2 family, the number of sysIO banks varies by device. There are different types of I/O buffers on the

different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast

memory blocks; these blocks are found in MachXO2-640/U and larger devices. These blocks can be configured as

RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT

usage.

The MachXO2 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks on MachXO2-

640U, MachXO2-1200/U and larger devices. These blocks are located at the ends of the on-chip Flash block. The

PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase rela-

tionships of the clocks.

MachXO2 devices provide commonly used hardened functions such as SPI controller, I²C controller and timer/

counter. MachXO2-640/U and higher density devices also provide User Flash Memory (UFM). These hardened

functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM can also

be accessed through the SPI, I²C and JTAG ports.

Every device in the family has a JTAG port that supports programming and configuration of the device as well as

access to the user logic. The MachXO2 devices are available for operation from 3.3V, 2.5V and 1.2V power sup-

plies, providing easy integration into the overall system.

PFU Blocks

The core of the MachXO2 device consists of PFU blocks, which can be programmed to perform logic, arithmetic,

distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0

to 3 as shown in Figure 2-3. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs

associated with each PFU block.

Figure 2-3. PFU Block Diagram

From

Routing

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

FCIN

FCO

Slice 3

Slice 0

Slice 1

Slice 2

D

FF/

D

FF/

D

FF/

Latch

To

Routing

2-2

Architecture

MachXO2 Family Data Sheet

Slices

Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2-1

shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU

contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8.

The control logic performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-

select and wider RAM/ROM functions.

Table 2-1. Resources and Modes Available per Slice

PFU Block

Slice

Resources

Modes

Slice 0

Slice 1

Slice 2

Slice 3

2 LUT4s and 2 Registers

Logic, Ripple, RAM, ROM

Logic, Ripple, ROM

Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for posi-

tive/negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the

carry-chain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the

adjacent PFU). Table 2-2 lists the signals associated with Slices 0-3.

Figure 2-4. Slice Diagram

FCO To Different Slice/PFU

Slice

FXB

FXA

OFX1

F1

A1

B1

C1

D1

CO

F/SUM

D

Q1

LUT4 &

Carry

Flip-flop/

Latch

To

CI

Routing

M1

M0

LUT5

Mux

From

OFX0

Routing

A0

CO

B0

C0

D0

F0

LUT4 &

Carry

F/SUM

Q0

D

Flip-flop/

CI

Latch

CE

CLK

LSR

Memory &

Control

FCI From

Different

Slice/PFU

Signals

For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:

• WCK is CLK

• WRE is from LSR

• DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2

• WAD [A:D] is a 4-bit address from slice 2 LUT input

2-3

Architecture

MachXO2 Family Data Sheet

Table 2-2. Slice Signal Descriptions

Function

Input

Type

Signal Names

Description

Data signal

A0, B0, C0, D0 Inputs to LUT4

A1, B1, C1, D1 Inputs to LUT4

Input

Data signal

Input

Multi-purpose

Control signal

Inter-PFU signal

Data signals

Inter-PFU signal

M0/M1

CE

Multi-purpose input

Clock enable

Input

LSR

Local set/reset

Input

CLK

System clock

Fast carry in¹

Input

FCIN

F0, F1

Q0, Q1

OFX0

OFX1

FCO

Output

LUT4 output register bypass signals

Register outputs

Output of a LUT5 MUX

Output of a LUT6, LUT7, LUT8²MUX depending on the slice

Fast carry out¹

1. See Figure 2-3 for connection details.

2. Requires two PFUs.

Modes of Operation

Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.

Logic Mode

In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16

possible input combinations. Any four input logic functions can be generated by programming this lookup table.

Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as

LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four

slices.

Ripple Mode

Ripple mode supports the efficient implementation of small arithmetic functions. In Ripple mode, the following func-

tions can be implemented by each slice:

• Addition 2-bit

• Subtraction 2-bit

• Add/subtract 2-bit using dynamic control

• Up counter 2-bit

• Down counter 2-bit

• Up/down counter with asynchronous clear

• Up/down counter with preload (sync)

• Ripple mode multiplier building block

• Multiplier support

• Comparator functions of A and B inputs

– A greater-than-or-equal-to B

– A not-equal-to B

– A less-than-or-equal-to B

2-4

Architecture

MachXO2 Family Data Sheet

Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con-

figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener-

ated on a per-slice basis to allow fast arithmetic functions to be constructed by concatenating slices.

RAM Mode

In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed by using each LUT block in Slice 0

and Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. A 16x2-bit

Pseudo Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other compan-

ion slice as the read-only port.

MachXO2 devices support distributed memory initialization.

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-

ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3

shows the number of slices required to implement different distributed RAM primitives. For more information about

using RAM in MachXO2 devices, please see TN1201, Memory Usage Guide for MachXO2 Devices.

Table 2-3. Number of Slices Required For Implementing Distributed RAM

SPR 16x4

PDPR 16x4

Number of slices

3

Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM

ROM Mode

ROM mode uses the LUT logic; hence, slices 0-3 can be used in ROM mode. Preloading is accomplished through

the programming interface during PFU configuration.

For more information on the RAM and ROM modes, please refer to TN1201, Memory Usage Guide for MachXO2

Devices.

Routing

There are many resources provided in the MachXO2 devices to route signals individually or as buses with related

control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-

ments.

The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2

(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connec-

tions in the horizontal and vertical directions.

The design tools take the output of the synthesis tool and places and routes the design. Generally, the place and

route tool is completely automatic, although an interactive routing editor is available to optimize the design.

Clock/Control Distribution Network

Each MachXO2 device has eight clock inputs (PCLK [T, C] [Banknum]_[2..0]) – three pins on the left side, two pins

each on the bottom and top sides and one pin on the right side. These clock inputs drive the clock nets. These

eight inputs can be differential or single-ended and may be used as general purpose I/O if they are not used to

drive the clock nets. When using a single ended clock input, only the PCLKT input can drive the clock tree directly.

The MachXO2 architecture has three types of clocking resources: edge clocks, primary clocks and secondary high

fanout nets. MachXO2-640U, MachXO2-1200/U and higher density devices have two edge clocks each on the top

and bottom edges. Lower density devices have no edge clocks. Edge clocks are used to clock I/O registers and

have low injection time and skew. Edge clock inputs are from PLL outputs, primary clock pads, edge clock bridge

outputs and CIB sources.

2-5

Architecture

MachXO2 Family Data Sheet

The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks

for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals,

MachXO2 devices also have eight secondary high fanout signals which can be used for global control signals, such

as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the

global clock network for internally-generated global clocks and control signals.

The maximum frequency for the primary clock network is shown in the MachXO2 External Switching Characteris-

tics table.

The primary clock signals for the MachXO2-256 and MachXO2-640 are generated from eight 17:1 muxes The

available clock sources include eight I/O sources and 9 routing inputs. Primary clock signals for the MachXO2-

640U, MachXO2-1200/U and larger devices are generated from eight 27:1 muxes The available clock sources

include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs.

Figure 2-5. Primary Clocks for MachXO2 Devices

Up to 8

8

11

8

Dynamic

Clock

27:1

Primary Clock 0

Enable

Dynamic

Clock

Primary Clock 1

Primary Clock 2

27:1

Enable

Dynamic

Clock

Enable

Dynamic

Clock

Primary Clock 3

Primary Clock 4

Enable

Dynamic

Clock

Enable

Dynamic

Clock

27:1

Primary Clock 5

Enable

Dynamic

Clock

Enable

Primary Clock 6

27:1

Clock

Switch

Dynamic

Clock

Enable

7

Primary Clock

27:1

Clock

Switch

Primary clocks for MachXO2-640U, MachXO2-1200/U and larger devices.

Note: MachXO2-640 and smaller devices do not have inputs from the Edge Clock Divider or PLL

and fewer routing inputs. These devices have 17:1 muxes instead of 27:1 muxes.

2-6

Architecture

MachXO2 Family Data Sheet

Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2-6. One of the eight

inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven

come from internal routing. The maximum frequency for the secondary clock network is shown in MachXO2 Exter-

nal Switching Characteristics table.

Figure 2-6. Secondary High Fanout Nets for MachXO2 Devices

1

7

Secondary High

Fanout Net 0

8:1

Secondary High

Fanout Net 1

8:1

Secondary High

Fanout Net 2

Secondary High

Fanout Net 3

8:1

Secondary High

Fanout Net 4

Secondary High

Fanout Net 5

8:1

Secondary High

Fanout Net 6

Secondary High

Fanout Net 7

8:1

Clock Pads

Routing

sysCLOCK Phase Locked Loops (PLLs)

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The MachXO2-640U, MachXO2-1200/U

and larger devices have one or more sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its

source can come from an external I/O pin or from internal routing. CLKFB is the feedback signal to the PLL which

can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference fre-

quency and thus synthesize a higher frequency clock output.

The MachXO2 sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency syn-

thesis allows the user to generate an output clock which is a non-integer multiple of the input frequency. For more

information about using the PLL with Fractional-N synthesis, please see TN1199, MachXO2 sysCLOCK PLL

Design and Usage Guide.

Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The

output dividers can have a value from 1 to 128. The CLKOS2 and CLKOS3 dividers may also be cascaded together

to generate low frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the

MachXO2 clock distribution network directly or general purpose routing resources can be used.

2-7

Architecture

MachXO2 Family Data Sheet

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is

detected. A block diagram of the PLL is shown in Figure 2-7.

The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2,

and CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock.

This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode,

the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the

t

parameter has been satisfied.

LOCK

The MachXO2 also has a feature that allows the user to select between two different reference clock sources

dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are

shown in the table.

The MachXO2 PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be

dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the

design to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are

updated through the WISHBONE port the PLL may lose lock and not relock until the t

isfied. The timing parameters for the PLL are shown in the table.

parameter has been sat-

LOCK

For more details on the PLL and the WISHBONE interface, see TN1199, MachXO2 sysCLOCK PLL Design and

Usage Guide.

Figure 2-7. PLL Diagram

DPHSRC

PHASESEL[1:0]

Dynamic

PHASEDIR

Phase

PHASESTEP

Adjust

CLKOP

CLKOS

CLKOP

Divider

Phase

Adjust/

A2

ClkEn

Synch

A0

B0

C0

D0

Mux

STDBY

(1 - 128)

Edge Trim

REFCLK

CLKOS

Divider

Phase

Adjust/

CLKI

B2

ClkEn

Synch

REFCLK

Mux

Divider

Phase detector,

VCO, and

(1 - 128)

Edge Trim

M (1 - 40)

loop filter.

FBKSEL

CLKFB

CLKOS2

Divider

Phase

Adjust

C2

ClkEn

Synch

Fractional-N

Synthesizer

FBKCLK

Mux

(1 - 128)

Divider

N (1 - 40)

CLKOS3

LOCK

CLKOS3

D1

Phase

Adjust

D2

ClkEn

Synch

Divider

Mux

(1 - 128)

Internal Feedback

CLKOP, CLKOS, CLKOS2, CLKOS3

Lock

Detect

4

RST, RESETM, RESETC, RESETD

ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3

PLLDATO[7:0] , PLLACK

PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]

2-8

Architecture

MachXO2 Family Data Sheet

Table 2-4 provides signal descriptions of the PLL block.

Table 2-4. PLL Signal Descriptions

Port Name

I/O

I

Description

CLKI

Input clock to PLL

Feedback clock

CLKFB

I

PHASESEL[1:0]

PHASEDIR

PHASESTEP

CLKOP

I

Select which output is affected by Dynamic Phase adjustment ports

Dynamic Phase adjustment direction

I

Dynamic Phase step – toggle shifts VCO phase adjust by one step.

Primary PLL output clock (with phase shift adjustment)

Secondary PLL output clock (with phase shift adjust)

Secondary PLL output clock2 (with phase shift adjust)

Secondary PLL output clock3 (with phase shift adjust)

O

CLKOS

CLKOS2

CLKOS3

PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and feed-

back signals.

LOCK

O

DPHSRC

STDBY

O

I

Dynamic Phase source – ports or WISHBONE is active

Standby signal to power down the PLL

RST

I

PLL reset without resetting the M-divider. Active high reset.

PLL reset - includes resetting the M-divider. Active high reset.

Reset for CLKOS2 output divider only. Active high reset.

Reset for CLKOS3 output divider only. Active high reset.

Enable PLL output CLKOP

RESETM

RESETC

RESETD

ENCLKOP

ENCLKOS

ENCLKOS2

ENCLKOS3

PLLCLK

I

Enable PLL output CLKOS when port is active

Enable PLL output CLKOS2 when port is active

Enable PLL output CLKOS3 when port is active

PLL data bus clock input signal

I

PLLRST

I

PLL data bus reset. This resets only the data bus not any register values.

PLL data bus strobe signal

PLLSTB

I

PLLWE

I

PLL data bus write enable signal

PLLADDR [4:0]

PLLDATI [7:0]

PLLDATO [7:0]

PLLACK

I

PLL data bus address

I

PLL data bus data input

O

PLL data bus data output

PLL data bus acknowledge signal

sysMEM Embedded Block RAM Memory

The MachXO2-640/U and larger devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a

9-Kbit RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes

including data buffering, PROM for the soft processor and FIFO.

sysMEM Memory Block

The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be

used in a variety of depths and widths as shown in Table 2-5.

2-9

Architecture

MachXO2 Family Data Sheet

Table 2-5. sysMEM Block Configurations

Memory Mode

Configurations

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

Single Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

True Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

Pseudo Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

FIFO

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device configuration. EBR initialization data can be

loaded from the UFM. To maximize the number of UFM bits, initialize the EBRs used in your design to an all-zero

pattern. Initializing to an all-zero pattern does not use up UFM bits. MachXO2 devices have been designed such

that multiple EBRs share the same initialization memory space if they are initialized to the same pattern.

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block

can also be utilized as a ROM.

Memory Cascading

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on specific design inputs.

Single, Dual, Pseudo-Dual Port and FIFO Modes

Figure 2-8 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM

modes, the input data and addresses for the ports are registered at the input of the memory array. The output data

of the memory is optionally registered at the memory array output.

2-10

Architecture

MachXO2 Family Data Sheet

Figure 2-8. sysMEM Memory Primitives

DI[8:0]

DIA[8:0]

AD[12:0]

DI[8:0]

ADW[8:0]

ADB[12:0]

CLKB

DI[17:0]

ADA[12:0]

CLKA

ADR[12:0]

CLKR

BE[1:0]

CLK

CE

CEB

CLKW

CEA

OCE

CER

EBR

CEW

RST

EBR

DO[8:0]

RSTB

RSTA

WEA

DO[17:0]

OCER

CSR[2:0]

WEB

RST

WE

CSB[2:0]

OCEB

CSA[2:0]

OCEA

CS[2:0]

CSW[2:0]

DOA[8:0]

DOB[8:0]

Single-Port RAM

True Dual Port RAM

Pseudo Dual Port RAM

AD[12:0]

AFF

FF

DI[17:0]

CLKW

WE

RST

FULLI

CSW[1:0]

AEF

CLK

CE

EF

DO[17:0]

ORE

OCE

DO[17:0]

EBR

CLKR

RE

RST

EMPTYI

CSR[1:0]

RPRST

CS[2:0]

FIFO RAM

ROM

Table 2-6. EBR Signal Descriptions

Port Name

Description

Active State

CLK

Clock

Rising Clock Edge

CE

Clock Enable

Active High

OCE¹

Output Clock Enable

Reset

Active High

RST

Active High

BE¹

Byte Enable

Active High

WE

Write Enable

Active High

AD

Address Bus

—

DI

Data In

—

DO

Data Out

—

CS

Chip Select

Active High

AFF

FIFO RAM Almost Full Flag

FIFO RAM Full Flag

FIFO RAM Almost Empty Flag

FIFO RAM Empty Flag

FIFO RAM Read Pointer Reset

—

FF

AEF

EF

RPRST

1. Optional signals.

2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively.

3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respec-

tively.

4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2).

5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the

read port chip select, ORE is the output read enable.

2-11

Architecture

MachXO2 Family Data Sheet

The EBR memory supports three forms of write behavior for single or dual port operation:

1. Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2. Write Through – A copy of the input data appears at the output of the same port. This mode is supported for

all data widths.

3. Read-Before-Write – When new data is being written, the old contents of the address appears at the output.

FIFO Configuration

The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out,

RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The

Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.

Table 2-7 shows the range of programming values for these flags.

Table 2-7. Programmable FIFO Flag Ranges

Flag Name

Programming Range

1 to max (up to 2^N-1)

1 to Full-1

Full (FF)

Almost Full (AF)

Almost Empty (AE)

Empty (EF)

1 to Full-1

0

N = Address bit width.

The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset

that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset

state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is

in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from

the FIFO.

Memory Core Reset

The memory core contains data output latches for ports A and B. These are simple latches that can be reset syn-

chronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with

port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and

associated resets for both ports are as shown in Figure 2-9.

Figure 2-9. Memory Core Reset

SET

D

Q

Memory Core

Port A[18:0]

Port B[18:0]

Output Data

Latches

SET

D

Q

RSTA

RSTB

GSRN

Programmable Disable

2-12

Architecture

MachXO2 Family Data Sheet

For further information on the sysMEM EBR block, please refer to TN1201, Memory Usage Guide for MachXO2

Devices.

EBR Asynchronous Reset

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before

the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-10. The GSR input

to the EBR is always asynchronous.

Figure 2-10. EBR Asynchronous Reset (Including GSR) Timing Diagram

Reset

Clock

Enable

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after

the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f

(EBR clock). The reset

MAX

release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during

device wake up must occur before the release of the device I/Os becoming active.

These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR sig-

nal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-10. The reset timing

rules apply to the RPReset input versus the RE input and the RST input versus the WE and RE inputs. Both RST

and RPReset are always asynchronous EBR inputs. For more details refer to TN1201, Memory Usage Guide for

MachXO2 Devices.

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.

Programmable I/O Cells (PIC)

The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respec-

tive sysIO buffers and pads. On the MachXO2 devices, the PIO cells are assembled into groups of four PIO cells

called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device.

On all the MachXO2 devices, two adjacent PIOs can be combined to provide a complementary output driver pair.

The MachXO2-640U, MachXO2-1200/U and higher density devices contain enhanced I/O capability. All PIO pairs

on these larger devices can implement differential receivers. Half of the PIO pairs on the top edge of these devices

can be configured as true LVDS transmit pairs. The PIO pairs on the bottom edge of these higher density devices

have on-chip differential termination and also provide PCI support.

2-13

Architecture

MachXO2 Family Data Sheet

Figure 2-11. Group of Four Programmable I/O Cells

1 PIC

PIO A

Input Register

Block

Output

Register Block

& Tristate

A

Register Block

PIO B

Input Register

Block

Output

Register Block

& Tristate

B

Register Block

Input

Output

Core Logic/

Routing

Gearbox

PIO C

Input Register

Block

Output

Register Block

& Tristate

C

Register Block

PIO D

Input Register

Block

Output

Register Block

& Tristate

D

Register Block

Notes:

1. Input gearbox is available only in PIC on the bottom edge of MachXO2-640U, MachXO2-1200/U and larger devices.

2. Output gearbox is available only in PIC on the top edge of MachXO2-640U, MachXO2-1200/U and larger devices.

2-14

Architecture

MachXO2 Family Data Sheet

PIO

The PIO contains three blocks: an input register block, output register block and tri-state register block. These

blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic.

Table 2-8. PIO Signal List

Pin Name

I/O Type

Input

Description

CE

D

Clock Enable

Input

Pin input from sysIO buffer.

INDD

INCK

Q0

Q1

D0

Output

Input

Register bypassed input.

Clock input

DDR positive edge input

Registered input/DDR negative edge input

Output signal from the core (SDR and DDR)

Output signal from the core (DDR)

Tri-state signal from the core

D1

Input

TD

Q

Input

Output

Input

Data output signals to sysIO Buffer

Tri-state output signals to sysIO Buffer

DQS shift 90-degree read clock

DQS shift 90-degree write clock

DDR input register polarity control signal from DQS

System clock for input and output/tri-state blocks.

Local set reset signal

TQ

DQSR90¹

DQSW90¹

DDRCLKPOL¹

SCLK

Input

RST

Input

1. Available in PIO on right edge only.

Input Register Block

The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condi-

tion high-speed interface signals before they are passed to the device core. In addition to this functionality, the input

register blocks for the PIOs on the right edge include built-in logic to interface to DDR memory.

Figure 2-12 shows the input register block for the PIOs located on the left, top and bottom edges. Figure 2-13

shows the input register block for the PIOs on the right edge.

Left, Top, Bottom Edges

Input signals are fed from the sysIO buffer to the input register block (as signal D). If desired, the input signal can

bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK).

If an input delay is desired, users can select a fixed delay. I/Os on the bottom edge also have a dynamic delay,

DEL[4:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input

block allows two modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK)

by one of the registers in the single data rate sync register block. In Generic DDR mode, two registers are used to

sample the data on the positive and negative edges of the system clock (SCLK) signal, creating two data streams.

2-15

Architecture

MachXO2 Family Data Sheet

Figure 2-12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges)

INCK

INDD

Programmable

Delay Cell

Q1

D

Q1

Q0

D/L Q

D

Q

Q0

D

Q

D

Q

SCLK

Right Edge

The input register block on the right edge is a superset of the same block on the top, bottom, and left edges. In

addition to the modes described above, the input register block on the right edge also supports DDR memory

mode.

In DDR memory mode, two registers are used to sample the data on the positive and negative edges of the modi-

fied DQS (DQSR90) in the DDR Memory mode creating two data streams. Before entering the core, these two data

streams are synchronized to the system clock to generate two data streams.

The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-

quate timing when data is transferred to the system clock domain from the DQS domain. The DQSR90 and

DDRCLKPOL signals are generated in the DQS read-write block.

Figure 2-13. MachXO2 Input Register Block Diagram (PIO on Right Edge)

INCK

INDD

Programmable

Q1

Q0

S1

S0

D

Q

D/L Q

Q1

D

Q

Delay Cell

D

Q

Q0

D

Q

DQSR90

DDRCLKPOL

SCLK

Output Register Block

The output register block registers signals from the core of the device before they are passed to the sysIO buffers.

Left, Top, Bottom Edges

In SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type

register or latch.

2-16

Architecture

MachXO2 Family Data Sheet

In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling

edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to

switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.

Figure 2-14 shows the output register block on the left, top and bottom edges.

Figure 2-14. MachXO2 Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)

Q

Q0

Q1

D0

D1

D/L Q

D

Q

D

Q

SCLK

TD

Output path

TQ

D/L Q

Tri-state path

Right Edge

The output register block on the right edge is a superset of the output register on left, top and bottom edges of the

device. In addition to supporting SDR and Generic DDR modes, the output register blocks for PIOs on the right

edge include additional logic to support DDR-memory interfaces. Operation of this block is similar to that of the out-

put register block on other edges.

In DDR memory mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling

edge the registered D1 input is registered into the register Q1. A multiplexer running off the DQSW90 signal is used

to switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.

Figure 2-15 shows the output register block on the right edge.

2-17

Architecture

MachXO2 Family Data Sheet

Figure 2-15. MachXO2 Output Register Block Diagram (PIO on the Right Edges)

Q

Q0

Q

D/L

D0

D1

Q1

D

Q

D Q

SCLK

DQSW90

Output Register Block

T0

TD

TQ

D

Q

D/L Q

Tristate Register Block

Tri-state Register Block

The tri-state register block registers tri-state control signals from the core of the device before they are passed to

the sysIO buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that

then feeds the output.

The tri-state register blocks on the right edge contain an additional register for DDR memory operation. In DDR

memory mode, the register TS input is fed into another register that is clocked using the DQSW90 signal. The out-

put of this register is used as a tri-state control.

Input Gearbox

Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed

as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2-9 shows the

gearbox signals.

Table 2-9. Input Gearbox Signal List

Name

I/O Type

Description

D

Input

High-speed data input after programmable delay in PIO A

input register block

ALIGNWD

SCLK

Input

Data alignment signal from device core

Slow-speed system clock

High-speed edge clock

Reset

ECLK[1:0]

RST

Input

Q[7:0]

Output

Low-speed data to device core:

Video RX(1:7): Q[6:0]

GDDRX4(1:8): Q[7:0]

GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7

GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3

2-18

Architecture

MachXO2 Family Data Sheet

These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by

the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment

based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the

data to the device core synchronized to the low-speed system clock. Figure 2-16 shows a block diagram of the

input gearbox.

Figure 2-16. Input Gearbox

Q0

Q0_

Q21

S0

S2

T0

T2

Q21

D

Q

D

Q

D

Q

Q10

Q32

CE

Q2

Q43

D

CE

Q4

Q6

Q65

Q43

Q65

S4

S6

T4

T6

D

Q

D

Q

D

Q

Q54

Q_6

CE

cdn

D

CE

D

Q7

Q_6

Q54

T7

T5

T3

S7

S5

D

Q

D

Q

D

Q

CE

Q_6

Q5

Q3

D

CE

Q65

Q54

Q32

Q10

S3

S1

D

Q

CE

Q43

Q32

Q1

T1

D

Q

D

Q21

CE

ECLK0/1

SCLK

SEL0

UPDATE

2-19

Architecture

MachXO2 Family Data Sheet

More information on the input gearbox is available in TN1203, Implementing High-Speed Interfaces with MachXO2

Devices.

Output Gearbox

Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed

as a 7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2-10 shows the

gearbox signals.

Table 2-10. Output Gearbox Signal List

Name

I/O Type

Output

Input

Description

High-speed data output

Q

D[7:0]

Low-speed data from device core

Video TX(7:1): D[6:0]

GDDRX4(8:1): D[7:0]

GDDRX2(4:1)(IOL-A): D[3:0]

GDDRX2(4:1)(IOL-C): D[7:4]

SCLK

Input

Slow-speed system clock

High-speed edge clock

Reset

ECLK [1:0]

RST

The gearboxes have three stage pipeline registers. The first stage registers sample the low-speed input data on the

low-speed system clock. The second stage registers transfer data from the low-speed clock registers to the high-

speed clock registers. The third stage pipeline registers controlled by high-speed edge clock shift and mux the

high-speed data out to the sysIO buffer. Figure 2-17 shows the output gearbox block diagram.

2-20

Architecture

MachXO2 Family Data Sheet

Figure 2-17. Output Gearbox

GND

Q67

S6

S4

0

1

T6

T4

Q67

0

1

D6

D Q

CE

D Q

S7

S5

Q45

0

1

D4

D Q

CE

0

1

D Q

ODDRx2_C

Q45

Q23

T2

Q23

Q01

S2

S0

0

D Q

CDN

0

1

D Q

CE

D Q

1

D2

D0

S3

S1

QC

T0

0

1

0

1

D Q

CE

Q/QA

Q12

Q34

T1

T3

D1

S1

Q10

Q32

0

1

D Q

CE

0

1

D Q

S0

0

1

S3

S5

0

1

D Q

CE

D3

D5

D7

S2

S4

ODDRx2_A

Q56

Q54

Q76

T5

T7

0

1

Q

D Q

CE

D Q

D

1

GND

0

1

S7

0

1

Q D

D Q

CE

S6

ODDRx2_C

SCLK

SEL /0

UPDATE

ECLK0/1

More information on the output gearbox is available in TN1203, Implementing High-Speed Interfaces with

MachXO2 Devices.

DDR Memory Support

Certain PICs on the right edge of MachXO2-640U, MachXO2-1200/U and larger devices, have additional circuitry

to allow the implementation of DDR memory interfaces. There are two groups of 14 or 12 PIOs each on the right

edge with additional circuitry to implement DDR memory interfaces. This capability allows the implementation of up

to 16-bit wide memory interfaces. One PIO from each group contains a control element, the DQS Read/Write

2-21

Architecture

MachXO2 Family Data Sheet

Block, to facilitate the generation of clock and control signals (DQSR90, DQSW90, DDRCLKPOL and DATAVALID).

These clock and control signals are distributed to the other PIO in the group through dedicated low skew routing.

DQS Read Write Block

Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at

the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock

(referred to as DQS) is not free-running so this approach cannot be used. The DQS Read Write block provides the

required clock alignment for DDR memory interfaces. DQSR90 and DQSW90 signals are generated by the DQS

Read Write block from the DQS input.

In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and

the internal system clock (during the read cycle) is unknown. The MachXO2 family contains dedicated circuits to

transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS

(delayed) and the system clock, a clock polarity selector is used. This circuit changes the edge on which the data is

registered in the synchronizing registers in the input register block. This requires evaluation at the start of each

read cycle for the correct clock polarity. Prior to the read operation in DDR memories, DQS is in tri-state (pulled by

termination). The DDR memory device drives DQS low at the start of the preamble state. A dedicated circuit in the

DQS Read Write block detects the first DQS rising edge after the preamble state and generates the DDRCLKPOL

signal. This signal is used to control the polarity of the clock to the synchronizing registers.

The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration

signals (6-bit bus) from a DLL on the right edge of the device. The DLL loop is compensated for temperature, volt-

age and process variations by the system clock and feedback loop.

sysIO Buffer

Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the

periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of

standards that are found in today’s systems including LVCMOS, TTL, PCI, SSTL, HSTL, LVDS, BLVDS, MLVDS

and LVPECL.

Each bank is capable of supporting multiple I/O standards. In the MachXO2 devices, single-ended output buffers,

ratioed input buffers (LVTTL, LVCMOS and PCI), differential (LVDS) and referenced input buffers (SSTL and HSTL)

are powered using I/O supply voltage (V

). Each sysIO bank has its own V

. In addition, each bank has a

CCIO

voltage reference, V , which allows the use of referenced input buffers independent of the bank V

.

REF

CCIO

MachXO2-256 and MachXO2-640 devices contain single-ended ratioed input buffers and single-ended output buf-

fers with complementary outputs on all the I/O banks. Note that the single-ended input buffers on these devices do

not contain PCI clamps. In addition to the single-ended I/O buffers these two devices also have differential and ref-

erenced input buffers on all I/Os. The I/Os are arranged in pairs, the two pads in the pair are described as “T” and

“C”, where the true pad is associated with the positive side of the differential input buffer and the comp (comple-

mentary) pad is associated with the negative side of the differential input buffer.

MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 devices contain three

types of sysIO buffer pairs.

1. Left and Right sysIO Buffer Pairs

The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers and

two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the left and

right of the devices also have differential and referenced input buffers.

2. Bottom sysIO Buffer Pairs

The sysIO buffer pairs in the bottom bank of the device consist of two single-ended output drivers and two sin-

gle-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the bottom also have

differential and referenced input buffers. Only the I/Os on the bottom banks have programmable PCI clamps

2-22

Architecture

MachXO2 Family Data Sheet

and differential input termination. The PCI clamp is enabled after V and V

are at valid operating levels

CCIO

CC

and the device has been configured.

3. Top sysIO Buffer Pairs

The sysIO buffer pairs in the top bank of the device consist of two single-ended output drivers and two single-

ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the top also have differ-

ential and referenced I/O buffers. Half of the sysIO buffer pairs on the top edge have true differential outputs.

The sysIO buffer pair comprising of the A and B PIOs in every PIC on the top edge have a differential output

driver. The referenced input buffer can also be configured as a differential input buffer.

Typical I/O Behavior During Power-up

The internal power-on-reset (POR) signal is deactivated when V and V

have reached V

level defined

CC

CCIO0

PORUP

in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the

POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all

V

banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that

CCIO

are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-

down to GND (some pins such as PROGRAMN and the JTAG pins have weak pull-up to V as the default func-

CCIO

tionality). The I/O pins will maintain the blank configuration until V and V

(for I/O banks containing configura-

CC

CCIO

tion I/Os) have reached V

levels at which time the I/Os will take on the user-configured settings only after a

PORUP

proper download/configuration.

There are various ways a user can ensure that there are no spurious signals on critical outputs as the device pow-

ers up. These are discussed in more detail in TN1202, MachXO2 sysIO Usage Guide.

Supported Standards

The MachXO2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be

further subdivided into LVCMOS, LVTTL, and PCI. The buffer supports the LVTTL, PCI, LVCMOS 1.2, 1.5, 1.8, 2.5,

and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive

strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS,

MLVDS and LVPECL output emulation is supported on all devices. The MachXO2-640U, MachXO2-1200/U and

higher devices support on-chip LVDS output buffers on approximately 50% of the I/Os on the top bank. Differential

receivers for LVDS, BLVDS, MLVDS and LVPECL are supported on all banks of MachXO2 devices. PCI support is

provided in the bottom bank of theMachXO2-640U, MachXO2-1200/U and higher density devices. Table 2-11 sum-

marizes the I/O characteristics of the MachXO2 PLDs.

Tables 2-11 and 2-12 show the I/O standards (together with their supply and reference voltages) supported by the

MachXO2 devices. For further information on utilizing the sysIO buffer to support a variety of standards please see

TN1202, MachXO2 sysIO Usage Guide.

Table 2-11. I/O Support Device by Device

MachXO2-1200U

MachXO2-2000/U,

MachXO2-4000,

MachXO2-7000

MachXO2-256,

MachXO2-640

MachXO2-640U,

MachXO2-1200

Number of I/O Banks

Type of Input Buffers

4

6

Single-ended (all I/O banks)

Differential Receivers (all I/O Differential Receivers (all I/O

banks)

Differential Receivers (all I/O

banks)

Differential input termination

(bottom side)

Differential input termination

(bottom side)

2-23

Architecture

MachXO2 Family Data Sheet

MachXO2-1200U

MachXO2-2000/U,

MachXO2-4000,

MachXO2-7000

MachXO2-256,

MachXO2-640

MachXO2-640U,

MachXO2-1200

Single-ended buffers with

complementary outputs (all I/O complementary outputs (all I/O

Single-ended buffers with

complementary outputs (all I/O

banks)

Types of Output Buffers

Differential buffers with true

LVDS outputs (50% on top

side)

Differential buffers with true

LVDS outputs (50% on top

side)

Differential Output Emulation

Capability

All I/O banks

No

All I/O banks

PCI Clamp Support

Clamp on bottom side only

Table 2-12. Supported Input Standards

VCCIO (Typ.)

Input Standard

Single-Ended Interfaces

LVTTL

3.3V

2.5V

1.8V

1.5

1.2V



²



²



²



LVCMOS33

LVCMOS25

²



LVCMOS18

LVCMOS15

²



LVCMOS12

PCI¹

²

SSTL18 (Class I, Class II)

SSTL25 (Class I, Class II)

HSTL18 (Class I, Class II)

Differential Interfaces

LVDS



BLVDS, MVDS, LVPECL, RSDS

Differential SSTL18 Class I, II

Differential SSTL25 Class I, II

Differential HSTL18 Class I, II



1. Bottom banks of MachXO2-640U, MachXO2-1200/U and higher density devices only.

2. Reduced functionality. Refer to TN1202, MachXO2 sysIO Usage Guide for more detail.

2-24

Architecture

MachXO2 Family Data Sheet

Table 2-13. Supported Output Standards

Output Standard

Single-Ended Interfaces

LVTTL

V_CCIO(Typ.)

3.3

2.5

1.8

1.5

1.2

—

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

LVCMOS33, Open Drain

LVCMOS25, Open Drain

LVCMOS18, Open Drain

LVCMOS15, Open Drain

LVCMOS12, Open Drain

PCI33

—

3.3

2.5

1.8

SSTL25 (Class I)

SSTL18 (Class I)

HSTL18(Class I)

Differential Interfaces

LVDS^{1, 2}

BLVDS, MLVDS, RSDS ²

LVPECL²

2.5, 3.3

2.5

3.3

Differential SSTL18

Differential SSTL25

Differential HSTL18

1.8

2.5

1.8

1. MachXO2-640U, MachXO2-1200/U and larger devices have dedicated LVDS buffers.

2. These interfaces can be emulated with external resistors in all devices.

sysIO Buffer Banks

The numbers of banks vary between the devices of this family. MachXO2-1200U, MachXO2-2000/U and higher

density devices have six I/O banks (one bank on the top, right and bottom side and three banks on the left side).

The MachXO2-1200 and lower density devices have four banks (one bank per side). Figures 2-18 and 2-19 show

the sysIO banks and their associated supplies for all devices.

2-25

Architecture

MachXO2 Family Data Sheet

Figure 2-18. MachXO2-1200U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 Banks

GND

VCCIO0

Bank 0

VCCIO5

GND

VCCIO1

GND

VCCIO4

GND

VCCIO3

GND

Bank 2

GND

VCCIO2

Figure 2-19. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks

GND

VCCIO0

Bank 0

VCCIO3

GND

VCCIO1

GND

Bank 2

GND

VCCIO2

2-26

Architecture

MachXO2 Family Data Sheet

Hot Socketing

The MachXO2 devices have been carefully designed to ensure predictable behavior during power-up and power-

down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of

the system. These capabilities make the MachXO2 ideal for many multiple power supply and hot-swap applica-

tions.

On-chip Oscillator

Every MachXO2 device has an internal CMOS oscillator. The oscillator output can be routed as a clock to the clock

tree or as a reference clock to the sysCLOCK PLL using general routing resources. The oscillator frequency can be

divided by internal logic. There is a dedicated programming bit and a user input to enable/disable the oscillator. The

oscillator frequency ranges from 2.08 MHz to 133 MHz. The software default value of the Master Clock (MCLK) is

nominally 2.08 MHz. When a different MCLK is selected during the design process, the following sequence takes

place:

1. Device powers up with a nominal MCLK frequency of 2.08 MHz.

2. During configuration, users select a different master clock frequency.

3. The MCLK frequency changes to the selected frequency once the clock configuration bits are received.

4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK fre-

quency of 2.08 MHz.

Table 2-14 lists all the available MCLK frequencies.

Table 2-14. Available MCLK Frequencies

MCLK (MHz, Nominal)

2.08 (default)

9.17

10.23

13.3

33.25

38

2.46

3.17

4.29

5.54

7

44.33

53.2

66.5

88.67

133

14.78

20.46

26.6

8.31

29.56

Embedded Hardened IP Functions and User Flash Memory

All MachXO2 devices provide embedded hardened functions such as SPI, I²C and Timer/Counter. MachXO2-640/U

and higher density devices also provide User Flash Memory (UFM). These embedded blocks interface through the

WISHBONE interface with routing as shown in Figure 2-20.

2-27

Architecture

MachXO2 Family Data Sheet

Figure 2-20. Embedded Function Block Interface

Configuration

Logic

Power

Control

Embedded Function Block (EFB)

2

I/Os for I C

2

I C (Primary)

(Primary)

Core

Logic/

2

I/Os for I C

2

I C (Secondary)

SPI

EFB

(Secondary)

Routing

WISHBONE

Interface

I/Os for SPI

Timer/Counter

PLL0

PLL1

UFM

Indicates connection

through core logic/routing.

Hardened I²C IP Core

Every MachXO2 device contains two I²C IP cores. These are the primary and secondary I²C IP cores. Either of the

two cores can be configured either as an I²C master or as an I²C slave. The only difference between the two IP

cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core.

When the IP core is configured as a master it will be able to control other devices on the I²C bus through the inter-

face. When the core is configured as the slave, the device will be able to provide I/O expansion to an I²C Master.

The I²C cores support the following functionality:

• Master and Slave operation

• 7-bit and 10-bit addressing

• Multi-master arbitration support

• Clock stretching

• Up to 400 KHz data transfer speed

• General call support

• Interface to custom logic through 8-bit WISHBONE interface

2-28

Architecture

MachXO2 Family Data Sheet

Figure 2-21. I²C Core Block Diagram

Configuration

Logic

Power

Control

EFB

2

Core

Logic/

I C Function

Routing

SCL

SDA

EFB

2

I C

Control

Logic

WISHBONE

Interface

Registers

Table 2-15 describes the signals interfacing with the I²C cores.

Table 2-15. I²C Core Signal Description

Signal Name

I/O

Description

Bi-directional clock line of the I²C core. The signal is an output if the I²C core is in master

mode. The signal is an input if the I²C core is in slave mode. MUST be routed directly to the

pre-assigned I/O of the chip. Refer to the Pinout Information section of this document for

detailed pad and pin locations of I²C ports in each MachXO2 device.

i2c_scl

Bi-directional

Bi-directional data line of the I²C core. The signal is an output when data is transmitted from

the I²C core. The signal is an input when data is received into the I²C core. MUST be routed

directly to the pre-assigned I/O of the chip. Refer to the Pinout Information section of this

document for detailed pad and pin locations of I²C ports in each MachXO2 device.

Interrupt request output signal of the I²C core. The intended usage of this signal is for it to be

connected to the WISHBONE master controller (i.e. a microcontroller or state machine) and

request an interrupt when a specific condition is met. These conditions are described with

the I²C register definitions.

i2c_sda

i2c_irqo

Bi-directional

Output

Wake-up signal – To be connected only to the power module of the MachXO2 device. The

cfg_wake

cfg_stdby

Output

signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I²C

Tab.

Stand-by signal – To be connected only to the power module of the MachXO2 device. The

signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I²C

Tab.

Hardened SPI IP Core

Every MachXO2 device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core

is configured as a master it will be able to control other SPI enabled chips connected to the SPI bus. When the core

is configured as the slave, the device will be able to interface to an external SPI master. The SPI IP core on

MachXO2 devices supports the following functions:

• Configurable Master and Slave modes

• Full-Duplex data transfer

• Mode fault error flag with CPU interrupt capability

• Double-buffered data register

• Serial clock with programmable polarity and phase

• LSB First or MSB First Data Transfer

• Interface to custom logic through 8-bit WISHBONE interface

2-29

Architecture

MachXO2 Family Data Sheet

There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes:

• TN1087, Minimizing System Interruption During Configuration Using TransFR Technology (Appendix B)

• TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices

Figure 2-22. SPI Core Block Diagram

Configuration

Logic

EFB

SPI Function

MISO

Core

Logic/

MOSI

SCK

Routing

EFB

SPI

Control

Logic

WISHBONE

Interface

Registers

MCSN

SCSN

Table 2-16 describes the signals interfacing with the SPI cores.

Table 2-16. SPI Core Signal Description

Signal Name

spi_csn[0]

spi_csn[1..7]

spi_scsn

I/O

O

Master/Slave

Master

Description

SPI master chip-select output

O

Master

Additional SPI chip-select outputs (total up to eight slaves)

SPI slave chip-select input

I

Slave

spi_irq

O

Master/Slave

Interrupt request

spi_clk

I/O

SPI clock. Output in master mode. Input in slave mode.

SPI data. Input in master mode. Output in slave mode.

SPI data. Output in master mode. Input in slave mode.

spi_miso

spi_mosi

Configuration Slave Chip Select (active low), dedicated for selecting the

User Flash Memory (UFM).

ufm_sn

I

Slave

Stand-by signal – To be connected only to the power module of the MachXO2

device. The signal is enabled only if the “Wakeup Enable” feature has been

set within the EFB GUI, SPI Tab.

cfg_stdby

O

Master/Slave

Wake-up signal – To be connected only to the power module of the MachXO2

device. The signal is enabled only if the “Wakeup Enable” feature has been

set within the EFB GUI, SPI Tab.

cfg_wake

O

Master/Slave

Hardened Timer/Counter

MachXO2 devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bi-directional,

16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter sup-

ports the following functions:

2-30

Architecture

MachXO2 Family Data Sheet

• Supports the following modes of operation:

– Watchdog timer

– Clear timer on compare match

– Fast PWM

– Phase and Frequency Correct PWM

• Programmable clock input source

• Programmable input clock prescaler

• One static interrupt output to routing

• One wake-up interrupt to on-chip standby mode controller.

• Three independent interrupt sources: overflow, output compare match, and input capture

• Auto reload

• Time-stamping support on the input capture unit

• Waveform generation on the output

• Glitch-free PWM waveform generation with variable PWM period

• Internal WISHBONE bus access to the control and status registers

• Stand-alone mode with preloaded control registers and direct reset input

Figure 2-23. Timer/Counter Block Diagram

EFB

Timer/Counter

Core

EFB

Timer/

Counter

Registers

Control

Logic

PWM

WISHBONE

Interface

Routing

Table 2-17. Timer/Counter Signal Description

Port

tc_clki

I/O

Description

I

Timer/Counter input clock signal

tc_rstn

tc_ic

Register tc_rstn_ena is preloaded by configuration to always keep this pin enabled

Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If

enabled, a rising edge of this signal will be detected and synchronized to capture tc_cnt value

into tc_icr for time-stamping.

tc_int

tc_oc

O

Without WISHBONE – Can be used as overflow flag

With WISHBONE – Controlled by three IRQ registers

Timer counter output signal

For more details on these embedded functions, please refer to TN1205, Using User Flash Memory and Hardened

Control Functions in MachXO2 Devices.

2-31

Architecture

MachXO2 Family Data Sheet

User Flash Memory (UFM)

MachXO2-640/U and higher density devices provide a User Flash Memory block, which can be used for a variety of

applications including storing a portion of the configuration image, initializing EBRs, to store PROM data or, as a

general purpose user Flash memory. The UFM block connects to the device core through the embedded function

block WISHBONE interface. Users can also access the UFM block through the JTAG, I²C and SPI interfaces of the

device. The UFM block offers the following features:

• Non-volatile storage up to 256Kbits

• 100K write cycles

• Write access is performed page-wise; each page has 128 bits (16 bytes)

• Auto-increment addressing

• WISHBONE interface

For more information on the UFM, please refer to TN1205, Using User Flash Memory and Hardened Control Func-

tions in MachXO2 Devices.

Standby Mode and Power Saving Options

MachXO2 devices are available in three options for maximum flexibility: ZE, HC and HE devices. The ZE devices

have ultra low static and dynamic power consumption. These devices use a 1.2V core voltage that further reduces

power consumption. The HC and HE devices are designed to provide high performance. The HC devices have a

built-in voltage regulator to allow for 2.5V V and 3.3V V while the HE devices operate at 1.2V V .

CC

MachXO2 devices have been designed with features that allow users to meet the static and dynamic power

requirements of their applications by controlling various device subsystems such as the bandgap, power-on-reset

circuitry, I/O bank controllers, power guard, on-chip oscillator, PLLs, etc. In order to maximize power savings,

MachXO2 devices support an ultra low power Stand-by mode. While most of these features are available in all

three device types, these features are mainly intended for use with MachXO2 ZE devices to manage power con-

sumption.

In the stand-by mode the MachXO2 devices are powered on and configured. Internal logic, I/Os and memories are

switched on and remain operational, as the user logic waits for an external input. The device enters this mode

when the standby input of the standby controller is toggled or when an appropriate I²C or JTAG instruction is issued

by an external master. Various subsystems in the device such as the band gap, power-on-reset circuitry etc can be

configured such that they are automatically turned “off” or go into a low power consumption state to save power

when the device enters this state.

2-32

Architecture

MachXO2 Family Data Sheet

Table 2-18. MachXO2 Power Saving Features Description

Device Subsystem

Feature Description

The bandgap can be turned off in standby mode. When the Bandgap is turned off, ana-

log circuitry such as the POR, PLLs, on-chip oscillator, and referenced and differential 

I/O buffers are also turned off. Bandgap can only be turned off for 1.2V devices.

Bandgap

The POR can be turned off in standby mode. This monitors VCC levels. In the event of

unsafe V_CCdrops, this circuit reconfigures the device. When the POR circuitry is turned

off, limited power detector circuitry is still active. This option is only recommended for ap-

plications in which the power supply rails are reliable.

Power-On-Reset (POR)

On-Chip Oscillator

PLL

The on-chip oscillator has two power saving features. It may be switched off if it is not

needed in your design. It can also be turned off in Standby mode.

Similar to the on-chip oscillator, the PLL also has two power saving features. It can be

statically switched off if it is not needed in a design. It can also be turned off in Standby

mode. The PLL will wait until all output clocks from the PLL are driven low before power-

ing off.

Referenced and differential I/O buffers (used to implement standards such as HSTL,

SSTL and LVDS) consume more than ratioed single-ended I/Os such as LVCMOS and

LVTTL. The I/O bank controller allows the user to turn these I/Os off dynamically on a

per bank selection.

I/O Bank Controller

Dynamic Clock Enable for Primary

Clock Nets

Each primary clock net can be dynamically disabled to save power.

Power Guard is a feature implemented in input buffers. This feature allows users to

switch off the input buffer when it is not needed. This feature can be used in both clock

and data paths. Its biggest impact is that in the standby mode it can be used to switch off

clock inputs that are distributed using general routing resources.

Power Guard

For more details on the standby mode refer to TN1198, Power Estimation and Management for MachXO2 Devices.

Power On Reset

MachXO2 devices have power-on reset circuitry to monitor V

and V

voltage levels during power-up and

CCIO

CCINT

operation. At power-up, the POR circuitry monitors V

and V

(controls configuration) voltage levels. It

CCINT

CCIO0

then triggers download from the on-chip configuration Flash memory after reaching the V

level specified in

PORUP

the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For devices

without voltage regulators (ZE and HE devices), V is the same as the V supply voltage. For devices with

CCINT

CC

voltage regulators (HC devices), V

is regulated from the V supply voltage. From this voltage reference, the

CCINT

CC

time taken for configuration and entry into user mode is specified as Flash Download Time (t

) in the DC

REFRESH

and Switching Characteristics section of this data sheet. Before and during configuration, the I/Os are held in tri-

state. I/Os are released to user functionality once the device has finished configuration. Note that for HC devices, a

separate POR circuit monitors external V

regulated power supply voltage level.

voltage in addition to the POR circuit that monitors the internal post-

CC

Once the device enters into user mode, the POR circuitry can optionally continue to monitor V

levels. If

CCINT

V

drops below V

level (with the bandgap circuitry switched on) or below V

level (with the

CCINT

PORDNBG

PORDNSRAM

bandgap circuitry switched off to conserve power) device functionality cannot be guaranteed. In such a situation

the POR issues a reset and begins monitoring the V and V voltage levels. V and V

CCINT

CCIO

PORDNBG

PORDNSRAM

are both specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data

sheet.

Note that once a ZE or HE device enters user mode, users can switch off the bandgap to conserve power. When

the bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a mini-

mal, low power POR circuit is still operational (this corresponds to the V

reset point described in the

PORDNSRAM

paragraph above). However this circuit is not as accurate as the one that operates when the bandgap is switched

on. The low power POR circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells

flip. If users are concerned about the V supply dropping below V (min) they should not shut down the bandgap

CC

or POR circuit.

2-33

Architecture

MachXO2 Family Data Sheet

Configuration and Testing

This section describes the configuration and testing features of the MachXO2 family.

IEEE 1149.1-Compliant Boundary Scan Testability

All MachXO2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access

port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan

path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in

and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port

consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with V

Bank 0 and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.

CCIO

For more details on boundary scan test, see AN8066, Boundary Scan Testability with Lattice sysIO Capability and

TN1087, Minimizing System Interruption During Configuration Using TransFR Technology.

Device Configuration

All MachXO2 devices contain two ports that can be used for device configuration. The Test Access Port (TAP),

which supports bit-wide configuration and the sysCONFIG port which supports serial configuration through I²C or

SPI. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532

In-System Configuration specification. There are various ways to configure a MachXO2 device:

1. Internal Flash Download

2. JTAG

3. Standard Serial Peripheral Interface (Master SPI mode) – interface to boot PROM memory

4. System microprocessor to drive a serial slave SPI port (SSPI mode)

5. Standard I²C Interface to system microprocessor

Upon power-up, the configuration SRAM is ready to be configured using the selected sysCONFIG port. Once a

configuration port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be

activated any time after power-up by sending the appropriate command through the TAP port. Optionally the de-

vice can run a CRC check upon entering the user mode. This will ensure that the device was configured correctly.

The sysCONFIG port has 10 dual-function pins which can be used as general purpose I/Os if they are not required

for configuration. See TN1204, MachXO2 Programming and Configuration Usage Guide for more information

about using the dual-use pins as general purpose I/Os.

Lattice design software uses proprietary compression technology to compress bit-streams for use in MachXO2

devices. Use of this technology allows Lattice to provide a lower cost solution. In the unlikely event that this technol-

ogy is unable to compress bitstreams to fit into the amount of on-chip Flash memory, there are a variety of tech-

niques that can be utilized to allow the bitstream to fit in the on-chip Flash memory. For more details, refer to

TN1204, MachXO2 Programming and Configuration Usage Guide.

The Test Access Port (TAP) has five dual purpose pins (TDI, TDO, TMS and TCK). These pins are dual function

pins - TDI, TDO, TMS and TCK can be used as general purpose I/O if desired. For more details, refer to TN1204,

MachXO2 Programming and Configuration Usage Guide.

TransFR (Transparent Field Reconfiguration)

TransFR is a unique Lattice technology that allows users to update their logic in the field without interrupting sys-

tem operation using a simple push-button solution. For more details refer to TN1087, Minimizing System Interrup-

tion During Configuration Using TransFR Technology for details.

Security and One-Time Programmable Mode (OTP)

2-34

Architecture

MachXO2 Family Data Sheet

For applications where security is important, the lack of an external bitstream provides a solution that is inherently

more secure than SRAM-based FPGAs. This is further enhanced by device locking. MachXO2 devices contain

security bits that, when set, prevent the readback of the SRAM configuration and non-volatile Flash memory

spaces. The device can be in one of two modes:

1. Unlocked – Readback of the SRAM configuration and non-volatile Flash memory spaces is allowed.

2. Permanently Locked – The device is permanently locked.

Once set, the only way to clear the security bits is to erase the device. To further complement the security of the

device, a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to

erase or re-program the Flash and SRAM OTP portions of the device. For more details, refer to TN1204, MachXO2

Programming and Configuration Usage Guide.

Dual Boot

MachXO2 devices can optionally boot from two patterns, a primary bitstream and a golden bitstream. If the primary

bitstream is found to be corrupt while being downloaded into the SRAM, the device shall then automatically re-boot

from the golden bitstream. Note that the primary bitstream must reside in the on-chip Flash. The golden image

MUST reside in an external SPI Flash. For more details, refer to TN1204, MachXO2 Programming and Configura-

tion Usage Guide.

Soft Error Detection

The SED feature is a CRC check of the SRAM cells after the device is configured. This check ensures that the

SRAM cells were configured successfully. This feature is enabled by a configuration bit option. The Soft Error

Detection can also be initiated in user mode via an input to the fabric. The clock for the Soft Error Detection circuit

is generated using a dedicated divider. The undivided clock from the on-chip oscillator is the input to this divider.

For low power applications users can switch off the Soft Error Detection circuit. For more details, refer to TN1206,

MachXO2 Soft Error Detection Usage Guide.

TraceID

Each MachXO2 device contains a unique (per device), TraceID that can be used for tracking purposes or for IP

security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits

are factory-programmed. The TraceID is accessible through the EFB WISHBONE interface and can also be

accessed through the SPI, I²C, or JTAG interfaces.

Density Shifting

The MachXO2 family has been designed to enable density migration within the same package. Furthermore, the

architecture ensures a high success rate when performing design migration from lower density devices to higher

density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density

device to a lower density device. However, the exact details of the final resource utilization will impact the likely suc-

cess in each case. For more details refer to the MachXO2 migration files.

2-35

MachXO2 Family Data Sheet

DC and Switching Characteristics

January 2013

Data Sheet DS1035

Absolute Maximum Ratings^{1, 2, 3, 4}

MachXO2 ZE/HE (1.2V)

MachXO2 HC (2.5V/3.3V)

Supply Voltage V . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V

CC

Output Supply Voltage V

. . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V

CCIO

I/O Tri-state Voltage Applied⁵. . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V

Dedicated Input Voltage Applied . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V

Storage Temperature (Ambient). . . . . . . . . . . . . . -55°C to 125°C . . . . . . . . . . . . . -55°C to 125°C

Junction Temperature (T ) . . . . . . . . . . . . . . . . . . -40°C to 125°C . . . . . . . . . . . . . -40°C to 125°C

J

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Overshoot and undershoot of -2V to (V_IHMAX+ 2) volts is permitted for a duration of <20ns.

5. The dual function I²C pins SCL and SDA are limited to -0.25V to 3.75V or to -0.3V with a duration of <20ns.

Recommended Operating Conditions¹

Symbol

Parameter

Core Supply Voltage for 1.2V Devices

Core Supply Voltage for 2.5V/3.3V Devices

I/O Driver Supply Voltage

Min.

1.14

2.375

1.14

0

Max.

1.26

3.465

85

Units

V

1

V_CC

V

1, 2, 3

V_CCIO

t_JCOM

t_JIND

V

Junction Temperature Commercial Operation

Junction Temperature Industrial Operation

°C

-40

100

1. Like power supplies must be tied together. For example, if V_CCIOand V_CCare both the same voltage, they must also be the same

supply.

2. See recommended voltages by I/O standard in subsequent table.

3. V_CCIOpins of unused I/O banks should be connected to the V_CCpower supply on boards.

Power Supply Ramp Rates¹

Symbol

Parameter

Min.

Typ.

Max.

Units

t_RAMP

Power supply ramp rates for all power supplies.

0.01

—

100

V/ms

1. Assumes monotonic ramp rates.

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

3-1

DS1035 DC and Switching_01.8

DC and Switching Characteristics

MachXO2 Family Data Sheet

Power-On-Reset Voltage Levels^{1, 2, 3, 4}

Symbol

Parameter

Min.

Typ.

Max.

Units

Power-On-Reset ramp up trip point (band gap based circuit

V_PORUP

0.9

—

1.06

V

monitoring V_CCINTand V_CCIO

)

Power-On-Reset ramp up trip point (band gap based circuit

monitoring external V_CCpower supply)

V_PORUPEXT

V_PORDNBG

1.5

—

2.1

0.93

—

V

Power-On-Reset ramp down trip point (band gap based circuit

monitoring V_CCINT

Power-On-Reset ramp down trip point (SRAM based circuit

monitoring V_CCINT

)

V_PORDNSRAM

—

0.6

)

1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under rec-

ommended operating conditions.

2. For devices without voltage regulators V_CCINTis the same as the V_CCsupply voltage. For devices with voltage regulators, V_CCINTis regu-

lated from the V_CCsupply voltage.

3. Note that V_PORUP(min.) and V_PORDNBG(max.) are in different process corners. For any given process corner V_PORDNBG(max.) is always

12.0mV below V_PORUP(min.).

4. V_PORUPEXTis for HC devices only. In these devices a separate POR circuit monitors the external V_CCpower supply.

Programming/Erase Specifications

Symbol

N_PROGCYC

t_RETENTION

Parameter

Min.

—

Max.¹

10,000

100,000

—

Units

Flash Programming cycles per t_RETENTION

Flash functional programming cycles

Data retention at 100°C junction temperature

Data retention at 85°C junction temperature

Cycles

—

10

Years

20

—

1. Maximum Flash memory reads are limited to 7.5E13 cycles over the lifetime of the product.

Hot Socketing Specifications^{1, 2, 3}

Symbol

Parameter

Condition

Max.

Units

µA

I_DK

Input or I/O leakage Current

0 < V_IN< V_IH(MAX)

+/-1000

1. Insensitive to sequence of V_CCand V_CCIO. However, assumes monotonic rise/fall rates for V_CCand V_CCIO

.

2. 0 < V_CC< V_CC(MAX), 0 < V_CCIO< V_CCIO(MAX).

3. I_DKis additive to I_PU, I_PDor I_BH

.

ESD Performance

Please refer to the MachXO2 Product Family Qualification Summary for complete qualification data, including ESD

performance.

3-2

DC and Switching Characteristics

MachXO2 Family Data Sheet

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min.

—

Typ.

—

Max.

+175

10

Units

µA

Clamp OFF and V_CCIO< V_IN< V_IH(MAX)

Clamp OFF and V_IN= V_CCIO

-10

—

µA

Clamp OFF and V_CCIO- 0.97V < V_IN

V_CCIO

<

—

-175

µA

1, 4

I_IL, I_IH

Input or I/O Leakage

Clamp OFF and 0V < V_IN< V_CCIO- 0.97V

Clamp OFF and V_IN= GND

—

10

µA

Clamp ON and 0V < V_IN< V_CCIO

—

10

I_PU

I_PD

I/O Active Pull-up Current 0 < V_IN< 0.7 V_CCIO

-30

-309

I/O Active Pull-down

V_IL(MAX) < V_IN< V_CCIO

Current

30

-30

—

305

—

µA

V

Bus Hold Low sustaining

V_IN= V_IL(MAX)

current

—

I_BHLS

I_BHHS

I_BHLO

I_BHHO

Bus Hold High sustaining

V_IN= 0.7V_CCIO

current

—

5

—

Bus Hold Low Overdrive

0  V_INV_CCIO

current

305

-309

Bus Hold High Overdrive

0  V_INV_CCIO

current

—

V_IL

(MAX)

V_IH

(MIN)

3

V_BHT

Bus Hold Trip Points

V_CCIO= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

_CC= Typ., V_IO= 0 to V_IH(MAX)

C1

C2

I/O Capacitance²

3

9

7

pf

V

Dedicated Input

Capacitance²

V_CCIO= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

_CC= Typ., V_IO= 0 to V_IH(MAX)

5.5

pf

V

V_CCIO= 3.3V, Hysteresis = Large

V_CCIO= 2.5V, Hysteresis = Large

—

450

250

125

100

250

150

60

—

mV

V

_CCIO= 1.8V, Hysteresis = Large

_CCIO= 1.5V, Hysteresis = Large

V

Hysteresis for Schmitt

Trigger Inputs⁵

V_HYST

V_CCIO= 3.3V, Hysteresis = Small

V

_CCIO= 2.5V, Hysteresis = Small

_CCIO= 1.8V, Hysteresis = Small

V

V_CCIO= 1.5V, Hysteresis = Small

40

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured

with the output driver active. Bus maintenance circuits are disabled.

2. T_A25°C, f = 1.0MHz.

3. Please refer to V_ILand V_IHin the sysIO Single-Ended DC Electrical Characteristics table of this document.

4. When V_IHis higher than V_CCIO, a transient current typically of 30ns in duration or less with a peak current of 6mA can occur on the high-to-

low transition. For true LVDS output pins in MachXO2-640U, MachXO2-1200/U and larger devices, V_IHmust be less than or equal to V_CCIO

.

5. With bus keeper circuit turned on. For more details, refer to TN1202, MachXO2 sysIO Usage Guide.

3-3

DC and Switching Characteristics

MachXO2 Family Data Sheet

Static Supply Current – ZE Devices^{1, 2, 3, 6}

Symbol

Parameter

Device

Typ.⁴

18

Units

µA

LCMXO2-256ZE

LCMXO2-640ZE

LCMXO2-1200ZE

LCMXO2-2000ZE

LCMXO2-4000ZE

LCMXO2-7000ZE

28

µA

56

µA

I_CC

Core Power Supply

80

µA

124

189

µA

Bank Power Supply⁵

V_CCIO= 2.5V

I_CCIO

All devices

0

mA

1. For further information on supply current, please refer to TN1198, Power Estimation and Management for MachXO2 Devices.

2. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at V_CCIO

or GND, on-chip oscillator is off, on-chip PLL is off. To estimate the impact of turning each of these items on, please refer to the following

table or for more detail with your specific design use the Power Calculator tool.

3. Frequency = 0 MHz.

4. T_J= 25°C, power supplies at nominal voltage.

5. Does not include pull-up/pull-down.

6. To determine the MachXO2 peak start-up current data, use the Power Calculator tool.

Static Power Consumption Contribution of Different Components – 

ZE Devices

The table below can be used for approximating static power consumption. For a more accurate power analysis for

your design please use the Power Calculator tool.

Symbol

Parameter

Bandgap DC power contribution

POR DC power contribution

Typ.

101

38

Units

µA

I_DCBG

I_DCPOR

µA

I_{DCIOBANKCONTROLLER}

DC power contribution per I/O bank controller

143

µA

3-4

DC and Switching Characteristics

MachXO2 Family Data Sheet

Static Supply Current – HC/HE Devices^{1, 2, 3, 6}

Symbol

Parameter

Device

Typ.⁴

1.15

1.84

3.48

3.49

4.80

8.44

8.45

12.87

1.39

2.55

4.06

Units

mA

LCMXO2-256HC

LCMXO2-640HC

LCMXO2-640UHC

LCMXO2-1200HC

LCMXO2-1200UHC

LCMXO2-2000HC

LCMXO2-2000UHC

LCMXO2-4000HC

LCMXO2-7000HC

LCMXO2-2000HE

LCMXO2-4000HE

LCMXO2-7000HE

I_CC

Core Power Supply

Bank Power Supply⁵

V_CCIO= 2.5V

I_CCIO

All devices

0

mA

1. For further information on supply current, please refer to TN1198, Power Estimation and Management for MachXO2 Devices.

2. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at V_CCIOor

GND, on-chip oscillator is off, on-chip PLL is off.

3. Frequency = 0 MHz.

4. T_J= 25°C, power supplies at nominal voltage.

5. Does not include pull-up/pull-down.

6. To determine the MachXO2 peak start-up current data, use the Power Calculator tool.

Programming and Erase Flash Supply Current – ZE Devices^{1, 2, 3, 4}

Symbol

Parameter

Core Power Supply

Bank Power Supply⁶

Device

LCMXO2-256ZE

LCMXO2-640ZE

LCMXO2-1200ZE

LCMXO2-2000ZE

LCMXO2-4000ZE

LCMXO2-7000ZE

All devices

Typ.⁵

13

14

15

17

18

20

0

Units

mA

I_CC

I_CCIO

1. For further information on supply current, please refer to TN1198, Power Estimation and Management for MachXO2 Devices.

2. Assumes all inputs are held at V_CCIOor GND and all outputs are tri-stated.

3. Typical user pattern.

4. JTAG programming is at 25 MHz.

5. TJ = 25°C, power supplies at nominal voltage.

6. Per bank. V_CCIO= 2.5V. Does not include pull-up/pull-down.

3-5

DC and Switching Characteristics

MachXO2 Family Data Sheet

Programming and Erase Flash Supply Current – HC/HE Devices^{1, 2, 3, 4}

Symbol

Parameter

Core Power Supply

Bank Power Supply⁶

Device

Typ.⁵

14.6

16.1

18.8

22.1

26.8

33.2

18.3

20.4

23.9

0

Units

mA

LCMXO2-256HC

LCMXO2-640HC

LCMXO2-640UHC

LCMXO2-1200HC

LCMXO2-1200UHC

LCMXO2-2000HC

LCMXO2-2000UHC

LCMXO2-4000HC

LCMXO2-7000HC

LCMXO2-2000HE

LCMXO2-2000UHE

LCMXO2-4000HE

LCMXO2-7000HE

All devices

I_CC

I_CCIO

1. For further information on supply current, please refer to TN1198, Power Estimation and Management for MachXO2 Devices.

2. Assumes all inputs are held at V_CCIOor GND and all outputs are tri-stated.

3. Typical user pattern.

4. JTAG programming is at 25 MHz.

5. T_J= 25°C, power supplies at nominal voltage.

6. Per bank. V_CCIO= 2.5V. Does not include pull-up/pull-down.

3-6

DC and Switching Characteristics

MachXO2 Family Data Sheet

sysIO Recommended Operating Conditions

V_CCIO(V)

V_REF(V)

Standard

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2

LVTTL

Min.

3.135

2.375

1.71

Typ.

3.3

2.5

1.8

1.5

1.2

3.3

2.5

1.8

2.5

3.3

2.5

1.8

2.5

1.8

Max.

3.465

2.625

1.89

Min.

—

Typ.

—

Max.

—

1.425

1.14

1.575

1.26

—

3.135

2.375

1.71

3.465

2.625

1.89

—

PCI³

—

SSTL25

1.15

0.833

0.816

—

1.25

0.9

—

1.35

0.969

1.08

—

SSTL18

HSTL18

1.71

1.89

LVDS25^{1, 2}

LVDS33^{1, 2}

LVPECL¹

BLVDS¹

2.375

3.135

2.375

1.71

2.625

3.465

2.625

1.89

—

RSDS¹

—

SSTL18D

SSTL25D

HSTL18D

—

2.375

1.71

2.625

1.89

—

1. Inputs on-chip. Outputs are implemented with the addition of external resistors.

2. MachXO2-640U, MachXO2-1200/U and larger devices have dedicated LVDS buffers

3. Input on the bottom bank of the MachXO2-640U, MachXO2-1200/U and larger devices only.

3-7

DC and Switching Characteristics

MachXO2 Family Data Sheet

sysIO Single-Ended DC Electrical Characteristics^{1, 2}

V_IL

V_IH

Input/Output

Standard

V_OLMax.

(V)

V_OHMin.

(V)

I_OLMax.⁴I_OHMax.⁴

Min. (V)³

Max. (V)

Min. (V)

Max. (V)

(mA)

4

-4

8

-8

0.4

V_CCIO- 0.4

12

16

24

0.1

4

-12

-16

-24

-0.1

-4

LVCMOS 3.3

LVTTL

-0.3

0.8

2.0

3.6

0.2

0.4

V_CCIO- 0.2

8

-8

V_CCIO- 0.4

LVCMOS 2.5

LVCMOS 1.8

-0.3

0.7

1.7

3.6

12

16

0.1

4

-12

-16

-0.1

-4

0.2

0.4

V

_CCIO- 0.2

V_CCIO- 0.4

_CCIO- 0.2

V_CCIO- 0.4

_CCIO- 0.2

V_CCIO- 0.4

_CCIO- 0.2

8

-8

0.35V_CCIO

0.65V_CCIO

12

0.1

4

-12

-0.1

-4

0.2

0.4

0.2

0.4

V

LVCMOS 1.5

LVCMOS 1.2

-0.3

0.35V_CCIO

0.65V_CCIO

3.6

8

-8

V

0.1

4

-0.1

-2

0.35V_CCIO

0.3V_CCIO

0.65V_CCIO

0.5V_CCIO

8

-6

0.2

0.1V_CCIO

0.54

NA

V

0.1

1.5

8

-0.1

-0.5

8

PCI

-0.3

3.6

0.9V_CCIO

V_CCIO- 0.62

NA

SSTL25 Class I

SSTL25 Class II

SSTL18 Class I

SSTL18 Class II

HSTL18 Class I

HSTL18 Class II

V_REF- 0.18 V_REF+ 0.18

_REF- 0.18 V_REF+0.18

_REF- 0.125 V_REF+0.125

V_REF- 0.125 V_REF+0.125

V

NA

8

NA

8

V

0.40

NA

V_CCIO- 0.40

NA

8

NA

8

V

_REF- 0.1

V_REF+0.1

0.40

NA

V_CCIO- 0.40

NA

V

NA

1. MachXO2 devices allow LVCMOS inputs to be placed in I/O banks where V_CCIOis different from what is specified in the applicable JEDEC

specification. This is referred to as a ratioed input buffer. In a majority of cases this operation follows or exceeds the applicable JEDEC spec-

ification. The cases where MachXO2 devices do not meet the relevant JEDEC specification are documented in the table below.

2. MachXO2 devices allow for LVCMOS referenced I/Os which follow applicable JEDEC specifications. For more details about mixed mode

operation please refer to please refer to TN1202, MachXO2 sysIO Usage Guide.

3. The dual function I²C pins SCL and SDA are limited to a V_ILmin of -0.25V or to -0.3V with a duration of <10ns.

4. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as

shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or

between the last GND in a bank and the end of a bank.

Input Standard

LVCMOS 33

LVCMOS 25

LVCMOS 18

V_CCIO(V)

1.5

V_ILMax. (V)

0.685

1.5

1.687

1.5

1.164

3-8

DC and Switching Characteristics

MachXO2 Family Data Sheet

sysIO Differential Electrical Characteristics

The LVDS differential output buffers are available on the top side of MachXO2-640U, MachXO2-1200/U and higher

density devices in the MachXO2 PLD family.

LVDS

Over Recommended Operating Conditions

Parameter

Symbol

V_INP, V_INM

V_THD

Parameter Description

Input Voltage

Test Conditions

V_CCIO= 3.3

Min.

0

Typ.

—

Max.

2.605

2.05

Units

V

V_CCIO= 2.5

0

—

V

Differential Input Threshold

Input Common Mode Voltage

100

0.05

—

mV

V

_CCIO= 3.3V

_CCIO= 2.5V

—

2.6

2.0

10

V_CM

V

—

V

I_IN

Input current

Power on

—

µA

V

V_OH

V_OL

V_OD

V_OD

V_OS

V_OS

I_OSD

Output high voltage for V_OPor V_OM

Output low voltage for V_OPor V_OM

Output voltage differential

Change in V_ODbetween high and low

Output voltage offset

R_T= 100 Ohm

—

1.375

1.025

350

—

R_T= 100 Ohm

0.90

250

—

V

(V_OP- V_OM), R_T= 100 Ohm

450

50

mV

V

(V_OP- V_OM)/2, R_T= 100 Ohm

V_OD= 0V driver outputs shorted

1.125

—

1.20

—

1.395

50

Change in V_OSbetween H and L

Output short circuit current

mV

mA

—

24

3-9

DC and Switching Characteristics

MachXO2 Family Data Sheet

LVDS Emulation

MachXO2 devices can support LVDS outputs via emulation (LVDS25E). The output is emulated using complemen-

tary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in

Figure 3-1 is one possible solution for LVDS standard implementation. Resistor values in Figure 3-1 are industry

standard values for 1% resistors.

Figure 3-1. LVDS Using External Resistors (LVDS25E)

VCCIO = 2.5

158

8mA

Zo = 100

+

-

100

VCCIO = 2.5

8mA

140

158

On-chip

Off-chip

On-chip

Emulated

LVDS

Buffer

Note: All resistors are 1ꢀ.

Table 3-1. LVDS25E DC Conditions

Over Recommended Operating Conditions

Parameter

Z_OUT

Description

Output impedance

Typ.

20

Units

Ohms

V

R_S

Driver series resistor

Driver parallel resistor

Receiver termination

Output high voltage

Output low voltage

158

R_P

140

R_T

100

V_OH

V_OL

V_OD

V_CM

Z_BACK

I_DC

1.43

1.07

0.35

1.25

100.5

6.03

V

Output differential voltage

Output common mode voltage

Back impedance

V

Ohms

mA

DC output current

3-10

DC and Switching Characteristics

MachXO2 Family Data Sheet

BLVDS

The MachXO2 family supports the BLVDS standard through emulation. The output is emulated using complemen-

tary LVCMOS outputs in conjunction with resistors across the driver outputs. The input standard is supported by

the LVDS differential input buffer. BLVDS is intended for use when multi-drop and bi-directional multi-point differen-

tial signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point dif-

ferential signals.

Figure 3-2. BLVDS Multi-point Output Example

Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential

2.5V

16mA

2.5V

16mA

80

45-90 ohms

80

2.5V

16mA

2.5V

16mA

80

. . .

+

-

+

-

2.5V

16mA

2.5V

16mA

Table 3-2. BLVDS DC Conditions¹

Over Recommended Operating Conditions

Nominal

Symbol

Z_OUT

Description

Zo = 45

10

Zo = 90

10

Units

Ohms

V

Output impedance

R_S

Driver series resistance

Left end termination

Right end termination

Output high voltage

80

R_TLEFT

R_TRIGHT

V_OH

45

90

45

90

1.376

1.124

0.253

1.250

11.236

1.480

1.020

0.459

1.250

10.204

V_OL

Output low voltage

V

V_OD

Output differential voltage

Output common mode voltage

DC output current

V

V_CM

I_DC

V

mA

1. For input buffer, see LVDS table.

3-11

DC and Switching Characteristics

MachXO2 Family Data Sheet

LVPECL

The MachXO2 family supports the differential LVPECL standard through emulation. This output standard is emu-

lated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the

devices. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Dif-

ferential LVPECL is one possible solution for point-to-point signals.

Figure 3-3. Differential LVPECL

V_CCIO= 3.3V

93 ohms

16mA

_CCIO= 3.3V

+

V

196 ohms

100 ohms

-

93 ohms

Off-chip

16mA

Transmission line, Zo = 100 ohm differential

Off-chip

On-chip

Table 3-3. LVPECL DC Conditions¹

Over Recommended Operating Conditions

Symbol

Z_OUT

Description

Output impedance

Nominal

10

Units

Ohms

R_S

Driver series resistor

Driver parallel resistor

Receiver termination

Output high voltage

Output low voltage

93

Ohms

V

R_P

196

R_T

100

V_OH

V_OL

V_OD

V_CM

Z_BACK

I_DC

2.05

1.25

0.80

1.65

100.5

12.11

V

Output differential voltage

Output common mode voltage

Back impedance

V

Ohms

mA

DC output current

1. For input buffer, see LVDS table.

For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni-

cal documentation at the end of the data sheet.

3-12

DC and Switching Characteristics

MachXO2 Family Data Sheet

RSDS

The MachXO2 family supports the differential RSDS standard. The output standard is emulated using complemen-

tary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The RSDS input

standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solu-

tion for RSDS standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resis-

tor values in Figure 3-4 are industry standard values for 1% resistors.

Figure 3-4. RSDS (Reduced Swing Differential Standard)

VCCIO = 2.5V

294

8mA

Zo = 100

+

VCCIO = 2.5V

121

100

-

294

8mA

On-chip

Off-chip

On-chip

Emulated

RSDS Buffer

Table 3-4. RSDS DC Conditions

Parameter

Z_OUT

R_S

Description

Typical

20

Units

Output impedance

Ohms

V

Driver series resistor

Driver parallel resistor

Receiver termination

Output high voltage

Output low voltage

294

R_P

121

R_T

100

V_OH

1.35

1.15

0.20

1.25

101.5

3.66

V_OL

V

V_OD

Output differential voltage

Output common mode voltage

Back impedance

V

V_CM

V

Z_BACK

I_DC

Ohms

mA

DC output current

3-13

DC and Switching Characteristics

MachXO2 Family Data Sheet

Typical Building Block Function Performance – HC/HE Devices¹

Pin-to-Pin Performance (LVCMOS25 12mA Drive)

Function

Basic Functions

16-bit decoder

-6 Timing

Units

8.9

7.5

8.3

ns

4:1 MUX

16:1 MUX

Register-to-Register Performance

Function

Basic Functions

16:1 MUX

-6 Timing

Units

412

297

324

161

MHz

16-bit adder

16-bit counter

64-bit counter

Embedded Memory Functions

1024x9 True-Dual Port RAM

(Write Through or Normal, EBR output registers)

183

MHz

Distributed Memory Functions

16x4 Pseudo-Dual Port RAM (one PFU)

500

MHz

1. The above timing numbers are generated using the Diamond design tool. Exact performance may vary

with device and tool version. The tool uses internal parameters that have been characterized but are not

tested on every device.

3-14

DC and Switching Characteristics

MachXO2 Family Data Sheet

Typical Building Block Function Performance – ZE Devices¹

Pin-to-Pin Performance (LVCMOS25 12mA Drive)

Function

Basic Functions

16-bit decoder

-3 Timing

Units

13.9

10.9

12.0

ns

4:1 MUX

16:1 MUX

Register-to-Register Performance

Function

Basic Functions

16:1 MUX

-3 Timing

Units

191

134

148

77

MHz

16-bit adder

16-bit counter

64-bit counter

Embedded Memory Functions

1024x9 True-Dual Port RAM

(Write Through or Normal, EBR output registers)

90

MHz

Distributed Memory Functions

16x4 Pseudo-Dual Port RAM (one PFU)

214

MHz

1. The above timing numbers are generated using the Diamond design tool. Exact performance may vary

with device and tool version. The tool uses internal parameters that have been characterized but are not

tested on every device.

Derating Logic Timing

Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case num-

bers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing num-

bers at a particular temperature and voltage.

3-15

DC and Switching Characteristics

MachXO2 Family Data Sheet

Maximum sysIO Buffer Performance

I/O Standard

LVDS25

Max. Speed

400

150

134

150

91

Units

MHz

LVDS25E

RSDS25

RSDS25E

BLVDS25

BLVDS25E

MLVDS25

MLVDS25E

LVPECL33

LVPECL33E

SSTL25_I

SSTL25_II

SSTL25D_I

SSTL25D_II

SSTL18_I

SSTL18_II

SSTL18D_I

SSTL18D_II

HSTL18_I

HSTL18_II

HSTL18D_I

HSTL18D_II

PCI33

LVTTL33

LVTTL33D

LVCMOS33

LVCMOS33D

LVCMOS25

LVCMOS25D

LVCMOS25R33

LVCMOS18

LVCMOS18D

LVCMOS18R33

LVCMOS18R25

LVCMOS15

LVCMOS15D

LVCMOS15R33

LVCMOS15R25

LVCMOS12

LVCMOS12D

91

3-16

DC and Switching Characteristics

MachXO2 Family Data Sheet

MachXO2 External Switching Characteristics – HC/HE Devices^{1, 2, 3, 4, 5, 6, 7}

Over Recommended Operating Conditions

-6

-5

-4

Parameter

Clocks

Description

Device

Min. Max. Min. Max. Min. Max. Units

Primary Clocks

Frequency for Primary Clock

Tree

8

f_{MAX_PRI}

All MachXO2 devices

—

388

—

323

—

269

—

MHz

ns

Clock Pulse Width for Primary

Clock

t_{W_PRI}

0.5

0.6

0.7

MachXO2-256HC-HE

MachXO2-640HC-HE

MachXO2-1200HC-HE

MachXO2-2000HC-HE

MachXO2-4000HC-HE

MachXO2-7000HC-HE

—

912

844

868

867

865

902

—

939

871

902

897

892

942

—

975

908

951

941

931

989

ps

Primary Clock Skew Within a

Device

t_{SKEW_PRI}

Edge Clock

MachXO2-1200 and

larger devices

8

f_{MAX_EDGE}Frequency for Edge Clock

—

400

—

333

—

278

MHz

ns

Pin-LUT-Pin Propagation Delay

Best case propagation delay

t_PD

All MachXO2 devices

6.72

6.96

7.24

through one LUT-4

General I/O Pin Parameters (Using Primary Clock without PLL)

MachXO2-256HC-HE

—

7.13

7.15

7.44

7.46

7.51

7.54

—

7.30

7.64

7.66

7.71

7.75

—

7.57

7.94

7.96

8.01

8.06

—

ns

MachXO2-640HC-HE

MachXO2-1200HC-HE

MachXO2-2000HC-HE

MachXO2-4000HC-HE

MachXO2-7000HC-HE

MachXO2-256HC-HE

MachXO2-640HC-HE

—

Clock to Output - PIO Output

Register

t_CO

t_SU

t_H

—

-0.06

-0.17

-0.20

-0.23

1.95

2.12

2.13

2.18

2.23

-0.06

-0.17

-0.20

-0.23

2.16

2.36

2.37

2.43

2.49

—

MachXO2-1200HC-HE -0.17

MachXO2-2000HC-HE -0.20

MachXO2-4000HC-HE -0.23

MachXO2-7000HC-HE -0.23

—

Clock to Data Setup - PIO

Input Register

—

MachXO2-256HC-HE

MachXO2-640HC-HE

1.75

—

MachXO2-1200HC-HE 1.88

MachXO2-2000HC-HE 1.89

MachXO2-4000HC-HE 1.94

MachXO2-7000HC-HE 1.98

—

Clock to Data Hold - PIO Input

Register

—

3-17

DC and Switching Characteristics

MachXO2 Family Data Sheet

-6

-5

-4

Parameter

Description

Device

Min. Max. Min. Max. Min. Max. Units

MachXO2-256HC-HE

MachXO2-640HC-HE

1.42

1.41

—

1.59

1.58

1.79

1.76

1.81

1.67

-0.24

-0.23

-0.24

-0.23

-0.25

-0.21

—

1.96

2.17

2.13

2.19

2.03

-0.24

-0.23

-0.24

-0.23

-0.25

-0.21

—

ns

Clock to Data Setup - PIO

Input Register with Data Input

Delay

MachXO2-1200HC-HE 1.63

MachXO2-2000HC-HE 1.61

MachXO2-4000HC-HE 1.66

MachXO2-7000HC-HE 1.53

t_{SU_DEL}

MachXO2-256HC-HE

MachXO2-640HC-HE

-0.24

-0.23

MachXO2-1200HC-HE -0.24

MachXO2-2000HC-HE -0.23

MachXO2-4000HC-HE -0.25

MachXO2-7000HC-HE -0.21

Clock to Data Hold - PIO Input

Register with Input Data Delay

t_{H_DEL}

Clock Frequency of I/O and

PFU Register

f_{MAX_IO}

All MachXO2 devices

—

388

—

323

—

269

MHz

General I/O Pin Parameters (Using Edge Clock without PLL)

MachXO2-1200HC-HE

—

7.53

7.45

7.53

—

7.76

7.68

7.76

—

8.10

8.00

8.10

—

ns

MachXO2-2000HC-HE

MachXO2-4000HC-HE

MachXO2-7000HC-HE

—

Clock to Output - PIO Output

Register

t_COE

—

MachXO2-1200HC-HE -0.19

MachXO2-2000HC-HE -0.19

MachXO2-4000HC-HE -0.16

MachXO2-7000HC-HE -0.19

MachXO2-1200HC-HE 1.97

MachXO2-2000HC-HE 1.97

MachXO2-4000HC-HE 1.89

MachXO2-7000HC-HE 1.97

MachXO2-1200HC-HE 1.56

MachXO2-2000HC-HE 1.56

MachXO2-4000HC-HE 1.74

MachXO2-7000HC-HE 1.66

MachXO2-1200HC-HE -0.23

MachXO2-2000HC-HE -0.23

MachXO2-4000HC-HE -0.34

MachXO2-7000HC-HE -0.29

-0.19

-0.16

-0.19

2.24

2.16

2.24

1.69

1.88

1.81

-0.23

-0.34

-0.29

-0.19

-0.16

-0.19

2.52

2.43

2.52

2.05

2.25

2.17

-0.23

-0.34

-0.29

—

Clock to Data Setup - PIO

Input Register

t_SUE

—

Clock to Data Hold - PIO Input

Register

t_HE

—

Clock to Data Setup - PIO

Input Register with Data Input

Delay

—

t_{SU_DELE}

—

Clock to Data Hold - PIO Input

Register with Input Data Delay

t_{H_DELE}

—

General I/O Pin Parameters (Using Primary Clock with PLL)

MachXO2-1200HC-HE

—

5.97

5.98

5.99

6.02

—

6.00

6.01

6.02

6.06

—

6.13

6.14

6.16

6.20

—

ns

MachXO2-2000HC-HE

MachXO2-4000HC-HE

MachXO2-7000HC-HE

Clock to Output - PIO Output

Register

t_COPLL

—

MachXO2-1200HC-HE 0.36

MachXO2-2000HC-HE 0.36

MachXO2-4000HC-HE 0.35

MachXO2-7000HC-HE 0.34

0.36

0.35

0.34

0.65

0.63

0.62

0.59

—

Clock to Data Setup - PIO

Input Register

t_SUPLL

—

3-18

DC and Switching Characteristics

MachXO2 Family Data Sheet

-6

-5

-4

Parameter

Description

Device

Min. Max. Min. Max. Min. Max. Units

MachXO2-1200HC-HE 0.41

MachXO2-2000HC-HE 0.42

MachXO2-4000HC-HE 0.43

MachXO2-7000HC-HE 0.46

MachXO2-1200HC-HE 2.88

MachXO2-2000HC-HE 2.87

MachXO2-4000HC-HE 2.96

MachXO2-7000HC-HE 3.05

MachXO2-1200HC-HE -0.83

MachXO2-2000HC-HE -0.83

MachXO2-4000HC-HE -0.87

MachXO2-7000HC-HE -0.91

—

0.48

0.49

0.50

0.54

3.19

3.18

3.28

3.35

-0.83

-0.87

-0.91

—

0.55

0.56

0.58

0.62

3.72

3.70

3.81

3.87

-0.83

-0.87

-0.91

—

ns

Clock to Data Hold - PIO Input

Register

t_HPLL

Clock to Data Setup - PIO

t_{SU_DELPLL}Input Register with Data Input

Delay

Clock to Data Hold - PIO Input

t_{H_DELPLL}

Register with Input Data Delay

Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned⁹

t_DVA

Input Data Valid After CLK

Input Data Hold After CLK

DDRX1 Input Data Speed

DDRX1 SCLK Frequency

—

0.742

—

0.317

—

0.702

—

0.344

—

0.668

—

0.368

—

UI

t_DVE

All MachXO2 devices,

all sides

f_DATA

f_DDRX1

300

150

250

125

208

104

Mbps

MHz

—

Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered⁹

t_SU

Input Data Setup Before CLK

Input Data Hold After CLK

DDRX1 Input Data Speed

DDRX1 SCLK Frequency

0.566

0.778

—

0.560

0.879

—

0.538

1.090

—

ns

t_HO

All MachXO2 devices,

all sides

f_DATA

300

250

208

Mbps

f_DDRX1

—

150

—

125

—

104

MHz

Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned⁹

t_DVA

t_DVE

Input Data Valid After CLK

Input Data Hold After CLK

—

0.316

—

0.342

—

0.364

—

UI

0.710

0.675

0.679

MachXO2-640U,

MachXO2-1200/U and

larger devices,

DDRX2 Serial Input Data

Speed

f_DATA

—

664

—

554

—

462

Mbps

bottom side only

f_DDRX2

f_SCLK

DDRX2 ECLK Frequency

SCLK Frequency

—

332

166

—

277

139

—

231

116

MHz

Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered⁹

t_SU

t_HO

Input Data Setup Before CLK

Input Data Hold After CLK

0.233

0.287

—

0.219

0.287

—

0.198

0.344

—

ns

MachXO2-640U,

MachXO2-1200/U and

larger devices,

DDRX2 Serial Input Data

Speed

f_DATA

—

664

—

554

—

462

Mbps

bottom side only

f_DDRX2

f_SCLK

DDRX2 ECLK Frequency

SCLK Frequency

—

332

166

—

277

139

—

231

116

MHz

3-19

DC and Switching Characteristics

MachXO2 Family Data Sheet

-6

Min. Max. Min. Max. Min. Max. Units

Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Aligned⁹

-5

-4

Parameter

Description

Device

t_DVA

t_DVE

Input Data Valid After ECLK

Input Data Hold After ECLK

—

0.290

—

0.320

—

0.345

—

UI

0.739

0.699

0.703

MachXO2-640U,

MachXO2-1200/U and

larger devices,

DDRX4 Serial Input Data

Speed

f_DATA

—

756

—

630

—

524

Mbps

bottom side only

f_DDRX4

f_SCLK

DDRX4 ECLK Frequency

SCLK Frequency

—

378

95

—

315

79

—

262

66

MHz

Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered⁹

t_SU

t_HO

Input Data Setup Before ECLK

Input Data Hold After ECLK

0.233

0.287

—

0.219

0.287

—

0.198

0.344

—

ns

MachXO2-640U,

MachXO2-1200/U and

larger devices,

DDRX4 Serial Input Data

Speed

f_DATA

—

756

—

630

—

524

Mbps

bottom side only

f_DDRX4

f_SCLK

DDRX4 ECLK Frequency

—

378

95

—

315

79

—

262

66

MHz

SCLK Frequency

7:1 LVDS Inputs (GDDR71_RX.ECLK.7:1)⁹

t_DVA

t_DVE

Input Data Valid After ECLK

Input Data Hold After ECLK

—

0.290

—

0.320

—

0.345

—

UI

0.739

0.699

0.703

DDR71 Serial Input Data

Speed

MachXO2-640U,

MachXO2-1200/U and

larger devices, bottom

side only

f_DATA

—

756

378

—

630

315

—

524

262

Mbps

MHz

f_DDR71

DDR71 ECLK Frequency

7:1 Input Clock Frequency

(SCLK) (minimum limited by

PLL)

f_CLKIN

—

108

—

90

—

75

MHz

Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned⁹

Output Data Invalid After CLK

Output

t_DIA

t_DIB

—

0.520

—

0.550

—

0.580

ns

Output Data Invalid Before

CLK Output

All MachXO2 devices,

all sides

f_DATA

DDRX1 Output Data Speed

—

300

150

—

250

125

—

208

104

Mbps

MHz

f_DDRX1

DDRX1 SCLK frequency

Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered⁹

Output Data Valid Before CLK

Output

t_DVB

1.210

—

1.510

—

1.870

—

ns

Output Data Valid After CLK

Output

t_DVA

1.210

—

1.510

—

1.870

—

ns

All MachXO2 devices,

all sides

f_DATA

f_DDRX1

DDRX1 Output Data Speed

300

150

250

125

208

104

Mbps

MHz

DDRX1 SCLK Frequency

(minimum limited by PLL)

—

Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned⁹

Output Data Invalid After CLK

Output

t_DIA

—

0.200

664

—

0.215

554

—

0.230

462

ns

Output Data Invalid Before

CLK Output

MachXO2-640U,

MachXO2-1200/U and

larger devices, top side

only

t_DIB

DDRX2 Serial Output Data

Speed

f_DATA

Mbps

f_DDRX2

f_SCLK

DDRX2 ECLK frequency

SCLK Frequency

—

332

166

—

277

139

—

231

116

MHz

3-20

DC and Switching Characteristics

MachXO2 Family Data Sheet

-6

-5

-4

Parameter

Description

Device

Min. Max. Min. Max. Min. Max. Units

Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered⁹

Output Data Valid Before CLK

Output

t_DVB

t_DVA

f_DATA

0.535

—

0.670

—

0.830

—

ns

Output Data Valid After CLK

Output

MachXO2-640U,

MachXO2-1200/U and

larger devices, top side

only

DDRX2 Serial Output Data

Speed

664

554

462

Mbps

DDRX2 ECLK Frequency

(minimum limited by PLL)

f_DDRX2

f_SCLK

—

332

166

—

277

139

—

231

116

MHz

SCLK Frequency

Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned⁹

Output Data Invalid After CLK

Output

t_DIA

—

0.200

756

—

0.215

630

—

0.230

524

ns

Output Data Invalid Before

CLK Output

MachXO2-640U,

MachXO2-1200/U and

larger devices, top side

only

t_DIB

DDRX4 Serial Output Data

Speed

f_DATA

Mbps

f_DDRX4

f_SCLK

DDRX4 ECLK Frequency

SCLK Frequency

—

378

95

—

315

79

—

262

66

MHz

Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered⁹

Output Data Valid Before CLK

Output

t_DVB

t_DVA

f_DATA

0.455

—

0.570

—

0.710

—

ns

Output Data Valid After CLK

Output

MachXO2-640U,

MachXO2-1200/U and

larger devices, top side

only

DDRX4 Serial Output Data

Speed

756

630

524

Mbps

DDRX4 ECLK Frequency

(minimum limited by PLL)

f_DDRX4

f_SCLK

—

378

95

—

315

79

—

262

66

MHz

SCLK Frequency

7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1⁹

Output Data Valid Before CLK

Output

t_DVB

—

0.160

—

0.180

—

0.200

ns

Output Data Valid After CLK

Output

t_DVA

MachXO2-640U,

MachXO2-1200/U and

larger devices, top side

only.

DDR71 Serial Output Data

Speed

f_DATA

—

756

378

—

630

315

—

524

262

Mbps

MHz

f_DDR71

DDR71 ECLK Frequency

7:1 Output Clock Frequency

(SCLK) (minimum limited by

PLL)

f_CLKOUT

—

108

—

90

—

75

MHz

3-21

DC and Switching Characteristics

MachXO2 Family Data Sheet

-6

-5

-4

Parameter

LPDDR⁹

Description

Device

Min. Max. Min. Max. Min. Max. Units

Input Data Valid After DQS

Input

t_DVADQ

t_DVEDQ

t_DQVBS

t_DQVAS

f_DATA

—

0.529

0.25

—

0.369

—

0.530

0.25

—

0.395

—

0.527

0.25

—

0.421

—

UI

Input Data Hold After DQS

Input

Output Data Invalid Before

DQS Output

—

UI

MachXO2-1200/U and

larger devices, right

side only.

Output Data Invalid After DQS

Output

—

UI

MEM LPDDR Serial Data

Speed

280

250

208

Mbps

f_SCLK

SCLK Frequency

—

0

140

280

—

0

125

250

—

0

104

208

MHz

f_LPDDR

DDR⁹

LPDDR Data Transfer Rate

Mbps

Input Data Valid After DQS

Input

t_DVADQ

t_DVEDQ

t_DQVBS

t_DQVAS

—

0.350

—

0.387

—

0.414

—

UI

Input Data Hold After DQS

Input

0.545

0.25

0.538

0.25

0.532

0.25

Output Data Invalid Before

DQS Output

MachXO2-1200/U and

larger devices, right

—

Output Data Invalid After DQS side only.

Output

—

f_DATA

MEM DDR Serial Data Speed

SCLK Frequency

—

300

150

300

—

250

125

250

—

208

104

208

Mbps

MHz

f_SCLK

f_{MEM_DDR}

DDR2⁹

MEM DDR Data Transfer Rate

N/A

Mbps

Input Data Valid After DQS

Input

t_DVADQ

t_DVEDQ

t_DQVBS

t_DQVAS

—

0.360

—

0.378

—

0.406

—

UI

Input Data Hold After DQS

Input

0.555

0.25

0.549

0.25

0.542

0.25

Output Data Invalid Before

DQS Output

—

MachXO2-1200/U and

larger devices, right

side only.

Output Data Invalid After DQS

Output

—

f_DATA

f_SCLK

MEM DDR Serial Data Speed

SCLK Frequency

—

300

150

—

250

125

—

208

104

Mbps

MHz

MEM DDR2 Data Transfer

Rate

f_{MEM_DDR2}

N/A

300

N/A

250

N/A

208

Mbps

1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14V. Other

operating conditions, including industrial, can be extracted from the Diamond software.

2. General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load.

3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).

4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.

5. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).

6. For Generic DDRX1 mode t_SU= t_HO= (t_DVE- t_DVA- 0.03ns)/2.

7. The t_{SU_DEL}and t_{H_DEL}values use the SCLK_ZERHOLD default step size. Each step is 105ps (-6), 113ps (-5), 120ps (-4).

8. This number for general purpose usage. Duty cycle tolerance is +/-10%.

9. Duty cycle is +/- 5% for system usage.

10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.

3-22

DC and Switching Characteristics

MachXO2 Family Data Sheet

MachXO2 External Switching Characteristics – ZE Devices^{1, 2, 3, 4, 5, 6, 7}

Over Recommended Operating Conditions

-3

-2

-1

Parameter

Clocks

Description

Device

Min. Max. Min. Max. Min. Max. Units

Primary Clocks

Frequency for Primary Clock

Tree

8

f_{MAX_PRI}

All MachXO2 devices

—

150

—

125

—

104

—

MHz

ns

Clock Pulse Width for Primary

Clock

t_{W_PRI}

All MachXO2 devices 1.00

1.20

1.40

MachXO2-256ZE

MachXO2-640ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

—

1250

1161

1213

1204

1195

1243

—

1272

1183

1267

1250

1233

1268

—

1296

1206

1322

1296

1269

1296

ps

Primary Clock Skew Within a

Device

t_{SKEW_PRI}

Edge Clock

MachXO2-1200 and

larger devices

8

f_{MAX_EDGE}

Frequency for Edge Clock

—

210

—

175

—

146

MHz

ns

Pin-LUT-Pin Propagation Delay

Best case propagation delay

through one LUT-4

t_PD

All MachXO2 devices

9.35

9.78

10.21

General I/O Pin Parameters (Using Primary Clock without PLL)

MachXO2-256ZE

MachXO2-640ZE

—

10.46

10.52

11.24

11.27

11.28

11.22

—

10.86

10.92

11.68

11.71

11.78

11.76

—

11.25

11.32

12.12

12.16

12.28

12.30

—

ns

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

MachXO2-256ZE

MachXO2-640ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

MachXO2-256ZE

MachXO2-640ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

—

Clock to Output - PIO Output

Register

t_CO

t_SU

t_H

—

-0.21

-0.22

-0.25

-0.27

-0.31

-0.33

3.96

4.01

3.95

3.94

3.96

3.93

-0.21

-0.22

-0.25

-0.27

-0.31

-0.33

4.25

4.31

4.29

4.36

4.37

-0.21

-0.22

-0.25

-0.27

-0.31

-0.33

4.65

4.71

4.73

4.74

4.87

4.91

—

Clock to Data Setup - PIO

Input Register

—

Clock to Data Hold - PIO Input

Register

—

3-23

DC and Switching Characteristics

MachXO2 Family Data Sheet

-3

-2

-1

Parameter

Description

Device

Min. Max. Min. Max. Min. Max. Units

MachXO2-256ZE

MachXO2-640ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

MachXO2-256ZE

MachXO2-640ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

2.62

2.56

2.30

2.25

2.39

2.17

-0.44

-0.43

-0.28

-0.31

-0.34

-0.21

—

2.91

2.85

2.57

2.50

2.60

2.33

-0.44

-0.43

-0.28

-0.31

-0.34

-0.21

—

3.14

3.08

2.79

2.70

2.76

2.43

-0.44

-0.43

-0.28

-0.31

-0.34

-0.21

—

ns

Clock to Data Setup - PIO

Input Register with Data Input

Delay

t_{SU_DEL}

Clock to Data Hold - PIO Input

Register with Input Data Delay

t_{H_DEL}

Clock Frequency of I/O and

PFU Register

f_{MAX_IO}

All MachXO2 devices

—

150

—

125

—

104

MHz

General I/O Pin Parameters (Using Edge Clock without PLL)

MachXO2-1200ZE

—

11.10

10.89

11.10

—

11.51

11.28

11.51

—

11.91

11.67

11.91

—

ns

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

—

Clock to Output - PIO Output

Register

t_COE

—

-0.23

-0.15

-0.23

3.81

3.60

3.81

2.78

3.11

2.94

-0.29

-0.46

-0.37

-0.23

-0.15

-0.23

4.11

3.89

4.11

3.11

3.48

3.30

-0.29

-0.46

-0.37

-0.23

-0.15

-0.23

4.52

4.28

4.52

3.40

3.79

3.60

-0.29

-0.46

-0.37

—

Clock to Data Setup - PIO

Input Register

t_SUE

—

Clock to Data Hold - PIO Input

Register

t_HE

—

Clock to Data Setup - PIO

Input Register with Data Input

Delay

—

t_{SU_DELE}

—

Clock to Data Hold - PIO Input

Register with Input Data Delay

t_{H_DELE}

—

General I/O Pin Parameters (Using Primary Clock with PLL)

MachXO2-1200ZE

—

7.95

7.97

7.98

8.02

—

8.07

8.10

8.14

—

8.19

8.22

8.23

8.26

—

ns

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

Clock to Output - PIO Output

Register

t_COPLL

—

0.85

0.84

0.83

0.85

0.84

0.83

0.89

0.86

0.85

0.81

—

Clock to Data Setup - PIO

Input Register

t_SUPLL

—

3-24

DC and Switching Characteristics

MachXO2 Family Data Sheet

-3

-2

-1

Parameter

Description

Device

Min. Max. Min. Max. Min. Max. Units

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

MachXO2-1200ZE

MachXO2-2000ZE

MachXO2-4000ZE

MachXO2-7000ZE

0.66

0.68

0.73

5.14

5.11

5.27

5.15

-1.36

-1.35

-1.43

-1.41

—

0.68

0.70

0.71

0.74

5.69

5.67

5.84

5.71

-1.36

-1.35

-1.43

-1.41

—

0.80

0.83

0.84

0.87

6.20

6.17

6.35

6.23

-1.36

-1.35

-1.43

-1.41

—

ns

Clock to Data Hold - PIO Input

Register

t_HPLL

Clock to Data Setup - PIO

Input Register with Data Input

Delay

t_{SU_DELPLL}

Clock to Data Hold - PIO Input

Register with Input Data Delay

t_{H_DELPLL}

Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned⁹

t_DVA

Input Data Valid After CLK

Input Data Hold After CLK

DDRX1 Input Data Speed

DDRX1 SCLK Frequency

—

0.670

—

0.382

—

0.684

—

0.401

—

0.693

—

0.417

—

UI

t_DVE

All MachXO2

devices, all sides

f_DATA

f_DDRX1

140

70

116

58

98

Mbps

MHz

—

49

Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered⁹

t_SU

Input Data Setup Before CLK

Input Data Hold After CLK

DDRX1 Input Data Speed

DDRX1 SCLK Frequency

1.319

0.717

—

1.412

1.010

—

1.462

1.340

—

98

49

ns

t_HO

All MachXO2

devices, all sides

f_DATA

140

116

Mbps

f_DDRX1

—

70

—

58

—

MHz

Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned⁹

t_DVA

t_DVE

Input Data Valid After CLK

Input Data Hold After CLK

—

0.361

—

0.346

—

0.334

—

UI

0.602

0.625

0.648

MachXO2-640U,

MachXO2-1200/U

and larger devices,

bottom side only

DDRX2 Serial Input Data

Speed

f_DATA

—

280

—

234

—

194

Mbps

f_DDRX2

f_SCLK

DDRX2 ECLK Frequency

SCLK Frequency

—

140

70

—

117

59

—

97

49

MHz

Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered⁹

t_SU

t_HO

Input Data Setup Before CLK

Input Data Hold After CLK

0.472

0.363

—

0.672

0.501

—

0.865

0.743

—

ns

MachXO2-640U,

MachXO2-1200/U

and larger devices,

bottom side only

DDRX2 Serial Input Data

Speed

f_DATA

—

280

—

234

—

194

Mbps

f_DDRX2

f_SCLK

DDRX2 ECLK Frequency

SCLK Frequency

—

140

70

—

117

59

—

97

49

MHz

Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input - GDDRX4_RX.ECLK.Aligned⁹

t_DVA

t_DVE

Input Data Valid After ECLK

Input Data Hold After ECLK

—

0.307

—

0.316

—

0.326

—

UI

0.662

0.650

0.649

MachXO2-640U,

MachXO2-1200/U

and larger devices,

bottom side only

DDRX4 Serial Input Data

Speed

f_DATA

—

420

—

352

—

292

Mbps

f_DDRX4

f_SCLK

DDRX4 ECLK Frequency

SCLK Frequency

—

210

53

—

176

44

—

146

37

MHz

3-25

DC and Switching Characteristics

MachXO2 Family Data Sheet

-3

Min. Max. Min. Max. Min. Max. Units

Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered⁹

-2

-1

Parameter

Description

Device

t_SU

t_HO

Input Data Setup Before ECLK

Input Data Hold After ECLK

0.434

0.385

—

0.535

0.395

—

0.630

0.463

—

ns

MachXO2-640U,

MachXO2-1200/U

and larger devices,

bottom side only

DDRX4 Serial Input Data

Speed

f_DATA

—

420

—

352

—

292

Mbps

f_DDRX4

f_SCLK

DDRX4 ECLK Frequency

SCLK Frequency

—

210

53

—

176

44

—

146

37

MHz

7:1 LVDS Inputs – GDDR71_RX.ECLK.7.1⁹

t_DVA

t_DVE

Input Data Valid After ECLK

Input Data Hold After ECLK

—

0.307

—

0.316

—

0.326

—

UI

0.662

0.650

0.649

DDR71 Serial Input Data

Speed

MachXO2-640U,

MachXO2-1200/U

and larger devices,

bottom side only

f_DATA

—

420

210

—

352

176

—

292

146

Mbps

MHz

f_DDR71

DDR71 ECLK Frequency

7:1 Input Clock Frequency

(SCLK) (minimum limited by

PLL)

f_CLKIN

—

60

—

50

—

42

MHz

Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned⁹

Output Data Invalid After CLK

Output

t_DIA

t_DIB

—

0.850

—

0.910

—

0.970

ns

Output Data Invalid Before

CLK Output

All MachXO2

devices, all sides

f_DATA

DDRX1 Output Data Speed

DDRX1 SCLK frequency

—

140

70

—

116

58

—

98

49

Mbps

MHz

f_DDRX1

Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered⁹

Output Data Valid Before CLK

Output

t_DVB

2.720

—

3.380

—

4.140

—

ns

Output Data Valid After CLK

Output

t_DVA

2.720

—

140

70

3.380

—

116

58

4.140

—

98

49

ns

All MachXO2

devices, all sides

f_DATA

f_DDRX1

DDRX1 Output Data Speed

Mbps

MHz

DDRX1 SCLK Frequency

(minimum limited by PLL)

—

Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned⁹

Output Data Invalid After CLK

Output

t_DIA

—

0.270

280

—

0.300

234

—

0.330

194

ns

Output Data Invalid Before

CLK Output

MachXO2-640U,

MachXO2-1200/U

and larger devices,

top side only

t_DIB

DDRX2 Serial Output Data

Speed

f_DATA

Mbps

f_DDRX2

f_SCLK

DDRX2 ECLK frequency

SCLK Frequency

—

140

70

—

117

59

—

97

49

MHz

3-26

DC and Switching Characteristics

MachXO2 Family Data Sheet

-3

-2

-1

Parameter

Description

Device

Min. Max. Min. Max. Min. Max. Units

Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered⁹

Output Data Valid Before CLK

Output

t_DVB

t_DVA

f_DATA

1.445

—

1.760

—

2.140

—

ns

Output Data Valid After CLK

Output

MachXO2-640U,

MachXO2-1200/U

and larger devices,

top side only

DDRX2 Serial Output Data

Speed

280

234

194

Mbps

DDRX2 ECLK Frequency

(minimum limited by PLL)

f_DDRX2

f_SCLK

—

140

70

—

117

59

—

97

49

MHz

SCLK Frequency

Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned⁹

Output Data Invalid After CLK

Output

t_DIA

—

0.270

420

—

0.300

352

—

0.330

292

ns

Output Data Invalid Before

CLK Output

MachXO2-640U,

MachXO2-1200/U

and larger devices,

top side only

t_DIB

DDRX4 Serial Output Data

Speed

f_DATA

Mbps

f_DDRX4

f_SCLK

DDRX4 ECLK Frequency

SCLK Frequency

—

210

53

—

176

44

—

146

37

MHz

Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered⁹

Output Data Valid Before CLK

Output

t_DVB

t_DVA

f_DATA

0.873

—

1.067

—

1.319

—

ns

Output Data Valid After CLK

Output

MachXO2-640U,

MachXO2-1200/U

and larger devices,

top side only

DDRX4 Serial Output Data

Speed

420

352

292

Mbps

DDRX4 ECLK Frequency

(minimum limited by PLL)

f_DDRX4

f_SCLK

—

210

53

—

176

44

—

146

37

MHz

SCLK Frequency

7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1⁹

Output Data Valid Before CLK

Output

t_DVB

—

0.240

—

0.270

—

0.300

ns

Output Data Valid After CLK

Output

t_DVA

MachXO2-640U,

MachXO2-1200/U

and larger devices,

top side only.

DDR71 Serial Output Data

Speed

f_DATA

—

420

210

—

352

176

—

292

146

Mbps

MHz

f_DDR71

DDR71 ECLK Frequency

7:1 Output Clock Frequency

(SCLK) (minimum limited by

PLL)

f_CLKOUT

—

60

—

50

—

42

MHz

3-27

DC and Switching Characteristics

MachXO2 Family Data Sheet

-3

-2

-1

Parameter

LPDDR⁹

Description

Device

Min. Max. Min. Max. Min. Max. Units

Input Data Valid After DQS

Input

t_DVADQ

t_DVEDQ

t_DQVBS

t_DQVAS

f_DATA

—

0.665

0.25

—

0.349

—

0.630

0.25

—

0.381

—

0.613

0.25

—

0.396

—

UI

Input Data Hold After DQS

Input

Output Data Invalid Before

DQS Output

—

UI

MachXO2-1200/U

and larger devices,

right side only.

Output Data Invalid After DQS

Output

—

UI

MEM LPDDR Serial Data

Speed

120

110

96

Mbps

f_SCLK

SCLK Frequency

—

0

60

—

0

55

—

0

48

96

MHz

f_LPDDR

DDR⁹

LPDDR Data Transfer Rate

120

110

Mbps

Input Data Valid After DQS

Input

t_DVADQ

t_DVEDQ

t_DQVBS

t_DQVAS

—

0.347

—

0.374

—

0.393

—

UI

Input Data Hold After DQS

Input

0.665

0.25

0.637

0.25

0.616

0.25

Output Data Invalid Before

DQS Output

MachXO2-1200/U

and larger devices,

—

Output Data Invalid After DQS right side only.

Output

—

f_DATA

MEM DDR Serial Data Speed

SCLK Frequency

—

140

70

—

116

58

—

98

49

98

Mbps

MHz

f_SCLK

f_{MEM_DDR}

DDR2⁹

MEM DDR Data Transfer Rate

N/A

140

N/A

116

N/A

Mbps

Input Data Valid After DQS

Input

t_DVADQ

t_DVEDQ

t_DQVBS

t_DQVAS

—

0.372

—

0.394

—

0.410

—

UI

Input Data Hold After DQS

Input

0.690

0.25

0.658

0.25

0.618

0.25

Output Data Invalid Before

DQS Output

—

MachXO2-1200/U

and larger devices,

right side only.

Output Data Invalid After DQS

Output

—

f_DATA

f_SCLK

MEM DDR Serial Data Speed

SCLK Frequency

—

140

70

—

116

58

—

98

49

Mbps

MHz

MEM DDR2 Data Transfer

Rate

f_{MEM_DDR2}

N/A

140

N/A

116

N/A

98

Mbps

1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14V. Other

operating conditions, including industrial, can be extracted from the Diamond software.

2. General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load.

3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).

4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.

5. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).

6. For Generic DDRX1 mode t_SU= t_HO= (t_DVE- t_DVA- 0.03ns)/2.

7. The t_{SU_DEL}and t_{H_DEL}values use the SCLK_ZERHOLD default step size. Each step is 167ps (-3), 182ps (-2), 195ps (-1).

8. This number for general purpose usage. Duty cycle tolerance is +/-10%.

9. Duty cycle is +/- 5% for system usage.

10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.

3-28

DC and Switching Characteristics

MachXO2 Family Data Sheet

Figure 3-5. Receiver RX.CLK.Aligned and MEM DDR Input Waveforms

RX CLK Input

or DQS Input

RX Data Input

or DQ Input

t

or t

RX.Aligned

DVA

DVADQ

DVE

DVEDQ

Figure 3-6. Receiver RX.CLK.Centered Waveforms

RX CLK Input

RX Data Input

RX.Centered

t

SU

HO

SU

HO

Figure 3-7. Transmitter TX.CLK.Aligned Waveforms

TX CLK Output

TX Data Output

TX.Aligned

t

DIA

DIB

DIA

DIB

Figure 3-8. Transmitter TX.CLK.Centered and MEM DDR Output Waveforms

TX CLK Output

or DQS Output

TX Data Output

or DQ Output

TX.Centered

t

or

t

or

t

or

t

or

DVA

DVB

DQVBS

DVA

DQVAS

DVB

DQVBS

t

DQVAS

3-29

DC and Switching Characteristics

MachXO2 Family Data Sheet

Figure 3-9. GDDR71 Video Timing Waveforms

756 Mbps

Clock In

125 MHz

Data Out

756 Mbps

Clock Out

125 MHz

Figure 3-10. Receiver GDDR71_RX. Waveforms

0

1

2

3

4

5

6

0

t_DVA

t_DVE

Figure 3-11. Transmitter GDDR71_TX. Waveforms

0

1

2

3

4

5

6

0

t_DIB

t_DIA

3-30

DC and Switching Characteristics

MachXO2 Family Data Sheet

sysCLOCK PLL Timing

Over Recommended Operating Conditions

Parameter

f_IN

Descriptions

Conditions

Min.

Max.

Units

Input Clock Frequency (CLKI, CLKFB)

7

400

MHz

Output Clock Frequency (CLKOP, CLKOS,

CLKOS2)

f_OUT

1.5625

0.0122

400

MHz

Output Frequency (CLKOS3 cascaded from

CLKOS2)

f_OUT2

f_VCO

f_PFD

PLL VCO Frequency

200

7

800

400

MHz

Phase Detector Input Frequency

AC Characteristics

t_DT

Output Clock Duty Cycle

Without duty trim selected³

f_OUT> 100MHz

45

-75

-6

55

75

%

7

t_{DT_TRIM}

Edge Duty Trim Accuracy

Output Phase Accuracy

4

t_PH

6

%

—

-120

0.9

—

0.5

—

1

150

0.007

180

0.009

160

0.011

230

0.12

230

0.12

120

—

ps p-p

UIPP

ps p-p

UIPP

ps p-p

UIPP

ps p-p

UIPP

ps p-p

UIPP

ps

Output Clock Period Jitter

f

_OUT< 100MHz

_OUT> 100MHz

Output Clock Cycle-to-cycle Jitter

Output Clock Phase Jitter

f_OUT< 100MHz

f

_PFD> 100MHz

_PFD< 100MHz

1, 8

t_OPJIT

f_OUT> 100MHz

_OUT< 100MHz

Output Clock Period Jitter (Fractional-N)

f

f_OUT> 100MHz

Output Clock Cycle-to-cycle Jitter 

(Fractional-N)

f_OUT< 100MHz

t_SPO

t_W

Static Phase Offset

Output Clock Pulse Width

PLL Lock-in Time

Divider ratio = integer

At 90% or 10%³

ns

2, 5

t_LOCK

15

ms

t_UNLOCK

PLL Unlock Time

50

ns

f_PFD 20 MHz

f_PFD< 20 MHz

90% to 90%

10% to 10%

1,000

0.02

—

ps p-p

UIPP

ns

6

t_IPJIT

Input Clock Period Jitter

t_HI

Input Clock High Time

t_LO

Input Clock Low Time

—

ns

5

t_STABLE

STANDBY High to PLL Stable

RST/RESETM Pulse Width

RST Recovery Time

15

ms

t_RST

—

ns

t_RSTREC

t_{RST_DIV}

t_{RSTREC_DIV}

1

—

ns

RESETC/D Pulse Width

RESETC/D Recovery Time

10

1

—

ns

—

ns

t_ROTATE-SETUPPHASESTEP Setup Time

10

—

ns

3-31

DC and Switching Characteristics

MachXO2 Family Data Sheet

sysCLOCK PLL Timing (Continued)

Over Recommended Operating Conditions

Parameter

Descriptions

Conditions

Min.

Max.

Units

t_{ROTATE_WD}

PHASESTEP Pulse Width

4

—

VCO Cycles

1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over

1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.

2. Output clock is valid after t_LOCKfor PLL reset and dynamic delay adjustment.

3. Using LVDS output buffers.

4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See TN1199, MachXO2 sysCLOCK PLL

Design and Usage Guide for more details.

5. At minimum f_PFD.As the f_PFDincreases the time will decrease to approximately 60% the value listed.

6. Maximum allowed jitter on an input clock. PLL unlock may occur if the input jitter exceeds this specification. Jitter on the input clock may be

transferred to the output clocks, resulting in jitter measurements outside the output specifications listed in this table.

7. Edge Duty Trim Accuracy is a percentage of the setting value. Settings available are 70 ps, 140 ps, and 280 ps in addition to the default

value of none.

8. Jitter values measured with the internal oscillator operating. The jitter values will increase with loading of the PLD fabric and in the presence

of SSO noise.

3-32

DC and Switching Characteristics

MachXO2 Family Data Sheet

MachXO2 Oscillator Output Frequency

Symbol

Parameter

Min.

Typ.

Max

Units

Oscillator Output Frequency (Commercial Grade Devices, 

0 to 85°C)

125.685

133

140.315

MHz

f_MAX

Oscillator Output Frequency (Industrial Grade Devices, 

-40 to 100°C)

124.355

133

141.645

MHz

t_DT

Output Clock Duty Cycle

43

50

57

0.02

0.1

%

UIPP

µs

1

t_OPJIT

Output Clock Period Jitter

STDBY Low to Oscillator Stable

0.01

0.012

0.05

t_STABLEOSC

1. Output Clock Period Jitter specified at 133MHz. The values for lower frequencies will be smaller UIPP. The typical value for 133MHz is 95ps

and for 2.08MHz the typical value is 1.54ns.

MachXO2 Standby Mode Timing – ZE Devices

Symbol

Parameter

Device

Min.

Typ.

—

Max

Units

ns

t_PWRDN

USERSTDBY High to Stop

All

—

13

LCMXO2-256

LCMXO2-640

LCMXO2-1200

LCMXO2-2000

LCMXO2-4000

LCMXO2-7000

All

µs

20

50

µs

t_PWRUP

USERSTDBY Low to Power Up

µs

t_WSTDBY

USERSTDBY Pulse Width

19

—

ns

t_BNDGAPSTBL

USERSTDBY High to Bandgap Stable

All

15

ns

MachXO2 Standby Mode Timing – HC/HE Devices

Symbol

Parameter

Device

Min.

Typ.

Max

Units

ns

t_PWRDN

USERSTDBY High to Stop

All

—

9

LCMXO2-256

LCMXO2-640

LCMXO2-640U

LCMXO2-1200

LCMXO2-1200U

LCMXO2-2000

LCMXO2-2000U

LCMXO2-4000

LCMXO2-7000

All

µs

20

50

µs

t_PWRUP

USERSTDBY Low to Power Up

USERSTDBY Pulse Width

µs

t_WSTDBY

18

—

ns

USERSTDBY Mode

BG, POR

t_PWRUP

t_PWRDN

USERSTDBY

t_WSTDBY

3-33

DC and Switching Characteristics

MachXO2 Family Data Sheet

Flash Download Time^{1, 2}

Symbol

Parameter

Device

LCMXO2-256

LCMXO2-640

LCMXO2-640U

LCMXO2-1200

LCMXO2-1200U

LCMXO2-2000

LCMXO2-2000U

LCMXO2-4000

LCMXO2-7000

Typ.

0.6

1.0

1.9

1.4

2.4

3.8

Units

ms

t_REFRESH

POR to Device I/O Active

1. Assumes sysMEM EBR initialized to an all zero pattern if they are used.

2. The Flash download time is measured starting from the maximum voltage of POR trip point.

JTAG Port Timing Specifications

Symbol

Parameter

Min.

—

20

10

8

Max.

25

—

Units

MHz

ns

f_MAX

TCK clock frequency

t_BTCPH

t_BTCPL

t_BTS

TCK [BSCAN] clock pulse width high

TCK [BSCAN] clock pulse width low

—

ns

TCK [BSCAN] setup time

—

ns

t_BTH

TCK [BSCAN] hold time

—

ns

t_BTCO

TAP controller falling edge of clock to valid output

TAP controller falling edge of clock to valid disable

TAP controller falling edge of clock to valid enable

BSCAN test capture register setup time

—

8

10

—

ns

t_BTCODIS

t_BTCOEN

t_BTCRS

ns

t_BTCRH

BSCAN test capture register hold time

20

—

ns

t_BUTCO

BSCAN test update register, falling edge of clock to valid output

BSCAN test update register, falling edge of clock to valid disable

BSCAN test update register, falling edge of clock to valid enable

25

ns

t_BTUODIS

t_BTUPOEN

ns

3-34

DC and Switching Characteristics

MachXO2 Family Data Sheet

Figure 3-12. JTAG Port Timing Waveforms

TMS

TDI

t

BTH

BTS

t

BTCP

BTCPL

BTCPH

TCK

TDO

t

BTCODIS

t

BTCO

BTCOEN

Valid Data

t

BTCRH

t

BTCRS

Data to be

captured

from I/O

Data Captured

t

BTUPOEN

BUTCO

BTUODIS

Data to be

driven out

to I/O

Valid Data

3-35

DC and Switching Characteristics

MachXO2 Family Data Sheet

sysCONFIG Port Timing Specifications

Symbol

All Configuration Modes

t_PRGM

Parameter

Min.

Max.

Units

PROGRAMN low pulse accept

PROGRAMN low pulse rejection

INITN low time

55

—

25

ns

us

ns

t_PRGMJ

t_INITL

55

t_DPPINIT

t_DPPDONE

t_IODISS

Slave SPI

f_MAX

PROGRAMN low to INITN low

PROGRAMN low to DONE low

PROGRAMN low to I/O disable

70

80

120

CCLK clock frequency

—

7.5

2

66

—

10

—

MHz

ns

t_CCLKH

t_CCLKL

CCLK clock pulse width high

CCLK clock pulse width low

CCLK setup time

t_STSU

t_STH

CCLK hold time

0

t_STCO

CCLK falling edge to valid output

CCLK falling edge to valid disable

CCLK falling edge to valid enable

Chip select high time

—

25

3

t_STOZ

t_STOV

t_SCS

t_SCSS

Chip select setup time

t_SCSH

Chip select hold time

3

Master SPI

f_MAX

MCLK clock frequency

MCLK clock pulse width high

MCLK clock pulse width low

MCLK setup time

—

3.75

5

133

—

MHz

ns

t_MCLKH

t_MCLKL

—

ns

t_STSU

—

ns

t_STH

MCLK hold time

1

—

ns

t_CSSPI

INITN high to chip select low

INITN high to first MCLK edge

100

0.75

200

1

ns

t_MCLK

us

I²C Port Timing Specifications^{1, 2}

Symbol

Parameter

Min.

Max.

Units

f_MAX

Maximum SCL clock frequency

—

400

KHz

1. MachXO2 supports the following modes:

• Standard-mode (Sm), with a bit rate up to 100 kbit/s (user and configuration mode)

• Fast-mode (Fm), with a bit rate up to 400 kbit/s (user and configuration mode)

2. Refer to the I²C specification for timing requirements.

SPI Port Timing Specifications¹

Symbol

Parameter

Min.

Max.

Units

f_MAX

Maximum SCK clock frequency

—

45

MHz

1. Applies to user mode only. For configuration mode timing specifications, refer to sysCONFIG Port Timing Specifications

table in this data sheet.

3-36

DC and Switching Characteristics

MachXO2 Family Data Sheet

Switching Test Conditions

Figure 3-13 shows the output test load used for AC testing. The specific values for resistance, capacitance, volt-

age, and other test conditions are shown in Table 3-5.

Figure 3-13. Output Test Load, LVTTL and LVCMOS Standards

V_T

R1

DUT

Test Point

CL

Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

R1

CL

Timing Ref.

LVTTL, LVCMOS 3.3 = 1.5V

LVCMOS 2.5 = V_CCIO/2

LVCMOS 1.8 = V_CCIO/2

LVCMOS 1.5 = V_CCIO/2

LVCMOS 1.2 = V_CCIO/2

1.5

VT

—

LVTTL and LVCMOS settings (L -> H, H -> L)



0pF

—

LVTTL and LVCMOS 3.3 (Z -> H)

LVTTL and LVCMOS 3.3 (Z -> L)

Other LVCMOS (Z -> H)

V_OL

V_OH

V_OL

V_OH

V_OL

V_OH

1.5

V_CCIO/2

188

0pF

Other LVCMOS (Z -> L)

V_CCIO/2

LVTTL + LVCMOS (H -> Z)

LVTTL + LVCMOS (L -> Z)

V_OH- 0.15

V_OL- 0.15

Note: Output test conditions for all other interfaces are determined by the respective standards.

3-37

MachXO2 Family Data Sheet

Pinout Information

January 3013

Data Sheet DS1035

Signal Descriptions

Signal Name

I/O

Descriptions

General Purpose

[Edge] indicates the edge of the device on which the pad is located. Valid edge designations

are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PFU row or the column of the device on which the PIO

Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When

Edge is L (Left) or R (Right), only need to specify Column Number.

[A/B/C/D] indicates the PIO within the group to which the pad is connected.

P[Edge] [Row/Column

Number]_[A/B/C/D]

Some of these user-programmable pins are shared with special function pins. When not used

as special function pins, these pins can be programmed as I/Os for user logic.

I/O

During configuration of the user-programmable I/Os, the user has an option to tri-state the 

I/Os and enable an internal pull-up, pull-down or buskeeper resistor. This option also applies

to unused pins (or those not bonded to a package pin). The default during configuration is for

user-programmable I/Os to be tri-stated with an internal pull-down resistor enabled. When the

device is erased, I/Os will be tri-stated with an internal pull-down resistor enabled. Some pins,

such as PROGRAMN and JTAG pins, default to tri-stated I/Os with pull-up resistors enabled

when the device is erased.

NC

—

No connect.

GND

GND – Ground. Dedicated pins. It is recommended that all GNDs are tied together.

V

_CC– The power supply pins for core logic. Dedicated pins. It is recommended that all VCCs

VCC

—

are tied to the same supply.

VCCIO – The power supply pins for I/O Bank x. Dedicated pins. It is recommended that all

VCCIOs located in the same bank are tied to the same supply.

VCCIOx

PLL and Clock Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)

Reference Clock (PLL) input pads: [LOC] indicates location. Valid designations are L (Left

PLL) and R (Right PLL). T = true and C = complement.

[LOC]_GPLL[T, C]_IN

—

Optional Feedback (PLL) input pads: [LOC] indicates location. Valid designations are L (Left

PLL) and R (Right PLL). T = true and C = complement.

[LOC]_GPLL[T, C]_FB

PCLK [n]_[2:0]

—

Primary Clock pads. One to three clock pads per side.

Test and Programming (Dual function pins used for test access port and during sysCONFIG™)

TMS

TCK

TDI

I

Test Mode Select input pin, used to control the 1149.1 state machine.

Test Clock input pin, used to clock the 1149.1 state machine.

I

Test Data input pin, used to load data into the device using an 1149.1 state machine.

Output pin – Test Data output pin used to shift data out of the device using 1149.1.

TDO

O

Optionally controls behavior of TDI, TDO, TMS, TCK. If the device is configured to use the

JTAG pins (TDI, TDO, TMS, TCK) as general purpose I/O, then:

If JTAGENB is low: TDI, TDO, TMS and TCK can function a general purpose I/O.

If JTAGENB is high: TDI, TDO, TMS and TCK function as JTAG pins.

JTAGENB

I

For more details, refer to TN1204, MachXO2 Programming and Configuration Usage Guide.

Configuration (Dual function pins used during sysCONFIG)

PROGRAMN

I

Initiates configuration sequence when asserted low. This pin always has an active pull-up.

Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up

is enabled.

INITN

I/O

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

4-1

DS1035 Pinout Information_01.7

Pinout Information

MachXO2 Family Data Sheet

Signal Name

I/O

Descriptions

General Purpose

Open Drain pin. Indicates that the configuration sequence is complete, and the start-up

sequence is in progress.

DONE

I/O

Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration

Clock for configuring an FPGA in SPI and SPIm configuration modes.

MCLK/CCLK

I/O

I

SN

Slave SPI active low chip select input.

CSSPIN

SI/SISPI

SO/SPISO

SCL

I/O Master SPI active low chip select output.

I/O Slave SPI serial data input and master SPI serial data output.

I/O Slave SPI serial data output and master SPI serial data input.

I/O Slave I²C clock input and master I²C clock output.

I/O Slave I²C data input and master I²C data output.

SDA

4-2

Pinout Information

MachXO2 Family Data Sheet

Pin Information Summary

MachXO2-256

MachXO2-640

MachXO2-640U

144 TQFP

32 QFN¹64 ucBGA 100 TQFP 132 csBGA 100 TQFP 132 csBGA

General Purpose I/O per Bank

Bank 0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

8

2

9

2

0

9

12

11

12

0

13

14

0

13

14

0

18

20

0

19

20

0

27

26

28

26

0

Total General Purpose Single Ended

I/O

21

44

55

78

79

107

Differential I/O per Bank

Bank 0

4

1

5

6

7

9

10

0

10

0

14

13

14

13

0

Bank 1

Bank 2

4

5

7

Bank 3

1

6

7

Bank 4

0

Bank 5

0

Total General Purpose Differential I/O

10

22

28

39

40

54

Dual Function I/O

High-speed Differential I/O

Bank 0

22

0

27

0

29

0

29

0

29

0

29

0

33

7

Gearboxes

Number of 7:1 or 8:1 Output Gearbox

Available (Bank 0)

0

7

Number of 7:1 or 8:1 Input Gearbox

Available (Bank 2)

DQS Groups

Bank 1

0

2

VCCIO Pins

Bank 0

2

1

2

1

0

2

0

2

0

2

0

2

0

2

0

3

0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

VCC

2

8

2

8

2

8

2

8

2

4

12

8

GND

10

32

99

NC

0

1

26

73

58

73

3

Total Count of Bonded Pins

31

62

96

135

1. Lattice recommends soldering the central thermal pad onto the top PCB ground for improved thermal resistance.

4-3

Pinout Information

MachXO2 Family Data Sheet

MachXO2-1200

100 TQFP 132 csBGA 144 TQFP

MachXO2-1200U

25 WLCSP

256 ftBGA

General Purpose I/O per Bank

Bank 0

18

21

20

0

25

26

28

25

0

27

26

28

26

0

11

0

50

52

Bank 1

Bank 2

7

52

Bank 3

0

16

Bank 4

0

16

Bank 5

0

20

Total General Purpose Single Ended I/O

79

104

107

18

206

Differential I/O per Bank

Bank 0

9

13

14

12

0

14

13

14

13

0

5

0

2

0

7

25

26

8

Bank 1

10

0

Bank 2

Bank 3

Bank 4

8

Bank 5

0

10

103

Total General Purpose Differential I/O

39

52

54

Dual Function I/O

High-speed Differential I/O

Bank 0

31

4

33

7

33

7

18

0

33

14

Gearboxes

Number of 7:1 or 8:1 Output Gearbox Available

(Bank 0)

4

5

7

0

14

Number of 7:1 or 8:1 Input Gearbox Available

(Bank 2)

DQS Groups

Bank 1

1

2

0

2

VCCIO Pins

Bank 0

2

3

0

3

0

3

0

1

0

1

0

4

1

2

1

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

VCC

2

8

4

10

1

4

12

8

2

8

24

1

GND

NC

1

0

Total Count of Bonded Pins

98

130

135

24

254

4-4

Pinout Information

MachXO2 Family Data Sheet

MachXO2-2000

MachXO2-2000U

100

TQFP

132

csBGA

144

TQFP

256

caBGA

256

ftBGA

484 ftBGA

General Purpose I/O per Bank

Bank 0

18

21

20

6

25

26

28

7

27

28

8

50

52

50

52

70

68

Bank 1

Bank 2

52

72

Bank 3

16

24

Bank 4

6

8

10

111

16

Bank 5

8

10

104

20

28

Total General Purpose Single-Ended I/O

79

206

278

Differential I/O per Bank

Bank 0

9

10

3

13

14

3

14

4

25

26

8

25

26

8

35

34

36

12

8

Bank 1

Bank 2

Bank 3

Bank 4

3

4

5

8

Bank 5

4

5

10

103

10

103

14

139

Total General Purpose Differential I/O

39

52

56

Dual Function I/O

High-speed Differential I/O

Bank 0

31

4

33

8

33

9

33

14

33

14

37

18

Gearboxes

Number of 7:1 or 8:1 Output Gearbox

Available (Bank 0)

4

8

9

14

18

Number of 7:1 or 8:1 Input Gearbox

Available (Bank 2)

10

14

DQS Groups

Bank 1

1

2

VCCIO Pins

Bank 0

2

1

3

1

3

1

4

1

2

1

4

1

2

1

10

3

Bank 1

Bank 2

Bank 3

Bank 4

4

Bank 5

3

VCC

2

8

4

10

1

4

12

4

8

24

1

8

24

1

12

48

GND

NC

1

105

378

Total Count of Bonded Pins

98

130

139

254

4-5

Pinout Information

MachXO2 Family Data Sheet

MachXO2-4000

132

csBGA

144

TQFP

184

csBGA

256

caBGA

256

ftBGA

332

caBGA

484

fpBGA

General Purpose I/O per Bank

Bank 0

25

26

28

7

27

29

9

37

50

52

50

52

68

70

68

Bank 1

Bank 2

39

52

70

72

Bank 3

10

16

24

Bank 4

8

10

114

12

16

Bank 5

10

104

15

20

28

Total General Purpose Single Ended I/O

150

206

274

278

Differential I/O per Bank

Bank 0

13

14

3

14

4

18

19

4

25

26

8

25

26

8

34

35

12

8

35

34

36

12

8

Bank 1

Bank 2

Bank 3

Bank 4

4

5

6

8

Bank 5

5

7

10

103

10

103

14

137

14

139

Total General Purpose Differential I/O

52

56

72

Dual Function I/O

High-speed Differential I/O

Bank 0

37

8

37

9

37

8

37

18

37

18

37

18

37

18

Gearboxes

Number of 7:1 or 8:1 Output Gearbox

Available (Bank 0)

8

9

18

Number of 7:1 or 8:1 Input Gearbox

Available (Bank 2)

14

12

DQS Groups

Bank 1

2

VCCIO Pins

Bank 0

3

1

3

1

3

1

4

1

2

1

4

1

2

1

4

2

1

2

10

3

Bank 1

Bank 2

Bank 3

Bank 4

4

Bank 5

3

VCC

4

10

1

4

12

1

4

16

1

8

24

1

8

24

1

8

27

5

12

48

GND

NC

105

378

Total Count of Bonded Pins

130

142

182

254

326

4-6

Pinout Information

MachXO2 Family Data Sheet

MachXO2-7000

144 TQFP

256 caBGA

256 ftBGA

332 caBGA

484 fpBGA

General Purpose I/O per Bank

Bank 0

27

29

9

50

52

50

52

68

70

82

84

Bank 1

Bank 2

52

70

84

Bank 3

16

24

28

Bank 4

10

114

16

24

Bank 5

20

30

32

Total General Purpose Single Ended I/O

206

278

334

Differential I/O per Bank

Bank 0

14

4

25

26

8

25

26

8

34

35

12

8

41

42

Bank 1

Bank 2

42

Bank 3

14

Bank 4

5

8

12

Bank 5

5

10

103

10

103

15

139

16

Total General Purpose Differential I/O

56

167

Dual Function I/O

High-speed Differential I/O

Bank 0

37

9

37

20

37

20

37

21

37

21

Gearboxes

Number of 7:1 or 8:1 Output Gearbox

Available (Bank 0)

9

20

21

Number of 7:1 or 8:1 Input Gearbox

Available (Bank 2)

14

DQS Groups

Bank 1

2

VCCIO Pins

Bank 0

3

1

4

1

2

1

4

1

2

1

4

2

1

2

10

3

Bank 1

Bank 2

Bank 3

Bank 4

4

Bank 5

3

VCC

4

12

1

8

24

1

8

24

1

8

27

1

12

48

GND

NC

49

Total Count of Bonded Pins

142

254

330

434

4-7

Pinout Information

MachXO2 Family Data Sheet

For Further Information

For further information regarding logic signal connections for various packages please refer to the MachXO2

Device Pinout Files.

Thermal Management

Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal

characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.

Users must complete a thermal analysis of their specific design to ensure that the device and package do not

exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package

specific thermal values.

For Further Information

For further information regarding Thermal Management, refer to the following:

• Thermal Management document

• TN1198, Power Estimation and Management for MachXO2 Devices

• The Power Calculator tool is included with the Lattice design tools, or as a standalone download from

www.latticesemi.com/software

4-8

MachXO2 Family Data Sheet

Ordering Information

January 2013

Data Sheet DS1035

MachXO2 Part Number Description

LCMXO2 – XXXX X X X – X XXXXXX X XX XX

Device Family

Device Status

MachXO2 PLD

Blank = Production Device

ES = Engineering Sample

R1 = Production Release 1 Device

50 = WLCSP package, 50 parts per reel

Logic Capacity

256 = 256 LUTs

640 = 640 LUTs

1200 = 1280 LUTs

2000 = 2112 LUTs

4000 = 4320 LUTs

7000 = 6864 LUTs

Shipping Method

Blank = Trays

TR = Tape and Reel

Grade

C = Commercial

I = Industrial

I/O Count

Blank = Standard Device

U = Ultra High I/O Device

Package

Power/ Performance

Z = Low Power

UWG25 = 25-Ball Halogen-Free WLCSP

(0.4 mm Pitch)

H = High Performance

SG32 = 32-Pin Halogen-Free QFN

(0.5 mm Pitch)

UMG64 = 64-Ball Halogen-Free ucBGA

(0.4 mm Pitch)

TG100 = 100-Pin Halogen-Free TQFP

TG144 = 144-Pin Halogen-Free TQFP

MG132 = 132-Ball Halogen-Free csBGA

(0.5 mm Pitch)

SupplyVoltage

C = 2.5V/3.3V

E = 1.2V

Speed

1 = Slowest

Low Power

2

MG184 = 184-Ball Halogen-Free csBGA

(0.5mm Pitch)

3 = Fastest

BG256 = 256-Ball Halogen-Free caBGA

(0.8 mm Pitch)

4 = Slowest

5

High Performance

FTG256= 256-Ball Halogen-Free ftBGA

(1.0 mm Pitch)

6 = Fastest

BG332 = 332-Ball Halogen-Free caBGA

FG484 = 484-Ball Halogen-Free fpBGA

(1.0 mm Pitch)

Ordering Information

MachXO2 devices have top-side markings, for commercial and industrial grades, as shown below:

LCMXO2

256ZE

1UG64C

Datecode

LCMXO2-1200ZE

1TG100C

Datecode

Notes:

1. Markings are abbreviated for small packages.

2. See PCN 05A-12 for information regarding a change to the top-side mark logo.

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

5-1

DS1035 Order Info_01.9

Ordering Information

MachXO2 Family Data Sheet

Ultra Low Power Commercial Grade Devices, Halogen Free (RoHS) Packaging

Part Number

LUTs

256

Supply Voltage

1.2V

Grade

-1

Package

Leads

32

Temp.

COM

LCMXO2-256ZE-1SG32C

LCMXO2-256ZE-2SG32C

LCMXO2-256ZE-3SG32C

LCMXO2-256ZE-1UMG64C

LCMXO2-256ZE-2UMG64C

LCMXO2-256ZE-3UMG64C

LCMXO2-256ZE-1TG100C

LCMXO2-256ZE-2TG100C

LCMXO2-256ZE-3TG100C

LCMXO2-256ZE-1MG132C

LCMXO2-256ZE-2MG132C

LCMXO2-256ZE-3MG132C

Halogen-Free QFN

Halogen-Free ucBGA

Halogen-Free TQFP

Halogen-Free csBGA

1.2V

-2

32

1.2V

-3

32

1.2V

-1

64

1.2V

-2

64

1.2V

-3

64

1.2V

-1

100

132

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

Part Number

LUTs

640

Supply Voltage

1.2V

Grade

-1

Package

Leads

100

Temp.

COM

LCMXO2-640ZE-1TG100C

LCMXO2-640ZE-2TG100C

LCMXO2-640ZE-3TG100C

LCMXO2-640ZE-1MG132C

LCMXO2-640ZE-2MG132C

LCMXO2-640ZE-3MG132C

Halogen-Free TQFP

Halogen-Free csBGA

1.2V

-2

100

1.2V

-3

100

1.2V

-1

132

1.2V

-2

132

1.2V

-3

132

Part Number

LUTs

1280

Supply Voltage

1.2V

Grade

-1

Package

Leads

100

132

144

Temp.

COM

LCMXO2-1200ZE-1TG100C

LCMXO2-1200ZE-2TG100C

LCMXO2-1200ZE-3TG100C

LCMXO2-1200ZE-1MG132C

LCMXO2-1200ZE-2MG132C

LCMXO2-1200ZE-3MG132C

LCMXO2-1200ZE-1TG144C

LCMXO2-1200ZE-2TG144C

LCMXO2-1200ZE-3TG144C

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

5-2

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

2112

Supply Voltage

1.2V

Grade

-1

Package

Leads

100

132

144

256

Temp.

COM

LCMXO2-2000ZE-1TG100C

LCMXO2-2000ZE-2TG100C

LCMXO2-2000ZE-3TG100C

LCMXO2-2000ZE-1MG132C

LCMXO2-2000ZE-2MG132C

LCMXO2-2000ZE-3MG132C

LCMXO2-2000ZE-1TG144C

LCMXO2-2000ZE-2TG144C

LCMXO2-2000ZE-3TG144C

LCMXO2-2000ZE-1BG256C

LCMXO2-2000ZE-2BG256C

LCMXO2-2000ZE-3BG256C

LCMXO2-2000ZE-1FTG256C

LCMXO2-2000ZE-2FTG256C

LCMXO2-2000ZE-3FTG256C

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

Part Number

LUTs

4320

Supply Voltage

1.2V

Grade

-1

Package

Leads

132

144

256

332

484

Temp.

COM

LCMXO2-4000ZE-1MG132C

LCMXO2-4000ZE-2MG132C

LCMXO2-4000ZE-3MG132C

LCMXO2-4000ZE-1TG144C

LCMXO2-4000ZE-2TG144C

LCMXO2-4000ZE-3TG144C

LCMXO2-4000ZE-1BG256C

LCMXO2-4000ZE-2BG256C

LCMXO2-4000ZE-3BG256C

LCMXO2-4000ZE-1FTG256C

LCMXO2-4000ZE-2FTG256C

LCMXO2-4000ZE-3FTG256C

LCMXO2-4000ZE-1BG332C

LCMXO2-4000ZE-2BG332C

LCMXO2-4000ZE-3BG332C

LCMXO2-4000ZE-1FG484C

LCMXO2-4000ZE-2FG484C

LCMXO2-4000ZE-3FG484C

Halogen-Free csBGA

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

5-3

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

6864

Supply Voltage

1.2V

Grade

-1

Package

Leads

144

256

332

484

Temp.

COM

LCMXO2-7000ZE-1TG144C

LCMXO2-7000ZE-2TG144C

LCMXO2-7000ZE-3TG144C

LCMXO2-7000ZE-1BG256C

LCMXO2-7000ZE-2BG256C

LCMXO2-7000ZE-3BG256C

LCMXO2-7000ZE-1FTG256C

LCMXO2-7000ZE-2FTG256C

LCMXO2-7000ZE-3FTG256C

LCMXO2-7000ZE-1BG332C

LCMXO2-7000ZE-2BG332C

LCMXO2-7000ZE-3BG332C

LCMXO2-7000ZE-1FG484C

LCMXO2-7000ZE-2FG484C

LCMXO2-7000ZE-3FG484C

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

Part Number

LUTs

1280

Supply Voltage

1.2V

Grade

-1

Package

Leads

100

132

144

Temp.

COM

LCMXO2-1200ZE-1TG100CR1¹

LCMXO2-1200ZE-2TG100CR1¹

LCMXO2-1200ZE-3TG100CR1¹

LCMXO2-1200ZE-1MG132CR1¹

LCMXO2-1200ZE-2MG132CR1¹

LCMXO2-1200ZE-3MG132CR1¹

LCMXO2-1200ZE-1TG144CR1¹

LCMXO2-1200ZE-2TG144CR1¹

LCMXO2-1200ZE-3TG144CR1¹

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1. Specifications for the “LCMXO2-1200ZE-speed package CR1” are the same as the “LCMXO2-1200ZE-speed package C” devices respec-

tively, except as specified in the R1 Device Specifications section on page 5-18 of this data sheet.

High-Performance Commercial Grade Devices with Voltage Regulator, Halogen Free

(RoHS) Packaging

Part Number

LUTs

256

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

32

Temp.

COM

LCMXO2-256HC-4SG32C

LCMXO2-256HC-5SG32C

LCMXO2-256HC-6SG32C

LCMXO2-256HC-4UMG64C

LCMXO2-256HC-5UMG64C

LCMXO2-256HC-6UMG64C

LCMXO2-256HC-4TG100C

LCMXO2-256HC-5TG100C

LCMXO2-256HC-6TG100C

LCMXO2-256HC-4MG132C

LCMXO2-256HC-5MG132C

LCMXO2-256HC-6MG132C

Halogen-Free QFN

Halogen-Free ucBGA

Halogen-Free TQFP

Halogen-Free csBGA

-5

32

-6

32

-4

64

-5

64

-6

64

-4

100

132

-5

-6

-4

-5

-6

5-4

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

640

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

100

Temp.

COM

LCMXO2-640HC-4TG100C

LCMXO2-640HC-5TG100C

LCMXO2-640HC-6TG100C

LCMXO2-640HC-4MG132C

LCMXO2-640HC-5MG132C

LCMXO2-640HC-6MG132C

Halogen-Free TQFP

Halogen-Free csBGA

-5

100

-6

100

-4

132

-5

132

-6

132

Part Number

LUTs

640

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

144

Temp.

COM

LCMXO2-640UHC-4TG144C

LCMXO2-640UHC-5TG144C

LCMXO2-640UHC-6TG144C

Halogen-Free TQFP

640

2.5V/3.3V

-5

144

640

2.5V/3.3V

-6

144

Part Number

LUTs

1280

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

100

132

144

Temp.

COM

LCMXO2-1200HC-4TG100C

LCMXO2-1200HC-5TG100C

LCMXO2-1200HC-6TG100C

LCMXO2-1200HC-4MG132C

LCMXO2-1200HC-5MG132C

LCMXO2-1200HC-6MG132C

LCMXO2-1200HC-4TG144C

LCMXO2-1200HC-5TG144C

LCMXO2-1200HC-6TG144C

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

-5

-6

-4

-5

-6

-4

-5

-6

Part Number

LUTs

1280

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

256

Temp.

COM

LCMXO2-1200UHC-4FTG256C

LCMXO2-1200UHC-5FTG256C

LCMXO2-1200UHC-6FTG256C

Halogen-Free ftBGA

2.5V/3.3V

-5

256

2.5V/3.3V

-6

256

5-5

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

2112

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

100

132

144

256

Temp.

COM

LCMXO2-2000HC-4TG100C

LCMXO2-2000HC-5TG100C

LCMXO2-2000HC-6TG100C

LCMXO2-2000HC-4MG132C

LCMXO2-2000HC-5MG132C

LCMXO2-2000HC-6MG132C

LCMXO2-2000HC-4TG144C

LCMXO2-2000HC-5TG144C

LCMXO2-2000HC-6TG144C

LCMXO2-2000HC-4BG256C

LCMXO2-2000HC-5BG256C

LCMXO2-2000HC-6BG256C

LCMXO2-2000HC-4FTG256C

LCMXO2-2000HC-5FTG256C

LCMXO2-2000HC-6FTG256C

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

Part Number

LUTs

2112

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

484

Temp.

COM

LCMXO2-2000UHC-4FG484C

LCMXO2-2000UHC-5FG484C

LCMXO2-2000UHC-6FG484C

Halogen-Free fpBGA

2.5V/3.3V

-5

484

2.5V/3.3V

-6

484

Part Number

LUTs

4320

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

132

144

256

332

484

Temp.

COM

LCMXO2-4000HC-4MG132C

LCMXO2-4000HC-5MG132C

LCMXO2-4000HC-6MG132C

LCMXO2-4000HC-4TG144C

LCMXO2-4000HC-5TG144C

LCMXO2-4000HC-6TG144C

LCMXO2-4000HC-4BG256C

LCMXO2-4000HC-5BG256C

LCMXO2-4000HC-6BG256C

LCMXO2-4000HC-4FTG256C

LCMXO2-4000HC-5FTG256C

LCMXO2-4000HC-6FTG256C

LCMXO2-4000HC-4BG332C

LCMXO2-4000HC-5BG332C

LCMXO2-4000HC-6BG332C

LCMXO2-4000HC-4FG484C

LCMXO2-4000HC-5FG484C

LCMXO2-4000HC-6FG484C

Halogen-Free csBGA

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

5-6

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

6864

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

144

256

332

484

Temp.

COM

LCMXO2-7000HC-4TG144C

LCMXO2-7000HC-5TG144C

LCMXO2-7000HC-6TG144C

LCMXO2-7000HC-4BG256C

LCMXO2-7000HC-5BG256C

LCMXO2-7000HC-6BG256C

LCMXO2-7000HC-4FTG256C

LCMXO2-7000HC-5FTG256C

LCMXO2-7000HC-6FTG256C

LCMXO2-7000HC-4BG332C

LCMXO2-7000HC-5BG332C

LCMXO2-7000HC-6BG332C

LCMXO2-7000HC-4FG484C

LCMXO2-7000HC-5FG484C

LCMXO2-7000HC-6FG484C

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

Part Number

LUTs

1280

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

100

132

144

Temp.

COM

LCMXO2-1200HC-4TG100CR1¹

LCMXO2-1200HC-5TG100CR1¹

LCMXO2-1200HC-6TG100CR1¹

LCMXO2-1200HC-4MG132CR1¹

LCMXO2-1200HC-5MG132CR1¹

LCMXO2-1200HC-6MG132CR1¹

LCMXO2-1200HC-4TG144CR1¹

LCMXO2-1200HC-5TG144CR1¹

LCMXO2-1200HC-6TG144CR1¹

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

-5

-6

-4

-5

-6

-4

-5

-6

1. Specifications for the “LCMXO2-1200HC-speed package CR1” are the same as the “LCMXO2-1200HC-speed package C” devices respec-

tively, except as specified in the R1 Device Specifications section on page 5-18 of this data sheet.

5-7

Ordering Information

MachXO2 Family Data Sheet

High-Performance Commercial Grade Devices without Voltage Regulator, Halogen Free

(RoHS) Packaging

Part Number

LUTs

2112

Supply Voltage

1.2V

Grade

-4

Package

Leads

100

144

132

256

Temp.

COM

LCMXO2-2000HE-4TG100C

LCMXO2-2000HE-5TG100C

LCMXO2-2000HE-6TG100C

LCMXO2-2000HE-4TG144C

LCMXO2-2000HE-5TG144C

LCMXO2-2000HE-6TG144C

LCMXO2-2000HE-4MG132C

LCMXO2-2000HE-5MG132C

LCMXO2-2000HE-6MG132C

LCMXO2-2000HE-4BG256C

LCMXO2-2000HE-5BG256C

LCMXO2-2000HE-6BG256C

LCMXO2-2000HE-4FTG256C

LCMXO2-2000HE-5FTG256C

LCMXO2-2000HE-6FTG256C

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free caBGA

Halogen-Free ftBGA

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

Part Number

LUTs

2112

Supply Voltage

Grade

-4

Package

Leads

484

Temp.

COM

LCMXO2-2000UHE-4FG484C

LCMXO2-2000UHE-5FG484C

LCMXO2-2000UHE-6FG484C

1.2V

Halogen-Free fpBGA

-5

484

-6

484

Part Number

LUTs

4320

Supply Voltage

1.2V

Grade

-4

Package

Leads

144

132

256

184

256

332

Temp.

COM

LCMXO2-4000HE-4TG144C

LCMXO2-4000HE-5TG144C

LCMXO2-4000HE-6TG144C

LCMXO2-4000HE-4MG132C

LCMXO2-4000HE-5MG132C

LCMXO2-4000HE-6MG132C

LCMXO2-4000HE-4BG256C

LCMXO2-4000HE-4MG184C

LCMXO2-4000HE-5MG184C

LCMXO2-4000HE-6MG184C

LCMXO2-4000HE-5BG256C

LCMXO2-4000HE-6BG256C

LCMXO2-4000HE-4FTG256C

LCMXO2-4000HE-5FTG256C

LCMXO2-4000HE-6FTG256C

LCMXO2-4000HE-4BG332C

LCMXO2-4000HE-5BG332C

LCMXO2-4000HE-6BG332C

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free caBGA

Halogen-Free csBGA

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

5-8

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

4320

Supply Voltage

Grade

-4

Package

Leads

484

Temp.

COM

LCMXO2-4000HE-4FG484C

LCMXO2-4000HE-5FG484C

LCMXO2-4000HE-6FG484C

1.2V

Halogen-Free fpBGA

-5

484

-6

484

Part Number

LUTs

6864

Supply Voltage

1.2V

Grade

-4

Package

Leads

144

256

332

484

Temp.

COM

LCMXO2-7000HE-4TG144C

LCMXO2-7000HE-5TG144C

LCMXO2-7000HE-6TG144C

LCMXO2-7000HE-4BG256C

LCMXO2-7000HE-5BG256C

LCMXO2-7000HE-6BG256C

LCMXO2-7000HE-4FTG256C

LCMXO2-7000HE-5FTG256C

LCMXO2-7000HE-6FTG256C

LCMXO2-7000HE-4BG332C

LCMXO2-7000HE-5BG332C

LCMXO2-7000HE-6BG332C

LCMXO2-7000HE-4FG484C

LCMXO2-7000HE-5FG484C

LCMXO2-7000HE-6FG484C

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging

Part Number

LUTs

256

Supply Voltage

1.2V

Grade

-1

Package

Leads

32

Temp.

IND

LCMXO2-256ZE-1SG32I

LCMXO2-256ZE-2SG32I

LCMXO2-256ZE-3SG32I

LCMXO2-256ZE-1UMG64I

LCMXO2-256ZE-2UMG64I

LCMXO2-256ZE-3UMG64I

LCMXO2-256ZE-1TG100I

LCMXO2-256ZE-2TG100I

LCMXO2-256ZE-3TG100I

LCMXO2-256ZE-1MG132I

LCMXO2-256ZE-2MG132I

LCMXO2-256ZE-3MG132I

Halogen-Free QFN

Halogen-Free ucBGA

Halogen-Free TQFP

Halogen-Free csBGA

1.2V

-2

32

1.2V

-3

32

1.2V

-1

64

1.2V

-2

64

1.2V

-3

64

1.2V

-1

100

132

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

Part Number

LCMXO2-640ZE-1TG100I

LCMXO2-640ZE-2TG100I

LCMXO2-640ZE-3TG100I

LCMXO2-640ZE-1MG132I

LUTs

640

Supply Voltage

Grade

-1

Package

Leads

100

Temp.

IND

1.2V

Halogen-Free TQFP

Halogen-Free csBGA

-2

100

IND

-3

100

IND

-1

132

IND

5-9

Ordering Information

MachXO2 Family Data Sheet

Part Number

LCMXO2-640ZE-2MG132I

LCMXO2-640ZE-3MG132I

LUTs

640

Supply Voltage

1.2V

Grade

-2

Package

Leads

132

Temp.

IND

Halogen-Free csBGA

640

1.2V

-3

132

IND

Part Number

LUTs

4320

Supply Voltage

Grade

-4

Package

Leads

184

Temp.

IND

LCMXO2-4000HE-4MG184I

LCMXO2-4000HE-5MG184I

LCMXO2-4000HE-6MG184I

1.2V

Halogen-Free csBGA

Halogen-Free caBGA

-5

184

IND

-6

184

IND

5-10

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

1280

Supply Voltage

1.2V

Grade

-1

Package

Leads

25

Temp.

IND

LCMXO2-1200ZE-1UWG25ITR¹

LCMXO2-1200ZE-1UWG25ITR50²

LCMXO2-1200ZE-1TG100I

LCMXO2-1200ZE-2TG100I

LCMXO2-1200ZE-3TG100I

LCMXO2-1200ZE-1MG132I

LCMXO2-1200ZE-2MG132I

LCMXO2-1200ZE-3MG132I

LCMXO2-1200ZE-1TG144I

LCMXO2-1200ZE-2TG144I

LCMXO2-1200ZE-3TG144I

Halogen-Free WLCSP

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

1.2V

-1

25

1.2V

-1

100

132

144

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1. This part number has a tape and reel quantity of 5,000 units with a minimum order quantity of 10,000 units. Order quantities must be in

increments of 10,000 units. For example, a 10,000 unit order will be shipped in two reels with one reel containing 5,000 units and the other

reel with less than 5,000 units (depending on test yields). Unserviced backlog will be canceled.

2. This part number has a tape and reel quantity of 50 units with a minimum order quantity of 50. Order quantities must be in increments of 50

units. For example, a 1000 unit order will be shipped as 20 reels of 50 units each.

Part Number

LUTs

2112

Supply Voltage

1.2V

Grade

-1

Package

Leads

100

132

144

256

Temp.

IND

LCMXO2-2000ZE-1TG100I

LCMXO2-2000ZE-2TG100I

LCMXO2-2000ZE-3TG100I

LCMXO2-2000ZE-1MG132I

LCMXO2-2000ZE-2MG132I

LCMXO2-2000ZE-3MG132I

LCMXO2-2000ZE-1TG144I

LCMXO2-2000ZE-2TG144I

LCMXO2-2000ZE-3TG144I

LCMXO2-2000ZE-1BG256I

LCMXO2-2000ZE-2BG256I

LCMXO2-2000ZE-3BG256I

LCMXO2-2000ZE-1FTG256I

LCMXO2-2000ZE-2FTG256I

LCMXO2-2000ZE-3FTG256I

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1. Samples can be ordered in minimum order quantities and increments of 50 units. Production volumes can be ordered in minimum order

quantities and increments of 10,000 units for the LCMXO2-1200ZE in the 25-ball WLCSP package.

5-11

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

4320

Supply Voltage

1.2V

Grade

-1

Package

Leads

132

144

256

332

484

Temp.

IND

LCMXO2-4000ZE-1MG132I

LCMXO2-4000ZE-2MG132I

LCMXO2-4000ZE-3MG132I

LCMXO2-4000ZE-1TG144I

LCMXO2-4000ZE-2TG144I

LCMXO2-4000ZE-3TG144I

LCMXO2-4000ZE-1BG256I

LCMXO2-4000ZE-2BG256I

LCMXO2-4000ZE-3BG256I

LCMXO2-4000ZE-1FTG256I

LCMXO2-4000ZE-2FTG256I

LCMXO2-4000ZE-3FTG256I

LCMXO2-4000ZE-1BG332I

LCMXO2-4000ZE-2BG332I

LCMXO2-4000ZE-3BG332I

LCMXO2-4000ZE-1FG484I

LCMXO2-4000ZE-2FG484I

LCMXO2-4000ZE-3FG484I

Halogen-Free csBGA

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

Part Number

LUTs

6864

Supply Voltage

1.2V

Grade

-1

Package

Leads

144

256

332

484

Temp.

IND

LCMXO2-7000ZE-1TG144I

LCMXO2-7000ZE-2TG144I

LCMXO2-7000ZE-3TG144I

LCMXO2-7000ZE-1BG256I

LCMXO2-7000ZE-2BG256I

LCMXO2-7000ZE-3BG256I

LCMXO2-7000ZE-1FTG256I

LCMXO2-7000ZE-2FTG256I

LCMXO2-7000ZE-3FTG256I

LCMXO2-7000ZE-1BG332I

LCMXO2-7000ZE-2BG332I

LCMXO2-7000ZE-3BG332I

LCMXO2-7000ZE-1FG484I

LCMXO2-7000ZE-2FG484I

LCMXO2-7000ZE-3FG484I

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

5-12

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

1280

Supply Voltage

1.2V

Grade

-1

Package

Leads

100

132

144

Temp.

IND

LCMXO2-1200ZE-1TG100IR1¹

LCMXO2-1200ZE-2TG100IR1¹

LCMXO2-1200ZE-3TG100IR1¹

LCMXO2-1200ZE-1MG132IR1¹

LCMXO2-1200ZE-2MG132IR1¹

LCMXO2-1200ZE-3MG132IR1¹

LCMXO2-1200ZE-1TG144IR1¹

LCMXO2-1200ZE-2TG144IR1¹

LCMXO2-1200ZE-3TG144IR1¹

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1.2V

-1

1.2V

-2

1.2V

-3

1. Specifications for the “LCMXO2-1200ZE-speed package IR1” are the same as the “LCMXO2-1200ZE-speed package I” devices respec-

tively, except as specified in the R1 Device Specifications section on page 5-18 of this data sheet.

High-Performance Industrial Grade Devices with Voltage Regulator, Halogen Free (RoHS)

Packaging

Part Number

LUTs

256

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

32

Temp.

IND

LCMXO2-256HC-4SG32I

LCMXO2-256HC-5SG32I

LCMXO2-256HC-6SG32I

LCMXO2-256HC-4UMG64I

LCMXO2-256HC-5UMG64I

LCMXO2-256HC-6UMG64I

LCMXO2-256HC-4TG100I

LCMXO2-256HC-5TG100I

LCMXO2-256HC-6TG100I

LCMXO2-256HC-4MG132I

LCMXO2-256HC-5MG132I

LCMXO2-256HC-6MG132I

Halogen-Free QFN

Halogen-Free ucBGA

Halogen-Free TQFP

Halogen-Free csBGA

-5

32

-6

32

-4

64

-5

64

-6

64

-4

100

132

-5

-6

-4

-5

-6

Part Number

LUTs

640

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

100

Temp.

IND

LCMXO2-640HC-4TG100I

LCMXO2-640HC-5TG100I

LCMXO2-640HC-6TG100I

LCMXO2-640HC-4MG132I

LCMXO2-640HC-5MG132I

LCMXO2-640HC-6MG132I

Halogen-Free TQFP

Halogen-Free csBGA

-5

100

-6

100

-4

132

-5

132

-6

132

Part Number

LUTs

640

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

144

Temp.

IND

LCMXO2-640UHC-4TG144I

LCMXO2-640UHC-5TG144I

LCMXO2-640UHC-6TG144I

Halogen-Free TQFP

640

2.5V/3.3V

-5

144

IND

640

2.5V/3.3V

-6

144

IND

5-13

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

1280

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

100

132

144

Temp.

IND

LCMXO2-1200HC-4TG100I

LCMXO2-1200HC-5TG100I

LCMXO2-1200HC-6TG100I

LCMXO2-1200HC-4MG132I

LCMXO2-1200HC-5MG132I

LCMXO2-1200HC-6MG132I

LCMXO2-1200HC-4TG144I

LCMXO2-1200HC-5TG144I

LCMXO2-1200HC-6TG144I

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

-5

-6

-4

-5

-6

-4

-5

-6

Part Number

LUTs

1280

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

256

Temp.

IND

LCMXO2-1200UHC-4FTG256I

LCMXO2-1200UHC-5FTG256I

LCMXO2-1200UHC-6FTG256I

Halogen-Free ftBGA

2.5V/3.3V

-5

256

IND

2.5V/3.3V

-6

256

IND

Part Number

LUTs

2112

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

100

132

144

256

Temp.

IND

LCMXO2-2000HC-4TG100I

LCMXO2-2000HC-5TG100I

LCMXO2-2000HC-6TG100I

LCMXO2-2000HC-4MG132I

LCMXO2-2000HC-5MG132I

LCMXO2-2000HC-6MG132I

LCMXO2-2000HC-4TG144I

LCMXO2-2000HC-5TG144I

LCMXO2-2000HC-6TG144I

LCMXO2-2000HC-4BG256I

LCMXO2-2000HC-5BG256I

LCMXO2-2000HC-6BG256I

LCMXO2-2000HC-4FTG256I

LCMXO2-2000HC-5FTG256I

LCMXO2-2000HC-6FTG256I

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

Part Number

LUTs

2112

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

484

Temp.

IND

LCMXO2-2000UHC-4FG484I

LCMXO2-2000UHC-5FG484I

LCMXO2-2000UHC-6FG484I

Halogen-Free fpBGA

2.5V/3.3V

-5

484

IND

2.5V/3.3V

-6

484

IND

5-14

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

4320

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

144

132

256

332

484

Temp.

IND

LCMXO2-4000HC-4TG144I

LCMXO2-4000HC-5TG144I

LCMXO2-4000HC-6TG144I

LCMXO2-4000HC-4MG132I

LCMXO2-4000HC-5MG132I

LCMXO2-4000HC-6MG132I

LCMXO2-4000HC-4BG256I

LCMXO2-4000HC-5BG256I

LCMXO2-4000HC-6BG256I

LCMXO2-4000HC-4FTG256I

LCMXO2-4000HC-5FTG256I

LCMXO2-4000HC-6FTG256I

LCMXO2-4000HC-4BG332I

LCMXO2-4000HC-5BG332I

LCMXO2-4000HC-6BG332I

LCMXO2-4000HC-4FG484I

LCMXO2-4000HC-5FG484I

LCMXO2-4000HC-6FG484I

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

Part Number

LUTs

6864

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

144

256

332

484

Temp.

IND

LCMXO2-7000HC-4TG144I

LCMXO2-7000HC-5TG144I

LCMXO2-7000HC-6TG144I

LCMXO2-7000HC-4BG256I

LCMXO2-7000HC-5BG256I

LCMXO2-7000HC-6BG256I

LCMXO2-7000HC-4FTG256I

LCMXO2-7000HC-5FTG256I

LCMXO2-7000HC-6FTG256I

LCMXO2-7000HC-4BG332I

LCMXO2-7000HC-5BG332I

LCMXO2-7000HC-6BG332I

LCMXO2-7000HC-4FG484I

LCMXO2-7000HC-5FG484I

LCMXO2-7000HC-6FG484I

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

-4

-5

-6

5-15

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

1280

Supply Voltage

2.5V/3.3V

Grade

-4

Package

Leads

100

132

144

Temp.

IND

LCMXO2-1200HC-4TG100IR1¹

LCMXO2-1200HC-5TG100IR1¹

LCMXO2-1200HC-6TG100IR1¹

LCMXO2-1200HC-4MG132IR1¹

LCMXO2-1200HC-5MG132IR1¹

LCMXO2-1200HC-6MG132IR1¹

LCMXO2-1200HC-4TG144IR1¹

LCMXO2-1200HC-5TG144IR1¹

LCMXO2-1200HC-6TG144IR1¹

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

-5

-6

-4

-5

-6

-4

-5

-6

1. Specifications for the “LCMXO2-1200HC-speed package IR1” are the same as the “LCMXO2-1200ZE-speed package I” devices respec-

tively, except as specified in the R1 Device Specifications section on page 5-18 of this data sheet.

High Performance Industrial Grade Devices Without Voltage Regulator, Halogen Free

(RoHS) Packaging

Part Number

LUTs

2112

Supply Voltage

1.2V

Grade

-4

Package

Leads

100

132

144

256

Temp.

IND

LCMXO2-2000HE-4TG100I

LCMXO2-2000HE-5TG100I

LCMXO2-2000HE-6TG100I

LCMXO2-2000HE-4MG132I

LCMXO2-2000HE-5MG132I

LCMXO2-2000HE-6MG132I

LCMXO2-2000HE-4TG144I

LCMXO2-2000HE-5TG144I

LCMXO2-2000HE-6TG144I

LCMXO2-2000HE-4BG256I

LCMXO2-2000HE-5BG256I

LCMXO2-2000HE-6BG256I

LCMXO2-2000HE-4FTG256I

LCMXO2-2000HE-5FTG256I

LCMXO2-2000HE-6FTG256I

Halogen-Free TQFP

Halogen-Free csBGA

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

Part Number

LUTs

2112

Supply Voltage

Grade

-4

Package

Leads

484

Temp.

IND

LCMXO2-2000UHE-4FG484I

LCMXO2-2000UHE-5FG484I

LCMXO2-2000UHE-6FG484I

1.2V

Halogen-Free fpBGA

-5

484

IND

-6

484

IND

5-16

Ordering Information

MachXO2 Family Data Sheet

Part Number

LUTs

4320

Supply Voltage

1.2V

Grade

-4

Package

Leads

132

144

256

332

484

Temp.

IND

LCMXO2-4000HE-4MG132I

LCMXO2-4000HE-5MG132I

LCMXO2-4000HE-6MG132I

LCMXO2-4000HE-4TG144I

LCMXO2-4000HE-5TG144I

LCMXO2-4000HE-6TG144I

LCMXO2-4000HE-4BG256I

LCMXO2-4000HE-5BG256I

LCMXO2-4000HE-6BG256I

LCMXO2-4000HE-4FTG256I

LCMXO2-4000HE-5FTG256I

LCMXO2-4000HE-6FTG256I

LCMXO2-4000HE-4BG332I

LCMXO2-4000HE-5BG332I

LCMXO2-4000HE-6BG332I

LCMXO2-4000HE-4FG484I

LCMXO2-4000HE-5FG484I

LCMXO2-4000HE-6FG484I

Halogen-Free csBGA

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

Part Number

LUTs

6864

Supply Voltage

1.2V

Grade

-4

Package

Leads

144

256

332

484

Temp.

IND

LCMXO2-7000HE-4TG144I

LCMXO2-7000HE-5TG144I

LCMXO2-7000HE-6TG144I

LCMXO2-7000HE-4BG256I

LCMXO2-7000HE-5BG256I

LCMXO2-7000HE-6BG256I

LCMXO2-7000HE-4FTG256I

LCMXO2-7000HE-5FTG256I

LCMXO2-7000HE-6FTG256I

LCMXO2-7000HE-4BG332I

LCMXO2-7000HE-5BG332I

LCMXO2-7000HE-6BG332I

LCMXO2-7000HE-4FG484I

LCMXO2-7000HE-5FG484I

LCMXO2-7000HE-6FG484I

Halogen-Free TQFP

Halogen-Free caBGA

Halogen-Free ftBGA

Halogen-Free caBGA

Halogen-Free fpBGA

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

1.2V

-4

1.2V

-5

1.2V

-6

5-17

Ordering Information

MachXO2 Family Data Sheet

R1 Device Specifications

The LCMXO2-1200ZE/HC “R1” devices have the same specifications as their Standard (non-R1) counterparts

except as listed below. For more details on the R1 to Standard migration refer to AN8086, Designing for Migration

from MachXO2-1200-R1 to Standard Non-R1) Devices.

• The User Flash Memory (UFM) cannot be programmed through the internal WISHBONE interface. It can still be

programmed through the JTAG/SPI/I²C ports.

• The on-chip differential input termination resistor value is higher than intended. It is approximately 200 as

opposed to the intended 100. It is recommended to use external termination resistors for differential inputs. The

on-chip termination resistors can be disabled through Lattice design software.

• Soft Error Detection logic may not produce the correct result when it is run for the first time after configuration. To

use this feature, discard the result from the first operation. Subsequent operations will produce the correct result.

• Under certain conditions, IIH exceeds data sheet specifications. The following table provides more details:

Pad Rising

IIH Max.

Pad Falling

IIH Min.

Steady State Pad Steady State Pad

Condition

VPAD > VCCIO

VPAD = VCCIO

VPAD < VCCIO

Clamp

OFF

ON

High IIH

Low IIL

10µA

1mA

10µA

1mA

10µA

-1mA

-10µA

-1mA

-10µA

1mA

10µA

1mA

OFF

10µA

• The user SPI interface does not operate correctly in some situations. During master read access and slave write

access, the last byte received does not generate the RRDY interrupt.

• In GDDRX2, GDDRX4 and GDDR71 modes, ECLKSYNC may have a glitch in the output under certain condi-

tions, leading to possible loss of synchronization.

• When using the hard I²C IP core, the I²C status registers I2C_1_SR and I2C_2_SR may not update correctly.

• PLL Lock signal will glitch high when coming out of standby. This glitch lasts for about 10µsec before returning

low.

• Dual boot only available on HC devices, requires tying VCC and VCCIO2 to the same 3.3V or 2.5V supply.

5-18

MachXO2 Family Data Sheet

Supplemental Information

Data Sheet DS1035

April 2012

For Further Information

A variety of technical notes for the MachXO2 family are available on the Lattice web site.

• TN1198, Power Estimation and Management for MachXO2 Devices

• TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide

• TN1201, Memory Usage Guide for MachXO2 Devices

• TN1202, MachXO2 sysIO Usage Guide

• TN1203, Implementing High-Speed Interfaces with MachXO2 Devices

• TN1204, MachXO2 Programming and Configuration Usage Guide

• TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices

• TN1206, MachXO2 SRAM CRC Error Detection Usage Guide

• TN1207, Using TraceID in MachXO2 Devices

• TN1074, PCB Layout Recommendations for BGA Packages

• TN1087, Minimizing System Interruption During Configuration Using TransFR Technology

• AN8086, Designing for Migration from MachXO2-1200-R1 to Standard (non-R1) Devices

• AN8066, Boundary Scan Testability with Lattice sysIO Capability

• MachXO2 Device Pinout Files

• Thermal Management document

• Lattice design tools

For further information on interface standards, refer to the following web sites:

• JEDEC Standards (LVTTL, LVCMOS, LVDS, DDR, DDR2, LPDDR): www.jedec.org

• PCI: www.pcisig.com

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

6-1

DS1035 Further Info_01.3

MachXO2 Family Data Sheet

Revision History

Data Sheet DS1035

January 2013

Date

Version

01.0

Section

—

Change Summary

November 2010

January 2011

Initial release.

01.1

All

Included ultra-high I/O devices.

DC and Switching

Characteristics

Recommended Operating Conditions table – Added footnote 3.

DC Electrical Characteristics table – Updated data for I_IL, I_IH. V_HYSTtyp-

ical values updated.

Generic DDRX2 Outputs with Clock and Data Aligned at Pin

(GDDRX2_TX.ECLK.Aligned) Using PCLK Pin for Clock Input tables –

Updated data for T_DIAand T_DIB.

Generic DDRX4 Outputs with Clock and Data Aligned at Pin

(GDDRX4_TX.ECLK.Aligned) Using PCLK Pin for Clock Input tables –

Updated data for T_DIAand T_DIB.

Power-On-Reset Voltage Levels table - clarified note 3.

Clarified VCCIO related recommended operating conditions specifica-

tions.

Added power supply ramp rate requirements.

Added Power Supply Ramp Rates table.

Updated Programming/Erase Specifications table.

Removed references to V_CCP.

Pinout Information

Included number of 7:1 and 8:1 gearboxes (input and output) in the pin

information summary tables.

Removed references to V_CCP.

April 2011

01.2

—

Data sheet status changed from Advance to Preliminary.

Updated MachXO2 Family Selection Guide table.

Updated Supported Input Standards table.

Updated sysMEM Memory Primitives diagram.

Added differential SSTL and HSTL IO standards.

Introduction

Architecture

DC and Switching

Characteristics

Updates following parameters: POR voltage levels, DC electrical char-

acteristics, static supply current for ZE/HE/HC devices, static power

consumption contribution of different components – ZE devices, pro-

gramming and erase Flash supply current.

Added VREF specifications to sysIO recommended operating condi-

tions.

Updating timing information based on characterization.

Added differential SSTL and HSTL IO standards.

Ordering Information Added Ordering Part Numbers for R1 devices, and devices in WLCSP

packages.

Added R1 device specifications.

May 2011

01.3

Multiple

Replaced “SED” with “SRAM CRC Error Detection” throughout the doc-

ument.

DC and Switching

Characteristics

Added footnote 1 to Program Erase Specifications table.

Pinout Information

Updated Pin Information Summary tables.

Signal name SO/SISPISO changed to SO/SPISO in the Signal Descrip-

tions table.

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

7-1

DS1035 Revision History

Revision History

MachXO2 Family Data Sheet

Date

Version

Section

Change Summary

August 2011

01.4

Architecture

Updated information in Clock/Control Distribution Network and sys-

CLOCK Phase Locked Loops (PLLs).

DC and Switching

Characteristics

Updated I_ILand I_IHconditions in the DC Electrical Characteristics table.

Pinout Information

Included number of 7:1 and 8:1 gearboxes (input and output) in the pin

information summary tables.

Updated Pin Information Summary table: Dual Function I/O, DQS

Groups Bank 1, Total General Purpose Single-Ended I/O, Differential 

I/O Per Bank, Total Count of Bonded Pins, Gearboxes.

Added column of data for MachXO2-2000 49 WLCSP.

Ordering Information Updated R1 Device Specifications text section with information on

migration from MachXO2-1200-R1 to Standard (non-R1) devices.

Corrected Supply Voltage typo for part numbers: LCMX02-2000UHE-

4FG484I, LCMX02-2000UHE-5FG484I, LCMX02-2000UHE-6FG484I.

Added footnote for WLCSP package parts.

Supplemental

Information

Removed reference to Stand-alone Power Calculator for MachXO2

Devices. Added reference to AN8086, Designing for Migration from

MachXO2-1200-R1 to Standard (non-R1) Devices.

August 2011

01.5

01.6

DC and Switching

Characteristics

Updated ESD information.

Ordering Information Updated footnote for ordering WLCSP devices.

February 2012

—

Data sheet status changed from preliminary to final.

Introduction

MachXO2 Family Selection Guide table – Removed references to 

49-ball WLCSP.

DC and Switching

Characteristics

Updated Flash Download Time table.

Modified Storage Temperature in the Absolute Maximum Ratings sec-

tion.

Updated I_DKmax in Hot Socket Specifications table.

Modified Static Supply Current tables for ZE and HC/HE devices.

Updated Power Supply Ramp Rates table.

Updated Programming and Erase Supply Current tables.

Updated data in the External Switching Characteristics table.

Corrected Absolute Maximum Ratings for Dedicated Input Voltage

Applied for LCMXO2 HC.

DC Electrical Characteristics table – Minor corrections to conditions for

I_IL, I_IH.

Pinout Information

Removed references to 49-ball WLCSP.

Signal Descriptions table – Updated description for GND, VCC, and

VCCIOx.

Updated Pin Information Summary table – Number of VCCIOs, GNDs,

VCCs, and Total Count of Bonded Pins for MachXO2-256, 640, and

640U and Dual Function I/O for MachXO2-4000 332caBGA.

Ordering Information Removed references to 49-ball WLCSP

February 2012

March 2012

01.7

01.8

All

Updated document with new corporate logo.

Introduction

Added 32 QFN packaging information to Features bullets and MachXO2

Family Selection Guide table.

DC and Switching

Characteristics

Changed ‘STANDBY’ to ‘USERSTDBY’ in Standby Mode timing dia-

gram.

Pinout Information

Removed footnote from Pin Information Summary tables.

7-2

Revision History

MachXO2 Family Data Sheet

Date

Version

Section

Change Summary

Added 32 QFN package to Pin Information Summary table.

March 2012

(cont.)

01.8

(cont.)

Pinout Information

(cont.)

Ordering Information Updated Part Number Description and Ordering Information tables for

32 QFN package.

Updated topside mark diagram in the Ordering Information section.

April 2012

01.9

Architecture

Removed references to TN1200.

Ordering Information Updated the Device Status portion of the MachXO2 Part Number

Description to include the 50 parts per reel for the WLCSP package.

Added new part number and footnote 2 for LCMXO2-1200ZE-

1UWG25ITR50.

Updated footnote 1 for LCMXO2-1200ZE-1UWG25ITR.

Supplemental

Information

Removed references to TN1200.

January 2013

02.0

Introduction

Architecture

Updated the total number IOs to include JTAGENB.

Supported Output Standards table – Added 3.3 V_CCIO(Typ.) to LVDS

row.

Changed SRAM CRC Error Detection to Soft Error Detection.

DC and Switching

Characteristics

Power Supply Ramp Rates table – Updated Units column for t_RAMP

symbol.

Added new Maximum sysIO Buffer Performance table.

sysCLOCK PLL Timing table – Updated Min. column values for f_IN, f_OUT

,

f

_OUT2and f_PFDparameters. Added t_SPOparameter. Updated footnote 6.

MachXO2 Oscillator Output Frequency table – Updated symbol name

for t_STABLEOSC.

DC Electrical Characteristics table – Updated conditions for I_IL,I_IHsym-

bols.

Corrected parameters tDQVBS and tDQVAS

Corrected MachXO2 ZE parameters tDVADQ and tDVEDQ

Included the MachXO2-4000HE 184 csBGA package.

Pinout Information

Ordering Information Updated part number.

7-3


型号：	DS1035
厂家：	LATTICE SEMICONDUCTOR
描述：	MachXO2â¢ Family Data Sheet MachXO2a ？ ¢系列数据表石英晶振
文件：	总106页 (文件大小：7831K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS1035 [LATTICE]

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