ML12061EP [LANSDALE]
Crystal Oscillator; 晶体振荡器型号: | ML12061EP |
厂家: | LANSDALE SEMICONDUCTOR INC. |
描述: | Crystal Oscillator |
文件: | 总9页 (文件大小:1245K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ML12061
Crystal Oscillator
Legacy Device: Motorola MC12061
The ML12061 is for use with an external crystal to form a crys-
tal controlled oscillator. In addition to the fundamental series mode
crystal, two bypass capacitors are required (plus usual power sup-
ply pin bypass capacitors). Translators are provided internally for
MECL and TTL outputs.
• Frequency Range = 2.0 to 20 MHz
• Operating Temperature Range = 0 to + 70°C
• Single Supply Operation: +5.0 Vdc or –5.2 V DC
• Three Outputs Available:
16
1
1.Complementary Sine Wave (600 mVpp typ)
2.Complementary MECL
3.Single Ended TTL
P DIP 16 = EP
PLASTIC PACKAGE
CASE 648
Figure 1. Block Diagram
V
AGC
Filter
Bias
CROSS REFERENCE/ORDERING INFORMATION
CC
Sine Wave
Output
Bypass
MECL
Output
0.1
µ
F
PACKAGE
P DIP 16
MOTOROLA
MC112061P
LANSDALE
ML12061EP
0.1
µF
–
+
–
+
7
1 V
CC
4
3
2
14
15
16
V
13
12
11
V
CC
CC
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
MECL
Sine
to
10
to
Voltage
Reg.
Crystal
Osc.
Ampl./
AGC
TTL
Trans-
lator
MECL
TTL
Output
AGC
6
5
8
V
9
V
EE
EE
Crystal
Note: 0.1 µF power supply
pin bypass capacitors
not shown.
Page 1 of 9
www.lansdale.com
Issue A
ML12061
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS
Test Limits
+25°C
Typ
Pin
Under
Test
0°C
+75°C
Characteristic
Symbol
Unit
Min
Max
Min
Max
Min
Max
I
1
–
–
13
16
19
–
–
mAdc
Power Supply Drain Current
CC
1
11
16
–
–
–
–
–
–
18
–
13
23
3.0
16
28
4.0
19
–
–
–
–
–
–
Input Current
I
14
15
–
–
–
–
–
–
–
–
250
250
–
–
–
–
µAdc
µAdc
mAdc
Vdc
inH
I
14
15
–
–
–
–
–
–
–
–
1.0
1.0
–
–
–
–
inL
Differential Offset Voltage
Output Voltage Level
∆V
4 to 7
2 to 3
–
–
–
–
40
–200
–
0
325
+200
–
–
–
–
V
2
3
–
–
–
–
–
–
3.5
3.5
–
–
–
–
–
–
out
Logic ‘1’ Output Voltage
V
12
13
4.0
4.0
4.16
4.16
4.04
4.04
–
–
4.19
4.19
4.1
4.1
4.28
4.28
Vdc
OH1
(Note 1)
V
OH2
10
2.4
–
2.4
–
–
2.4
–
Logic ‘0’ Output Voltage
V
12
13
2.98
2.98
3.43
3.43
3.0
3.0
–
–
3.44
3.44
3.02
3.02
3.47
3.47
Vdc
OL1
(Note 1)
V
OL2
10
10
–
–
0.5
0.5
–
–
–
–
0.5
0.5
–
–
0.5
0.5
Logic ‘1’ Threshold Voltage
Logic ‘0’ Threshold Voltage
Output Short Circuit Current
V
12
13
3.98
3.98
–
–
4.02
4.02
–
–
–
–
4.08
4.08
–
–
Vdc
Vdc
OHA
V
12
13
–
–
3.45
3.45
–
–
–
–
3.46
3.46
–
–
3.49
3.49
OLA
I
10
20
60
20
–
60
20
60
mAdc
OS
NOTE: 1. Devices will meet standard MECL logic levels using V
= –5.2 Vdc and V = 0.
CC
EE
Page 2 of 9
www.lansdale.com
Issue A
ML12061
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE/CURRENT VALUES
Volts
@ Test Temperature
V
V
V
V
V
V
V
CCL
IHmax
4.16
ILmin
3.19
IHAmin
ILAmax
3.51
IHT
0°C
+25°C
+75°C
3.86
3.90
3.96
4.0
4.0
4.0
4.75
4.75
4.75
4.19
4.28
3.21
3.23
3.52
3.55
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic
Symbol
Gnd
V
ILmin
V
V
V
IHT
V
CCL
IHmax
IHAmin
ILAmax
Power Supply Drain Current
I
1
–
–
–
–
–
–
8
CC
1
11
16
–
14
–
–
15
–
–
–
–
–
–
–
–
–
–
–
–
–
8
8,9
8
Input Current
I
14
15
14
15
15
14
–
–
–
–
–
–
–
–
8
8
inH
I
14
15
15
14
–
–
–
–
–
–
–
–
–
–
8,14
8,15
inL
Differential Offset Voltage
Output Voltage Level
∆V
4 to 7
2 to 3
–
–
–
–
–
–
–
–
5,6
4
–
–
8
–
V
out
2
3
–
–
–
–
–
–
–
–
4
4
–
–
8
8
Logic ‘1’ Output Voltage
V
12
13
14
15
15
14
–
–
–
–
–
–
–
–
8
8
OH1
(Note 1)
V
OH2
10
15
14
–
–
–
11,16
8,9
Logic ‘0’ Output Voltage
V
12
13
15
14
14
15
–
–
–
–
–
–
–
–
8
8
OL1
(Note 1)
V
OL2
10
10
14
14
15
15
–
–
–
–
–
–
11,16
–
8,9
8,9
Logic ‘1’ Threshold Voltage
Logic ‘0’ Threshold Voltage
Output Short Circuit Current
V
12
13
–
–
–
–
14
15
15
14
–
–
–
–
8
8
OHA
V
12
13
–
–
–
–
15
14
14
15
–
–
–
–
8
8
OLA
I
10
15
14
–
–
–
11,16
8,9,10
OS
NOTE: 1. Devices will meet standard MECL logic levels using V
= –5.2 Vdc and V = 0.
CC
EE
Page 3 of 9
www.lansdale.com
Issue A
ML12061
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE/CURRENT VALUES
Volts mA
@ Test Temperature
V
CC
V
CCH
I
I
I
IL
OL
OH
0°C
+25°C
+75°C
5.0
5.0
5.0
5.25
5.25
5.25
16
–0.4
–0.4
–0.4
–2.5
–2.5
–2.5
16
16
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic
Symbol
Gnd
V
V
CCH
I
I
I
IL
CC
OL
OH
Power Supply Drain Current
I
1
1
–
–
–
–
8
CC
1
11
16
1
–
–
–
–
–
–
–
–
–
–
–
–
8
8,9
8
11,16
16
Input Current
I
14
15
16
16
–
–
–
–
–
–
–
–
8
8
inH
I
14
15
16
16
–
–
–
–
–
–
–
–
8,14
8,15
inL
Differential Offset Voltage
Output Voltage Level
∆V
4 to 7
2 to 3
1
–
–
–
–
–
–
–
–
–
8
–
V
out
2
3
1
1
–
–
–
–
–
–
–
–
8
8
Logic ‘1’ Output Voltage
V
12
13
16
16
–
–
–
–
–
–
12
13
8
8
OH1
(Note 1)
V
OH2
10
–
–
–
10
–
8,9
Logic ‘0’ Output Voltage
V
12
13
16
16
–
–
–
–
–
–
12
13
8
8
OL1
(Note 1)
V
OL2
10
10
–
–
–
10
10
–
–
–
–
8,9
8,9
11,16
Logic ‘1’ Threshold Voltage
Logic ‘0’ Threshold Voltage
Output Short Circuit Current
V
12
13
16
16
–
–
–
–
–
–
12
13
8
8
OHA
V
12
13
16
16
–
–
–
–
–
–
12
13
8
8
OLA
I
10
–
–
–
–
–
8,9,10
OS
NOTE: 1. Devices will meet standard MECL logic levels using V
= –5.2 Vdc and V = 0.
CC
EE
Page 4 of 9
www.lansdale.com
Issue A
ML12061
LANSDALE Semiconductor, Inc.
Figure 6. AC Characteristics – MECL and TTL Outputs
t +
t –
+200 mV
–200 mV
V
= + 2.0 Vdc
CC
80%
50%
0.1
µF
20%
Input (Pin 15)
t + +
t – –
t – –
16
11
450
15
13
50%
TTL Output
(Pin 10)
Pulse Generator
(EH 137 or Equiv)
PRF = 2.0 MHz
12
10
450
t + +
80%
t+ = t – = 2.0 0.2 ns
50%
MECL Output
(Pin 13)
14
1.2 k
20%
t –
t +
t –
t + –
80%
t – +
400
MECL Output
(Pin 12)
+ 2.0
8
9
50%
20%
Vdc
MMD6150
or Equiv
C
T
0.1
µF
t +
All input and output cables to the scope
C =15pF=totalparasiticcapacitancewhich
T
MMD7000
or Equiv
are equal lengths of 50 Ω coaxial cable.
includes probe, wiring, and load capaci-
tance.
Unused outputs are connected to a 50 Ω
1% resistor to ground.
V
= – 3.0 Vdc
EE
– 3.0 Vdc
TEST VOLTAGES/WAVEFORMS
APPLIED TO PINS LISTED BELOW:
Test Limits
Pin
0°C
+25°C
+75°C
Under
Test
Characteristic
Symbol
Min Max Min Typ Max Min Max Unit Pulse In Pulse Out +2.0 Vdc –3.0 Vdc Gnd
Propagation Delay
t
10
10
12
12
13
13
—
—
—
—
—
—
22
19
5.2
5.0
4.8
5.0
—
—
—
—
—
—
17 25
12 18
4.3 5.5
3.7 5.2
4.0 5.0
4.0 5.0
—
—
—
—
—
—
27 ns
18
15
10
10
12
12
13
13
11,16
8,9
14
15+10+
t
15–10–
15+12–
15–12+
15+13+
t
t
5.8
5.2
t
5.2
t
5.1
15–13–
Rise Time
Fall Time
t
t
12
13
—
—
4.0
4.0
—
—
3.0 4.0
3.0 4.0
—
—
4.4 ns
4.4 ns
15
15
12
13
11,16
11,16
8,9
8,9
14
14
12+
13+
t
t
12
13
—
—
4.0
4.0
—
—
3.0 4.0
3.0 4.0
—
—
4.0 ns
4.0 ns
15
15
12
13
11,16
11,16
8,9
8,9
14
14
12–
13–
TEST VOLTAGE APPLIED
TO PINS LISTED BELOW
Pin
Under
Test
+25°C
Characteristic
Sine Wave Amplitude
Min
Typ
Unit
+2.0 Vdc
–3.0 Vdc
2
3
650
650
750
750
mVp-p
1
8,9
Figure 7. AC Test Circuit – Sine Wave Output
0.1 µF
All output cables to the scope are equal lengths of 50 Ω coaxial
cable. All unused cables must be terminated with a 50 Ω 1%
resistor to ground.
V
= + 2.0 Vdc
CC
0.1 µF
0.1
450Ω resistor and the scopeterminationimpedanceconstitute
a 10:1 attenuator probe.
µF
1
4
450
450
3
2
Crystal — Reeves Hoffman Series Mode,
Series Resistance Minimum at Fundamental
f = 10 MHz
R
= 5 Ω
E
6
5
8
9
*R = 15 kΩ is inserted only for test purposes. When used
S
*R
S
V
= – 3.0 Vdc
with the above specified crystal, it guarantees oscillation
with any crystal which has an equivalent series
resistance
EE
R
p
0.1
µF
155 Ω
Crystal
R : will improve start up problems value: 200–500 Ω
p
Page 5 of 9
www.lansdale.com
Issue A
ML12061
LANSDALE Semiconductor, Inc.
The ML12061 consists of three basic sections: an oscillator
with AGC and two translators. Buffered complementary sine
wave outputs are available from the oscillator section. The
that the higher harmonic levels (greater than the fifth) are
increased when the MECL translator is being driven.
Typically, the MECL outputs (pins 12 and 13) will drive up
translators convert these sine wave outputs to levels compatible to five gates and the TTL output (pin10) will drive up to ten
with MECL and/or TTL.
gates.
Series mode crystals should be used with the oscillator. If it
is necessary or desirable to adjust the crystal frequency, a reac- Noise Characteristics
tive element can be inserted in series with the crystal — an
Noise level evaluation of the sine wave outputs operation at
inductor to lower the frequency or a capacitor to raise it. When or 9.0 MHz, indicates the following characteristics:
such an adjustment is necessary, it is recommended that the
crystal be specified slightly lower in frequency and a series
trimmer capacitor be added to bring the oscillator back on fre-
quency. As the oscillator frequency is changed from the natural
resonance of the crystal, more and more dependence is placed
on the external reactance, and temperature drift of the trim-
ming components then affects overall oscillator performance.
The ML12061 is designed to operate from a single supply —
either +5.0 Vdc or –5.2 Vdc. Although each translator has sep-
1. Noise floor (200 kHz from oscillator center frequency) is
approximately –122 dB when referenced to a 1.0 Hz
bandwidth. Noise floor is not sensitive to load conditions
and/or translator operation.
2. Close-in noise (100 Hz from oscillator center frequency)
is approximately –88 dB when referenced to a 1.0 Hz
bandwidth.
Figure 8. Frequency Variation Due to Temperature
arate V
and V supply pins, the circuit is NOT designed
CC
EE
+10
to operate from both voltage levels at the same time. The sepa-
V
= +5.0 Vdc
CC
rate V pin from the TTL translator helps minimize transient
EE
disturbance. If neither translator is being used, all unused pins
T
= 25°C
crystal
0
(9 thru 16) should be connected to V (pin 8). With the
EE
ML12061
translators not powered, supply current drain is typically
reduced from 42 mA to 23 mA for the ML12061.
–10
Frequency Stability
Output frequency of different oscillator circuits (of a given
device type number) will vary somewhat when used with a
given test setup. However, the variation should be within
approximately 0.001ꢀ from unit to unit. Frequency variations
with temperature (independent of the crystal, which is held at
25°C) are small — about –0.08ppm/°C for ML12061 operating
at 8.0 MHz.
–20
–30
ML12061
–55
–25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (
°)
A
Signal Characteristics
Figure 9. Driving Low Impedance Loads
The sine wave outputs at either pin 2 or pin 3 will typically
+5.0 V
range from 800 mV
(no load) to 500 mV
(120 ohm AC
p-p
p-p
load). Approximately 500 mV
can be provided across 50
0.1
µF
0.1 µF
p-p
ohms by slightly increasing the DC current in the output buffer
by the addition of an external resistor (680 ohms) from pin 2
or 3 to ground, as shown in Figure 9. Frequency drift is typi-
cally less than 0.0003ꢀ when going from a high-impedance
load (1 megohm, 15pF) to the 50 ohm load of Figure 9. The
0.1 µF
7
6
1
4
0.1 µF
2 or 3
DC voltage level at pin 2 or 3 is nominally 3.5 Vdc with V
= +5.0 Vdc.
CC
680
50
Harmonic distortion content in the sine wave outputs is crys-
tal as well as circuit dependent. The largest harmonic (third)
will usually be at least 15 dB down from the fundamental. The
harmonic content is approximately load independent except
5
8
* See text under signal characteristics.
Page 6 of 9
www.lansdale.com
Issue A
ML12061
LANSDALE Semiconductor, Inc.
Figure 10. MECL Translator Load Capability
Figure 11. TTL Translator Load Capability
V
= +5.0 V
CC
V
= +5.0 V
+5.0 V
CC
11
0.1
µF
16
0.1 µF
270
13
Sine
to
MECL
to
TTL
Trans-
lator
10
12
MECL
All
15 pF
15 pF
diodes
MBD101
or
1.5 k
8
8.2 k
Equiv
9
Figure 12. Noise Measurement Test Circuit
+5.0 V
0.1
µF
0.1 µF
ANALYZER SETTING
Video
Filter
Measurement
Noise Floor
Sweep
50 kHz/div
Close-In Noise 20 kHz/div
Bandwidth
10 kHz
10 Hz
0.1 µF
10 Hz
10 Hz
7
1
4
8
0.1 µF
2 or 3
To HP8552B/53B
Spectrum Analyzer
or Equiv
750
6
5
Page 7 of 9
www.lansdale.com
Issue A
ML12061
LANSDALE Semiconductor, Inc.
Figure 13. Circuit Schematic
RESISTOR
R1 (2 Places)
R2 (2 Places)
R3 (2 Places)
ML12061
200 Ω
400 Ω
2 kΩ
Page 8 of 9
www.lansdale.com
Issue A
ML12061
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 16 = EP
PLASTIC PACKAGE
(ML12061EP)
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
PLANE
–T–
G
H
J
K
L
M
S
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
M
T
A
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 9 of 9
www.lansdale.com
Issue A
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RCD
ML1206EL-R0825-FT101Q
Fixed Resistor, Metal Glaze/thick Film, 0.5W, 0.0825ohm, 1% +/-Tol, 100ppm/Cel, 1206,
RCD
ML1206EL-R0887-FB101W
Fixed Resistor, Metal Glaze/thick Film, 0.5W, 0.0887ohm, 1% +/-Tol, 100ppm/Cel, 1206,
RCD
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