M3100A-M01 [KEYSIGHT]
PXIe Digitizers with Optional Real-Time;
| 型号： | M3100A-M01 |
| 厂家： | 
Keysight Technologies |
| 描述： | PXIe Digitizers with Optional Real-Time |
| 文件： | 总9页 (文件大小：1033K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Keysight M3100A
PXIe Digitizers with Optional Real-Time
Sequencing and FPGA Programming
100 MSa/s, 14 Bits, 4/8 Channels
Data Sheet
02 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Improve Your Measurement Fidelity, Signal Integrity
and Measurement Throughput
The M3102A are high-performance, high-bandwidth digitizers with an advanced
data acquisition system (DAQ). Performance meets simplicity thanks to easy-to-
use programming libraries, real-time sequencing technology (HVI Hard Virtual
Instrumentation), and graphical FPGA programming technology.
Features
100 MSa/s simultaneous sampling, 14 bits, 4/8 channels, 100 MHz BW 1
Advanced data acquisition system (DAQ)
– Flexible triggering (HW trigger, HVI trigger, SW trigger)
– Programmable cycles and data bursts to avoid PC saturation
Optional HW programming for high-performance applications
– Real-time sequencing (HVI technology)
– FPGA programming
– Xilinx Kintex-7, 325T or 410T FPGA
Up to 2 GB of onboard RAM (~ 1 Gsamples)
Mechanical/interface
– 1 slot 3U (PXIe)
– Up to 1.6 GB/s transfer BW with P2P capabilities (PCIe Gen 2)
– Independent DMA channels for fast and efficient data transfer
Applications
General purpose digitizer
Hardware-in-the-loop (HIL)/automated test equipment (ATE)
R&D/scientific research equipment
Aerospace & defense (A/D)
1. 100 MHz refer to the Front End bandwidth. This digitizer can operate in 1st and 2nd Nyquist zones
(using undersampling technique), but its real-time BW is limited by Nyquist to some 50 MHz. As an
example for a band-limited signal of 70 MHz with a 10 MHz signal bandwidth the aliased component
will appear between 25 to 35 MHz (30 ± 5 MHz).
03 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Programming Technology and Software Tools
Software programming
– Easy-to-use native programming libraries for most common languages: C, C++, Visual
Studio, LabVIEW, MATLAB, Python, and more
Hardware programming (optional)
– Real-time sequencing (Hard Virtual Instrumentation or HVI technology)
– Graphical flowchart-style M3601A design environment (-HV1 option required on HW)
– Ultra-fast, fully-parallelized hard real-time execution
– Ultra-fast, time-deterministic decision-making
– Off-the-shelf inter-module synchronization & data exchange
– FPGA programming
– Graphical M3602A FPGA design environment (-FP1 option required on HW)
– No FPGA know-how required
– Include high-level to low-level design elements: off-the-shelf DSP blocks, MATLAB/
Simulink designs, Xilinx CORE Generator IP cores, Xilinx VIVADO/ISE projects, VHDL or
Verilog code
– Ultra-fast, one-click compiling and on-the-fly programming
No programming
– Ready-to-use SD1 SPF (software front panels)
PXIe Arbitrary Waveform Generators, Digitizers and Combination Modules
Outputs (AWGs)
Inputs (Digitizers)
Product
Type
Speed
Bits
Ch
BW
Speed
Bits
Ch
BW
(MSa/s)
(MHz)
(MSa/s)
(MHz)
M3202A
M3201A
M3102A
M3100A
M3302A
M3300A
AWG
1000
500
14
16
2/4
2/4
DC-400
DC-200
AWG
Digitizer
Digitizer
Combo
Combo
500
100
500
100
14
14
14
14
2/4 DC-200
4/8 DC-100
500
500
16
16
2
DC-200
DC-200
2
DC-200
2/4
4/8 DC-100
04 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Functional Block Diagram
Channel 1
Channel 1
output
Channel x
Input settings
Full scale, Z,
coupling (as
available)
Prescaler
÷
Data
acquisition
(DAQx)
Channel x
output
Analog
trigger
Channel n
Channel n
output
Figure 1. M3100A input functional block diagram, all channels have identical input structure
Ordering Information 1
Product
Description
M3100A
PXIe digitizer: 100 MSa/s, 14 Bits
Options
Description
M3100A-CH4 / -CH8
M3100A-CLF
Four channels 2 / eight channels
Fixed sampling clock, low jitter 2
M3100A-M01 / -M12 / -M20
HW programming options
M3100A-HVI
Memory 16 MB, 8 MSamples 2 / 128 MB, 60 MSamples / 2 GB, 1 GSamples
Description
Enabled HVI programming, requires an HVI design environment license (M3601A)
Enabled FPGA programming, requires -K32 or -K41 option and an FPGA design environment license (M3602A)
FPGA, Xilinx 7K325T / 7K410T, required for -FP1 option only (needs memory option -M20)
M3100A-FP1
M3100A-K32 / -K41
Related software
M3601A
Description
HVI design environment
FPGA design environment
M3602A
1. All options must be selected at time of purchase and are not upgradable
2. These options represent the standard configuration
05 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Technical Specifications and Characteristics
General characteristics
M3100A-CH4
M3100A-CH8
Parameter
Min Typ Max Min Typ Max Units
Comments
Inputs and outputs
Channels
4
1
1
1
8
8
1
1
1
8
Out
Reference clock 1
Reference clock 2
Triggers/markers 1, 3
Triggers/markers 2, 3
Input channels overview
Sampling rate
Out
In
In/out
In/out
Reconfigurable
Reconfigurable
100
14
100
14
MSa/s
Bits
Voltage resolution
Input frequency
DC
100 DC
<50
100 MHz
Real-time BW
50
50
MHz
ps
Time skew
<50
Between channels
Built-in functionalities
Input conditioning blocks
Analog trigger processors
Data acquisition blocks
Onboard memory
RAM memory
4
4
4
8
8
8
1 per channel
1 per channel
1 per channel
16
2048 16
2048 MBytes
1. At front panel
2. At backplane
3. Markers available from firmware version v3.0 or later
06 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
I/O specifications
Analog input characteristics
Number of channels
CH4 or CH8
Sampling rate
100 MSa/s option CLF
Configurable inputs: impedance
Configurable inputs: Coupling
Input voltage range (50Ω)
Input voltage range (HiZ)
Bandwidth limit filters
50Ω or 1 MΩ (HiZ)
AC or DC
400 mVpp to 6Vpp (continue: variable attenuator at input)
200 mVpp to 20Vpp (continue: variable attenuator at input)
100 MHz
Effective number of bits (ENOB)1
10.8 bits @30MHz (typical)
−142 dBm/Hz @30 MHz (typical)
67 dB @30 MHz (typical)
79 dBc (typical)
Noise floor
SINAD
Spurious free dynamic range (SFDR) + Total Harmonic Distorsion
1. measured at -1 DBFS input signal with 1.5 Vpp 50Ω
M3100A
Parameter
Min
Typ
Max
Units
Comments
Reference clock output
Frequency
10 or 100
MHz
mVpp
dBm
Ω
Generated from the internal clock. User selectable
Voltage
800
2
On a 50 Ω load
On a 50 Ω load
AC coupled
Power
Source impedance
50
External I/O trigger/marker
VIH
2
0
5
V
VIL
0.8
3.3
0.5
V
VOH
2.4
0
V
On a high Z load
On a high Z load
VOL
V
Input impedance
Source impedance
Speed
10
K Ω
–
TTL
500
Mbps
07 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Data acquisition blocks (DAQs) specifications
M3100A-CH4
Typ
M3100A-CH8
Typ
Parameter
Min
Max
Min
Max Units
Comments
General specifications
DAQs
4
5
8
5
1 per channel
Aggregated speed
Acquisition burst multiple
Acquisition RAM capacity
Acquisition RAM capacity effic.
Trigger
400
800 MSa/s
For all onboard DAQs combined
Samples Burst length must be a multiple of this value
957M Samples Maximum depends on onboard RAM
15
957M
15
93.5
93.5
%
Effic. = waveform size / waveform size in RAM
Selec.
Selec.
Hardware trigger (analog channels, input
trigger, backplane triggers), software trigger
DAQ specifications
Speed
100
100 MSa/s
Bits
Per DAQ
Resolution
14
14
Clock system specifications
M3100A-CH4
M3100A-CH8
Min Typ Max Units
Parameter
Min
Typ
Max
Comments
General specifications
Clock frequency
100
100
MHz
08 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
System Specifications
Environmental specifications (PXI Express)
M3100A-CH4
Typ
M3100A-CH8
Typ
Parameter
Min
Max
Min
Max Units
Comments
System bus
Slots
1
1
Slot
PXI Express (CompactPCI Express compatible)
Automatic gen negotiation, chassis dependent
Automatic lane negotiation, chassis dependent
PCI Express type
PCI Express link
PCI Express speed
Sustainable throughput
Power dissipation
3.3V PXIe power supply
12V PXIe power supply
Gen 1
1
Gen 2 Gen 1
Gen 2
4
–
4
1
Lanes
400
200
1600
800
400
200
1600 MBytes/s Depends on # of lanes, chassis, congestion, and more
800 MPoints/s Depends on # of lanes, chassis, congestion, and more
1.5
2
1.5
2
A
A
~ 5 W
~ 24 W
Environmental 1
Temperature range
Operating
Non-operating
0 to +55°C (10,000 feet)
-40 to +70 °C (up to 15,000 feet)
Max operative altitude
2000 m (10,000 feet)
10 to 95% at 40 °C
5 to 95%
Operating Humidity range (%RH)
Non-operating Humidity range (%RH): 5 to 95
Calibration interval
EMC
1 year
Complies with European EMC Directive
– IEC/EN 61326-1
– CISPR Pub 11 Group 1, class A
This ISM device is in compliance with Canadian ICES-001
Cet appareil ISM est conforme à la norme NMB-001 du Canada.
This ISM device is in compliance with Australian and New Zealand RCM
This ISM device is in compliance with South Korea EMC KCC
1. Samples of this product have been type tested in accordance with the Keysight Environmental Test Manual and verified to be robust against the environ-
mental stresses of Storage, Transportation and End-use; those stresses include but are not limited to temperature, humidity, shock, vibration, altitude and
power line conditions. Test Methods are aligned with IEC 60068-2 and levels are similar to MIL-PRF-28800F Class 3.
09 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
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© Keysight Technologies, 2017 - 2018
Published in USA, February 20, 2018
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