16861A-008 [KEYSIGHT]
Portable Logic Analyzers;
| 型号： | 16861A-008 |
| 厂家： | 
Keysight Technologies |
| 描述： | Portable Logic Analyzers |
| 文件： | 总22页 (文件大小：2683K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Keysight 16860A Series
Portable Logic Analyzers
Data Sheet
Introduction
Keysight’s 16860A Series is the industry’s highest-performance portable logic analyzer – providing you the
best insight so you can solve your toughest digital debug challenges.
– High-speed state and timing with deep memory – Capture the most system activity (up to 128 Mb) at
the highest resolution to identify the root cause of a problem and symptom widely separated in time
– Signal integrity – Quickly identify problem signals with simultaneous eye diagrams on all channels
– Probing and application support – Customize a system for your specific needs with a comprehensive set
of probing options and application-specific software
– Upgradable – Purchase the capability you need now, then upgrade as your needs evolve
Models
16861A
16862A
16863A
16864A
Channels
34
68
102
136
Max timing sample rate
Quarter channel timing
sample rate
2.5 GHz full channel/5.0 GHz half channel
—
10 GHz
—
10 GHz
(Option T10)
(Option T10)
Max state clock rate
Maximum state data rate
Timing zoom
350 MHz standard, 700 MHz (Option 700)
700 Mb/s standard, 1400 Mb/s (Option 700)
12.5 GHz at 256 K deep
Memory depth
2 Mb standard; 4 Mb, 8 Mb, 16 Mb, 32 Mb, 64 Mb, 128 Mb optional
(2x in half-channel timing, 4x in quarter-channel timing)
Probe/signal compatibility
U4200A Series single-ended direct connect probes, 90-pin single-ended and differential
probes
03 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
Identify Problem Signals on All Channels Simultaneously
As timing and voltage margins continue to shrink, confidence in signal integrity becomes an
increasingly vital requirement in the design validation process. Eye scan lets you acquire signal
integrity information on all the buses in your design (and under a wide variety of operating
conditions) in a matter of minutes. Identify problem signals quickly for further investigation with
an oscilloscope. Results can be viewed for each individual signal or as a composite of multiple
signals or buses.
Figure 1. Eye scan automatically sets sample positions for accurate state capture and also provides a
signal integrity view of each input signal, without the need for an oscilloscope.
04 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
Unleash the Power of a Logic Analyzer Plus an Oscilloscope
Seamless oscilloscope integration with View Scope
Easily make time-correlated measurements between Keysight logic analyzers and
oscilloscopes. The time-correlated logic analyzer and oscilloscope waveforms are integrated
into a single logic analyzer waveform display for easy viewing and analysis. You can also trigger
the oscilloscope from the logic analyzer (or vice versa); automatically de-skew the waveforms;
and maintain marker tracking between the two instruments. View Scope allows you to perform
the following more effectively:
– Validate signal integrity
– Track down problems caused by signal integrity
– Validate correct operation of A/D and D/A converters
– Validate correct logical and timing relationships between the analog and digital portions of
a design
Connection
The Keysight logic analyzer and oscilloscope can be physically connected with standard
BNC and LAN connections. Two BNC cables are connected for cross triggering, and the LAN
connection is used to transfer data between the instruments. The View Scope correlation
software is standard in the logic analyzer’s application software.
The View Scope software includes:
– Ability to import some or all of the captured oscilloscope waveforms
– Auto scaling of the scope waveforms for the best fit in the logic analyzer display
Feature
Benefit
Automated setup
Quickly get to your first measurement by using the logic analyzer’s
Help wizard for easy setup, regardless of which supported Keysight
oscilloscope you connect to.
Integrated waveform display
Instantly validate the logical and timing relationships between the
analog and digital portions of your design. View oscilloscope and
logic analyzer waveforms integrated into a single logic analyzer
waveform display.
Automatic measurement de-skew
Save time and gain confidence in measurement results with
measurements that are automatically de-skewed in time.
Start your debug approach from either the analog or digital domain
with the flexibility to trigger the oscilloscope from the logic analyzer
(or vice versa).
Cross trigger the logic analyzer and
oscilloscope
Tracking markers
Precisely relate information on the oscilloscope’s display to the
corresponding point in time on the logic analyzer display with
tracking markers. The oscilloscope’s time markers automatically
track adjustments of the logic analyzer’s global markers.
05 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
Debug, Verify, and Optimize DDR, LPDDR, and ONFi Memory Systems
The 16860A Series logic analyzers, in conjunction with memory specific probing solutions and
B4661A Memory Analysis Software, provide a cost-effective platform for debugging, verifying
and optimizing memory designs operating at ≤ 1400 MT/s. You can get a comprehensive view
into your system’s memory operation with bus decode, transaction overview, compliance
testing and performance analysis.
The 16860A Series supports Add/Cmd/Data state mode measurements for the following DDR
and LPDDR memory families. For higher speed or channel count DDR/2/3, LPDDR/2/3, DDR4
and LPDDR4 memory applications, refer to Keysight’s U4164A logic analyzer module which is
designed specifically for high-speed memory applications.
Supported memory device speeds for 16860A Series logic analyzers
Memory family
Memory device
clock rate
Memory device
data rate
Required state speed option
350 MHz clock
700 MHz clock
standard
Option 700
DDR
DDR2
DDR3
LPDDR
LPDDR2
LPDDR3
< 350 MHz
< 350 MHz
< 700 MHz
< 350 MHz
< 700 MHz
< 700 MHz
< 700 Mb/s
< 700 Mb/s
< 1400 Mb/s
< 700 Mb/s
< 1400 Mb/s
< 1400 Mb/s
√
√
√
√
√
√
√
√
√
In addition, the 2.5 GHz timing mode provides a 3:1 ratio of sample rate to data rate so you can
perform timing measurements on DDR/LPDDR devices with < 400 MHz clock rate/
< 800 Mb/s data rate. When a 16862A or 16864A logic analyzer is configured with the 10 GHz
quarter channel timing option, the analyzer is capable of capturing Open NAND Flash Interface
(ONFi) traffic. Analysis of captured ONFi traffic is provided through the Performance Analysis
option (4FP/4NP/4TP) of the B4661A Memory Analysis Software.
06 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
Get Instant Insight into your Design with Multiple Views and Analysis Tools
When you want to understand what your target is doing and why, you need acquisition and
analysis tools that rapidly consolidate data and provide insight into your system’s behavior.
Optional analysis and automated measurement packages
B4601C
Serial to parallel analysis package. This general purpose software enables easy viewing
and analysis of serial data by converting it into a parallel format, thereby eliminating the
tedious, time-consuming, and error-prone task of sifting through thousands of captured
1’s and 0’s.
B4602A
B4610A
Signal extractor tool. This tool processes input signals and based on xml algorithms and
creates a mapping of captured signals into new bus and signal names.
Data import package. Use the logic analyzer GUI to view data obtained from tools other
than a logic analyzer.
B4655A
B4656A
FPGA dynamic probe application software for Xilinx (B4655A) and Altera (B4656A).
The FPGA dynamic probe provides unprecedented visibility into your FPGA’s internal
activity. Make incremental real-time measurements in seconds without stopping the
FPGA, changing the design or modifying design timing. Quickly set up the logic analyzer
with automatic pin mapping and signal bus naming by leveraging the work you did in your
design environment.
B4661A
Memory Analysis Software for logic analyzers. This package includes standard and
optional licensed software. Standard features are always available for use. Optional
licensed features require the purchase of a license to enable the full functionality of the
option. Options include:
– DDR decoder with physical address trigger tool
– LPDDR decoder
– DDR and LPDDR compliance violation analysis
– DDR3/4 and LPDDR2/3/4 performance analysis
89601B-300
Digital vector signal analysis software, hardware connectivity for logic analyzers.
Perform time-domain, spectrum and modulation quality analysis on digital baseband and
IF signals with Keysight’s 89600 Vector Signal Analysis software, running on the logic
analyzer. www.keysight.com/find/dvsa
07 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Logic Analyzer Specifications and Characteristics
State (synchronous) sampling mode
16861A
16862A
16863A
16864A
Channels
34
68
102
(96 data and
6 clock)
136
(128 data and
8 clock)
(32 data and
2 clock)
(64 data and
4 clock)
Sampling option: Single clock
Clock (clock is on Pod 1)
Clock qualifiers
1
1
0
1
3
0
1
4
0
1
4
1
Reset qualifier
Sampling option: Multiple clocks
Clocks or clock qualifiers
Reset qualifier
2
0
4
0
4
0
4
0
Clock channels can be used as data channels.
The state sampling clock mode specifies how the clock inputs are used for sampling. The
availability of these state sampling clock modes depends on the state sampling option that you
select.
– Master - All pods sampled by the master clock definition.
–
–
In single clock mode, only the clock signal on Pod 1 can be used.
In multiple clocks, either a single clock signal can be used or a combination of clocks
can be used.
– Dual sample - In the dual sample clock mode, you can capture two samples per clock
edge with two different threshold offsets and separate sampling positions. These separate
threshold offsets and sampling positions allow you to set independent thresholds and
sampling positions for Read and Write in DDR/LPDDR captures and for Rising and Falling
edge in general-purpose data captures.
– Master/slave - Master pod is sampled on master clock and slave pod is sampled on slave
clock, but the captured data of both slave and master clocks is saved together when the
master clock occurs.
– Demux - Data being probed by one pod is demultiplexed into the logic analyzer memory
that is normally used for two pods. The demultiplex mode uses the master and slave clocks
to demultiplex the data.
350 MHz
(Base configuration)
700 MHz
(Option 700)
350 MHz
(Base configuration)
Sampling option
Available clock modes
Single clock
Master
Single clock
Master
Multiple clocks
Master
Dual sample
Dual sample
Master/slave
Demux
Maximum state data
rate (spec) 1
Captures data up to
Captures data up to
Captures data up to
350 Mbps on either edge 700 Mbps on either edge 700 Mbps on any
of a clock up to 350 MHz of the clock up to
700 MHz
combination of multiple
clocks up to 350 MHz
Captures data up to
Captures data up to
700 Mbps on both edges 1400 Mbps on both
of a clock up to 350 MHz edges of the clock up to
700 MHz
Maximum state clock
frequency
Minimum state clock
frequency
350 MHz
700 MHz
350 MHz
0 MHz
12.5 MHz (single edge),
6.25 MHz (both edges)
12.5 MHz (single edge),
6.25 MHz (both edges)
Minimum time between 1430 ps
active clock edges
715 ps
1430 ps
700 MHz
Maximum trigger
sequencer speed
700 MHz
1400 MHz
1. Specification (spec): Represents warranted performance of a calibrated instrument that has been stored for a
minimum of 2 hours within the operating temperature range of 5 to 40 °C, unless otherwise stated, and after
a 45-minute warm-up period. The specifications include measurement uncertainty.
08 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Logic Analyzer Specifications and Characteristics (Continued)
State mode functional characteristics
Single clock
Multiple clocks
Minimum setup time
80 ps
250 ps
Minimum hold time
80 ps
250 ps
Minimum data valid window
Sample position adjustment range
Sample position adjustment resolution
Minimum state clock pulse width
Clock qualifier setup time
160 ps
7 ns typical
20 ps typical
Single edge: 200 ps
500 ps
12 ns typical
80 ps typical
Single edge: 250 ps
200 ps
250 ps
Clock qualifier hold time
200 ps
250 ps
RESET clock qualifier setup time
RESET clock qualifier hold time
Minimum slave to master clock time
Minimum master to slave clock time
Minimum slave to slave clock time
Time tag resolution
2 ns
0 ps
N/A
N/A
N/A
80 ps
N/A
N/A
350 ps
150 ps
1.43 ns
80 ps
Maximum time count between stored states
Maximum trigger sequence steps
Trigger sequence step branching
Trigger position
66 days
8
66 days
16
Arbitrary 4-way if/then/else
Start, center, end or user-defined
– 16 patterns evaluated as =, !=, >,
>=, <, <=
– 8 double-bounded ranges
evaluated as in range, not in range
– 4 edge detectors in timing, 3 in
transitional timing
– 1 occurrence counter per sequence
level
Arbitrary 4-way if/then/else
Start, center, end or user-defined
– 16 patterns evaluated as =, !=, >, >=, <, <=
– 8 double-bounded ranges evaluated as in range, not in
range
– 4 edge detectors in timing, 3 in transitional timing
– 1 occurrence counter per sequence level
– 3 timers
Trigger resources
– 4 flags
– 1 arm in
– 1 timer
– Global counters - 2
– 4 flags
– 1 arm in
– Burst patterns
– Event counters - 2
999,999,999
64 bits
128 bits single label
200 sample clock period to 27 hours
5 ns
Maximum occurrence counter
Maximum range width
Maximum pattern width
Timer range
999,999,999
64 bits
128 bits single label
100 ns to 27 hours
5 ns
Timer resolution
Timer accuracy
Timer reset latency
± (8 sample clock period + 2 ns + 0.01%) ± (8 sample clock period + 2 ns + 0.01%)
80 sample clock period 80 sample clock period
09 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Logic Analyzer Specifications and Characteristics (Continued)
Timing (asynchronous) sampling mode
Feature
Full channel
2.5 GHz
400 ps to 10 ns
Up to 128 M
Half channel
5.0 GHz
200 ps
Quarter channel (Optional on 16862A or 16864A, requires options -700 and –T10
10 GHz
100 ps
Up to 512 M
Max sample rate
Sample period
Memory depth
Up to 256 M
Timing mode functional characteristics
Minimum data pulse width
Timing interval accuracy
– Within a 16 channel pod
– Across 16 channel pods
Maximum trigger sequencer speed
Maximum trigger sequence steps
Trigger sequence step branching
Trigger position
1 sample period + 200 ps
± (1 sample period + 130 ps + 0.01% of time interval reading) 1
± (1 sample period + 400 ps + 0.01% of time interval reading) 1
2.5 GHz
8
Arbitrary 4-way if/then/else
Start, center, end or user-defined
Trigger resources
16 patterns evaluated as =, !=, >, >=, <, <=
8 double-bounded ranges evaluated as in range, not in range
4 edge detectors in timing, 3 in transitional timing
1 occurrence counter per sequence level
1 timer
4 flags
1 arm in
Burst trigger
2 event counters
Arbitrary Boolean combinations
Go to
Trigger resource conditions
Trigger actions
Trigger and fill memory
Trigger and go to
Trigger, send e-mail and fill memory
Occurrence counter reset
Set
Flag actions
Clear
Pulse set
Pulse clear
Maximum occurrence counter
Maximum range width
Maximum pattern width
Timer range
999,999,999
64 bits
128 bits single label
200 sample clock period to 27 hours
5 ns
Timer resolution
Timer accuracy
Timer reset latency
± (8 sample clock period + 2 ns + 0.01%)
80 sample clock period
Timing zoom (Captured simultaneously with timing or state sampling mode capture)
Timing analysis sample rate
Timing interval accuracy
– Within a 16 channel block
– Between 16 channel blocks
Memory depth
12.5 GHz (80 ps sample resolution)
± (80 ps + 130 ps + 0.01% of time interval reading)
± (80 ps + 400 ps + 0.01% of time interval reading)
256 K samples
Trigger position
Minimum data pulse width
Start, center, end or user-defined
1 sample period + 200 ps
1. With single-ended flying lead and Soft Touch Pro probes.
10 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860 Series Instrument Characteristics
Standard data views
Waveform
Integrated display of data as digital waveforms, analog waveforms imported from an external
oscilloscope, and/or as a chart of a bus’ values over time
Listing
Displays data as a state listing
Compare
Source code
Compares data from different acquisitions and highlights differences
Displays time-correlated source code and inverse assembly simultaneously in a split display
Define the trigger event by simply clicking on a line of source code
Obtain source-code-level views of dynamically loaded software or code moved from ROM to RAM
during a boot-up sequence using address offsets
Requires access to source files via the LAN or instrument hard drive to provide source code correlation
Source correlation does not require any modification or recompilation of your source code
Displays eye diagrams across all buses and signals simultaneously, allowing you to identify problem
signals quickly
Eye scan
Data display
Numeric bases for data display
Binary, hex, octal, decimal, signed decimal (two’s complement), ASCII, symbols and processor
mnemonics
Symbolic support/object file format compatibility
Number of symbols/ranges
Object file formats supported
Unlimited (limited only by amount of virtual memory available on 16860 Series logic analyzers)
IEEE-695, Aout, Omf86, Omf96, Omf386, Sysrof, ELF/DWARF1 1, ELF/DWARF2 1, ELF/Stabs1, ELF/
Stabs2, ELF/Mdebug Stabs, TICOFF/COFF, TICOFF/Stabs
ASCII
GPA (general purpose ASCII)
User-defined symbols
Available data/file formats
ala
Specify a mnemonic for a given bit pattern for a label or bus
Contains information to reconstruct the display appearance, instrument settings and trace data
(optional) that were present when the file was created
xml
csv
alb
Extensible markup language for configuration portability and programmability
CSV (comma-separated values) format for transferring data to other applications like Microsoft Excel
Export logic analyzer data for post-processing. Alb data (module binary format) can be parsed using
programming tools
Standard analysis tools
Filter/colorize
Find (next/previous)
Show, hide or color certain samples in a trace for easier identification and analysis
Locate specific data/events in a captured trace
1. Supports C++ name de-mangling.
11 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860 Series Instrument Characteristics (Continued)
16860A Series PC characteristics
Operating system
Processor
Microsoft Windows 7 embedded (64-bit)
3 GHz Intel i5 quad core processor
Chipset
Intel Q77
System memory
Removable SSD
Installed on SSD
8 GB
256 GB
Operating system, latest revision of the logic and protocol application software, optional application
software ordered with the logic analyzer
16860A Series instrument controls
LCD touch-screen display
Large 38.1-cm (15-in.) touch-screen display makes is easy to view a large number of waveforms or
states
Front-panel hot keys
Front-panel knob
Keyboard and mouse
Dedicated hot keys for selecting run mode and disabling touch screen
General-purpose knob adjusts viewing and measurement parameters
USB keyboard and USB mouse
16860A Series video display modes
Touch-screen display standard
Size: 38.1-cm (15-in.)
Resolution: 1024 x 768
External display
Simultaneous display capability; Front panel and external
Programmability
You can write programs to control the logic analyzer application from remote computers on the local area network using COM. The
COM automation server is part of the logic analyzer application. This software allows you to write programs to control the logic
analyzer. All measurement functionality is controllable via the COM interface.
The remote programming interface works through the COM automation objects, methods and properties provided for controlling the
logic analyzer application.
12 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Interfaces
Peripheral interfaces
Display
One 15-pin XGA connector and one DisplayPort connector
Audio ports
Line in, line out, mic in
USB ports
Two 3.0 ports on rear, two 2.0 ports on front, two 2.0 ports on rear
Connectivity interfaces
LAN
Connector
10Base-T, 100Base-T, 1000Base-T
RJ-45
Interface with external instrumentation
Trigger or arm external devices or receive signals that can be used to arm measurement hardware within the logic analyzer with trigger in/out
Trigger in
Input
Rising edge or falling edge
Action taken
Input signal level
Threshold level
When received, the logic analyzer takes the actions described in the trigger sequence step
± 6 V max
Selectable: ECL, LVPECL, LVTTL, PECL, TTL
User defined (± 5 V in 50 mV increments)
Minimum signal amplitude
Connector
200 mV
BNC
Input resistance
Trigger out
3.2 kΩ nominal
Trigger
Select one event from the following as the trigger out event: logic analyzer trigger, flag 1, flag 2, flag 3 or
flag 4
Mode
Feedthrough
Polarity
Active high
Output signal
VOH (output high level) 2.0 V min
VOL (output low level) 0.5 V max
Signal load
50 Ω (For good signal quality, the trigger out signal should be terminated in 50 Ω to ground)
Connector
BNC
External reference clock in
10 MHz ± 0.01%
Signal swing
Connector
Minimum 200 mVp-p swing, Maximum 5 Vp-p swing
BNC
13 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Physical Characteristics
Dimensions
16861A, 16862A,
16863A, 16864A
Height 291.57 mm (11.48 in)
Width 450.65 mm (17.74 in)
Add 1.25 inches to the width to account for probes that plug into the right side of
the instrument
Depth 456.54 mm (17.97 in)
Power
16861A
100 to 120 V ± 10%, 50/60/400 Hz
100 to 240 V ± 10% 50/60 Hz
325 W max
16862A
16863A
16864A
100 to 120 V ± 10%, 50/60/400 Hz
100 to 240 V ± 10% 50/60 Hz
325 W max
100 to 120 V ± 10%, 50/60/400 Hz
100 to 240 V ± 10% 50/60 Hz
325 W max
100 to 120 V ± 10%, 50/60/400 Hz
100 to 240 V ± 10% 50/60 Hz
325 W max
Weight
16861A
16862A
16863A
16864A
Max net
Max shipping
23.3 kg (51 lbs)
23.3 kg (51 lbs)
23.3 kg (51 lbs)
23.3 kg (51 lbs)
12.5 kg (27.6 lbs)
12.5 kg (27.6 lbs)
12.5 kg (27.6 lbs)
12.5 kg (27.6 lbs)
Instrument operating environment
Temperature
Operating 5 °C to 40 °C
Non-operating –40 °C to +65 °C
Operating up to 90% relative humidity (non-condensing) at 40 °C
Operating up to 90% relative humidity (non-condensing) at 40 °C
Non-operating up to 90% relative humidity (non-condensing) at 65 °C
Operating up to 4000 meters (13,000 ft)
Humidity
Altitude
Non-operating up to 15300 meters (50,000 ft)
Extra notes regarding 16860A Series:
1. Pollution degree 2
2. Installation category II
3. These instruments are intended for use in an indoor lab environment
14 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
Ordering Information
A complete logic analysis system includes the logic analyzer, probes, optional application
software and accessories. Use the information on the following pages to configure a portable
logic analysis system.
16860A Series portable logic analyzer
The base configuration of each 16860A Series logic analyzer includes 350 MHz state, 2.5 GHz
timing (full channel) and 2 Mb memory depth standard.
Configuring a logic analyzer to meet your application needs and budget is as easy as 1, 2, 3.
1. Select a channel count to determine the model number. Once the model number is
determined, use the entries in that column for the remaining configuration selections.
2. Select the desired state and timing speeds. Note: 10 GHz quarter channel timing mode is
available on the 16862A and 16864A models only.
3. Select the memory depth. Memory depth is defaulted to 2 Mb if no selection is made.
Model
16861A
16862A
16863A
16864A
Channels
Channels
State speed
350 MHz
700 MHz
34
68
102
136
Standard
16861A-700
Standard
16862A-700
Standard
16863A-700
Standard
16864A-700
Timing speed (quarter channel mode)
10 GHz
Memory depth
2 Mb
—
16862A-T10 1
—
16864A-T10 1
Standard
Standard
Standard
Standard
4 Mb
8 Mb
16 Mb
32 Mb
64 Mb
128 Mb
16861A-004
16861A-008
16861A-016
16861A-032
16861A-064
16861A-128
16862A-004
16862A-008
16862A-016
16862A-032
16862A-064
16862A-128
16863A-004
16863A-008
16863A-016
16863A-032
16863A-064
16863A-128
16864A-004
16864A-008
16864A-016
16864A-032
16864A-064
16864A-128
1. Option 16862A-T10 requires 16862A-700. Option 16864A-T10 requires 16864A-700.
Each 16860 Series logic analyzer includes the following:
– USB keyboard
– USB mouse
– Accessory bag
– Power cord
– 3 year warranty
15 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Probing Options
Logic analyzer probes are required and ordered separately. Please specify probes when ordering to ensure the correct connection
between the logic analyzer and the device under test.
Consider the following when determining how you’ll connect to the DUT. For more detailed information on probing options, please refer
to the Probing Solutions for Logic Analyzers data sheet (pub number: 5968-4632E).
Flying lead probes
Connector probes – Mictor
Measure individual signals physically
far apart or located where a probe
connector hasn’t been designed in. A
wide variety of accessories provide
the flexibility to connect to IC pins,
traces, pads, vias and any signal that
resides on the surface of the board.
This reliable and cost-effective
connector solution supports data
rates up to 600 Mb/s. Mictor probes
require a 38-pin Mictor connector
designed into your target system.
DDR/LPDDR BGA probes
BGA probes work in existing designs
and eliminate the need for up front
planning or re-design. BGA probes
allow you to get signal access to the
DDR/LPDDR signals, connecting
directly to the balls of the DRAM,
enabling you to operate at full speed
and acquire high-speed signals
without impacting the performance
of your design.
Soft Touch connectorless probes
Soft Touch connectorless probes
ensure signal quality with
< 0.7 pF of capacitive loading. They
are compatible with all surface
finishes, including lead-free. The
probe requires a soft touch footprint
designed into your target system.
ZIF probes
ZIF probes provide convenient and
reliable connection between the BGA
probe wings and the U4201A cable
that connects to the logic analyzer.
Connector probes – Samtec
This high-performance connector
solution supports data rates up to
1.5 Gb/s. The probe requires a
100-pin Samtec connector designed
into your target system.
16 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Probing Options (Continued)
Direct connect and 90-pin probing options
There are two styles of general purpose probes compatible with 16860A Series logic analyzers: direct connect probes and 90-pin
probes. Direct connect probes connect directly to the DUT and the 160-pin connector of the logic analyzer.
Connection to 160-pin connector
of the logic analyzer
Connection to DUT
Figure 2. U4203A direct connect flying lead probe connected to a logic analyzer.
90-pin probes require a U4201A logic analyzer cable between the 90-pin probe connector and the connector of the logic analyzer.
Connection
to DUT
To connect to pods of a
90-pin probe
To connect to a logic
analyzer pod
Figure 3. U4201A logic analyzer cable.
17 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Probing Options (Continued)
Direct connect probes
Probe type
Flying lead
Soft Touch Pro
Mictor
Number of channels, signal support for clock and data
34-channel, single-ended data, differential clock
34-channel, single-ended data, differential clock
34-channel, single-ended data, single-ended clock
34 channel, single-ended data, single-ended clock
(used for quarter channel timing applications)
Order
U4203A
U4204A
U4205A
U4206A
Soft Touch Pro
90-pin probes for use with U4201A logic analyzer cables
The following logic analyzer probes require a U4201A cable to connect to. The maximum
number of U4201A cables per 16860A series logic analyzers is:
– 16861A: 1
– 16862A: 2
– 16863A: 3
– 16864A: 4
Probe type
Number of channels, signal
support for clock and data
Uses one or both of a
U4201A cable’s pod
connections
Order
Flying lead
Flying lead
Soft Touch pro
Soft Touch pro
Samtec
17 channel, differential data,
differential clock
17 channel, single-ended data,
differential clock
17 channel, differential data,
differential clock
17 channel, single-ended data,
differential clock
17 channel, differential data,
differential clock
34 channel, single-ended data,
single-ended clock
One
E5381B
E5382B
E5405B
E5406A
E5379A
E5380B
One
One
Both
One
Both
Mictor
18 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Probing Options (Continued)
DDR/LPDDR interposers and probes
The following provides a high-level overview of memory probing components and 16860A
Series logic analyzer compatibility. To ensure you order the correct quantity and combination of
components for your specific DDR/LPDDR implementation, refer to the data sheet for a specific
component for more detailed information. The following include 16860A Series configuration
files for easy setup. Refer to page 5 for logic analyzer state speed option requirements.
DRAMs, DIMMs and SO-DIMMs operating at ≤ 1400 MT/s
Form factor
Signal access 1 Requires component, qty
16860A Series compatibility
16862A 2 16863A 2 16864A
x4/x8, 78-ball
Command,
Address, Control
and Data 1
Command,
Address, Control
and Data 1
– W3633A BGA interposer, 1
– E5847A ZIF probe, 1
– U4201A cable, 2
– W3631A BGA interposer, 1
– E5845A ZIF probe, 1
– U4201A cable, 2
– W3636A BGA interposer, 1
– E5845A ZIF probe, 1
– U4201A cable, 3
√
√
√
√
√
√
√
√
√
x16, 96-ball,
stacked die
under 2G
x16, 96-ball,
non-stacked die, Address, Control
2
Command,
No data
all depths
and Data 1
DIMM
240-pin DDR3
SDRAM DIMM
2
2
Command,
Address, Control
and Partial
Data 1
Command,
Address, Control
(No data)
– FS2352B DIMM
interposer, 1
– U4201A cable, 4
√
√
√
√
√
√
√
√
√
240-pin DDR3
SDRAM DIMM
– FS2372 DIMM interposer, 1
– U4201A cable, 4
√
SO-DIMM
240-pin
DDR3 SDRAM
SO-DIMM
2
2
2
Command,
Address, Control
and Partial
Data 1
Command,
Address, Control
(No data)
– FS2354 DIMM interposer, 1
– Cables connection to logic
analyzer included standard
with interposer
– FS2374 SO-DIMM
interposer, 1
√
2
240-pin
DDR3 SDRAM
SO-DIMM
√
– U4201A cable, 4
1. Refer to the data sheet for a given interposer for information on specific signal access.
2. The required U4201A cables may be more than what a given 16860A Series logic analyzer will support. If the
number of U4201A cables is more than what the analyzer supports, some signals will not be available for that
model. The maximum number of U4201A cables per analyzer are two for the 16862A, three for the 16863A
and four for the 16864A.
19 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
Add-in Application Software
If you request the email delivery option, you will be sent an electronic copy of the Entitlement
Certificate so you can redeem your license and begin using the software, often on the same
day.
Order the appropriate option number for the desired application and license type you order.
– Fixed perpetual license - The license is locked to the PC where the software operates.
– Floating/server perpetual license - The license is locked to a license server from which the
software automatically checks out the necessary licenses. Licenses are checked back into
the server once your analysis session is terminated.
– Transportable perpetual license - The license is locked to the PC where the software
operates, however the license can be moved. The deletion from one host PC is confirmed
prior to issuing a license for another host PC.
Model number Add-in application software Ordering information
Fixed license
Floating/server Transportable
license
license
B4601C
Serial-to-parallel analysis
package
B4601C-010
B4601C-020
B4602A
B4610A
B4655A
Signal extractor tool
Data import package
FPGA dynamic probe
application software for Xilinx
FPGA dynamic probe
application software for Altera
Memory analysis software for
logic analyzers
B4602A-010
B4610A-010
B4655A-011
B4602A-020
B4610A-020
B4655A-012
B4656A
B4661A
B4656A-010
B4656A-020
DDR decoder with physical
address trigger tool
B4661A-1FP
B4661A-1NP
B4661A-1TP
LPDDR decoder
DDR and LPDDR compliance
violation analysis
B4661A-2FP
B4661A-3FP
B4661A-2NP
B4661A-3NP
B4661A-2TP
B4661A-3TP
DDR3/4 and LPDDR2/3/4
performance analysis
Digital Vector Signal
Analysis software, hardware
connectivity for logic
analyzers
B4661A-4FP
B4661A-4NP
B4661A-4TP
89601B
89601B-300
Floating/server license count provided with each purchase of the floating/server license
product-option. Each use of the application uses a single count of the floating/server license.
Purchase the quantity of the product-option to cover the maximum simultaneous use of the
application.
Product-option
B4601C-020
B4602A-020
B4610A-020
B4655A-012
B4656A-020
B4661A-1NP
B4661A-2NP
B4661A-3NP
B4661A-4NP
Count =
1
2
1
1
1
2
4
4
4
20 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
Accessories
Model number
Description
E5867A
Additional 1686X removable hard drive assembly, includes 256 GB or greater
SSD (imaged with operating system and logic analyzer software)
After-purchase upgrades
Buy what you need today and upgrade in the future. The 16860A Series logic analyzer’s state
speed, timing speed and memory depth can be independently upgraded. When ordering, if
you request the email delivery option, you will be sent an electronic copy of the Entitlement
Certificate so you can redeem your license and begin using the upgraded capability, often on
the same day.
For model
Channels
16861A
34
16862A
68
16863A
102
16864A
136
State speed
700 MHz
Timing speed (quarter channel mode)
10 GHz
Memory depth
4 Mb
8 Mb
16 Mb
32 Mb
64 Mb
16861AU-700
16862AU-700
16862AU-T10 1
16863AU-700
—
16864AU-700
16864AU-T10 2
—
16861AU-004
16861AU-008
16861AU-016
16861AU-032
16861AU-064
16861AU-128
16862AU-004
16862AU-008
16862AU-016
16862AU-032
16862AU-064
16862AU-128
16863AU-004
16863AU-008
16863AU-016
16863AU-032
16863AU-064
16863AU-128
16864AU-004
16864AU-008
16864AU-016
16864AU-032
16864AU-064
16864AU-128
128 Mb
1. 16862AU-T10 upgrade requires that the 16862A already have 16862A-700 installed or that a 16862AU-700
upgrade license is also purchased with 16862AU-T10.
2. 16864AU-T10 upgrade requires that the 16864A already have 16864AU-700 installed or that a 16864AU-700
upgrade license is also purchased with 16864AU-T10.
Related literature
Publication title
Publication number
5968-4632E
5989-0423EN
5989-5595EN
5992-0984EN
5990-3179EN
Probing Solutions for Logic Analyzers - Data Sheet
B4655A FPGA Dynamic Probe for Xilinx - Data Sheet
B4656A FPGA Dynamic Probe for Altera - Data Sheet
B4661A Memory Analysis Software for Logic Analyzers - Data Sheet
W3630A Series DDR3 BGA Probes for Logic Analyzers and Oscilloscopes –
Data Sheet
21 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
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22 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
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© Keysight Technologies, 2016
Published in USA, September 1, 2016
5992-1723EN
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