IRFRC20TRLPBFA [KERSEMI]
Power MOSFET; 功率MOSFET
| 型号： | IRFRC20TRLPBFA |
| 厂家： | 
Kersemi Electronic Co., Ltd. |
| 描述： | Power MOSFET |
| 文件： | 总7页 (文件大小：4340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
Power MOSFET
FEATURES
• Dynamic dV/dt Rating
PRODUCT SUMMARY
VDS (V)
600
Available
• Repetitive Avalanche Rated
RoHS*
• Surface Mount (IRFRC20/SiHFRC20)
COMPLIANT
RDS(on) (Ω)
VGS = 10 V
4.4
Qg (Max.) (nC)
18
3.0
• Straight Lead (IRFUC20/SiHFUC20)
• Available in Tape and Reel
• Fast Switching
Q
Q
gs (nC)
gd (nC)
8.9
Configuration
Single
• Ease of Paralleling
• Lead (Pb)-free Available
D
DPAK
(TO-252)
IPAK
(TO-251)
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
G
The D PAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFUC/SiHFUC series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surcace mount applications.
S
N-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
IRFRC20PbF
SiHFRC20-E3
IRFRC20
DPAK (TO-252)
IRFRC20TRLPbFa
SiHFRC20TL-E3a
IRFRC20TRLa
DPAK (TO-252)
IRFRC20TRPbFa
SiHFRC20T-E3a
IRFRC20TRa
DPAK (TO-252)
IRFRC20TRRPbFa
SiHFRC20TR-E3a
IRFRC20TRRa
IPAK (TO-251)
IRFUC20PbF
SiHFUC20-E3
IRFUC20
Lead (Pb)-free
SnPb
SiHFRC20
SiHFRC20TLa
SiHFRC20Ta
SiHFRC20TRa
SiHFUC20
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
600
20
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
V
VGS
TC = 25 °C
TC =100°C
2.0
Continuous Drain Current
V
GS at 10 V
ID
1.3
A
Pulsed Drain Currenta
IDM
8.0
Linear Derating Factor
0.33
0.020
450
2.0
W/°C
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
EAS
IAR
mJ
A
Repetitive Avalanche Energya
EAR
4.2
mJ
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
TC = 25 °C
42
PD
W
V/ns
°C
TA = 25 °C
2.5
dV/dt
3.0
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
TJ, Tstg
- 55 to + 150
260d
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 206 mH, RG = 25 Ω, IAS = 2.0 A (see fig. 12).
c. ISD ≤ 2.0 A, dI/dt ≤ 40 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
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1
IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Maximum Junction-to-Ambient
RthJA
-
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
RthJC
-
-
-
-
50
°C/W
Maximum Junction-to-Case (Drain)
3.0
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS
ΔVDS/TJ
VGS(th)
IGSS
VGS = 0 V, ID = 250 µA
Reference to 25 °C, ID = 1 mA
VDS = VGS, ID = 250 µA
600
-
-
V
V/°C
V
V
DS Temperature Coefficient
-
0.88
-
Gate-Source Threshold Voltage
Gate-Source Leakage
2.0
-
-
-
-
-
-
4.0
100
100
500
4.4
-
VGS
=
20 V
-
nA
VDS = 600 V, VGS = 0 V
-
-
Zero Gate Voltage Drain Current
IDSS
µA
V
DS = 480 V, VGS = 0 V, TJ = 125 °C
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
RDS(on)
gfs
VGS = 10 V
ID = 1.2 Ab
-
Ω
VDS = 50 V, ID = 1.2 A
1.4
S
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Ciss
Coss
Crss
Qg
-
-
-
-
-
-
-
-
-
-
350
48
8.6
-
-
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
-
-
pF
nC
18
3.0
8.9
-
ID = 2.0 A, VDS = 360 V,
see fig. 6 and 13b
Qgs
Qgd
td(on)
tr
VGS = 10 V
-
-
10
23
30
25
-
VDD = 300 V, ID = 2.0 A,
ns
RG = 18 Ω, RD = 135 Ω, see fig. 10b
Turn-Off Delay Time
Fall Time
td(off)
tf
-
-
D
Between lead,
Internal Drain Inductance
LD
LS
-
-
4.5
7.5
-
-
6 mm (0.25") from
package and center of
die contact
nH
G
Internal Source Inductance
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
D
MOSFET symbol
showing the
integral reverse
p - n junction diode
IS
-
-
-
-
2.0
8.0
A
G
Pulsed Diode Forward Currenta
ISM
S
Body Diode Voltage
VSD
trr
TJ = 25 °C, IS = 2.0 A, VGS = 0 Vb
-
-
-
-
1.6
580
1.3
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
290
0.67
ns
µC
TJ = 25 °C, IF = 2.0 A, dI/dt = 100 A/µsb
Qrr
ton
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
RD
VDS
VGS
D.U.T.
RG
+
V
-
DD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on) tr
td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
L
VDS
VDS
Vary tp to obtain
required IAS
tp
VDD
D.U.T
IAS
RG
+
-
VDD
VDS
10 V
0.01 Ω
tp
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
-
VDS
D.U.T.
VG
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
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IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
D.U.T
• Low leakage inductance
current transformer
-
+
-
-
+
RG
• dV/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VDD
Driver gate drive
P.W.
P.W.
Period
Period
D =
V
= 10 V*
GS
D.U.T. I waveform
SD
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V waveform
DS
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Ripple ≤ 5 %
Inductor current
I
SD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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相关型号：
IRFRC20TRPBF
Power Field-Effect Transistor, 2A I(D), 600V, 4.4ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, DPAK-3
INFINEON
IRFRC20TRRPBF
Power Field-Effect Transistor, 2A I(D), 600V, 4.4ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, DPAK-3
INFINEON
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