IRFR9120NTRR [KERSEMI]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRFR9120NTRR |
| 厂家： | 
Kersemi Electronic Co., Ltd. |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总10页 (文件大小：3887K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFR/U9120N
HEXFET® Power MOSFET
l Ultra Low On-Resistance
l P-Channel
l Surface Mount (IRFR9120N)
l Straight Lead (IRFU9120N)
l Advanced Process Technology
l Fast Switching
D
VDSS = -100V
RDS(on) = 0.48Ω
G
ID = -6.6A
l Fully Avalanche Rated
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
knownfor, providesthedesignerwithanextremelyefficient
and reliable device for use in a wide variety of applications.
D -Pak
I-Pak
TO -252AA
TO -251AA
The D-Pak is designed for surface mounting using vapor
phase, infrared, orwavesolderingtechniques. Thestraight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ -10V
Continuous Drain Current, VGS @ -10V
Pulsed Drain Current
-6.6
-4.2
-26
A
PD @TC = 25°C
Power Dissipation
40
W
W/°C
V
Linear Derating Factor
0.32
± 20
100
-6.6
4.0
VGS
EAS
IAR
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
EAR
dv/dt
TJ
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
mJ
-5.0
V/ns
-55 to + 150
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
–––
–––
Max.
3.1
50
Units
RθJC
RθJA
RθJA
Junction-to-Ambient (PCB mount)**
Junction-to-Ambient
°C/W
110
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IRFR/U9120N
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
-100 ––– –––
Conditions
VGS = 0V, ID = -250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– -0.11 ––– V/°C Reference to 25°C, ID = -1mA
RDS(on)
VGS(th)
gfs
Static Drain-to-Source On-Resistance ––– ––– 0.48
Ω
V
S
VGS = -10V, ID = -3.9A
VDS = VGS, ID = -250µA
VDS = -50V, ID = -4.0A
VDS = -100V, VGS = 0V
VDS = -80V, VGS = 0V, TJ = 150°C
VGS = 20V
Gate Threshold Voltage
-2.0 ––– -4.0
1.4 ––– –––
Forward Transconductance
––– ––– -25
––– ––– -250
––– ––– 100
––– ––– -100
––– ––– 27
––– ––– 5.0
––– ––– 15
IDSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
IGSS
VGS = -20V
Qg
ID = -4.0A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
nC
ns
VDS = -80V
VGS = -10V, See Fig. 6 and 13
VDD = -50V
–––
–––
–––
–––
14 –––
47 –––
28 –––
31 –––
RiseTime
ID = -4.0A
td(off)
tf
Turn-Off Delay Time
FallTime
RG = 12 Ω
RD =12 Ω, See Fig. 10
Between lead,
D
LD
LS
Internal Drain Inductance
Internal Source Inductance
–––
–––
4.5 –––
6mm (0.25in.)
nH
pF
G
from package
–––
7.5
and center of die contactꢀ
VGS = 0V
S
Ciss
Coss
Crss
Input Capacitance
––– 350 –––
––– 110 –––
Output Capacitance
VDS = -25V
Reverse Transfer Capacitance
–––
70 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
showing the
D
IS
-6.6
––– –––
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– -26
p-n junction diode.
S
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
––– ––– -1.6
––– 100 150
––– 420 630
V
TJ = 25°C, IS = -3.9A, VGS = 0V
TJ = 25°C, IF = -4.0A
ns
nC
Qrr
ton
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
ꢀThis is applied for I-PAK, LS of D-PAK is measured between
Starting TJ = 25°C, L = 13mH
RG = 25Ω, IAS = -3.9A. (See Figure 12)
ISD ≤ -4.0A, di/dt ≤ 300A/µs, VDD ≤ V(BR)DSS
TJ ≤ 150°C
lead and center of die contact
Uses IRF9520N data and test conditions.
,
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IRFR/U9120N
100
10
1
100
10
1
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
TOP
TOP
BOTTOM -4.5V
BOTTOM -4.5V
-4.5V
-4.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
°
°
T = 150 C
J
T = 25 C
J
0.1
0.1
0.1
0.1
1
10
100
1
10
100
-V , Drain-to-Source Voltage (V)
DS
-V , Drain-to-Source Voltage (V)
DS
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
100
2.5
-6.7A
=
I
D
2.0
°
T = 25 C
J
10
1.5
1.0
0.5
0.0
°
T = 150 C
J
1
V
= -50V
DS
20µs PULSE WIDTH
V
= -10V
GS
0.1
4
5
6
7
8
9
10
-60 -40 -20
0
20 40 60 80 100 120 140 160
°
-V , Gate-to-Source Voltage (V)
GS
T , Junction Temperature( C)
J
Fig 4. Normalized On-Resistance
Fig 3. Typical Transfer Characteristics
Vs. Temperature
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IRFR/U9120N
20
16
12
8
800
600
400
200
0
I
D
= -4.0 A
V
= 0V,
f = 1MHz
C SHORTED
ds
GS
V
V
V
=-80V
=-50V
=-20V
DS
DS
DS
C
= C + C
iss
gs
gd
gd ,
C
= C
rss
C
= C + C
gd
oss
ds
C
iss
C
C
oss
rss
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
5
10
15
20
25
1
10
100
Q
, Total Gate Charge (nC)
G
-V , Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance Vs.
Fig 6. Typical Gate Charge Vs.
Drain-to-Source Voltage
Gate-to-Source Voltage
100
100
10
1
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10us
°
T = 150 C
J
10
°
T = 25 C
100us
J
1ms
1
10ms
°
T = 25 C
C
°
T = 150 C
Single Pulse
J
V
= 0 V
GS
0.1
0.2
0.1
0.8
1.4
2.0
2.6
1
10
100
1000
-V
SD
,Source-to-Drain Voltage (V)
-V , Drain-to-Source Voltage (V)
DS
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
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IRFR/U9120N
RD
8.0
6.0
4.0
2.0
0.0
VDS
VGS
D.U.T.
RG
-
+
VDD
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
t
t
r
t
t
f
d(on)
d(off)
V
GS
10%
25
50
T
75
100
125
°
150
, Case Temperature ( C)
C
90%
V
DS
Fig 9. Maximum Drain Current Vs.
Fig 10b. Switching Time Waveforms
Case Temperature
10
D = 0.50
1
0.20
0.10
0.05
P
DM
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
0.1
t
1
t
2
Notes:
1. Duty factor D =
t / t
1 2
2. Peak T = P
J
x Z
+ T
C
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFR/U9120N
L
V
DS
250
200
150
100
50
I
D
TOP
-1.7A
-2.5A
BOTTOM -3.9A
D.U.T
-
+
R
G
VDD
I
A
AS
DRIVER
-20V
0.01
t
Ω
p
15V
Fig 12a. Unclamped Inductive Test Circuit
I
AS
0
25
50
75
100
125
150
°
Starting T , Junction Temperature( C)
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
t
p
V
(BR)DSS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
Q
G
.2µF
12V
.3µF
-10V
-
V
+
DS
Q
Q
GD
GS
D.U.T.
V
GS
V
G
-3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
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IRFR/U9120N
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T*
-
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
+
-
VDD
VGS
* Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
Period
D =
P.W.
V
[
=10V
] ***
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
[
[
DD
]
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
]
SD
Ripple ≤ 5%
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For P-Channel HEXFETS
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IRFR/U9120N
Package Outline
TO-252AA Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
- A -
1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
4
2
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
10.42 (.410)
9.40 (.370)
1.02 (.040)
1.64 (.025)
LEAD ASSIG NM ENTS
1 - GATE
1
3
2 - DRA IN
3 - SOURCE
4 - DRA IN
0.51 (.020)
MIN.
- B -
1.52 (.060)
1.15 (.045)
0.89 (.035)
0.64 (.025)
3X
0.58 (.023)
0.46 (.018)
1.14 (.045)
2X
0.25 (.010)
M
A M B
0.76 (.030)
NOTES:
2.28 (.090)
1
2
3
4
DIMENSIONING & TOLERANCING PER ANSI Y 14.5M, 1982.
CONTROLLING DIMENSION : INCH.
4.57 (.180)
CONFORMS TO JEDE C OUTLINE TO-252AA.
DIMENSIONS SHOW N ARE BEFORE SOLDER DIP,
SOLDER DIP M AX. +0.16 (.006).
Part Marking Information
TO-252AA (D-Pak)
EXA M PLE : THIS IS AN IRFR120
W ITH ASSEM BLY
A
INTERNATIO NAL
RE CTIFIE R
LOT CODE 9U1P
FIRST PO RTIO N
OF PA RT NUM BER
IRFR
120
1P
9U
ASSEM B LY
SECO ND PORTION
O F PART NUM BER
LO T
CODE
8 / 10
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IRFR/U9120N
Package Outline
TO-251AA Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
- A -
0.58 (.023)
0.46 (.018)
1.27 (.050)
5.46 (.215)
0.88 (.035)
5.21 (.205)
LEAD ASSIGNM ENTS
1 - GATE
4
2 - DRAIN
6.45 (.245)
5.68 (.224)
3 - SOURCE
4 - DRAIN
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
3
- B -
NOTES:
1
2
3
4
DIM ENS IONING & TOLERANCING PER ANSI Y14.5M , 1982.
CONTROLLING DIMENSION : INCH.
2.28 (.090)
1.91 (.075)
9.65 (.380)
8.89 (.350)
CONFORMS TO JEDEC OUTLINE TO-252AA.
DIM ENS IONS SHOW N ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
1.14 (.045)
0.76 (.030)
1.14 (.045)
0.89 (.035)
3X
0.89 (.035)
0.64 (.025)
3X
0.25 (.010)
M
A M B
0.58 (.023)
0.46 (.018)
2.28 (.090)
2X
Part Marking Information
TO-251AA (I-Pak)
EXAM PLE : THIS IS AN IRFU120
W ITH ASSEM BLY
INTE RNATIONAL
RECTIFIER
LO T CODE 9U1P
FIRST PO RTION
OF PART NUM BER
IRFU
120
1P
9U
SECOND PO RTIO N
OF PART NUM B ER
AS SEM BLY
LOT
CO DE
9 / 10
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IRFR/U9120N
Tape & Reel Information
TO-252AA
TR
TR L
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIR ECTIO N
FEED DIR ECTIO N
N O TES :
1. C O NTRO LLING D IM EN SIO N : M ILLIM ETER.
2. ALL D IM EN SIO N S ARE SH O W N IN M ILLIM ETERS ( INC HES ).
3. O U TLINE C O N FO RM S TO EIA-481 & EIA-541.
13 INC H
16 m m
NO TES :
1. O U TLINE CO N FO RM S TO EIA-481.
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