IRFR9024 [KERSEMI]
Power MOSFET; 功率MOSFET
| 型号： | IRFR9024 |
| 厂家： | 
Kersemi Electronic Co., Ltd. |
| 描述： | Power MOSFET |
| 文件： | 总7页 (文件大小：4492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFR9024, IRFU9024, SiHFR9024, SiHFU9024
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Dynamic dV/dt Rating
- 60
• Repetitive Avalanche Rated
Available
R
DS(on) (Ω)
VGS = - 10 V
0.28
• Surface Mount (IRFR9024/SiHFR9024)
RoHS*
COMPLIANT
Qg (Max.) (nC)
Qgs (nC)
19
• Straight Lead (IRFU9024/SiHFU9024)
5.4
• Available in Tape and Reel
Qgd (nC)
11
• P-Channel
Configuration
Single
• Fast Switching
S
• Lead (Pb)-free Available
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effictiveness.
DPAK
(TO-252)
IPAK
(TO-251)
G
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU/SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surcace mount applications.
D
P-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
IRFR9024PbF
SiHFR9024-E3
IRFR9024
DPAK (TO-252)
IRFR9024TRPbFa
SiHFR9024T-E3a
IRFR9024TRa
DPAK (TO-252)
IRFR9024TRLPbFa
SiHFR9024TL-E3a
IRFR9024TRLa
SiHFR9024TLa
DPAK (TO-252)
IRFR9024TRRPbFa
SiHFR9024TR-E3a
IPAK (TO-251)
IRFU9024PbF
SiHFU9024-E3
IRFU9024
Lead (Pb)-free
-
-
SnPb
SiHFR9024
SiHFR9024Ta
SiHFU9024
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
- 60
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
V
VGS
20
TC = 25 °C
TC =100°C
- 8.8
- 5.6
- 35
Continuous Drain Current
VGS at - 10 V
ID
A
Pulsed Drain Currenta
IDM
Linear Derating Factor
0.33
W/°C
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
0.020
300
EAS
IAR
mJ
A
- 8.8
5.0
Repetitive Avalanche Energya
EAR
mJ
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
TC = 25 °C
42
PD
W
V/ns
°C
TA = 25 °C
2.5
dV/dt
- 4.5
- 55 to + 150
260d
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
TJ, Tstg
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 25 V, starting TJ = 25 °C, L = 4.5 mH, RG = 25 Ω, IAS = - 8.8 A (see fig. 12).
c. ISD ≤ - 11 A, dI/dt ≤ 140 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
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1
IRFR9024, IRFU9024, SiHFR9024,
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Maximum Junction-to-Ambient
RthJA
-
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
RthJC
-
-
-
-
50
°C/W
Maximum Junction-to-Case (Drain)
3.0
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS
ΔVDS/TJ
VGS(th)
IGSS
VGS = 0 V, ID = 250 µA
Reference to 25 °C, ID = 1 mA
VDS = VGS, ID = 250 µA
- 60
-
-
V
V/°C
V
V
DS Temperature Coefficient
-
- 0.063
-
Gate-Source Threshold Voltage
Gate-Source Leakage
- 2.0
-
-
-
-
-
-
- 4.0
100
- 100
- 500
0.28
-
VGS
=
20 V
-
nA
VDS = - 60 V, VGS = 0 V
-
-
Zero Gate Voltage Drain Current
IDSS
µA
V
DS = - 48 V, VGS = 0 V, TJ = 125 °C
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
RDS(on)
gfs
VGS = - 10 V
ID = - 5.3 Ab
-
Ω
VDS = - 25 V, ID = - 5.3 A
2.9
S
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Ciss
Coss
Crss
Qg
-
-
-
-
-
-
-
-
-
-
570
360
65
-
-
-
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz
pF
nC
-
19
5.4
11
-
ID = - 11 A, VDS = - 48 V,
see fig. 6 and 13b
Qgs
Qgd
td(on)
tr
V
GS = - 10 V
-
-
13
68
15
29
-
V
DD = - 30 V, ID = - 11 A,
ns
RG = 18 Ω, RD = 2.5 Ω, see fig. 10b
Turn-Off Delay Time
Fall Time
td(off)
tf
-
-
D
Between lead,
Internal Drain Inductance
Internal Source Inductance
LD
LS
-
-
4.5
7.5
-
-
6 mm (0.25") from
package and center of
die contact
nH
G
S
Drain-Source Body Diode Characteristics
D
MOSFET symbol
showing the
integral reverse
p - n junction diode
Continuous Source-Drain Diode Current
IS
-
-
-
-
- 8.8
- 35
A
G
Pulsed Diode Forward Currenta
ISM
S
Body Diode Voltage
VSD
trr
TJ = 25 °C, IS = - 8.8 A, VGS = 0 Vb
-
-
-
-
- 6.3
200
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
100
0.32
ns
µC
TJ = 25 °C, IF = - 11 A, dI/dt = 100 A/µsb
Qrr
ton
0.64
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
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2
IRFR9024, IRFU9024, SiHFR9024, SiHFU9024
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 2 -Typical Output Characteristics, TC = 150 °C
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3
IRFR9024, IRFU9024, SiHFR9024,
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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IRFR9024, IRFU9024, SiHFR9024, SiHFU9024
RD
VDS
VGS
D.U.T.
RG
+
V
-
DD
- 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
td(on) tr
td(off) tf
VGS
10 %
90 %
VDS
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFR9024, IRFU9024, SiHFR9024,
L
IAS
VDS
Vary tp to obtain
required IAS
VDS
D.U.T.
IAS
RG
-
V
+
DD
VDD
tp
- 10 V
0.01 Ω
tp
VDS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
- 10 V
12 V
0.2 µF
0.3 µF
-
QGS
QGD
V
+
DS
D.U.T.
VG
VGS
- 3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
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IRFR9024, IRFU9024, SiHFR9024, SiHFU9024
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-
+
-
+
-
RG
+
-
• dV/dt controlled by RG
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VDD
Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
Period
D =
P.W.
V
= - 10 V*
GS
D.U.T. I waveform
SD
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V waveform
DS
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Ripple ≤ 5 %
Inductor current
I
SD
* VGS = - 5 V for logic level and - 3 V drive devices
Fig. 14 - For P-Channel
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