C1206C105M3VACTU_技术文档

SurfaceꢀMountꢀMultilayerꢀCeramicꢀChipꢀCapacitorsꢀ(SMDꢀMLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Overview

KEMET’s Y5V dielectric features an 85°C maximum

applicationsꢀinꢀwhichꢀdielectricꢀlosses,ꢀhighꢀinsulationꢀresistanceꢀ

operating temperature and is considered “general-purpose.”

TheꢀElectronicsꢀComponents,ꢀAssembliesꢀ&ꢀMaterialsꢀ

Associationꢀ(EIA)ꢀcharacterizesꢀY5VꢀdielectricꢀasꢀaꢀClassꢀIIIꢀ

material.ꢀComponentsꢀofꢀthisꢀclassiﬁcationꢀareꢀﬁxed,ꢀceramicꢀ

dielectricꢀcapacitorsꢀsuitedꢀforꢀbypassꢀandꢀdecouplingꢀorꢀotherꢀ

andꢀcapacitanceꢀstabilityꢀareꢀnotꢀofꢀmajorꢀimportance.ꢀY5Vꢀexhibitsꢀ

aꢀpredictableꢀchangeꢀinꢀcapacitanceꢀwithꢀrespectꢀtoꢀtimeꢀandꢀ

voltageꢀandꢀdisplaysꢀwideꢀvariationsꢀinꢀcapacitanceꢀwithꢀreferenceꢀ

toꢀambientꢀtemperature.ꢀCapacitanceꢀchangeꢀisꢀlimitedꢀtoꢀ+22%,ꢀ

-82% from -30°C to +85°C.

Applications

Beneﬁts

Typical applications include limited temperature, decoupling and

bypass.

• -30°C to +85°C operating temperature range

• Lead (Pb)-Free, RoHS and REACH compliant

• EIA 0402, 0603, 0805, 1206, and 1210 case sizes

• DC voltage ratings of 6.3 V, 10 V, 16 V, 25 V, and 50 V

•ꢀ Capacitanceꢀofferingsꢀrangingꢀfromꢀ0.022ꢀμFꢀtoꢀ22ꢀμF

• Available capacitance tolerance of +80%/ -20%

• Non-polar device, minimizing installation concerns

•ꢀ 100%ꢀpureꢀmatteꢀtin-platedꢀterminationꢀﬁnishꢀthatꢀallowingꢀforꢀ

excellent solderability

Click image above for interactive 3D content

Open PDF in Adobe Reader for full functionality

Ordering Information

C

1210

C

226

Z

4

V

A

C

TU

Case Size Speciﬁcation/

Capacitance

Code (pF)

Capacitance

Tolerance

Failure Rate/

Design

Packaging/Grade

(C-Spec)²

Ceramic

Voltage Dielectric

TerminationꢀFinish¹

(L" x W")

Series

0402

0603

0805

1206

1210

C = Standard 2ꢀSigniﬁcantꢀDigitsꢀ Z = +80%/ -20% 9 = 6.3 V V = Y5V

A = N/A

C = 100% Matte Sn Blank = Bulk

TU = 7" Reel

+ Number of Zeros

8 = 10 V

4 = 16 V

3 = 25 V

5 = 50 V

Unmarked

¹Additional termination ﬁnish options may be available. Contact KEMET for details.

²Additional reeling or packaging options may be available. Contact KEMET for details.

One world. One KEMET

C1005_Y5V_SMD • 6/6/2014

1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Dimensions – Millimeters (Inches)

L

W

T

B

S

EIA

Size

Code

Metric

Size

Code

S

L

W

Width

T

B

Mounting

Technique

Separation

Minimum

Length

Thickness

Bandwidth

0402

0603

0805

1206

1210

1005

1608

2012

3216

3225

1.00 (.040) ± 0.05 (.002) 0.50 (.020) ± 0.05 (.002)

1.60 (.063) ± 0.15 (.006) 0.80 (.032) ± 0.15 (.006)

2.00 (.079) ± 0.20 (.008) 1.25 (.049) ± 0.20 (.008)

3.20 (.126) ± 0.20 (.008) 1.60 (.063) ± 0.20 (.008)

3.20 (.126) ± 0.20 (.008) 2.50 (.098) ± 0.20 (.008)

0.30 (.012) ± 0.10 (.004)

0.35 (.014) ± 0.15 (.006)

0.50 (0.02) ± 0.25 (.010)

0.30 (.012)

0.70 (.028)

0.75 (.030)

SolderꢀReﬂowꢀOnly

See Table 2 for

Thickness

Solder Wave or Solder

Reﬂow

N/A

SolderꢀReﬂowꢀOnly

Qualiﬁcation/Certiﬁcation

CommercialꢀGradeꢀproductsꢀareꢀsubjectꢀtoꢀinternalꢀqualiﬁcation.ꢀDetailsꢀregardingꢀtestꢀmethodsꢀandꢀconditionsꢀareꢀreferencedꢀinꢀ

Tableꢀ4,ꢀPerformanceꢀ&ꢀReliability.

Environmental Compliance

Leadꢀ(Pb)-Free,ꢀRoHS,ꢀandꢀREACHꢀcompliantꢀwithoutꢀexemptionsꢀ(excludingꢀSnPbꢀterminationꢀﬁnishꢀoption).ꢀ

C1005_Y5V_SMD • 6/6/2014

2

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

Operating Temperature Range

-30°C to +85°C

+22%, -82%

7.0%

CapacitanceꢀChangeꢀwithꢀReferenceꢀtoꢀ+25°Cꢀandꢀ0ꢀVDCꢀAppliedꢀ(TCC)

Aging Rate (Maximum % Capacitance Loss/Decade Hour)

250% of rated voltage

DielectricꢀWithstandingꢀVoltageꢀ(DWV)

Dissipation Factor (DF) Maximum Limit @ 25ºC

Insulation Resistance (IR) Limit @ 25°C

(5ꢀ±1ꢀsecondsꢀandꢀcharge/dischargeꢀnotꢀexceedingꢀ50ꢀmA)

10% (6.3 and 10 V), 7% (16 and 25 V) and 5% (50 V)

See Insulation Resistance Limit Table

(Rated voltage applied for 120 ±5 seconds @ 25°C)

Regarding aging rate: Capacitance measurements (including tolerance) are indexed to a referee time of 1,000 hours.

To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Capacitance and Dissipation Factor (DF) measured under the following conditions:

1 kHz ±50 Hz and 1.0 ±0.2 Vrms

120 Hz ±10 Hz and 0.5 ±0.1 Vrms if capacitance >10 µF

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known as

Automatic Level Control (ALC). The ALC feature should be switched to "ON."

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Rated DC

Voltage

Capacitance

Value

Dissipation Factor

(Maximum %)

Capacitance

Insulation

Resistance

Dielectric

Y5V

Shiftꢀ

> 25

16/25

< 16

7.5

All

10.0

15.0

±30%

10% of Initial Limit

Insulation Resistance Limit Table

100 Megohm

EIA Case Size

50 Megohm

Microfarads or 10 GΩ

All

≥ꢀ16ꢀV

≤ꢀ10ꢀV

C1005_Y5V_SMD • 6/6/2014

3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Table 1 – Capacitance Range/Selection Waterfall (0402 – 1210 Case Sizes)

Case Size/

Series

Voltage Code

C0402C

C0603C

C0805C

C1206C

C1210C

9

8

4

9

8

4

3

9

8

4

3

5

9

8

4

3

5

9

8

4

3

5

Capacitance

Code

Capacitance

Rated Voltage (VDC)

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

Capacitance Tolerance

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

0.12 µF

0.15 µF

0.18 µF

0.22 µF

0.27 µF

0.33 µF

0.39 µF

0.47 µF

0.56 µF

0.68 µF

0.82 µF

1.0 µF

223

273

333

393

473

563

683

823

104

124

154

184

224

274

334

394

474

564

684

824

105

125

155

185

225

335

475

565

685

106

156

226

M

Z

BB BB BB CF CF CF CF DC DC DC DC DC

BB BB BB CF CF CF CF DD DD DD DD DD

BB² BB¹ BB¹ CF CF CF CF DD DD DD DD DD

BB BB BB CF CF CF CF DD DD DD DD DD

BB BB BB CG CG CG CG DC DC DC DC DC

CG CG CG CG DC DC DC DC

BB

CG CG CG CG DC DC DC DC DG EC EC EC EC

FD FD FD FD FD

FF FF FF FF FF

FH FH FH FH FH

FD FD FD

FJ FJ FJ

FE FE FE

FT FT FT

FG FG FG

FH FH FH

FT FT FT

CG CG CG CG DC DC DC DC

EB EB EB EB

EC EC EC EC

EB EB EB EB

CG CG CG

CG CG

DC DC DC DC

DD DD DD DD

DE DE DE DE

DG DG DG DG

BB

BB BB

CG CG CG CG DG DG DG DG DG EF EF EF EG

1.2 µF

1.5 µF

1.8 µF

2.2 µF

3.3 µF

4.7 µF

5.6 µF

6.8 µF

DC DC DC

DD DD DD

DG DG DG

DL DL DG

DG DG DG

DF DF

EC EC EC

ED ED ED

EH EH EH

EM EM EM

EJ EJ EJ

EJ EJ

DG DG

10 µF

15 µF

22 µF

EH EH EH EH

FH FH FH

FH FH FH FH

EH EH

Rated Voltage (VDC)

Voltage Code

Capacitance

Code

9

8

4

9

8

4

3

9

8

4

3

5

9

8

4

3

5

9

8

4

3

5

Capacitance

Case Size/

Series

C0402C

C0603C

C0805C

C1206C

C1210C

C1005_Y5V_SMD • 6/6/2014

4

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Table 2 – Chip Thickness/Packaging Quantities

Paper Quantity

Plastic Quantity

7" Reel 13" Reel

Thickness Case Thickness ±

Code

Size

Range (mm)

7" Reel

13" Reel

BB

CF

CG

DC

DD

DL

DE

DF

DG

EB

EC

EH

ED

EF

EM

EG

EJ

0402

0603

0805

1206

1210

0.50 ± 0.05

0.80 ± 0.07

0.80 ± 0.10

0.78 ± 0.10

0.90 ± 0.10

0.95 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

0.78 ± 0.10

0.90 ± 0.10

1.00 ± 0.10

1.20 ± 0.15

1.25 ± 0.15

1.60 ± 0.15

1.70 ± 0.20

0.95 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

1.55 ± 0.15

1.85 ± 0.20

1.90 ± 0.20

10,000

4,000

0

50,000

15,000

10,000

0

4,000

2,500

4,000

2,500

2,000

4,000

2,500

2,000

1,500

10,000

8,000

10,000

8,000

4,000

0

4,000

10,000

0

FD

FE

FF

FG

FH

FJ

FT

7" Reel

13" Reel

7" Reel

13" Reel

Thickness

Code

Case

Size

Thickness ±

Range (mm)

Paper Quantity

Plastic Quantity

Package quantity based on ﬁnished chip thickness speciﬁcations.

C1005_Y5V_SMD • 6/6/2014

5

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC-7351

Density Level A:

Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

EIA

Size

Code

Metric

Size

Code

C

Y

X

V1

V2

C

Y

X

V1

V2

C

Y

X

V1

V2

0402

0603

0805

1206

1210

1210¹

1005

1608

2012

3216

3225

0.50

0.72

2.20

1.20

0.45

0.62

1.90

1.00

0.40

0.52

1.60

0.80

0.90

1.00

1.60

1.50

1.15

1.35

1.60

1.10

1.55

1.90

2.80

2.90

4.00

4.40

5.60

5.65

5.60

2.10

2.60

2.90

3.80

3.90

0.80

0.90

1.50

1.40

0.95

1.15

1.40

1.00

1.45

1.80

2.70

2.80

3.10

3.50

4.70

1.50

2.00

2.30

3.20

3.30

0.60

0.75

1.40

1.30

0.75

0.95

1.20

0.90

1.35

1.70

2.60

2.70

2.40

2.80

4.00

1.20

1.70

2.00

2.90

3.00

¹Only for capacitance values ≥ 22 µF

Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reﬂow solder

processes. KEMET only recommends wave soldering of EIA 0603, 0805, and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reﬂow solder processes.

Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform qualiﬁcation

testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).

Image below based on Density Level B for an EIA 1210 case size.

V1

Y

V2

X

C

Grid Placement Courtyard

C1005_Y5V_SMD • 6/6/2014

6

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Soldering Process

Recommended Soldering Technique:

ꢀ •ꢀSolderꢀwaveꢀorꢀsolderꢀreﬂowꢀforꢀEIAꢀcaseꢀsizesꢀ0603,ꢀ0805ꢀandꢀ1206

ꢀ •ꢀAllꢀotherꢀEIAꢀcaseꢀsizesꢀareꢀlimitedꢀtoꢀsolderꢀreﬂowꢀonly

Recommended Reﬂow Soldering Proﬁle:

KEMET’sꢀfamiliesꢀofꢀsurfaceꢀmountꢀmultilayerꢀceramicꢀcapacitorsꢀ(SMDꢀMLCCs)ꢀareꢀcompatibleꢀwithꢀwaveꢀ(singleꢀorꢀdual),ꢀconvection,ꢀ

IRꢀorꢀvaporꢀphaseꢀreﬂowꢀtechniques.ꢀPreheatingꢀofꢀtheseꢀcomponentsꢀisꢀrecommendedꢀtoꢀavoidꢀextremeꢀthermalꢀstress.ꢀKEMET’sꢀ

recommendedꢀproﬁleꢀconditionsꢀforꢀconvectionꢀandꢀIRꢀreﬂowꢀreﬂectꢀtheꢀproﬁleꢀconditionsꢀofꢀtheꢀIPC/J-STD-020ꢀstandardꢀforꢀmoistureꢀ

sensitivityꢀtesting.ꢀTheseꢀdevicesꢀcanꢀsafelyꢀwithstandꢀaꢀmaximumꢀofꢀthreeꢀreﬂowꢀpassesꢀatꢀtheseꢀconditions.

T_P

T_L

Termination Finish

t_P

Maximum Ramp Up Rate = 3°C/sec

Maximum Ramp Down Rate = 6°C/sec

Proﬁle Feature

SnPb

100% Matte Sn

t_L

Preheat/Soak

T_smax

T_smin

Temperature Minimum (T_Smin

Temperature Maximum (T_Smax

Time (t_S) from T_Sminto T_Smax

)

100°C

150°C

200°C

)

t_S

60 – 120 seconds

Ramp-Up Rate (T_Lto T_P)

Liquidous Temperature (T_L)

Time Above Liquidous (t_L)

Peak Temperature (T_P)

3°C/second maximum 3°C/second maximum

25

183°C

60 – 150 seconds

235°C

217°C

60 – 150 seconds

260°C

25° C to Peak

Time

TimeꢀWithinꢀ5°CꢀofꢀMaximumꢀ

20 seconds maximum 30 seconds maximum

Peak Temperature (t_P)

Ramp-Down Rate (T_Pto T_L) 6°C/second maximum 6°C/second maximum

Time 25°C to Peak

6 minutes maximum

8 minutes maximum

Temperature

Note 1: All temperatures refer to the center of the package, measured on the

capacitor body surface that is facing up during assembly reﬂow.

C1005_Y5V_SMD • 6/6/2014

7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress

Reference

Test or Inspection Method

TerminalꢀStrength

JIS–C–6429

Appendix 1, Note: Force of 1.8 kg for 60 seconds.

Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm for C0G.

Flexible termination system – 3.0 mm (minimum).

Board Flex

JIS–C–6429

Magniﬁcationꢀ50ꢀX.ꢀConditions:

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀa)ꢀMethodꢀB,ꢀ4ꢀhoursꢀ@ꢀ155°C,ꢀdryꢀheatꢀ@ꢀ235°C

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀb)ꢀMethodꢀBꢀ@ꢀ215°Cꢀcategoryꢀ3

Solderability

J–STD–002

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀc)ꢀMethodꢀD,ꢀcategoryꢀ3ꢀ@ꢀ260°C

Temperature Cycling

Biased Humidity

JESD22ꢀMethodꢀJA–104

MIL–STD–202ꢀMethodꢀ103

1,000ꢀCyclesꢀ(-55°Cꢀtoꢀ+125°C).ꢀMeasurementꢀatꢀ24ꢀhoursꢀ+/-ꢀ2ꢀhoursꢀafterꢀtestꢀconclusion.

LoadꢀHumidity:ꢀ1,000ꢀhoursꢀ85°C/85%ꢀRHꢀandꢀratedꢀvoltage.ꢀAddꢀ100ꢀKꢀohmꢀresistor.ꢀMeasurementꢀ

atꢀ24ꢀhoursꢀ+/-ꢀ2ꢀhoursꢀafterꢀtestꢀconclusion.

LowꢀVoltꢀHumidity:ꢀ1,000ꢀhoursꢀ85°C/85%ꢀRHꢀandꢀ1.5ꢀV.ꢀAddꢀ100ꢀKꢀohmꢀresistor.ꢀ

Measurementꢀatꢀ24ꢀhoursꢀ+/-ꢀ2ꢀhoursꢀafterꢀtestꢀconclusion.

tꢀ=ꢀ24ꢀhours/cycle.ꢀStepsꢀ7aꢀandꢀ7bꢀnotꢀrequired.ꢀUnpowered.

Measurementꢀatꢀ24ꢀhoursꢀ+/-ꢀ2ꢀhoursꢀafterꢀtestꢀconclusion.

-55°C/+125°C. Note: Number of cycles required – 300, maximum transfer time – 20 seconds, dwell

time – 15 minutes. Air – Air.

Moisture Resistance

ThermalꢀShock

MIL–STD–202ꢀMethodꢀ106

MIL–STD–202ꢀMethodꢀ107

MIL–STD–202ꢀMethodꢀ108

HighꢀTemperatureꢀLife

Storage Life

1,000ꢀhoursꢀatꢀ125°Cꢀ(85°CꢀforꢀX5R,ꢀZ5UꢀandꢀY5V)ꢀwithꢀ2ꢀXꢀratedꢀvoltageꢀapplied.

/EIA–198

MIL–STD–202ꢀMethodꢀ108 150°C,ꢀ0ꢀVDCꢀforꢀ1,000ꢀhours.

5ꢀg'sꢀforꢀ20ꢀmin.,ꢀ12ꢀcyclesꢀeachꢀofꢀ3ꢀorientations.ꢀNote:ꢀUseꢀ8"ꢀXꢀ5"ꢀPCBꢀ0.031"ꢀthickꢀ7ꢀsecureꢀ

Vibration

MIL–STD–202ꢀMethodꢀ204 pointsꢀonꢀoneꢀlongꢀsideꢀandꢀ2ꢀsecureꢀpointsꢀatꢀcornersꢀofꢀoppositeꢀsides.ꢀPartsꢀmountedꢀwithinꢀ2"ꢀ

from any secure point. Test from 10 – 2,000 Hz

MechanicalꢀShock

MIL–STD–202ꢀMethodꢀ213 Figureꢀ1ꢀofꢀMethodꢀ213,ꢀConditionꢀF.

Resistance to Solvents MIL–STD–202ꢀMethodꢀ215 Addꢀaqueousꢀwashꢀchemical,ꢀOKEMꢀCleanꢀorꢀequivalent.

Storage and Handling

Ceramicꢀchipꢀcapacitorsꢀshouldꢀbeꢀstoredꢀinꢀnormalꢀworkingꢀenvironments.ꢀWhileꢀtheꢀchipsꢀthemselvesꢀareꢀquiteꢀrobustꢀinꢀotherꢀ

environments,ꢀsolderabilityꢀwillꢀbeꢀdegradedꢀbyꢀexposureꢀtoꢀhighꢀtemperatures,ꢀhighꢀhumidity,ꢀcorrosiveꢀatmospheres,ꢀandꢀlongꢀtermꢀ

storage.ꢀInꢀaddition,ꢀpackagingꢀmaterialsꢀwillꢀbeꢀdegradedꢀbyꢀhighꢀtemperature–ꢀreelsꢀmayꢀsoftenꢀorꢀwarpꢀandꢀtapeꢀpeelꢀforceꢀmayꢀ

increase.ꢀKEMETꢀrecommendsꢀthatꢀmaximumꢀstorageꢀtemperatureꢀnotꢀexceedꢀ40ºCꢀandꢀmaximumꢀstorageꢀhumidityꢀnotꢀexceedꢀ70%ꢀ

relativeꢀhumidity.ꢀTemperatureꢀﬂuctuationsꢀshouldꢀbeꢀminimizedꢀtoꢀavoidꢀcondensationꢀonꢀtheꢀpartsꢀandꢀatmospheresꢀshouldꢀbeꢀfreeꢀofꢀ

chlorineꢀandꢀsulfurꢀbearingꢀcompounds.ꢀForꢀoptimizedꢀsolderabilityꢀchipꢀstockꢀshouldꢀbeꢀusedꢀpromptly,ꢀpreferablyꢀwithinꢀ1.5ꢀyearsꢀofꢀ

receipt.

C1005_Y5V_SMD • 6/6/2014

8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Construction

Detailed Cross Section

Dielectric Material

(BaTiO₃)

Dielectric Material

(BaTiO₃)

Barrier Layer

(Ni)

Termination Finish

(100% Matte Sn)

Base Metal

(Cu)

Inner Electrodes

(Ni)

Base Metal

(Cu)

Barrier Layer

(Ni)

Termination Finish

(100% Matte Sn)

Inner Electrodes

(Ni)

Capacitor Marking (Optional):

Laser marking option is not available on:

•ꢀ C0G,ꢀUltraꢀStableꢀX8RꢀandꢀY5Vꢀdielectricꢀdevicesꢀ

• EIA 0402 case size devices

•ꢀ EIAꢀ0603ꢀcaseꢀsizeꢀdevicesꢀwithꢀFlexibleꢀTerminationꢀoption.

• KPS Commercial and Automotive grade stacked devices.

Theseꢀcapacitorsꢀareꢀsuppliedꢀunmarkedꢀonly.

C1005_Y5V_SMD • 6/6/2014

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Tape & Reel Packaging Information

KEMETꢀoffersꢀmultilayerꢀceramicꢀchipꢀcapacitorsꢀpackagedꢀinꢀ8,ꢀ12ꢀandꢀ16ꢀmmꢀtapeꢀonꢀ7"ꢀandꢀ13"ꢀreelsꢀinꢀaccordanceꢀwithꢀEIAꢀ

Standardꢀ481.ꢀThisꢀpackagingꢀsystemꢀisꢀcompatibleꢀwithꢀallꢀtape-fedꢀautomaticꢀpickꢀandꢀplaceꢀsystems.ꢀSeeꢀTableꢀ2ꢀforꢀdetailsꢀonꢀ

reelingꢀquantitiesꢀforꢀcommercialꢀchips.

Bar Code Label

Anti-Static Reel

®

Embossed Plastic* or

Punched Paper Carrier.

Chip and KPS Orientation in Pocket

(except 1825 Commercial, and 1825 and 2225 Military)

KEMET

Sprocket Holes

Embossment or Punched Cavity

8 mm, 12 mm

or 16 mm Carrier Tape

Anti-Static Cover Tape

(.10 mm (.004") Maximum Thickness)

178 mm (7.00")

or

330 mm (13.00")

*EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only.

Table 5 – Carrier Tape Conﬁguration – Embossed Plastic & Punched Paper (mm)

EIA Case Size

01005 – 0402

0603 – 1210

Tape Size (W)*

Pitch (P₁)*

8

2

4

1805 – 1808

12

16

8

4

≥ꢀ1812

8

KPS 1210

8

KPSꢀ1812ꢀ&ꢀ2220

Arrayꢀ0508ꢀ&ꢀ0612

12

4

*Refer to Figures 1 & 2 for W and P₁carrier tape reference locations.

*Refer to Tables 6 & 7 for tolerance speciﬁcations.

C1005_Y5V_SMD • 6/6/2014 10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ± 0.2 mm]

2

E

1

Po

ØDo

Ao

F

Ko

W

E

2

B

1

Bo

S

1

P

1

T

1

Embossment

For cavity size,

see Note 1 Table 4

Center Lines of Cavity

ØD

1

Cover Tape

is for tape feeder reference only,

including draft concentric about B

B

1

o

.

User Direction of Unreeling

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

D₁Minimum

Note 1

1.0

(0.039)

R Reference S₁Minimum

T

T₁

Tape Size

8 mm

D₀

E₁

P₀

P₂

Note 2

Note 3

Maximum

25.0

(0.984)

1.5 +0.10/-0.0

(0.059 +0.004/-0.0)

1.75 ±0.10

4.0 ±0.10

2.0 ±0.05

0.600

(0.024)

0.600

(0.024)

0.100

(0.004)

12 mm

16 mm

(0.069 ±0.004) (0.157 ±0.004) (0.079 ±0.002)

1.5

(0.059)

30

(1.181)

Variable Dimensions — Millimeters (Inches)

B₁Maximum

Note 4

4.35

(0.171)

E₂

T₂

W

Tape Size

8 mm

Pitchꢀ

F

P₁

A₀,B₀ꢀ&ꢀK₀

Minimum

6.25

(0.246)

Maximum

2.5

(0.098)

Maximum

8.3

(0.327)

3.5 ±0.05

(0.138 ±0.002) (0.157 ±0.004)

4.0 ±0.10

Single (4 mm)

Singleꢀ(4ꢀmm)ꢀ&ꢀ

8.2

10.25

5.5 ±0.05

8.0 ±0.10

4.6

12.3

12 mm

16 mm

Note 5

Double (8 mm)

(0.323)

(0.404)

(0.217 ±0.002) (0.315 ±0.004)

(0.181)

(0.484)

12.1

(0.476)

14.25

(0.561)

7.5 ±0.05 12.0 ±0.10

(0.138 ±0.002) (0.157 ±0.004)

4.6

(0.181)

16.3

(0.642)

Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and

hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 6).

3. If S₁< 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).

4. B₁dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with sufﬁcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3).

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see Figure 4).

(e) for KPS Series product, A₀and B₀are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

C1005_Y5V_SMD • 6/6/2014 11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ± 0.2 mm]

E

1

Po

ØDo

0

A

F

W

2

E

0

B

Bottom Cover Tape

P

1

G

Cavity Size,

See

1

T

1

T

Top Cover Tape

Center Lines of Cavity

Note 1, Table 7

Bottom Cover Tape

User Direction of Unreeling

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

R Reference

Note 2

Tape Size

8 mm

D₀

E₁

P₀

P₂

T₁Maximum

0.10

G Minimum

1.5 +0.10 -0.0

(0.059 +0.004 -0.0)

1.75 ±0.10

(0.069 ±0.004)

4.0 ±0.10

(0.157 ±0.004)

2.0 ±0.05

(0.079 ±0.002) (0.004) Maximum

0.75

(0.030)

25

(0.984)

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

Pitch

E2 Minimum

F

P₁

T Maximum

W Maximum

A₀B₀

2.0 ±0.05

(0.079 ±0.002)

4.0 ±0.10

8.3

(0.327)

8.3

Half (2 mm)

Single (4 mm)

6.25

(0.246)

3.5 ±0.05

(0.138 ±0.002)

1.1

(0.098)

Note 1

8 mm

(0.157 ±0.004)

(0.327)

1. The cavity deﬁned by A₀, B₀and T shall surround the component with sufﬁcient clearance that:

a) the component does not protrude beyond either surface of the carrier tape.

b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

c) rotation of the component is limited to 20° maximum (see Figure 3).

d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).

e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 6).

C1005_Y5V_SMD • 6/6/2014 12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force: 1.0 Kg minimum.

2. Cover Tape Peel Strength: Theꢀtotalꢀpeelꢀstrengthꢀofꢀtheꢀcoverꢀtapeꢀfromꢀtheꢀcarrierꢀtapeꢀshallꢀbe:ꢀ

Tape Width

8 mm

Peel Strength

0.1 to 1.0 Newton (10 to 100 gf)

0.1 to 1.3 Newton (10 to 130 gf)

12 and 16 mm

Theꢀdirectionꢀofꢀtheꢀpullꢀshallꢀbeꢀoppositeꢀtheꢀdirectionꢀofꢀtheꢀcarrierꢀtapeꢀtravel.ꢀTheꢀpullꢀangleꢀofꢀtheꢀcarrierꢀtapeꢀshallꢀbeꢀ165°ꢀtoꢀ180°ꢀ

fromꢀtheꢀplaneꢀofꢀtheꢀcarrierꢀtape.ꢀDuringꢀpeeling,ꢀtheꢀcarrierꢀand/orꢀcoverꢀtapeꢀshallꢀbeꢀpulledꢀatꢀaꢀvelocityꢀofꢀ300ꢀ±10ꢀmm/minute.

3. Labeling:ꢀBarꢀcodeꢀlabelingꢀ(standardꢀorꢀcustom)ꢀshallꢀbeꢀonꢀtheꢀsideꢀofꢀtheꢀreelꢀoppositeꢀtheꢀsprocketꢀholes.ꢀRefer to EIA

Standards 556 and 624.

Figure 3 – Maximum Component Rotation

°

T

Maximum Component Rotation

Top View

Maximum Component Rotation

Side View

Typical Pocket Centerline

Tape

Maximum

°

T

s

Width (mm) Rotation (

)

8,12

16 – 200

20

10

Bo

Tape

Maximum

°

S

Width (mm) Rotation (

)

8,12

16 – 56

72 – 200

20

10

5

Typical Component Centerline

Ao

Figure 4 – Maximum Lateral Movement

Figure 5 – Bending Radius

Embossed

Carrier

Punched

Carrier

8 mm & 12 mm Tape

16 mm Tape

0.5 mm maximum

1.0 mm maximum

R

Bending

Radius

R

C1005_Y5V_SMD • 6/6/2014 13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Figure 6 – Reel Dimensions

Full Radius,

See Note

W3 (Includes

flange distortion

at outer edge)

Access Hole at

Slot Location

(Ø 40 mm minimum)

W

2 (Measured at hub)

D

(See Note)

A

N

C

(Arbor hole

W

1 (Measured at hub)

diameter)

If present,

tape slot in core

for tape start:

2.5 mm minimum width x

10.0 mm minimum depth

B

(see Note)

Note: Drive spokes optional; if used, dimensions B and D shall apply.

Table 8 – Reel Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

Tape Size

8 mm

A

B Minimum

C

D Minimum

178 ±0.20

(7.008 ±0.008)

or

330 ±0.20

(13.000 ±0.008)

1.5

(0.059)

13.0 +0.5/-0.2

(0.521 +0.02/-0.008)

20.2

(0.795)

12 mm

16 mm

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

N Minimum

W₁

W₂Maximum

W₃

8.4 +1.5/-0.0

(0.331 +0.059/-0.0)

14.4

(0.567)

50

(1.969)

12.4 +2.0/-0.0

18.4

Shallꢀaccommodateꢀtapeꢀwidthꢀ

withoutꢀinterference

12 mm

16 mm

(0.488 +0.078/-0.0)

(0.724)

16.4 +2.0/-0.0

(0.646 +0.078/-0.0)

22.4

(0.882)

C1005_Y5V_SMD • 6/6/2014 14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

Embossed Carrier

Carrier Tape

Round Sprocket Holes

Punched Carrier

8 mm & 12 mm only

START

END

Top Cover Tape

Elongated Sprocket Holes

(32 mm tape and wider)

100 mm

Minimum Leader

400 mm Minimum

Trailer

160 mm Minimum

Components

Top Cover Tape

Figure 8 – Maximum Camber

Elongated sprocket holes

(32 mm & wider tapes)

Carrier Tape

Round Sprocket Holes

1 mm Maximum, either direction

Straight Edge

250 mm

Figure 9 – Bulk Cassette Packaging (Ceramic Chips Only)

Meets Dimensional Requirements IEC–286 and EIAJ 7201

Unit mm *Reference

53 3*

10*

1.5 ± ⁰₀^.1

2.0 ± ₀⁰_.1

3.0 ± ⁰₀^.2

5 0*

110 ± 0.7

Table 9 – Capacitor Dimensions for Bulk Cassette

Cassette Packaging – Millimeters

EIA Size Metric Size

S Separation

Minimum

Number of

Pieces/Cassette

L Length

W Width

B Bandwidth

T Thickness

Code

0402

1005

1.0 ±0.05

1.6 ±0.07

0.5 ±0.05

0.8 ±0.07

0.2 to 0.4

0.2 to 0.5

0.3

0.5 ±0.05

0.8 ±0.07

50,000

0603

1608

0.7

15,000

C1005_Y5V_SMD • 6/6/2014 15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

KEMET Corporation

World Headquarters

Europe

Asia

Southern Europe

Paris, France

Tel: 33-1-4646-1006

Northeast Asia

Hong Kong

Tel: 852-2305-1168

2835 KEMET Way

Simpsonville, SC 29681

Sasso Marconi, Italy

Tel: 39-051-939111

Shenzhen,ꢀChina

Tel: 86-755-2518-1306

Mailing Address:

P.O. Box 5928

Greenville, SC 29606

Beijing,ꢀChina

Central Europe

Landsberg, Germany

Tel: 49-8191-3350800

Tel: 86-10-5829-1711

www.kemet.com

Tel: 864-963-6300

Fax: 864-963-6521

Shanghai,ꢀChina

Tel: 86-21-6447-0707

Kamen, Germany

Tel: 49-2307-438110

Corporate Ofﬁces

Fort Lauderdale, FL

Tel: 954-766-2800

Taipei, Taiwan

Tel: 886-2-27528585

Northern Europe

Bishop’sꢀStortford,ꢀUnitedꢀKingdomꢀ

Tel: 44-1279-460122

North America

Southeast Asia

Singapore

Southeast

Tel: 65-6586-1900

Lake Mary, FL

Tel: 407-855-8886

Espoo, Finland

Tel: 358-9-5406-5000

Penang, Malaysia

Tel: 60-4-6430200

Northeast

Wilmington, MA

Tel: 978-658-1663

Bangalore, India

Tel: 91-806-53-76817

Central

Novi, MI

Tel: 248-306-9353

West

Milpitas, CA

Tel: 408-433-9950

Mexico

Guadalajara, Jalisco

Tel: 52-33-3123-2141

Note: KEMET reserves the right to modify minor details of internal and external construction at any time in the interest of product improvement. KEMET does not

assume any responsibility for infringement that might result from the use of KEMET Capacitors in potential circuit designs. KEMET is a registered trademark of

KEMET Electronics Corporation.

C1005_Y5V_SMD • 6/6/2014 16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Disclaimer

Allꢀproductꢀspeci ꢀcations,ꢀstatements,ꢀinformationꢀandꢀdataꢀ(collectively,ꢀtheꢀ“Information”)ꢀinꢀthisꢀdatasheetꢀareꢀsubjectꢀtoꢀchange.ꢀTheꢀcustomerꢀisꢀresponsibleꢀforꢀcheckingꢀandꢀ

verifyingꢀtheꢀextentꢀtoꢀwhichꢀtheꢀInformationꢀcontainedꢀinꢀthisꢀpublicationꢀisꢀapplicableꢀtoꢀanꢀorderꢀatꢀtheꢀtimeꢀtheꢀorderꢀisꢀplaced.

AllꢀInformationꢀgivenꢀhereinꢀisꢀbelievedꢀtoꢀbeꢀaccurateꢀandꢀreliable,ꢀbutꢀitꢀisꢀpresentedꢀwithoutꢀguarantee,ꢀwarranty,ꢀorꢀresponsibilityꢀofꢀanyꢀkind,ꢀexpressedꢀorꢀimplied.

StatementsꢀofꢀsuitabilityꢀforꢀcertainꢀapplicationsꢀareꢀbasedꢀonꢀKEMETꢀElectronicsꢀCorporation’sꢀ(“KEMET”)ꢀknowledgeꢀofꢀtypicalꢀoperatingꢀconditionsꢀforꢀsuchꢀapplications,ꢀbutꢀareꢀ

notꢀintendedꢀtoꢀconstituteꢀ–ꢀandꢀKEMETꢀspeci ꢀcallyꢀdisclaimsꢀ–ꢀanyꢀwarrantyꢀconcerningꢀsuitabilityꢀforꢀaꢀspeci ꢀcꢀcustomerꢀapplicationꢀorꢀuse.ꢀTheꢀInformationꢀisꢀintendedꢀforꢀuseꢀonlyꢀ

byꢀcustomersꢀwhoꢀhaveꢀtheꢀrequisiteꢀexperienceꢀandꢀcapabilityꢀtoꢀdetermineꢀtheꢀcorrectꢀproductsꢀforꢀtheirꢀapplication.ꢀAnyꢀtechnicalꢀadviceꢀinferredꢀfromꢀthisꢀInformationꢀorꢀotherwiseꢀ

providedꢀbyꢀKEMETꢀwithꢀreferenceꢀtoꢀtheꢀuseꢀofꢀKEMET’sꢀproductsꢀisꢀgivenꢀgratis,ꢀandꢀKEMETꢀassumesꢀnoꢀobligationꢀorꢀliabilityꢀforꢀtheꢀadviceꢀgivenꢀorꢀresultsꢀobtained.

AlthoughꢀKEMETꢀdesignsꢀandꢀmanufacturesꢀitsꢀproductsꢀtoꢀtheꢀmostꢀstringentꢀqualityꢀandꢀsafetyꢀstandards,ꢀgivenꢀtheꢀcurrentꢀstateꢀofꢀtheꢀart,ꢀisolatedꢀcomponentꢀfailuresꢀmayꢀstillꢀ

occur.ꢀAccordingly,ꢀcustomerꢀapplicationsꢀwhichꢀrequireꢀaꢀhighꢀdegreeꢀofꢀreliabilityꢀorꢀsafetyꢀshouldꢀemployꢀsuitableꢀdesignsꢀorꢀotherꢀsafeguardsꢀ(suchꢀasꢀinstallationꢀofꢀprotectiveꢀ

circuitryꢀorꢀredundancies)ꢀinꢀorderꢀtoꢀensureꢀthatꢀtheꢀfailureꢀofꢀanꢀelectricalꢀcomponentꢀdoesꢀnotꢀresultꢀinꢀaꢀriskꢀofꢀpersonalꢀinjuryꢀorꢀpropertyꢀdamage.

Althoughꢀallꢀproduct–relatedꢀwarnings,ꢀcautionsꢀandꢀnotesꢀmustꢀbeꢀobserved,ꢀtheꢀcustomerꢀshouldꢀnotꢀassumeꢀthatꢀallꢀsafetyꢀmeasuresꢀareꢀindictedꢀorꢀthatꢀotherꢀmeasuresꢀmayꢀnotꢀ

be required.

C1005_Y5V_SMD • 6/6/2014 17


型号：	C1206C105M3VACTU
厂家：	KEMET CORPORATION
描述：	Capacitor, Ceramic, Chip, General Purpose, 1uF, 25V, ±20%, Y5V, 1206 (3216 mm), Sn/NiBar, -30º ~ +85ºC, 7" Reel/Unmarked 电容器
文件：	总17页 (文件大小：1459K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C1206C105M3VACTU [KEMET]

相关型号：

C1206C105M4PAC7025

C1206C105M4RACTU

C1206C105M4VACTU

C1206C105M5RAC

C1206C105M5RACAUTO

C1206C105M5RACTM

C1206C105M8VAC

C1206C105M8VAC

C1206C105M8VAC7800

C1206C105M8VACTU

C1206C105Z3VACTU

C1206C106J1RACTU