C0805C105M4PACTM_技术文档

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Overview

KEMET’s X5R dielectric features an 85°C maximum operating

temperature and is considered “semi-stable.” The Electronics

Components, Assemblies & Materials Association (EIA)

characterizes X5R dielectric as a Class II material. Components

of this classiﬁcation are ﬁxed, ceramic dielectric capacitors

suited for bypass and decoupling applications or for frequency

discriminating circuits where Q and stability of capacitance

characteristics are not critical. X5R exhibits a predictable change

in capacitance with respect to time and voltage and boasts

a minimal change in capacitance with reference to ambient

temperature. Capacitance change is limited to ±15% from -55°C

to +85°C.

Applications

Beneﬁts

Typical applications include decoupling, bypass, and ﬁltering.

• -55°C to +85°C operating temperature range

• Pb-Free and RoHS Compliant

• Temperature stable dielectric

• EIA 0201, 0402, 0603, 0805, 1206, and 1210 case sizes

• DC voltage ratings of 4 V, 6.3 V, 10 V, 16 V, 25 V, 35 V, and 50 V

• Capacitance offerings ranging from 0.01 μF to 100 μF

• Available capacitance tolerances of ±10% and ±20%

• Non-polar device, minimizing installation concerns

• 100% pure matte tin-plated termination ﬁnish allowing for

excellent solderability

Ordering Information

C

1206

C

107

M

9

P

A

C

TU

Case Size

(L" x W")

Speciﬁcation/ Capacitance Code Capacitance

Failure Rate/

Design

Packaging/Grade

(C–Spec)²

Ceramic

Voltage

Dielectric

Termination Finish¹

Series

(pF)

Tolerance

0201

0402

0603

0805

1206

1210

C = Standard

2 Signiﬁcant

Digits + Number M = ±20%

of Zeros

K = ±10%

7 = 4 V

P = X5R A = N/A

C = 100% Matte Sn Blank = Bulk

TU = 7" Reel

9 = 6.3 V

8 = 10 V

4 = 16 V

3 = 25 V

6 = 35 V

5 = 50 V

Unmarked

TM = 7" Reel

Marked

¹Additional termination ﬁnish options may be available. Contact KEMET for details.

²Additional reeling or packaging options may be available. Contact KEMET for details.

One world. One KEMET

C1006_X5R_SMD • 2/27/2013

1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Dimensions – Millimeters (Inches)

100% Tin or SnPb Plate

L

W

B

T

Nickel Plate

S

Conductive Metalization

Electrodes

EIA

Size

Code

Metric

Size

Code

S

L

W

Width

T

B

Mounting

Technique

Separation

Minimum

Length

Thickness

Bandwidth

0201

0402

0603

0805

1206

1210¹

0603

1005

1608

2012

3216

3225

0.60 (.024) ± 0.03 (.001) 0.30 (.012) ± 0.03 (.001)

1.00 (.040) ± 0.05 (.002) 0.50 (.020) ± 0.05 (.002)

1.60 (.063) ± 0.15 (.006) 0.80 (.032) ± 0.15 (.006)

2.00 (.079) ± 0.20 (.008) 1.25 (.049) ± 0.20 (.008)

3.20 (.126) ± 0.20 (.008) 1.60 (.063) ± 0.20 (.008)

3.20 (.126) ± 0.20 (.008) 2.50 (.098) ± 0.20 (.008)

0.15 (.006) ± 0.05 (.002)

0.30 (.012) ± 0.10 (.004)

0.35 (.014) ± 0.15 (.006)

0.50 (0.02) ± 0.25 (.010)

N/A

Solder Reﬂow Only

0.30 (.012)

0.70 (.028)

0.75 (.030)

See Table 2 for

Thickness

Solder Wave or

Solder Reﬂow

N/A

Solder Reﬂow Only

¹For capacitance values ≥ 22 µF add 0.10 (0.004) to the length and width tolerance dimension and add 0.15 (0.006) to the positive bandwidth tolerance dimension.

Qualiﬁcation/Certiﬁcation

Commercial Grade products are subject to internal qualiﬁcation. Details regarding test methods and conditions are referenced in

Table 4, Performance & Reliability.

Environmental Compliance

Pb-Free and RoHS Compliant.

C1006_X5R_SMD • 2/27/2013

2

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

Operating Temperature Range

-55°C to +85°C

±15%

Capacitance Change with Reference to +25°C and 0 VDC Applied (TCC)

Aging Rate (Maximum % Capacitance Loss/Decade Hour)

4.0%

250% of rated voltage

Dielectric Withstanding Voltage (DWV)

Dissipation Factor (DF) Maximum Limit @ 25ºC

Insulation Resistance (IR) Limit @ 25°C

(5 ±1 seconds and charge/discharge not exceeding 50 mA)

See Dissipation Factor Limit Table

See Insulation Resistance Limit Table

(Rated voltage applied for 120 ±5 seconds @ 25°C)

Regarding aging rate: Capacitance measurements (including tolerance) are indexed to a referee time of 48 or 1,000 hours. Please refer to a part number speciﬁc

datasheet for referee time details.

To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Capacitance and dissipation factor (DF) measured under the following conditions:

1 kHz ±50 Hz and 1.0 ±0.2 Vrms if capacitance ≤ 10 µF

120 Hz ±10 Hz and 0.5 ±0.1 Vrms if capacitance > 10 µF

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known as

Automatic Level Control (ALC). The ALC feature should be switched to "ON."

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Rated DC

Voltage

Capacitance

Dissipation Factor

(Maximum %)

Capacitance

Insulation

Resistance

Dielectric

X5R

Value

Shift

> 25

25

3.0

7.5

All

±20%

10% of Initial Limit

< 25

< 0.56 µF

≥ 0.56 µF

7.5

12.0

Dissipation Factor Limit Table

Rated DC Voltage Capacitance

Dissipation Factor

50 – 200 V

25 V

All

3%

5%

All

< 25 V

< 0.56 µF

≥ 0.56 µF

5%

10%

C1006_X5R_SMD • 2/27/2013

3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Insulation Resistance Limit Table

1,000 Megohm

Microfarads or 100 GΩ

500 Megohm

Microfarads or 10 GΩ

EIA Case Size

0201

0402

0603

0805

1206

1210

N/A

ALL

< 0.012 µF

< 0.047 µF

< 0.22 µF

< 0.39 µF

≥ 0.012 µF

≥ 0.047 µF

≥ 0.22 µF

≥ 0.39 µF

C1006_X5R_SMD • 2/27/2013

4

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Table 1 – Capacitance Range/Selection Waterfall (1005 – 1210 Case Sizes)

Series

C0201

C0402

C0603

C0805

C1206

C1210

Cap

Code

Voltage Code

7

9

8

4

7

9

8

4

3

5

7

9

8

4

3

5

7

9

8

4

3

5

9

8

4

3

5

9

8

4

3

6

5

Cap

Voltage DC

Cap Tolerance

Product Availability and Chip Thickness Codes – See Table 2 for Chip Thickness Dimensions

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 uF

0.12 uF

0.15 uF

0.18 uF

0.22 uF

0.27 uF

0.33 uF

0.39 uF

0.47 uF

0.56 uF

0.68 uF

0.82 uF

1.0 uF

1.2 uF

1.5 uF

1.8 uF

2.2 uF

2.7 uF

3.3 uF

3.9 uF

4.7 uF

5.6 uF

6.8 uF

8.2 uF

10 uF

12 uF

15 uF

18 uF

22 uF

103

123

153

183

223

273

333

393

473

563

683

823

104

124

154

184

224

274

334

394

474

564

684

824

105

125

155

185

225

275

335

395

475

565

685

825

106

126

156

186

226

276

336

396

476

107

K

M

AB AB AB AB

BB BB BB BB

AB AB

BB BB

CC CC CC CC

EB EB EB EB

EC EC EC EC

ED ED ED ED

EE EE EE EE

EF EF EF EF

EF EF EF EG

EC EC EC EC

EE EE EE EE

EF EF EF EF

EH EH EH EH

ED ED ED ED

EH EH EH EH

EK EK EH

FD FD FD FD FD

FF FF FF FF FF

BB BB

DC DC DC DC DC

DD DD DD DD DD

DE DE DE DE DE

DF DF DF DF DF

DG DG DG DG DG

DC DC DC DC

DD DD DD DD

DG DG DG DG

DL DL DL DL

DL DL DL DG

DG DG DG DG

DG DG DH DH DG

DG DG DG

BB BB BB

FH FH FH FH FH FH

FD FD FD FD

FG FG FG FG

FH FH FH FH

FJ FJ FJ FJ

FK FK FK FK

FG FG FG FE

FJ FJ FJ FJ

FK FK FK FG

FT FT FT FH FT¹

FD¹ FD FG

BB¹ BB¹ BB¹

BB¹

CC CC CC CC

CC¹ CC¹

BC¹

CC CC CC

DG DG DG

EK EK EH

ED ED EH

EH EH EH EH

CC¹ CC¹

DG DG DG DG

DG¹ DG¹

FF FF FG

FG FG FH

FH FH FJ FS¹

EH EH¹

27 uF

33 uF

39 uF

47 uF

DH¹ DG¹

EH¹ EH¹

EH¹

FS¹ FS¹ FS¹

FS¹

100 uF

Voltage DC

Voltage Code

7

9

8

4

7

9

8

3

5

4

7

9

8

4

3

5

7

9

8

4

3

5

9

8

4

3

5

9

8

4

3

6

5

Cap

Cap Code

C

1206

C

107

M

9

P

A

C

TU

Series

C0201

C0402

C0603

C0805

C1206

C1210

Case Size

(L" x W")

Speciﬁcation/ Capacitance Code Capacitance

Failure Rate/

Design

Packaging/Grade

(C–Spec)²

xx¹ Availa

C

bl

e

ra

o

m

n

i

l

c

y in M tolerance.

Voltage

Dielectric

Termination Finish¹

Series

(pF)

Tolerance

0201

C = Standard

2 Signiﬁcant

Digits + Number M = ±20%

of Zeros

K = ±10%

7 = 4 V

P = X5R A = N/A

C = 100% Matte Sn Blank = Bulk

TU = 7" Reel

0402

0603

0805

1206

1210

9 = 6.3 V

8 = 10 V

4 = 16 V

3 = 25 V

6 = 35 V

5 = 50 V

Unmarked

TM = 7" Reel

Marked

C1006_X5R_SMD • 2/27/2013

5

Roll Over for

Order Info.

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Table 2 – Chip Thickness/Packaging Quantities

Paper Quantity

7" Reel 13" Reel

Plastic Quantity

7" Reel 13" Reel

Thickness Case Thickness ±

Code

Size

Range (mm)

AB

BB

BC

CC

DC

DD

DL

DE

DF

DG

DH

EB

EK

EC

ED

EE

EF

EH

FD

FE

FF

0201

0402

0603

0805

1206

1210

0.30 ± 0.03

0.50 ± 0.05

0.50 ± 0.10

0.80 ± 0.10

0.78 ± 0.10

0.90 ± 0.10

0.95 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

1.25 ± 0.20

0.78 ± 0.10

0.80 ± 0.10

0.90 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.20 ± 0.15

1.60 ± 0.20

0.95 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

1.55 ± 0.15

1.85 ± 0.20

1.90 ± 0.20

2.10 ± 0.20

2.50 ± 0.20

15,000

10,000

4,000

0

50,000

10,000

0

4,000

2,500

4,000

2,000

4,000

2,500

2,000

4,000

2,500

2,000

1,500

2,000

1,000

10,000

8,000

10,000

8,000

10,000

8,000

4,000

8,000

4,000

0

4,000

10,000

0

FG

FH

FJ

FT

FK

FS

7" Reel

13" Reel

7" Reel

13" Reel

Thickness

Code

Case

Size

Thickness ±

Range (mm)

Paper Quantity

Plastic Quantity

Package quantity based on ﬁnished chip thickness speciﬁcations.

C1006_X5R_SMD • 2/27/2013

6

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC–7351

Density Level A:

Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

EIA

Size

Code

Metric

Size

Code

C

Y

X

V1

V2

C

Y

X

V1

V2

C

Y

X

V1

V2

0201

0402

0603

0805

1206

1210

1210¹

0603

1005

1608

2012

3216

3225

0.38

0.56

0.52

1.80

1.00

0.33

0.46

0.42

1.50

0.80

0.28

0.36

0.32

1.20

0.60

0.50

0.90

1.00

1.60

1.50

0.72

1.15

1.35

1.60

0.72

1.10

1.55

1.90

2.80

2.90

2.20

4.00

4.40

5.60

5.65

5.60

1.20

2.10

2.60

2.90

3.80

3.90

0.45

0.80

0.90

1.50

1.40

0.62

0.95

1.15

1.40

0.62

1.00

1.45

1.80

2.70

2.80

1.90

3.10

3.50

4.70

1.00

1.50

2.00

2.30

3.20

3.30

0.40

0.60

0.75

1.40

1.30

0.52

0.75

0.95

1.20

0.52

0.90

1.35

1.70

2.60

2.70

1.60

2.40

2.80

4.00

0.80

1.20

1.70

2.00

2.90

3.00

¹Only for capacitance values ≥ 22 µF

Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reﬂow solder

processes. KEMET only recommends wave soldering of EIA 0603, 0805 and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reﬂow solder processes.

Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform qualiﬁcation

testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).

Soldering Process

Recommended Soldering Technique:

• Solder wave or solder reﬂow for EIA case sizes 0603, 0805 and 1206

• All other EIA case sizes are limited to solder reﬂow only

Recommended Soldering Proﬁle:

• KEMET recommends following the guidelines outlined in IPC/JEDEC J–STD–020

C1006_X5R_SMD • 2/27/2013

7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress

Reference

Test or Inspection Method

Terminal Strength

JIS–C–6429

Appendix 1, Note: Force of 1.8 kg for 60 seconds.

Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm for C0G.

Flexible termination system – 3.0 mm (minimum).

Board Flex

JIS–C–6429

Magniﬁcation 50 X. Conditions:

a) Method B, 4 hours @ 155°C, dry heat @ 235°C

b) Method B @ 215°C category 3

Solderability

J–STD–002

c) Method D, category 3 @ 260°C

Temperature Cycling

Biased Humidity

JESD22 Method JA–104

MIL–STD–202 Method 103

1,000 Cycles (-55°C to +125°C). Measurement at 24 hours +/- 2 hours after test conclusion.

Load Humidity: 1,000 hours 85°C/85% RH and rated voltage. Add 100 K ohm resistor. Measurement

at 24 hours +/- 2 hours after test conclusion.

Low Volt Humidity: 1,000 hours 85°C/85% RH and 1.5 V. Add 100 K ohm resistor.

Measurement at 24 hours +/- 2 hours after test conclusion.

t = 24 hours/cycle. Steps 7a and 7b not required. Unpowered.

Measurement at 24 hours +/- 2 hours after test conclusion.

-55°C/+125°C. Note: Number of cycles required – 300, maximum transfer time – 20 seconds, dwell

time – 15 minutes. Air – Air.

Moisture Resistance

Thermal Shock

MIL–STD–202 Method 106

MIL–STD–202 Method 107

MIL–STD–202 Method 108

/EIA–198

High Temperature Life

Storage Life

1,000 hours at 125°C (85°C for X5R, Z5U and Y5V) with 2 X rated voltage applied.

MIL–STD–202 Method 108 150°C, 0 VDC for 1,000 hours.

5 g's for 20 min., 12 cycles each of 3 orientations. Note: Use 8" X 5" PCB 0.031" thick 7 secure

MIL–STD–202 Method 204 points on one long side and 2 secure points at corners of opposite sides. Parts mounted within 2"

from any secure point. Test from 10 – 2,000 Hz

Vibration

Mechanical Shock

MIL–STD–202 Method 213 Figure 1 of Method 213, Condition F.

Resistance to Solvents MIL–STD–202 Method 215 Add aqueous wash chemical, OKEM Clean or equivalent.

Storage and Handling

Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in other

environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres, and long term

storage. In addition, packaging materials will be degraded by high temperature– reels may soften or warp and tape peel force may

increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximum storage humidity not exceed 70%

relative humidity. Temperature ﬂuctuations should be minimized to avoid condensation on the parts and atmospheres should be free of

chlorine and sulfur bearing compounds. For optimized solderability chip stock should be used promptly, preferably within 1.5 years of

receipt.

C1006_X5R_SMD • 2/27/2013

8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Construction

Reference

Item

Material

A

B

C

D

E

Finish

100% Matte Sn

Termination

System

Barrier Layer

Base Metal

Ni

Cu

Inner Electrode

Dielectric Material

Ni

BaTiO₃

Note: Image is exaggerated in order to clearly identify all components of construction.

C1006_X5R_SMD • 2/27/2013

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Capacitor Marking (Optional):

These surface mount multilayer ceramic capacitors are

normally supplied unmarked. If required, they can be marked

as an extra cost option. Marking is available on most KEMET

devices but must be requested using the correct ordering

code identiﬁer(s). If this option is requested, two sides of the

ceramic body will be laser marked with a “K” to identify KEMET,

followed by two characters (per EIA–198 - see table below) to

identify the capacitance value. EIA 0603 case size devices are

limited to the “K” character only.

Marking appears in legible contrast. Illustrated below is an

example of an MLCC with laser marking of “KA8”, which

designates a KEMET device with rated capacitance of 100 µF.

Orientation of marking is vendor optional.

_

KA8

Laser marking option is not available on:

• C0G, Ultra Stable X8R and Y5V dielectric devices

• EIA 0402 case size devices

• EIA 0603 case size devices with Flexible Termination option.

• KPS Commercial and Automotive Grade stacked devices.

Capacitance (pF) For Various Alpha/Numeral Identiﬁers

Numeral

Alpha

Character

9

0

1

2

3

4

5

6

7

8

Capacitance (pF)

A

B

C

D

E

F

G

H

J

0.1

0.11

0.12

0.13

0.15

0.16

0.18

0.2

1 0

1.1

1 2

1 3

1 5

1 6

1 8

2 0

2 2

2.4

2.7

3 0

3 3

3 6

3 9

4 3

4.7

5.1

5 6

6 2

6 8

7 5

8 2

9.1

2 5

3 5

4 0

4 5

5 0

6 0

7 0

8 0

9 0

10

11

12

13

15

16

18

20

22

24

27

30

33

36

39

43

47

51

56

62

68

75

82

91

25

35

40

45

50

60

70

80

90

100

110

120

130

150

160

180

200

220

240

270

300

330

360

390

430

470

510

560

620

680

750

820

910

250

350

400

450

500

600

700

800

900

1,000

1,100

1,200

1,300

1,500

1,600

1,800

2,000

2,200

2,400

2,700

3,000

3,300

3,600

3,900

4,300

4,700

5,100

5,600

6,200

6,800

7,500

8,200

9,100

2,500

3,500

4,000

4,500

5,000

6,000

7,000

8,000

9,000

10,000

11,000

12,000

13,000

15,000

16,000

18,000

20,000

22,000

24,000

27,000

30,000

33,000

36,000

39,000

43,000

47,000

51,000

56,000

62,000

68,000

75,000

82,000

91,000

25,000

35,000

40,000

45,000

50,000

60,000

70,000

80,000

90,000

100,000 1,000,000

110,000 1,100,000

120,000 1,200,000

130,000 1,300,000

150,000 1,500,000

160,000 1,600,000

180,000 1,800,000

200,000 2,000,000

220,000 2,200,000

240,000 2,400,000

270,000 2,700,000

300,000 3,000,000

330,000 3,300,000

360,000 3,600,000

390,000 3,900,000

430,000 4,300,000

470,000 4,700,000

510,000 5,100,000

560,000 5,600,000

620,000 6,200,000

680,000 6,800,000

750,000 7,500,000

820,000 8,200,000

910,000 9,100,000

250,000 2,500,000

350,000 3,500,000

400,000 4,000,000

450,000 4,500,000

500,000 5,000,000

600,000 6,000,000

700,000 7,000,000

800,000 8,000,000

900,000 9,000,000

10,000,000

11,000,000

12,000,000

13,000,000

15,000,000

16,000,000

18,000,000

20,000,000

22,000,000

24,000,000

27,000,000

30,000,000

33,000,000

36,000,000

39,000,000

43,000,000

47,000,000

51,000,000

56,000,000

62,000,000

68,000,000

75,000,000

82,000,000

91,000,000

25,000,000

35,000,000

40,000,000

45,000,000

50,000,000

60,000,000

70,000,000

80,000,000

90,000,000

100,000,000

110,000,000

120,000,000

130,000,000

150,000,000

160,000,000

180,000,000

200,000,000

220,000,000

240,000,000

270,000,000

300,000,000

330,000,000

360,000,000

390,000,000

430,000,000

470,000,000

510,000,000

560,000,000

620,000,000

680,000,000

750,000,000

820,000,000

910,000,000

250,000,000

350,000,000

400,000,000

450,000,000

500,000,000

600,000,000

700,000,000

800,000,000

900,000,000

0.22

0.24

0.27

0.3

K

L

M

N

P

Q

R

S

T

U

V

W

X

Y

Z

a

0.33

0.36

0.39

0.43

0.47

0.51

0.56

0.62

0.68

0.75

0.82

0.91

0.25

0.35

0.4

b

d

e

0.45

0.5

f

m

n

0.6

0.7

t

0.8

y

0.9

C1006_X5R_SMD • 2/27/2013 10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Tape & Reel Packaging Information

KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with EIA

Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for details on

reeling quantities for commercial chips.

Bar Code Label

Anti-Static Reel

®

Embossed Plastic* or

Punched Paper Carrier.

Chip and KPS Orientation in Pocket

(except 1825 Commercial, and 1825 and 2225 Military)

KEMET

Sprocket Holes

Embossment or Punched Cavity

8 mm, 12 mm

or 16 mm Carrier Tape

Anti-Static Cover Tape

(.10 mm (.004") Maximum Thickness)

178 mm (7.00")

or

330 mm (13.00")

*EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only.

Table 5 – Carrier Tape Conﬁguration – Embossed Plastic & Punched Paper (mm)

EIA Case Size

01005 – 0402

0603 – 1210

Tape Size (W)*

Pitch (P₁)*

8

2

4

1805 – 1808

12

16

8

4

≥ 1812

8

KPS 1210

8

KPS 1812 & 2220

Array 0508 & 0612

12

4

*Refer to Figures 1 & 2 for W and P₁carrier tape reference locations.

*Refer to Tables 6 & 7 for tolerance speciﬁcations.

C1006_X5R_SMD • 2/27/2013 11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ± 0.2 mm]

2

E

1

Po

ØDo

Ao

F

Ko

W

E

2

B

1

Bo

S

1

P

1

T

1

Embossment

For cavity size,

see Note 1 Table 4

Center Lines of Cavity

ØD

1

Cover Tape

is for tape feeder reference only,

including draft concentric about B

B

1

o

.

User Direction of Unreeling

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

D₁Minimum

Note 1

1.0

(0.039)

R Reference S₁Minimum

T

T₁

Tape Size

8 mm

D₀

E₁

P₀

P₂

Note 2

Note 3

Maximum

25.0

(0.984)

1.5 +0.10/-0.0

(0.059 +0.004/-0.0)

1.75 ±0.10

4.0 ±0.10

2.0 ±0.05

0.600

(0.024)

0.600

(0.024)

0.100

(0.004)

12 mm

16 mm

(0.069 ±0.004) (0.157 ±0.004) (0.079 ±0.002)

1.5

(0.059)

30

(1.181)

Variable Dimensions — Millimeters (Inches)

B₁Maximum

Note 4

4.35

(0.171)

E₂

T₂

W

Tape Size

8 mm

Pitch

F

P₁

A₀,B₀& K₀

Minimum

6.25

(0.246)

Maximum

2.5

(0.098)

Maximum

8.3

(0.327)

3.5 ±0.05

(0.138 ±0.002) (0.157 ±0.004)

4.0 ±0.10

Single (4 mm)

Single (4 mm) &

Double (8 mm)

8.2

10.25

5.5 ±0.05

8.0 ±0.10

4.6

12.3

12 mm

16 mm

Note 5

(0.323)

(0.404)

(0.217 ±0.002) (0.315 ±0.004)

(0.181)

(0.484)

12.1

(0.476)

14.25

(0.561)

7.5 ±0.05 12.0 ±0.10

(0.138 ±0.002) (0.157 ±0.004)

4.6

(0.181)

16.3

(0.642)

Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and

hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 6).

3. If S₁< 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).

4. B₁dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with sufﬁcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3).

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see Figure 4).

(e) for KPS Series product, A₀and B₀are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

C1006_X5R_SMD • 2/27/2013 12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ± 0.2 mm]

E

1

Po

ØDo

0

A

F

W

2

E

0

B

Bottom Cover Tape

P

1

G

Cavity Size,

See

1

T

1

T

Top Cover Tape

Center Lines of Cavity

Note 1, Table 7

Bottom Cover Tape

User Direction of Unreeling

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

R Reference

Note 2

Tape Size

8 mm

D₀

E₁

P₀

P₂

T₁Maximum

G Minimum

1.5 +0.10 -0.0

(0.059 +0.004 -0.0)

1.75 ±0.10

(0.069 ±0.004)

4.0 ±0.10

(0.157 ±0.004)

2.0 ±0.05

(0.079 ±0.002) (0.004) Maximum

0.10

0.75

(0.030)

25

(0.984)

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

Pitch

E2 Minimum

F

P₁

T Maximum

W Maximum

A₀B₀

2.0 ±0.05

(0.079 ±0.002)

4.0 ±0.10

8.3

(0.327)

8.3

Half (2 mm)

Single (4 mm)

6.25

(0.246)

3.5 ±0.05

(0.138 ±0.002)

1.1

(0.098)

Note 1

8 mm

(0.157 ±0.004)

(0.327)

1. The cavity deﬁned by A₀, B₀and T shall surround the component with sufﬁcient clearance that:

a) the component does not protrude beyond either surface of the carrier tape.

b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

c) rotation of the component is limited to 20° maximum (see Figure 3).

d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).

e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 6).

C1006_X5R_SMD • 2/27/2013 13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force: 1.0 Kg minimum.

2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be:

Tape Width

8 mm

Peel Strength

0.1 to 1.0 Newton (10 to 100 gf)

0.1 to 1.3 Newton (10 to 130 gf)

12 and 16 mm

The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be 165° to 180°

from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of 300 ±10 mm/minute.

3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA

Standards 556 and 624.

Figure 3 – Maximum Component Rotation

°

T

Maximum Component Rotation

Top View

Maximum Component Rotation

Side View

Typical Pocket Centerline

Tape

Maximum

°

T

s

Width (mm) Rotation (

)

8,12

16 – 200

20

10

Bo

Tape

Maximum

°

S

Width (mm) Rotation (

)

8,12

16 – 56

72 – 200

20

10

5

Typical Component Centerline

Ao

Figure 4 – Maximum Lateral Movement

Figure 5 – Bending Radius

Embossed

Carrier

Punched

Carrier

8 mm & 12 mm Tape

16 mm Tape

0.5 mm maximum

1.0 mm maximum

R

Bending

Radius

R

C1006_X5R_SMD • 2/27/2013 14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Figure 6 – Reel Dimensions

Full Radius,

See Note

W3 (Includes

flange distortion

at outer edge)

Access Hole at

Slot Location

(Ø 40 mm minimum)

W

2 (Measured at hub)

D

(See Note)

A

N

C

(Arbor hole

W

1 (Measured at hub)

diameter)

If present,

tape slot in core

for tape start:

2.5 mm minimum width x

10.0 mm minimum depth

B

(see Note)

Note: Drive spokes optional; if used, dimensions B and D shall apply.

Table 8 – Reel Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

Tape Size

8 mm

A

B Minimum

C

D Minimum

178 ±0.20

(7.008 ±0.008)

or

330 ±0.20

(13.000 ±0.008)

1.5

(0.059)

13.0 +0.5/-0.2

(0.521 +0.02/-0.008)

20.2

(0.795)

12 mm

16 mm

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

N Minimum

W₁

W₂Maximum

W₃

8.4 +1.5/-0.0

(0.331 +0.059/-0.0)

14.4

(0.567)

50

(1.969)

12.4 +2.0/-0.0

18.4

Shall accommodate tape width

without interference

12 mm

16 mm

(0.488 +0.078/-0.0)

(0.724)

16.4 +2.0/-0.0

(0.646 +0.078/-0.0)

22.4

(0.882)

C1006_X5R_SMD • 2/27/2013 15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

Embossed Carrier

Carrier Tape

Round Sprocket Holes

Punched Carrier

8 mm & 12 mm only

START

END

Top Cover Tape

Elongated Sprocket Holes

(32 mm tape and wider)

100 mm

Minimum Leader

400 mm Minimum

Trailer

160 mm Minimum

Components

Top Cover Tape

Figure 8 – Maximum Camber

Elongated sprocket holes

(32 mm & wider tapes)

Carrier Tape

Round Sprocket Holes

1 mm Maximum, either direction

Straight Edge

250 mm

Bulk Cassette Packaging (Ceramic Chips Only)

Meets Dimensional Requirements IEC–286 and EIAJ 7201

Unit mm *Reference

53 3*

10*

1.5 ± ⁰₀^.1

2.0 ± ₀⁰_.1

3.0 ± ⁰₀^.2

5 0*

110 ± 0.7

Capacitor Dimensions for Bulk Cassette

Cassette Packaging – Millimeters

EIA Size Metric Size

S Separation

Minimum

Number of

Pieces/Cassette

L Length

W Width

B Bandwidth

T Thickness

Code

0402

1005

1.0 ±0.05

1.6 ±0.07

0.5 ±0.05

0.8 ±0.07

0.2 to 0.4

0.2 to 0.5

0.3

0.5 ±0.05

0.8 ±0.07

50,000

0603

1608

0.7

15,000

C1006_X5R_SMD • 2/27/2013 16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

KEMET Corporation

World Headquarters

Europe

Asia

Southern Europe

Paris, France

Tel: 33-1-4646-1006

Northeast Asia

Hong Kong

Tel: 852-2305-1168

2835 KEMET Way

Simpsonville, SC 29681

Sasso Marconi, Italy

Tel: 39-051-939111

Shenzhen, China

Tel: 86-755-2518-1306

Mailing Address:

P.O. Box 5928

Greenville, SC 29606

Beijing, China

Central Europe

Landsberg, Germany

Tel: 49-8191-3350800

Tel: 86-10-5829-1711

www.kemet.com

Tel: 864-963-6300

Fax: 864-963-6521

Shanghai, China

Tel: 86-21-6447-0707

Kamen, Germany

Tel: 49-2307-438110

Corporate Ofﬁces

Fort Lauderdale, FL

Tel: 954-766-2800

Taipei, Taiwan

Tel: 886-2-27528585

Northern Europe

Bishop’s Stortford, United Kingdom

Tel: 44-1279-460122

North America

Southeast Asia

Singapore

Southeast

Tel: 65-6586-1900

Lake Mary, FL

Tel: 407-855-8886

Espoo, Finland

Tel: 358-9-5406-5000

Penang, Malaysia

Tel: 60-4-6430200

Northeast

Wilmington, MA

Tel: 978-658-1663

Bangalore, India

Tel: 91-806-53-76817

Central

Novi, MI

Tel: 248-994-1030

West

Milpitas, CA

Tel: 408-433-9950

Mexico

Guadalajara, Jalisco

Tel: 52-33-3123-2141

Note: KEMET reserves the right to modify minor details of internal and external construction at any time in the interest of product improvement. KEMET does not

assume any responsibility for infringement that might result from the use of KEMET Capacitors in potential circuit designs. KEMET is a registered trademark of

KEMET Electronics Corporation.

C1006_X5R_SMD • 2/27/2013 17

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Other KEMET Resources

Tools

Resource

Location

Conﬁgure A Part: CapEdge

SPICE & FIT Software

http://capacitoredge.kemet.com

http://www.kemet.com/spice

http://www.kemet.com/keask

http://www.kemet.com:8080/elc

Search Our FAQs: KnowledgeEdge

Electrolytic LifeCalculator

Product Information

Resource

Location

Products

Technical Resources (Including Soldering Techniques)

RoHS Statement

http://www.kemet.com/products

http://www.kemet.com/technicalpapers

http://www.kemet.com/rohs

Quality Documents

http://www.kemet.com/qualitydocuments

Product Request

Resource

Location

http://www.kemet.com/sample

http://www.kemet.com/kits

Sample Request

Engineering Kit Request

Contact

Resource

Location

Website

Contact Us

Investor Relations

Call Us

www.kemet.com

http://www.kemet.com/contact

http://www.kemet.com/ir

1-877-MyKEMET

Twitter

http://twitter.com/kemetcapacitors

Disclaimer

All product speciﬁcations, statements, information and data (collectively, the “Information”) are subject to change without notice.

All Information given herein is believed to be accurate and reliable, but is presented without guarantee, warranty, or responsibility of any kind, expressed or implied.

Statements of suitability for certain applications are based on our knowledge of typical operating conditions for such applications, but are not intended to constitute – and we

speciﬁcally disclaim – any warranty concerning suitability for a speciﬁc customer application or use. This Information is intended for use only by customers who have the requisite

experience and capability to determine the correct products for their application. Any technical advice inferred from this Information or otherwise provided by us with reference to the

use of our products is given gratis, and we assume no obligation or liability for the advice given or results obtained.

Although we design and manufacture our products to the most stringent quality and safety standards, given the current state of the art, isolated component failures may still occur.

Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards (such as installation of protective circuitry or

redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or property damage.

Although all product-related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicated or that other measures may not

be required.

C1006_X5R_SMD • 2/27/2013 18

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Digitally signed by Jeannette Calvo

DN: c=US, st=FL, l=Fort Lauderdale, o=KEMET Corp., ou=Marketing

Communications, cn=Jeannette Calvo, email=jeannettecalvo@kemet.com

Date: 2013.03.05 15:31:58 -05'00'

C1006_X5R_SMD • 2/27/2013 19


型号：	C0805C105M4PACTM
厂家：	KEMET CORPORATION
描述：	Ceramic Capacitor, Multilayer, Ceramic, 16V, 20% +Tol, 20% -Tol, X5R, 15% TC, 1uF, Surface Mount, 0805, CHIP, ROHS COMPLIANT 电容器
文件：	总19页 (文件大小：902K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C0805C105M4PACTM [KEMET]

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