C0603C107K4PACTU_技术文档

SurfaceꢀMountꢀMultilayerꢀCeramicꢀChipꢀCapacitorsꢀ(SMDꢀMLCCs)

X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Overview

KEMET’sꢀX5Rꢀdielectricꢀfeaturesꢀanꢀ85°Cꢀmaximumꢀ

orꢀforꢀfrequencyꢀdiscriminatingꢀcircuitsꢀwhereꢀQꢀandꢀstabilityꢀ

operatingꢀtemperatureꢀandꢀisꢀconsideredꢀ“semi-stable.”ꢀTheꢀ

Electronics Components, Assemblies & Materials Association

(EIA)ꢀcharacterizesꢀX5RꢀdielectricꢀasꢀaꢀClassꢀIIꢀmaterial.ꢀ

Componentsꢀofꢀthisꢀclassiﬁcationꢀareꢀﬁxed,ꢀceramicꢀdielectricꢀ

capacitorsꢀsuitedꢀforꢀbypassꢀandꢀdecouplingꢀapplicationsꢀ

ofꢀcapacitanceꢀcharacteristicsꢀareꢀnotꢀcritical.ꢀX5Rꢀexhibitsꢀaꢀ

predictableꢀchangeꢀinꢀcapacitanceꢀwithꢀrespectꢀtoꢀtimeꢀandꢀ

voltageꢀandꢀboastsꢀaꢀminimalꢀchangeꢀinꢀcapacitanceꢀwithꢀ

referenceꢀtoꢀambientꢀtemperature.ꢀCapacitanceꢀchangeꢀisꢀlimitedꢀ

toꢀ±15%ꢀfromꢀ−55°Cꢀtoꢀ+85°C.

Applications

Beneﬁts

Typicalꢀapplicationsꢀincludeꢀdecoupling,ꢀbypass,ꢀandꢀﬁltering.ꢀ

•ꢀ −55°Cꢀtoꢀ+85°Cꢀoperatingꢀtemperatureꢀrange

• Lead (Pb)-Free, RoHS and REACH compliant

•ꢀ Temperatureꢀstableꢀdielectric

• EIA 0201, 0402, 0603, 0805, 1206, 1210, and 1812 case sizes

•ꢀ DCꢀvoltageꢀratingsꢀofꢀ4ꢀV,ꢀ6.3ꢀV,ꢀ10ꢀV,ꢀ16ꢀV,ꢀ25ꢀV,ꢀ35ꢀV,ꢀandꢀ50ꢀV

•ꢀ Capacitanceꢀofferingsꢀrangingꢀfromꢀ0.01ꢀμFꢀtoꢀ100ꢀμF

•ꢀ Availableꢀcapacitanceꢀtolerancesꢀofꢀ±10%ꢀandꢀ±20%

•ꢀ Non-polarꢀdevice,ꢀminimizingꢀinstallationꢀconcerns

•ꢀ 100%ꢀpureꢀmatteꢀtin-platedꢀterminationꢀﬁnishꢀallowingꢀforꢀ

excellent solderability

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Ordering Information

C

1206

C

107

M

9

P

A

C

TU

Case Size Speciﬁcation/ Capacitance

Capacitance RatedꢀVoltageꢀ

FailureꢀRate/

Design

Termination

Packaging/Gradeꢀ

Ceramic

Dielectric

P = X5R

(L" x W")

Series

Code (pF)

Tolerance

(VDC)

Finish¹

(C–Spec)

0201

0402

0603

0805

1206

1210

C = Standard

Two

Kꢀ=ꢀ±10%

Mꢀ=ꢀ±20%

7 = 4

A = N/A

Cꢀ=ꢀ100%ꢀ

Matte Sn

Seeꢀ"Packagingꢀ

C-SpecꢀOrderingꢀ

Options Table"

below

signiﬁcantꢀ

digitsꢀ+ꢀ

numberꢀofꢀ

zeros.

9 = 6.3

8 = 10

4 = 16

3 = 25

6 = 35

5 = 50

¹Additional termination ﬁnish options may be available. Contact KEMET for details.

One world. One KEMET

C1006_X5R_SMD • 2/29/2016

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Packaging C-Spec Ordering Options Table

Packaging/Grade

Packaging Type¹

Ordering Code (C-Spec)

BulkꢀBagꢀ/ꢀUnmarked

7"ꢀReelꢀ/ꢀUnmarked

Notꢀrequiredꢀ(Blank)

TU

7411 (EIA 0603 and smaller case sizes)

13"ꢀReelꢀ/ꢀUnmarked

7" Reel / Marked

7210ꢀ(EIAꢀ0805ꢀandꢀlargerꢀcaseꢀsizes)

TM

7040 (EIA 0603 and smaller case sizes)

13" Reel / Marked

7215ꢀ(EIAꢀ0805ꢀandꢀlargerꢀcaseꢀsizes)

7"ꢀReelꢀ/ꢀUnmarkedꢀ/ꢀ2mmꢀpitch²

13"ꢀReelꢀ/ꢀUnmarkedꢀ/ꢀ2mmꢀpitch²

7081

7082

¹Default packaging is "Bulk Bag". An ordering code C-Spec is not required for "Bulk Bag" packaging.

¹The terms "Marked" and "Unmarked" pertain to laser marking option of capacitors. All packaging options labeled as "Unmarked" will contain capacitors that have

not been laser marked. Please contact KEMET if you require a laser marked option. For more information see "Capacitor Marking".

²The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case size

devices. For more information regarding 2 mm pitch option see "Tape & Reel Packaging Information".

Dimensions – Millimeters (Inches)

L

W

T

B

S

EIA

Size

Code

Metric

Size

Code

S

L

W

Width

T

B

Mounting

Technique

Separation

Minimum

Length

Thickness

Bandwidth

0201

0402¹

0603

0805

1206²

0603

1005

1608

2012

3216

0.60ꢀ(0.024)ꢀ±0.03ꢀ(0.001) 0.30ꢀ(0.012)ꢀ±0.03ꢀ(0.001)

1.00ꢀ(0.040)ꢀ±0.05ꢀ(0.002) 0.50ꢀ(0.020)ꢀ±0.05ꢀ(0.002)

1.60ꢀ(0.063)ꢀ±0.15ꢀ(0.006) 0.80ꢀ(0.032)ꢀ±0.15ꢀ(0.006)

2.00ꢀ(0.079)ꢀ±0.20ꢀ(0.008) 1.25ꢀ(0.049)ꢀ±0.20ꢀ(0.008)

3.20ꢀ(0.126)ꢀ±0.20ꢀ(0.008) 1.60ꢀ(0.063)ꢀ±0.20ꢀ(0.008)

0.15ꢀ(0.006)ꢀ±0.05ꢀ(0.002)

0.30ꢀ(0.012)ꢀ±0.10ꢀ(0.004)

0.35ꢀ(0.014)ꢀ±0.15ꢀ(0.006)

0.50ꢀ(0.02)ꢀ±0.25ꢀ(0.010)

N/A

SolderꢀReﬂowꢀ

Only

0.30 (0.012)

0.70 (0.028)

0.75 (0.030)

SeeꢀTableꢀ2ꢀforꢀ

Thickness

Solder Wave or

SolderꢀReﬂow

N/A

SolderꢀReﬂowꢀ

1210³

3225

3.20ꢀ(0.126)ꢀ±0.20ꢀ(0.008) 2.50ꢀ(0.098)ꢀ±0.20ꢀ(0.008)

0.50ꢀ(0.02)ꢀ±0.25ꢀ(0.010)

Only

¹For capacitance values ≥ 4.7 µF add 0.15 (0.006) to the width and length tolerance dimensions.

²For capacitance values ≥ 22 µF add 0.10 (0.004) to the positive bandwidth tolerance dimension.

³For capacitance values ≥ 22 µF add 0.10 (0.004) to the length and width tolerance dimension and add 0.15 (0.006) to the positive bandwidth tolerance dimension.

C1006_X5R_SMD • 2/29/2016

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Qualiﬁcation/Certiﬁcation

CommercialꢀGradeꢀproductsꢀareꢀsubjectꢀtoꢀinternalꢀqualiﬁcation.ꢀDetailsꢀregardingꢀtestꢀmethodsꢀandꢀconditionsꢀareꢀreferencedꢀinꢀ

Tableꢀ4,ꢀPerformanceꢀ&ꢀReliability.

Environmental Compliance

Leadꢀ(Pb)-Free,ꢀRoHS,ꢀandꢀREACHꢀcompliantꢀwithoutꢀexemptions.ꢀ

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

OperatingꢀTemperatureꢀRange

−55°Cꢀtoꢀ+85°Cꢀꢀ

±15%

CapacitanceꢀChangeꢀwithꢀReferenceꢀtoꢀ+25°Cꢀandꢀ0ꢀVdcꢀAppliedꢀ(TCC)

¹AgingꢀRateꢀ(Maximumꢀ%ꢀCapacitanceꢀLoss/DecadeꢀHour)

5.0%

250%ꢀofꢀratedꢀvoltage

²DielectricꢀWithstandingꢀVoltageꢀ(DWV)

³DissipationꢀFactorꢀ(DF)ꢀMaximumꢀLimitꢀ@ꢀ25°C

⁴InsulationꢀResistanceꢀ(IR)ꢀMinimumꢀLimitꢀ@ꢀ25°C

(5ꢀ±ꢀ1ꢀsecondsꢀandꢀcharge/dischargeꢀnotꢀexceedingꢀ50mA)

See Dissipation Factor Limit Table

SeeꢀInsulationꢀResistanceꢀLimitꢀTable

(Ratedꢀvoltageꢀappliedꢀforꢀ120ꢀ±ꢀ5ꢀsecsꢀ@ꢀ25°C)

¹Regarding Aging Rate: Capacitance measurements (including tolerance) are indexed to a referee time of 48 or 1,000 hours. Please refer to a part number speciﬁc

datasheet for referee time details.

²DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the capacitor.

³Capacitance and dissipation factor (DF) measured under the following conditions:

1 kHz ±50 Hz and 1.0 ±0.2 Vrms if capacitance ≤ 10 µF

120 Hz ±10 Hz and 0.5 ±0.1 Vrms if capacitance > 10 µF

⁴To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known as

Automatic Level Control (ALC). The ALC feature should be switched to "ON."

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Rated DC

Voltage

Capacitance

Dissipation Factor

(Maximumꢀ%)ꢀ

Capacitance

Insulationꢀ

Resistance

Dielectric

X5R

Value

Shiftꢀ

> 25

25

All

3.0

7.5

< 2.2 µF

≥ꢀ2.2ꢀµF

< 0.56 µF

≥ꢀ0.56ꢀµF

20.0

7.5

±20%

10%ꢀofꢀInitialꢀLimit

< 25

20.0

C1006_X5R_SMD • 2/29/2016

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Dissipation Factor Limit Table

Rated

DC Voltage

Dissipation Factor

(Maximum %)

Capacitance

> 25

25

All

2.5

< 2.2 µF

≥ꢀ2.2ꢀµF

< 0.56 µF

≥ꢀ0.56ꢀµF

5.0

10.0

5.0

< 25

10.0

Insulation Resistance Limit Table

1,000 Megohm

EIA Case Size

500 Megohm

Microfarads or 100 GΩ Microfarads or 10 GΩ

100 Megohm

Microfarads

N/A

0201

0402

0603

0805

1206

1210

1812

N/A

ALL

< .012 µF

< .047 µF

< 0.15 µF

< 0.47 µF

< 0.39 µF

< 2.2 µF

≥ꢀ.012ꢀµFꢀ<ꢀ1.0ꢀµF

≥ꢀ.047ꢀµfꢀ<ꢀ1.0ꢀµF

≥ꢀ0.15ꢀµFꢀ<ꢀ1.0ꢀµF

≥ꢀ0.47ꢀµFꢀ<ꢀ1.0ꢀµF

≥ꢀ0.39ꢀµFꢀ<ꢀ1.0ꢀµF

≥ꢀ2.2ꢀµFꢀ

≥ꢀ1.0ꢀµF

N/A

C1006_X5R_SMD • 2/29/2016

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Table 1 – Capacitance Range/Selection Waterfall (0201 – 0805 Case Sizes)

Case Size/

Series

C0201C

C0402C

C0603C

C0805C

Capacitance

Code

Voltage Code

7

9

8

4

7

9

8

4

3

5

7

9

8

4

3

5

7

9

8

4

3

5

Capacitance

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes – See Table 2 for Chip Thickness Dimensions

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

0.12 µF

0.15 µF

0.18 µF

0.22 µF

0.27 µF

0.33 µF

0.39 µF

0.47 µF

0.56 µF

0.68 µF

0.82 µF

1.0 µF

1.2 µF

1.5 µF

1.8 µF

2.2 µF

2.7 µF

3.3 µF

3.9 µF

4.7 µF

5.6 µF

6.8 µF

8.2 µF

10 µF

12 µF

15 µF

18 µF

22 µF

103

123

153

183

223

273

333

393

473

563

683

823

104

124

154

184

224

274

334

394

474

564

684

824

105

125

155

185

225

275

335

395

475

565

685

825

106

126

156

186

226

476

K

M

AB AB AB AB BB BB BB BB

BB BB BB BB

AB AB

BB BB BB BB

CG CG CG CG CG

BB BB

CG CG CG CG

CG CG CG CG CG

CG CG CG CG

CG CG CG CG CJ

BB BB

DG DG DG DG DG

DP DP DP DP DP

DP DP DP DP DE

DF DF DF DF DF

BB BB BB BB

DP DP DP DP DG DG

DN DN DN DN

DP DP DP DP

DG DG DG DG DG

DL DL DL DL

DL DL DL DG

DG DG DG DG

DG DG DG DG DG

DG DG DG

BB BB BB¹

BB¹

CG CG CG CG

CG CG

BE¹ BE¹

CG CG CG

DG DG DG

BF¹ BF¹

CG¹ CG¹ CG¹

DG DG DG DG DH

DG DG DH¹

DH¹ DH¹

47 µF

Rated Voltage (VDC)

Voltage Code

Capacitance

Code

7

9

8

4

7

9

8

3

5

4

7

9

8

4

3

5

7

9

8

4

3

5

Capacitance

Case Size/Series

C0201C

C0402C

C0603C

C0805C

xx¹ Available only in M tolerance.

C1006_X5R_SMD • 2/29/2016

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Table 1 – Capacitance Range/Selection Waterfall (1206 – 1812 Case Sizes)

Case Size/

Series

C1206C

C1210C

C1812C

Capacitance

Code

Voltage Code

9

8

4

3

5

9

8

4

3

6

5

3

6

5

Capacitance

Rated Voltage (VDC)

Cap Tolerance

Product Availability and Chip Thickness Codes – See Table 2 for Chip Thickness Dimensions

0.27 µF

0.33 µF

0.39 µF

0.47 µF

0.56 µF

0.68 µF

0.82 µF

1.0 µF

1.2 µF

1.5 µF

1.8 µF

2.2 µF

2.7 µF

3.3 µF

3.9 µF

4.7 µF

5.6 µF

6.8 µF

8.2 µF

10 µF

274

334

394

474

564

684

824

105

125

155

185

225

275

335

395

475

565

685

825

106

126

156

186

226

476

107

K

M

EB

EC

ED

EE

EF

EP

EC

EF

EH

ED

EH

EK

ED

EH

EB

EC

ED

EE

EF

EP

EC

EF

EH

ED

EH

EK

ED

EH

EB

EC

ED

EE

EF

EP

EC

EF

EH

ED

EH

EB

EC

ED

EE

EF

EP

EC

EF

EH

ED

EH

FD

FF

FH

FD

FJ

FG

FH

FJ

FT

FG

FJ

FK

FT

FD

FF

FG

FS

FS¹

FD

FF

FH

FD

FJ

FG

FH

FJ

FT

FG

FJ

FK

FT

FD

FF

FG

FS

FS¹

FD

FF

FH

FD

FJ

FG

FH

FJ

FT

FG

FJ

FK

FT

FG

FH

FS

FS¹

FD

FF

FH

FD

FJ

FG

FH

FJ

FT

FE

FJ

FD

FF

FH

EH

FG

FT

EH

FT

FS

GK

12 µF

15 µF

18 µF

22 µF

47 µF

100 µF

EH

EH¹

FS

Rated Voltage (VDC)

Voltage Code

Capacitance

Code

9

8

4

3

5

9

8

4

3

6

5

3

6

5

Capacitance

Case Size/Series

C1206C

C1210C

C1812C

xx¹ Available only in M tolerance.

C1006_X5R_SMD • 2/29/2016

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Table 2A – Chip Thickness/Tape & Reel Packaging Quantities

Paper Quantity¹

7" Reel 13" Reel

Plastic Quantity

7" Reel 13" Reel

Thickness Case Thickness ±

Code

Size¹

Range (mm)

AB

BB

BE

BF

CG

CJ

DN

DP

DL

DE

DF

DG

DH

EB

EK

EC

ED

EE

EF

EP

EH

FD

FE

FF

0201

0402

0603

0805

1206

1210

1812

0.30ꢀ±ꢀ0.03

0.50ꢀ±ꢀ0.05

0.50ꢀ±ꢀ0.15

0.50ꢀ±ꢀ0.20

0.80ꢀ±ꢀ0.10*

0.80ꢀ±ꢀ0.15*

0.78ꢀ±ꢀ0.10*

0.90ꢀ±ꢀ0.10*

0.95ꢀ±ꢀ0.10

1.00ꢀ±ꢀ0.10

1.10ꢀ±ꢀ0.10

1.25ꢀ±ꢀ0.15

1.25ꢀ±ꢀ0.20

0.78ꢀ±ꢀ0.10

0.80ꢀ±ꢀ0.10

0.90ꢀ±ꢀ0.10

1.00ꢀ±ꢀ0.10

1.10ꢀ±ꢀ0.10

1.20ꢀ±ꢀ0.15

1.20ꢀ±ꢀ0.20

1.60ꢀ±ꢀ0.20

0.95ꢀ±ꢀ0.10

1.00ꢀ±ꢀ0.10

1.10ꢀ±ꢀ0.10

1.25ꢀ±ꢀ0.15

1.55ꢀ±ꢀ0.15

1.85ꢀ±ꢀ0.20

1.90ꢀ±ꢀ0.20

2.10ꢀ±ꢀ0.20

2.50ꢀ±ꢀ0.30

1.60ꢀ±ꢀ0.20

15,000

10,000

0

50,000

10,000

50,000

0

4,000

15,000

0

4,000

15,000

0

4,000

2,500

4,000

2,000

4,000

2,500

2,000

4,000

2,500

2,000

1,000

10,000

8,000

10,000

8,000

10,000

8,000

4,000

0

4,000

10,000

0

FG

FH

FJ

FT

FK

FS

GK

7" Reel

13" Reel

7" Reel

13" Reel

Thickness

Code

Case

Size¹

Thickness ±

Range (mm)

Paper Quantity¹

Plastic Quantity

Package quantity based on ﬁnished chip thickness speciﬁcations.

¹If ordering using the 2 mm Tape and Reel pitch option, the packaging quantity outlined in the table above will be doubled. This option is limited to EIA 0603 (1608 metric)

case size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.

C1006_X5R_SMD • 2/29/2016

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Table 2B – Bulk Packaging Quantities

Loose Packaging

Packaging Type

BulkꢀBagꢀ(default)

PackagingꢀC-Spec¹

N/A²

Case Size

Packaging Quantities (pieces/unit packaging)

EIA (in)

Metric (mm)

Minimum

Maximum

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

50,000

1

20,000

¹The "Packaging C-Spec" is a 4 to 8 digit code which identiﬁes the packaging type and/or product grade. When ordering, the proper code must be included in the 15th

through 22nd character positions of the ordering code. See "Ordering Information" section of this document for further details. Commercial Grade product ordered without

a packaging C-Spec will default to our standard "Bulk Bag" packaging. Contact KEMET if you require a bulk bag packaging option for Automotive Grade products.

²A packaging C-Spec (see note 1 above) is not required for "Bulk Bag" packaging (excluding Anti-Static Bulk Bag and Automotive Grade products). The 15th through

22nd character positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to out standard "Bulk Bag" packaging.

C1006_X5R_SMD • 2/29/2016

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC–7351

Density Level A:

Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

EIA

Size

Code

Metric

Size

Code

C

Y

X

V1

V2

C

Y

X

V1

V2

C

Y

X

V1

V2

0201

0402

0603

0805

1206

1210

1210¹

0603

1005

1608

2012

3216

3225

0.38

0.56

0.52

1.80

1.00

0.33

0.46

0.42

1.50

0.80

0.28

0.36

0.32

1.20

0.60

0.50

0.90

1.00

1.60

1.50

0.72

1.15

1.35

1.60

0.72

1.10

1.55

1.90

2.80

2.90

2.20

4.00

4.40

5.60

5.65

5.60

1.20

2.10

2.60

2.90

3.80

3.90

0.45

0.80

0.90

1.50

1.40

0.62

0.95

1.15

1.40

0.62

1.00

1.45

1.80

2.70

2.80

1.90

3.10

3.50

4.70

1.00

1.50

2.00

2.30

3.20

3.30

0.40

0.60

0.75

1.40

1.30

0.52

0.75

0.95

1.20

0.52

0.90

1.35

1.70

2.60

2.70

1.60

2.40

2.80

4.00

0.80

1.20

1.70

2.00

2.90

3.00

¹Only for capacitance values ≥ 22 µF

Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reﬂow solder

processes. KEMET only recommends wave soldering of EIA 0603, 0805 and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reﬂow solder processes.

Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform qualiﬁcation

testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).

Image below based on Density Level B for an EIA 1210 case size.

V1

Y

V2

X

C

Grid Placement Courtyard

C1006_X5R_SMD • 2/29/2016

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Soldering Process

Recommended Soldering Technique:

ꢀ •ꢀSolderꢀwaveꢀorꢀsolderꢀreﬂowꢀforꢀEIAꢀcaseꢀsizesꢀ0603,ꢀ0805ꢀandꢀ1206

ꢀ •ꢀAllꢀotherꢀEIAꢀcaseꢀsizesꢀareꢀlimitedꢀtoꢀsolderꢀreﬂowꢀonly

Recommended Reﬂow Soldering Proﬁle:

KEMET’sꢀfamiliesꢀofꢀsurfaceꢀmountꢀmultilayerꢀceramicꢀcapacitorsꢀ(SMDꢀMLCCs)ꢀareꢀcompatibleꢀwithꢀwaveꢀ(singleꢀorꢀdual),ꢀconvection,ꢀ

IRꢀorꢀvaporꢀphaseꢀreﬂowꢀtechniques.ꢀPreheatingꢀofꢀtheseꢀcomponentsꢀisꢀrecommendedꢀtoꢀavoidꢀextremeꢀthermalꢀstress.ꢀKEMET’sꢀ

recommendedꢀproﬁleꢀconditionsꢀforꢀconvectionꢀandꢀIRꢀreﬂowꢀreﬂectꢀtheꢀproﬁleꢀconditionsꢀofꢀtheꢀIPC/J-STD-020ꢀstandardꢀforꢀmoistureꢀ

sensitivityꢀtesting.ꢀTheseꢀdevicesꢀcanꢀsafelyꢀwithstandꢀaꢀmaximumꢀofꢀthreeꢀreﬂowꢀpassesꢀatꢀtheseꢀconditions.

T_P

T_L

Termination Finish

t_P

Maximum Ramp Up Rate = 3°C/sec

Maximum Ramp Down Rate = 6°C/sec

Proﬁle Feature

SnPb

100%ꢀMatteꢀSn

t_L

Preheat/Soak

T_smax

T_smin

TemperatureꢀMinimumꢀ(T_Smin

TemperatureꢀMaximumꢀ(T_Smax

Time (t_S)ꢀfromꢀT_Sminto T_Smax

)

100°C

150°C

200°C

)

t_S

60 – 120 seconds

Ramp-UpꢀRateꢀ(T_Lto T_P)

LiquidousꢀTemperatureꢀ(T_L)

TimeꢀAboveꢀLiquidousꢀ(t_L)

PeakꢀTemperatureꢀ(T_P)

3°C/secondꢀmaximum 3°C/secondꢀmaximum

25

183°C

60 – 150 seconds

235°C

217°C

60 – 150 seconds

260°C

25° C to Peak

Time

TimeꢀWithinꢀ5°CꢀofꢀMaximumꢀ

20ꢀsecondsꢀmaximum 30ꢀsecondsꢀmaximum

PeakꢀTemperatureꢀ(t_P)

Ramp-Down Rate (T_Pto T_L) 6°C/secondꢀmaximum 6°C/secondꢀmaximum

Timeꢀ25°CꢀtoꢀPeakꢀ

6ꢀminutesꢀmaximum

8ꢀminutesꢀmaximum

Temperature

Note 1: All temperatures refer to the center of the package, measured on the

capacitor body surface that is facing up during assembly reﬂow.

C1006_X5R_SMD • 2/29/2016 10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress

Reference

Test or Inspection Method

TerminalꢀStrength

JIS–C–6429

Appendixꢀ1,ꢀNote:ꢀForceꢀofꢀ1.8ꢀkgꢀforꢀ60ꢀseconds.

Appendixꢀ2,ꢀNote:ꢀStandardꢀterminationꢀsystemꢀ–ꢀ2.0ꢀmmꢀ(minimum)ꢀforꢀallꢀexceptꢀ3ꢀmmꢀforꢀC0G.ꢀ

Flexibleꢀterminationꢀsystemꢀ–ꢀ3.0ꢀmmꢀ(minimum).

Board Flex

JIS–C–6429

Magniﬁcationꢀ50ꢀX.ꢀConditions:

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀa)ꢀMethodꢀB,ꢀ4ꢀhoursꢀatꢀ155°C,ꢀdryꢀheatꢀatꢀ235°C

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀb)ꢀMethodꢀBꢀatꢀ215°Cꢀcategoryꢀ3

Solderability

J–STD–002

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀc)ꢀMethodꢀD,ꢀcategoryꢀ3ꢀatꢀ260°C

TemperatureꢀCycling

BiasedꢀHumidity

JESD22ꢀMethodꢀJA–104

MIL–STD–202ꢀMethodꢀ103

1,000ꢀCyclesꢀ(−55°Cꢀtoꢀ+125°C).ꢀMeasurementꢀatꢀ24ꢀhoursꢀ+/-ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

LoadꢀHumidity:ꢀ1,000ꢀhoursꢀ85°C/85%ꢀRHꢀandꢀratedꢀvoltage.ꢀAddꢀ100ꢀKꢀohmꢀresistor.ꢀ

Measurementꢀatꢀ24ꢀhoursꢀ+/-ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

LowꢀVoltꢀHumidity:ꢀ1,000ꢀhoursꢀ85°C/85%ꢀRHꢀandꢀ1.5ꢀV.ꢀAddꢀ100ꢀKꢀohmꢀresistor.ꢀ

Measurementꢀatꢀ24ꢀhoursꢀ+/-ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

tꢀ=ꢀ24ꢀhours/cycle.ꢀStepsꢀ7aꢀandꢀ7bꢀnotꢀrequired.ꢀ

MoistureꢀResistance

ThermalꢀShock

MIL–STD–202ꢀMethodꢀ106

MIL–STD–202ꢀMethodꢀ107

Measurementꢀatꢀ24ꢀhoursꢀ+/-ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

−55°C/+125°C.ꢀNote:ꢀNumberꢀofꢀcyclesꢀrequiredꢀ–ꢀ300.ꢀMaximumꢀtransferꢀtimeꢀ–ꢀ20ꢀseconds.ꢀDwellꢀ

timeꢀ–ꢀ15ꢀminutes.ꢀAirꢀ–ꢀAir.

1,000ꢀhoursꢀatꢀ85°Cꢀwithꢀ2ꢀXꢀratedꢀvoltageꢀappliedꢀexcludingꢀtheꢀfollowing:

Case Size

0402

Capacitance

≥ꢀ0.22ꢀµF

≥ꢀ1.0ꢀµF

Applied Voltage

MIL–STD–202ꢀMethodꢀ108

0603

HighꢀTemperatureꢀLife

/EIA–198

0805

≥ꢀ4.7ꢀµF

1.5 X

1206

≥ꢀ2.2ꢀµF

1210

≥ꢀ10ꢀµF

StorageꢀLife

Vibration

MIL–STD–202ꢀMethodꢀ108

150°C,ꢀ0ꢀVDCꢀforꢀ1,000ꢀhours.

5ꢀg'sꢀforꢀ20ꢀminutes,ꢀ12ꢀcyclesꢀeachꢀofꢀ3ꢀorientations.ꢀNote:ꢀUseꢀ8"ꢀXꢀ5"ꢀPCBꢀ0.031"ꢀthickꢀ7ꢀsecureꢀ

MIL–STD–202ꢀMethodꢀ204 pointsꢀonꢀoneꢀlongꢀsideꢀandꢀ2ꢀsecureꢀpointsꢀatꢀcornersꢀofꢀoppositeꢀsides.ꢀPartsꢀmountedꢀwithinꢀ2"ꢀ

fromꢀanyꢀsecureꢀpoint.ꢀTestꢀfromꢀ10ꢀ–ꢀ2,000ꢀHz

MechanicalꢀShock

MIL–STD–202ꢀMethodꢀ213

Figureꢀ1ꢀofꢀMethodꢀ213,ꢀConditionꢀF.

Resistance to Solvents MIL–STD–202ꢀMethodꢀ215

Addꢀaqueousꢀwashꢀchemical,ꢀOKEMꢀCleanꢀorꢀequivalent.

Storage and Handling

Ceramicꢀchipꢀcapacitorsꢀshouldꢀbeꢀstoredꢀinꢀnormalꢀworkingꢀenvironments.ꢀWhileꢀtheꢀchipsꢀthemselvesꢀareꢀquiteꢀrobustꢀinꢀotherꢀ

environments,ꢀsolderabilityꢀwillꢀbeꢀdegradedꢀbyꢀexposureꢀtoꢀhighꢀtemperatures,ꢀhighꢀhumidity,ꢀcorrosiveꢀatmospheres,ꢀandꢀlongꢀtermꢀ

storage.ꢀInꢀaddition,ꢀpackagingꢀmaterialsꢀwillꢀbeꢀdegradedꢀbyꢀhighꢀtemperature–ꢀreelsꢀmayꢀsoftenꢀorꢀwarpꢀandꢀtapeꢀpeelꢀforceꢀmayꢀ

increase.ꢀKEMETꢀrecommendsꢀthatꢀmaximumꢀstorageꢀtemperatureꢀnotꢀexceedꢀ40ºCꢀandꢀmaximumꢀstorageꢀhumidityꢀnotꢀexceedꢀ70%ꢀ

relativeꢀhumidity.ꢀTemperatureꢀﬂuctuationsꢀshouldꢀbeꢀminimizedꢀtoꢀavoidꢀcondensationꢀonꢀtheꢀpartsꢀandꢀatmospheresꢀshouldꢀbeꢀfreeꢀofꢀ

chlorineꢀandꢀsulfurꢀbearingꢀcompounds.ꢀForꢀoptimizedꢀsolderabilityꢀchipꢀstockꢀshouldꢀbeꢀusedꢀpromptly,ꢀpreferablyꢀwithinꢀ1.5ꢀyearsꢀofꢀ

receipt.

C1006_X5R_SMD • 2/29/2016 11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Construction (Typical)

Detailed Cross Section

Dielectric Material

(BaTiO₃)

Dielectric Material

(BaTiO₃)

Barrier Layer

(Ni)

Termination Finish

(100% Matte Sn)

End Termination/

External Electrode

(Cu)

Inner Electrodes

(Ni)

End Termination/

External Electrode

(Cu)

Barrier Layer

(Ni)

Termination Finish

(100% Matte Sn)

Inner Electrodes

(Ni)

C1006_X5R_SMD • 2/29/2016 12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Capacitor Marking (Optional):

Theseꢀsurfaceꢀmountꢀmultilayerꢀceramicꢀcapacitorsꢀareꢀ

normallyꢀsuppliedꢀunmarked.ꢀIfꢀrequired,ꢀtheyꢀcanꢀbeꢀmarkedꢀ

asꢀanꢀextraꢀcostꢀoption.ꢀMarkingꢀisꢀavailableꢀonꢀmostꢀKEMETꢀ

devicesꢀbutꢀmustꢀbeꢀrequestedꢀusingꢀtheꢀcorrectꢀorderingꢀ

codeꢀidenti ꢀer(s).ꢀIfꢀthisꢀoptionꢀisꢀrequested,ꢀtwoꢀsidesꢀofꢀtheꢀ

ceramicꢀbodyꢀwillꢀbeꢀlaserꢀmarkedꢀwithꢀaꢀ“K”ꢀtoꢀidentifyꢀKEMET,ꢀ

followedꢀbyꢀtwoꢀcharactersꢀ(perꢀEIA–198ꢀ-ꢀseeꢀtableꢀbelow)ꢀtoꢀ

identifyꢀtheꢀcapacitanceꢀvalue.ꢀEIAꢀ0603ꢀcaseꢀsizeꢀdevicesꢀareꢀ

limitedꢀtoꢀtheꢀ“K”ꢀcharacterꢀonly.

Markingꢀappearsꢀinꢀlegibleꢀcontrast.ꢀIllustratedꢀbelowꢀisꢀanꢀ

exampleꢀofꢀanꢀMLCCꢀwithꢀlaserꢀmarkingꢀofꢀ“KA8”,ꢀwhichꢀ

designatesꢀaꢀKEMETꢀdeviceꢀwithꢀratedꢀcapacitanceꢀofꢀ100ꢀµF.ꢀ

Orientationꢀofꢀmarkingꢀisꢀvendorꢀoptional.ꢀ

2-Digit

KEMET

Capacitance

ID

Code

Laserꢀmarkingꢀoptionꢀisꢀnot available on:

•ꢀ C0G,ꢀUltraꢀStableꢀX8RꢀandꢀY5Vꢀdielectricꢀdevicesꢀ

• EIA 0402 case size devices

•ꢀ EIAꢀ0603ꢀcaseꢀsizeꢀdevicesꢀwithꢀFlexibleꢀTerminationꢀoption.

•ꢀ KPSꢀCommercialꢀandꢀAutomotiveꢀGradeꢀstackedꢀdevices.

•ꢀ X7Rꢀdielectricꢀproductsꢀinꢀcapacitanceꢀvaluesꢀoutlinedꢀbelow

EIA Case Size

0603

Metric Size Code

Capacitance

≤ꢀ170ꢀpF

1608

2012

3216

3225

4520

4532

4564

5650

5664

0805

≤ꢀ150ꢀpF

1206

≤ꢀ910ꢀpF

1210

≤ꢀ2,000ꢀpF

≤ꢀ3,900ꢀpF

≤ꢀ6,700ꢀpF

≤ꢀ0.018ꢀµF

≤ꢀ0.027ꢀµF

≤ꢀ0.033ꢀµF

1808

1812

1825

2220

2225

C1006_X5R_SMD • 2/29/2016 13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Capacitor Marking (Optional) cont’d

Capacitance (pF) For Various Alpha/Numeral Identiﬁers

Numeral

Alpha

Character

9

0

1

2

3

4

5

6

7

8

Capacitance (pF)

A

B

C

D

E

F

0.1

0.11

0.12

0.13

0.15

0.16

0.18

0.2

1 0

1.1

1 2

1 3

1 5

1 6

1 8

2 0

2 2

2.4

2.7

3 0

3 3

3 6

3 9

4 3

4.7

5.1

5 6

6 2

6 8

7 5

8 2

9.1

2 5

3 5

4 0

4 5

5 0

6 0

7 0

8 0

9 0

10

11

12

13

15

16

18

20

22

24

27

30

33

36

39

43

47

51

56

62

68

75

82

91

25

35

40

45

50

60

70

80

90

100

110

120

130

150

160

180

200

220

240

270

300

330

360

390

430

470

510

560

620

680

750

820

910

250

350

400

450

500

600

700

800

900

1,000

1,100

1,200

1,300

1,500

1,600

1,800

2,000

2,200

2,400

2,700

3,000

3,300

3,600

3,900

4,300

4,700

5,100

5,600

6,200

6,800

7,500

8,200

9,100

2,500

3,500

4,000

4,500

5,000

6,000

7,000

8,000

9,000

10,000

11,000

12,000

13,000

15,000

16,000

18,000

20,000

22,000

24,000

27,000

30,000

33,000

36,000

39,000

43,000

47,000

51,000

56,000

62,000

68,000

75,000

82,000

91,000

25,000

35,000

40,000

45,000

50,000

60,000

70,000

80,000

90,000

100,000 1,000,000

110,000 1,100,000

120,000 1,200,000

130,000 1,300,000

150,000 1,500,000

160,000 1,600,000

180,000 1,800,000

200,000 2,000,000

220,000 2,200,000

240,000 2,400,000

270,000 2,700,000

300,000 3,000,000

330,000 3,300,000

360,000 3,600,000

390,000 3,900,000

430,000 4,300,000

470,000 4,700,000

510,000 5,100,000

560,000 5,600,000

620,000 6,200,000

680,000 6,800,000

750,000 7,500,000

820,000 8,200,000

910,000 9,100,000

250,000 2,500,000

350,000 3,500,000

400,000 4,000,000

450,000 4,500,000

500,000 5,000,000

600,000 6,000,000

700,000 7,000,000

800,000 8,000,000

900,000 9,000,000

10,000,000

11,000,000

12,000,000

13,000,000

15,000,000

16,000,000

18,000,000

20,000,000

22,000,000

24,000,000

27,000,000

30,000,000

33,000,000

36,000,000

39,000,000

43,000,000

47,000,000

51,000,000

56,000,000

62,000,000

68,000,000

75,000,000

82,000,000

91,000,000

25,000,000

35,000,000

40,000,000

45,000,000

50,000,000

60,000,000

70,000,000

80,000,000

90,000,000

100,000,000

110,000,000

120,000,000

130,000,000

150,000,000

160,000,000

180,000,000

200,000,000

220,000,000

240,000,000

270,000,000

300,000,000

330,000,000

360,000,000

390,000,000

430,000,000

470,000,000

510,000,000

560,000,000

620,000,000

680,000,000

750,000,000

820,000,000

910,000,000

250,000,000

350,000,000

400,000,000

450,000,000

500,000,000

600,000,000

700,000,000

800,000,000

900,000,000

G

H

J

0.22

0.24

0.27

0.3

K

L

M

N

P

Qꢀ

R

S

T

0.33

0.36

0.39

0.43

0.47

0.51

0.56

0.62

0.68

0.75

0.82

0.91

0.25

0.35

0.4

Uꢀ

Vꢀ

W

X

Yꢀ

Z

a

b

d

e

0.45

0.5

fꢀ

m

n

0.6

0.7

t

0.8

y

0.9

C1006_X5R_SMD • 2/29/2016 14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Tape & Reel Packaging Information

KEMETꢀoffersꢀmultilayerꢀceramicꢀchipꢀcapacitorsꢀpackagedꢀinꢀ8,ꢀ12ꢀandꢀ16ꢀmmꢀtapeꢀonꢀ7"ꢀandꢀ13"ꢀreelsꢀinꢀaccordanceꢀwithꢀEIAꢀ

Standardꢀ481.ꢀThisꢀpackagingꢀsystemꢀisꢀcompatibleꢀwithꢀallꢀtape-fedꢀautomaticꢀpickꢀandꢀplaceꢀsystems.ꢀSeeꢀTableꢀ2ꢀforꢀdetailsꢀonꢀ

reelingꢀquantitiesꢀforꢀcommercialꢀchips.

Bar Code Label

Anti-Static Reel

®

Embossed Plastic* or

Punched Paper Carrier.

Chip and KPS Orientation in Pocket

(except 1825 Commercial, and 1825 and 2225 Military)

KEMET

Sprocket Holes

Embossment or Punched Cavity

8 mm, 12 mm

or 16 mm Carrier Tape

Anti-Static Cover Tape

(.10 mm (.004") Maximum Thickness)

178 mm (7.00")

or

330 mm (13.00")

*EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only.

Table 5 – Carrier Tape Conﬁguration, Embossed Plastic & Punched Paper (mm)

New 2 mm Pitch Reel Options*

Embossed Plastic Punched Paper

Tape

Packaging

Ordering Code

(C-Spec)

C-3190

7" Reel

13" Reel

7" Reel

13" Reel

EIA Case Size Size

(W)*

Packaging Type/Options

Pitchꢀ(P₁)*

01005 – 0402

0603

8

2

2/4

4

2

2/4

4

Automotiveꢀgradeꢀ7"ꢀreelꢀunmarked

Automotiveꢀgradeꢀ13"ꢀreelꢀunmarked

Commercialꢀgradeꢀ7"ꢀreelꢀunmarked

Commercialꢀgradeꢀ13"ꢀreelꢀunmarked

C-3191

C-7081

0805

8

4

C-7082

1206 – 1210

1805 – 1808

≥ꢀ1812

8

4

* 2 mm pitch reel only available for 0603 EIA case size.

2 mm pitch reel for 0805 EIA case size under development.

12

16

8

4

8

Beneﬁts of Changing from 4 mm to 2 mm Pitching Spacing

• Lower placement costs

•ꢀ Doubleꢀtheꢀpartsꢀonꢀeachꢀreelꢀresultsꢀinꢀfewerꢀreelꢀ

changesꢀandꢀincreasedꢀef ꢀciency

•ꢀ Fewerꢀreelsꢀresultꢀinꢀlowerꢀpackaging,ꢀshippingꢀandꢀ

storageꢀcosts,ꢀreducingꢀwaste

KPS 1210

8

KPS 1812 & 2220

Array 0508 & 0612

12

4

12

4

*Refer to Figures 1 & 2 for W and P₁carrier tape reference locations.

*Refer to Tables 6 & 7 for tolerance speciﬁcations.

C1006_X5R_SMD • 2/29/2016 15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ± 0.2 mm]

2

E

1

Po

ØDo

Ao

F

Ko

W

E

2

B

1

Bo

S

1

P

1

T

1

Embossment

For cavity size,

see Note 1 Table 4

Center Lines of Cavity

ØD

1

Cover Tape

is for tape feeder reference only,

including draft concentric about B

B

1

o

.

User Direction of Unreeling

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

D₁ꢀMinimum

Note 1

1.0

(0.039)

RꢀReference S₁ꢀMinimum

T

T₁

Tape Size

8 mm

D₀

E₁

P₀

P₂

Note 2

Note 3

Maximum

25.0

(0.984)

1.5ꢀ+0.10/-0.0ꢀ

(0.059ꢀ+0.004/-0.0)

1.75ꢀ±0.10ꢀ

4.0ꢀ±0.10ꢀ

2.0ꢀ±0.05

0.600

(0.024)

0.600

(0.024)

0.100

(0.004)

12 mm

16 mm

(0.069ꢀ±0.004) (0.157ꢀ±0.004) (0.079ꢀ±0.002)

1.5

(0.059)

30

(1.181)

Variable Dimensions — Millimeters (Inches)

B₁ꢀMaximum

Note 4

4.35

(0.171)

E₂

T₂

W

Tape Size

8 mm

Pitchꢀ

F

P₁

A₀,B₀& K₀

Minimum

6.25

(0.246)

Maximum

2.5

(0.098)

Maximum

8.3

(0.327)

3.5ꢀ±0.05ꢀ

(0.138ꢀ±0.002) (0.157ꢀ±0.004)

4.0ꢀ±0.10

Singleꢀ(4ꢀmm)

Singleꢀ(4ꢀmm)ꢀ&ꢀ

Doubleꢀ(8ꢀmm)

8.2

10.25

5.5ꢀ±0.05ꢀ

8.0ꢀ±0.10

4.6

12.3

12 mm

16 mm

Note 5

(0.323)

(0.404)

(0.217ꢀ±0.002) (0.315ꢀ±0.004)

(0.181)

(0.484)

12.1

(0.476)

14.25

(0.561)

7.5ꢀ±0.05 12.0ꢀ±0.10

(0.138ꢀ±0.002)ꢀ (0.157ꢀ±0.004)ꢀ

4.6

(0.181)

16.3

(0.642)

Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and

hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 6).

3. If S₁< 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).

4. B₁dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with sufﬁcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3).

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see Figure 4).

(e) for KPS Series product, A₀and B₀are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

C1006_X5R_SMD • 2/29/2016 16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ± 0.2 mm]

E

1

Po

ØDo

0

A

F

W

2

E

0

B

Bottom Cover Tape

P

1

G

Cavity Size,

See

1

T

1

T

Top Cover Tape

Center Lines of Cavity

Note 1, Table 7

Bottom Cover Tape

User Direction of Unreeling

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

RꢀReference

Tape Size

8 mm

D₀

E₁

P₀

P₂

T₁Maximum

GꢀMinimum

Note 2

0.10

1.5ꢀ+0.10ꢀ-0.0ꢀ

(0.059ꢀ+0.004ꢀ-0.0)

1.75ꢀ±0.10ꢀ

(0.069ꢀ±0.004)

4.0ꢀ±0.10ꢀ

(0.157ꢀ±0.004)

2.0ꢀ±0.05ꢀ

(0.079ꢀ±0.002)

0.75

(0.030)

25

(0.984)

(0.004)

Maximum

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

Pitch

E2ꢀMinimum

F

P₁

TꢀMaximum

WꢀMaximum

A₀B₀

2.0ꢀ±0.05ꢀ

(0.079ꢀ±0.002)

ꢀ4.0ꢀ±0.10ꢀ

8.3

(0.327)

8.3

Halfꢀ(2ꢀmm)

Singleꢀ(4ꢀmm)

6.25

(0.246)

3.5ꢀ±0.05ꢀ

(0.138ꢀ±0.002)

1.1

(0.098)

Note 1

8 mm

(0.157ꢀ±0.004)

(0.327)

1. The cavity deﬁned by A₀, B₀and T shall surround the component with sufﬁcient clearance that:

a) the component does not protrude beyond either surface of the carrier tape.

b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

c) rotation of the component is limited to 20° maximum (see Figure 3).

d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).

e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 6).

C1006_X5R_SMD • 2/29/2016 17

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force:ꢀ1.0ꢀKgꢀminimum.

2. Cover Tape Peel Strength: Theꢀtotalꢀpeelꢀstrengthꢀofꢀtheꢀcoverꢀtapeꢀfromꢀtheꢀcarrierꢀtapeꢀshallꢀbe:ꢀ

Tape Width

8 mm

Peel Strength

0.1ꢀtoꢀ1.0ꢀNewtonꢀ(10ꢀtoꢀ100ꢀgf)

0.1ꢀtoꢀ1.3ꢀNewtonꢀ(10ꢀtoꢀ130ꢀgf)

12 and 16 mm

Theꢀdirectionꢀofꢀtheꢀpullꢀshallꢀbeꢀoppositeꢀtheꢀdirectionꢀofꢀtheꢀcarrierꢀtapeꢀtravel.ꢀTheꢀpullꢀangleꢀofꢀtheꢀcarrierꢀtapeꢀshallꢀbeꢀ165°ꢀtoꢀ180°ꢀ

fromꢀtheꢀplaneꢀofꢀtheꢀcarrierꢀtape.ꢀDuringꢀpeeling,ꢀtheꢀcarrierꢀand/orꢀcoverꢀtapeꢀshallꢀbeꢀpulledꢀatꢀaꢀvelocityꢀofꢀ300ꢀ±10ꢀmm/minute.

3. Labeling:ꢀBarꢀcodeꢀlabelingꢀ(standardꢀorꢀcustom)ꢀshallꢀbeꢀonꢀtheꢀsideꢀofꢀtheꢀreelꢀoppositeꢀtheꢀsprocketꢀholes.ꢀRefer to EIA

Standards 556 and 624.

Figure 3 – Maximum Component Rotation

°

T

Maximum Component Rotation

Top View

Maximum Component Rotation

Side View

Typical Pocket Centerline

Tape

Maximum

°

T

s

Width (mm) Rotation (

)

8,12

16 – 200

20

10

Bo

Tape

Maximum

°

S

Width (mm) Rotation (

)

8,12

16 – 56

72 – 200

20

10

5

Typical Component Centerline

Ao

Figure 5 – Bending Radius

Figure 4 – Maximum Lateral Movement

Embossed

Carrier

Punched

Carrier

8 mm & 12 mm Tape

16 mm Tape

0.5 mm maximum

1.0 mm maximum

R

Bending

Radius

R

C1006_X5R_SMD • 2/29/2016 18

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Figure 6 – Reel Dimensions

Full Radius,

See Note

W3 (Includes

flange distortion

at outer edge)

Access Hole at

Slot Location

(Ø 40 mm minimum)

W

2 (Measured at hub)

D

(See Note)

A

N

C

(Arbor hole

W

1 (Measured at hub)

diameter)

If present,

tape slot in core

for tape start:

2.5 mm minimum width x

10.0 mm minimum depth

B

(see Note)

Note: Drive spokes optional; if used, dimensions B and D shall apply.

Table 8 – Reel Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

Tape Size

8 mm

A

BꢀMinimum

C

DꢀMinimum

178ꢀ±0.20ꢀ

(7.008ꢀ±0.008)ꢀ

or

330ꢀ±0.20

(13.000ꢀ±0.008)

1.5

(0.059)

13.0ꢀ+0.5/-0.2ꢀ

(0.521ꢀ+0.02/-0.008)

20.2

(0.795)

12 mm

16 mm

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

NꢀMinimum

W₁

W₂ꢀMaximum

W₃

8.4ꢀ+1.5/-0.0

(0.331ꢀ+0.059/-0.0)

14.4

(0.567)

50

(1.969)

12.4ꢀ+2.0/-0.0

18.4

Shallꢀaccommodateꢀtapeꢀwidthꢀ

withoutꢀinterference

12 mm

16 mm

(0.488ꢀ+0.078/-0.0)ꢀꢀ

(0.724)

16.4ꢀ+2.0/-0.0

(0.646ꢀ+0.078/-0.0)

22.4

(0.882)

C1006_X5R_SMD • 2/29/2016 19

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

Embossed Carrier

Carrier Tape

Round Sprocket Holes

Punched Carrier

8 mm & 12 mm only

START

END

Top Cover Tape

Elongated Sprocket Holes

(32 mm tape and wider)

100 mm

Minimum Leader

400 mm Minimum

Trailer

160 mm Minimum

Components

Top Cover Tape

Figure 8 – Maximum Camber

Elongated sprocket holes

(32 mm & wider tapes)

Carrier Tape

Round Sprocket Holes

1 mm Maximum, either direction

Straight Edge

250 mm

C1006_X5R_SMD • 2/29/2016 20

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

KEMET Corporation

World Headquarters

Europe

Asia

Southern Europe

Sasso Marconi, Italy

Tel: 39-051-939111

Northeast Asia

HongꢀKong

Tel: 852-2305-1168

2835 KEMET Way

Simpsonville, SC 29681

Skopje,ꢀMacedonia

Tel: 389-2-55-14-623

Shenzhen,ꢀChina

Tel: 86-755-2518-1306

MailingꢀAddress:

P.O. Box 5928

Greenville, SC 29606

Beijing,ꢀChina

Central Europe

Landsberg,ꢀGermanyꢀꢀ

Tel: 49-8191-3350800

Tel: 86-10-5877-1075

www.kemet.com

Tel: 864-963-6300

Fax: 864-963-6521

Shanghai,ꢀChina

Tel: 86-21-6447-0707

Kamen, Germany

Tel: 49-2307-438110

Corporate Ofﬁces

FortꢀLauderdale,ꢀFL

Tel: 954-766-2800

Seoul,ꢀSouthꢀKorea

Tel: 82-2-6294-0550

Northern Europe

Wyboston,ꢀUnitedꢀKingdomꢀ

Tel: 44-1480-273082

Taipei, Taiwan

Tel: 886-2-27528585

North America

Northeast

Wilmington,ꢀMA

Tel: 978-658-1663

Espoo, Finland

Tel: 358-9-5406-5000

Southeast Asia

Singapore

Tel: 65-6701-8033

Southeast

Lake Mary, FL

Tel: 407-855-8886

Penang,ꢀMalaysia

Tel: 60-4-6430200

Central

Novi, MI

Tel: 248-994-1030

Bangalore,ꢀIndia

Tel: 91-806-53-76817

Irving,ꢀTX

Tel: 972-915-6041

West

Milpitas, CA

Tel: 408-433-9950

Mexico

Guadalajara,ꢀJaliscoꢀ

Tel: 52-33-3123-2141

Note: KEMET reserves the right to modify minor details of internal and external construction at any time in the interest of product improvement. KEMET does not

assume any responsibility for infringement that might result from the use of KEMET Capacitors in potential circuit designs. KEMET is a registered trademark of

KEMET Electronics Corporation.

C1006_X5R_SMD • 2/29/2016 21

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – X5R Dielectric, 4 – 50 VDC (Commercial Grade)

Disclaimer

Allꢀproductꢀspeci ꢀcations,ꢀstatements,ꢀinformationꢀandꢀdataꢀ(collectively,ꢀtheꢀ“Information”)ꢀinꢀthisꢀdatasheetꢀareꢀsubjectꢀtoꢀchange.ꢀTheꢀcustomerꢀisꢀresponsibleꢀforꢀcheckingꢀandꢀ

verifyingꢀtheꢀextentꢀtoꢀwhichꢀtheꢀInformationꢀcontainedꢀinꢀthisꢀpublicationꢀisꢀapplicableꢀtoꢀanꢀorderꢀatꢀtheꢀtimeꢀtheꢀorderꢀisꢀplaced.

AllꢀInformationꢀgivenꢀhereinꢀisꢀbelievedꢀtoꢀbeꢀaccurateꢀandꢀreliable,ꢀbutꢀitꢀisꢀpresentedꢀwithoutꢀguarantee,ꢀwarranty,ꢀorꢀresponsibilityꢀofꢀanyꢀkind,ꢀexpressedꢀorꢀimplied.

StatementsꢀofꢀsuitabilityꢀforꢀcertainꢀapplicationsꢀareꢀbasedꢀonꢀKEMETꢀElectronicsꢀCorporation’sꢀ(“KEMET”)ꢀknowledgeꢀofꢀtypicalꢀoperatingꢀconditionsꢀforꢀsuchꢀapplications,ꢀbutꢀareꢀ

notꢀintendedꢀtoꢀconstituteꢀ–ꢀandꢀKEMETꢀspeci ꢀcallyꢀdisclaimsꢀ–ꢀanyꢀwarrantyꢀconcerningꢀsuitabilityꢀforꢀaꢀspeci ꢀcꢀcustomerꢀapplicationꢀorꢀuse.ꢀTheꢀInformationꢀisꢀintendedꢀforꢀuseꢀonlyꢀ

byꢀcustomersꢀwhoꢀhaveꢀtheꢀrequisiteꢀexperienceꢀandꢀcapabilityꢀtoꢀdetermineꢀtheꢀcorrectꢀproductsꢀforꢀtheirꢀapplication.ꢀAnyꢀtechnicalꢀadviceꢀinferredꢀfromꢀthisꢀInformationꢀorꢀotherwiseꢀ

providedꢀbyꢀKEMETꢀwithꢀreferenceꢀtoꢀtheꢀuseꢀofꢀKEMET’sꢀproductsꢀisꢀgivenꢀgratis,ꢀandꢀKEMETꢀassumesꢀnoꢀobligationꢀorꢀliabilityꢀforꢀtheꢀadviceꢀgivenꢀorꢀresultsꢀobtained.

AlthoughꢀKEMETꢀdesignsꢀandꢀmanufacturesꢀitsꢀproductsꢀtoꢀtheꢀmostꢀstringentꢀqualityꢀandꢀsafetyꢀstandards,ꢀgivenꢀtheꢀcurrentꢀstateꢀofꢀtheꢀart,ꢀisolatedꢀcomponentꢀfailuresꢀmayꢀstillꢀ

occur.ꢀAccordingly,ꢀcustomerꢀapplicationsꢀwhichꢀrequireꢀaꢀhighꢀdegreeꢀofꢀreliabilityꢀorꢀsafetyꢀshouldꢀemployꢀsuitableꢀdesignsꢀorꢀotherꢀsafeguardsꢀ(suchꢀasꢀinstallationꢀofꢀprotectiveꢀ

circuitryꢀorꢀredundancies)ꢀinꢀorderꢀtoꢀensureꢀthatꢀtheꢀfailureꢀofꢀanꢀelectricalꢀcomponentꢀdoesꢀnotꢀresultꢀinꢀaꢀriskꢀofꢀpersonalꢀinjuryꢀorꢀpropertyꢀdamage.

Althoughꢀallꢀproduct–relatedꢀwarnings,ꢀcautionsꢀandꢀnotesꢀmustꢀbeꢀobserved,ꢀtheꢀcustomerꢀshouldꢀnotꢀassumeꢀthatꢀallꢀsafetyꢀmeasuresꢀareꢀindictedꢀorꢀthatꢀotherꢀmeasuresꢀmayꢀnotꢀ

beꢀrequired.

C1006_X5R_SMD • 2/29/2016 22


型号：	C0603C107K4PACTU
厂家：	KEMET CORPORATION
描述：	X5R Dielectric, 4 â 50 VDC (Commercial Grade)
文件：	总22页 (文件大小：1385K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C0603C107K4PACTU [KEMET]

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