C0603C104Z3VACTU_技术文档

SurfaceꢀMountꢀMultilayerꢀCeramicꢀChipꢀCapacitorsꢀ(SMDꢀMLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Overview

KEMET’sꢀY5Vꢀdielectricꢀfeaturesꢀanꢀ85°Cꢀmaximumꢀ

highꢀinsulationꢀresistanceꢀandꢀcapacitanceꢀstabilityꢀareꢀnotꢀ

operatingꢀtemperatureꢀandꢀisꢀconsideredꢀ“general-purpose.”ꢀ ofꢀmajorꢀimportance.ꢀY5Vꢀexhibitsꢀaꢀpredictableꢀchangeꢀinꢀ

TheꢀElectronicsꢀComponents,ꢀAssembliesꢀ&ꢀMaterialsꢀ

Associationꢀ(EIA)ꢀcharacterizesꢀY5VꢀdielectricꢀasꢀaꢀClassꢀ

IIIꢀmaterial.ꢀComponentsꢀofꢀthisꢀclassiﬁcationꢀareꢀﬁxed,ꢀ

ceramicꢀdielectricꢀcapacitorsꢀsuitedꢀforꢀbypassꢀandꢀ

decouplingꢀorꢀotherꢀapplicationsꢀinꢀwhichꢀdielectricꢀlosses,ꢀ

capacitanceꢀwithꢀrespectꢀtoꢀtimeꢀandꢀvoltageꢀandꢀdisplaysꢀ

wideꢀvariationsꢀinꢀcapacitanceꢀwithꢀreferenceꢀtoꢀambientꢀ

temperature.ꢀCapacitanceꢀchangeꢀisꢀlimitedꢀtoꢀ+22%,ꢀ−82%ꢀ

fromꢀ−30°Cꢀtoꢀ+85°C.

Applications

Beneﬁts

Typicalꢀapplicationsꢀincludeꢀlimitedꢀtemperature,ꢀdecouplingꢀ

and bypass.

•ꢀ −30°Cꢀtoꢀ+85°Cꢀoperatingꢀtemperatureꢀrange

• Lead (Pb)-free, RoHS and REACH compliant

• EIA 0402, 0603, 0805, 1206, and 1210 case sizes

•ꢀ DCꢀvoltageꢀratingsꢀofꢀ6.3ꢀV,ꢀ10ꢀV,ꢀ16ꢀV,ꢀ25ꢀV,ꢀandꢀ50ꢀV

•ꢀ Capacitanceꢀofferingsꢀrangingꢀfromꢀ0.022ꢀμFꢀtoꢀ22ꢀμF

•ꢀ Availableꢀcapacitanceꢀtoleranceꢀofꢀ+80%/−20%ꢀ

•ꢀ Non-polarꢀdevice,ꢀminimizingꢀinstallationꢀconcerns

•ꢀ 100%ꢀpureꢀmatteꢀtin-platedꢀterminationꢀﬁnishꢀthatꢀallowingꢀ

for excellent solderability

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Ordering Information

C

1210

C

226

Z

4

V

A

C

TU

Rated

Case Size Speciﬁcation/ Capacitance

(L" x W")

Capacitance

Tolerance

FailureꢀRate/

Design

Packaging/

Grade (C-Spec)

Ceramic

Voltageꢀ Dielectric

(VDC)

9 = 6.3

8 = 10

4 = 16

3 = 25

5 = 50

TerminationꢀFinish¹

Cꢀ=ꢀ100%ꢀMatteꢀSn

Series

Codeꢀ(pF)

0402

0603

0805

1206

1210

C = Standard Twoꢀsigniﬁcantꢀ Zꢀ=ꢀ+80%/−20%

V = Y5V

A = N/A

See

"Packagingꢀ

C-Spec

Orderingꢀ

Options

Mꢀ=ꢀ±20%

digitsꢀ+ꢀnumberꢀ

of zeros

Table" below

¹Additional termination ﬁnish options may be available. Contact KEMET for details.

One world. One KEMET

C1005_Y5V_SMD • 7/21/2016

1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Packaging C-Spec Ordering Options Table

Packaging/Grade

Packaging Type¹

Ordering Code (C-Spec)

BulkꢀBag/Unmarked

7"ꢀReel/Unmarked

Notꢀrequiredꢀ(Blank)

TU

7411 (EIA 0603 and smaller case sizes)

13"ꢀReel/Unmarked

7" Reel/Marked

7210ꢀ(EIAꢀ0805ꢀandꢀlargerꢀcaseꢀsizes)

TM

7040 (EIA 0603 and smaller case sizes)

13" Reel/Marked

7215ꢀ(EIAꢀ0805ꢀandꢀlargerꢀcaseꢀsizes)

7"ꢀReel/Unmarked/2mmꢀpitch²

13"ꢀReel/Unmarked/2mmꢀpitch²

7081

7082

¹Default packaging is "Bulk Bag". An ordering code C-Spec is not required for "Bulk Bag" packaging.

¹The terms "Marked" and "Unmarked" pertain to laser marking option of capacitors. All packaging options labeled as "Unmarked" will contain capacitors

that have not been laser marked. Please contact KEMET if you require a laser marked option. For more information see "Capacitor Marking".

²The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case

size devices. For more information regarding 2 mm pitch option see "Tape & Reel Packaging Information".

Dimensions – Millimeters (Inches)

L

ꢁ

ꢂ

ꢀ

S

EIA Size

Code

Metric Size

Code

L

W

Width

T

B

Mounting

Technique

Separation

Minimum

Length

Thickness

Bandwidth

1.00 (0.040)

±0.05 (0.002)

1.60 (0.063)

±0.15 (0.006)

2.00 (0.079)

±0.20 (0.008)

3.20 (0.126)

±0.20 (0.008)

3.20 (0.126)

±0.20 (0.008)

0.50 (0.020)

±0.05 (0.002)

0.80 (0.032)

±0.15 (0.006)

1.25 (0.049)

±0.20 (0.008)

1.60 (0.063)

±0.20 (0.008)

2.50 (0.098)

±0.20 (0.008)

0.30 (0.012)

±0.10 (0.004)

0.35 (0.014)

±0.15 (0.006)

0.50 (0.02)

±0.25 (0.010)

0.50 (0.02)

±0.25 (0.010)

0.50 (0.02)

±0.25 (0.010)

SolderꢀReﬂowꢀ

0402

0603

0805

1206

1210

1005

1608

2012

3216

3225

0.30 (0.012)

0.70 (0.028)

0.75 (0.030)

Only

See Table 2 for

Thickness

Solder Wave or

SolderꢀReﬂow

N/A

SolderꢀReﬂowꢀ

Only

C1005_Y5V_SMD • 7/21/2016

2

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Qualiﬁcation/Certiﬁcation

CommercialꢀGradeꢀproductsꢀareꢀsubjectꢀtoꢀinternalꢀqualiﬁcation.ꢀDetailsꢀregardingꢀtestꢀmethodsꢀandꢀconditionsꢀareꢀ

referencedꢀinꢀTableꢀ4,ꢀPerformanceꢀ&ꢀReliability.

Environmental Compliance

Leadꢀ(Pb)-free,ꢀRoHS,ꢀandꢀREACHꢀcompliantꢀwithoutꢀexemptions.

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

OperatingꢀTemperatureꢀRange

−30°Cꢀtoꢀ+85°Cꢀꢀ

+22%,ꢀ−82%

7.0%

CapacitanceꢀChangeꢀwithꢀReferenceꢀto

+25°Cꢀandꢀ0ꢀVdcꢀAppliedꢀ(TCC)

¹AgingꢀRateꢀ(Maximumꢀ%ꢀCapacitanceꢀLoss/DecadeꢀHour)

250%ꢀofꢀratedꢀvoltage

(5±1ꢀsecondsꢀandꢀcharge/dischargeꢀnotꢀexceedingꢀ50mA)

²DielectricꢀWithstandingꢀVoltageꢀ(DWV)

³DissipationꢀFactorꢀ(DF)ꢀMaximumꢀLimitꢀatꢀ25°C

⁴InsulationꢀResistanceꢀ(IR)ꢀMinimumꢀLimitꢀatꢀ25°C

10%ꢀ(6.3ꢀVꢀandꢀ10ꢀV),ꢀ7%ꢀ(16ꢀVꢀandꢀ25ꢀV)ꢀandꢀ5%ꢀ(50ꢀVꢀ)

SeeꢀInsulationꢀResistanceꢀLimitꢀTable

(Ratedꢀvoltageꢀappliedꢀforꢀ120±5ꢀsecondsꢀatꢀ25°C)

¹Regarding Aging Rate: Capacitance measurements (including tolerance) are indexed to a referee time of 48 or 1,000 hours. Please refer to a part

number speciﬁc datasheet for referee time details.

²DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the

capacitor.

³Capacitance and dissipation factor (DF) measured under the following conditions:

1kHz ± 50Hz and 1.0 ± 0.2 Vrms if capacitance ≤10µF

120Hz ± 10Hz and 0.5 ± 0.1 Vrms if capacitance >10µF

⁴To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 & Agilent E4980 have a feature known as

Automatic Level Control (ALC). The ALC feature should be switched to "ON".

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Rated DC

Capacitance DissipationꢀFactorꢀ Capacitance

Insulation

Dielectric

Y5V

Voltage

Value

(Maximumꢀ%)

Shift

Resistance

> 25

16/25

< 16

7.5

10%ꢀofꢀInitialꢀ

All

10.0

15.0

±30%

Limit

Insulation Resistance Limit Table

100 Megohm

EIA Case Size

50 Megohm

Microfarads or 10 GΩ

All

≥ꢀ16ꢀV

≤ꢀ10ꢀV

C1005_Y5V_SMD • 7/21/2016

3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Table 1 – Capacitance Range/Selection Waterfall (0402 – 1210 Case Sizes)

Case Size/

Series

Voltage Code

C0402C

C0603C

C0805C

C1206C

C1210C

9

8

4

9

8

4

3

9

8

4

3

5

9

8

4

3

5

9

8

4

3

5

Capacitance

Code

Capacitance

Rated Voltage (VDC)

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

Capacitance Tolerance

22,000ꢀpF

27,000ꢀpF

33,000ꢀpF

39,000ꢀpF

47,000ꢀpF

56,000ꢀpF

68,000ꢀpF

82,000ꢀpF

0.10ꢀµF

0.12ꢀµF

0.15ꢀµF

0.18ꢀµF

0.22ꢀµF

0.27ꢀµF

0.33ꢀµF

0.39ꢀµF

0.47ꢀµF

0.56ꢀµF

0.68ꢀµF

0.82ꢀµF

1.0ꢀµF

223

273

333

393

473

563

683

823

104

124

154

184

224

274

334

394

474

564

684

824

105

125

155

185

225

335

475

565

685

106

156

226

M

Z

BB BB BB CF CF CF CF DN DN DN DN DN

BB BB BB CF CF CF CF DP DP DP DP DP

BB BB BB CF CF CF CF DO DO DO DO DO

BB BB BB CF CF CF CF DP DP DP DP DP

BB BB BB CG CG CG CG DN DN DN DN DN

CG CG CG CG DN DN DN DN

BB

CG CG CG CG DN DN DN DN DG EC EC EC EC

FD FD FD FD FD

FF FF FF FF FF

FH FH FH FH FH

FD FD FD

FJ FJ FJ

FE FE FE

FT FT FT

FG FG FG

FH FH FH

FH² FH² FH²

CG CG CG CG DN DN DN DN

CG CG CG CG DG DG DG DG

EB EB EB EB

EC EC EC EC

EB EB EB EB

CG CG CG

CG CG

DN DN DN DN

DG DG DG DG

DP DP DP DP

DP DP DP DG

DG DG DG DG

BB

BB BB

CG CG CG CG DP DP DP DG DG EP EP EP EP

1.2ꢀµF

1.5ꢀµF

1.8ꢀµF

2.2ꢀµF

3.3ꢀµF

4.7ꢀµF

5.6ꢀµF

6.8ꢀµF

DN DN DN

DP DP DP

DG DG DG

DL DL DG

DG DG DG

DF DF

EC EC EC

ED ED ED

EC EC EC

EH EH EH

EM² EM² EM²

EJ EJ EJ

EJ EJ

DG DG

10ꢀµF

15ꢀµF

22ꢀµF

EH EH EH EH

FH FH FH

FT² FT² FS FS

EH EH

Rated Voltage (VDC)

Voltage Code

Capacitance

Code

9

8

4

9

8

4

3

9

8

4

3

5

9

8

4

3

5

9

8

4

3

5

Capacitance

Case Size/

Series

C0402C

C0603C

C0805C

C1206C

C1210C

xx² Only available in Z tolerance.

C1005_Y5V_SMD • 7/21/2016

4

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Table 2A – Chip Thickness/Tape & Reel Packaging Quantities

Paper Quantity¹

Plastic Quantity

Thickness Case Thickness ±

Code

Size1 Range (mm)

7" Reel

13" Reel

7" Reel

13" Reel

BB

CF

CG

DN

DO

DP

DL

DF

DG

EB

EC

ED

EP

EM

EH

EJ

FD

FE

FF

0402

0603

0805

1206

1210

0.50±0.05

0.80±0.07*

0.80±0.10*

0.78±0.10*

0.80±0.10*

0.90±0.10*

0.95±0.10

1.10±0.10

1.25±0.15

0.78±0.10

0.90±0.10

1.00±0.10

1.20±0.20

1.25±0.15

1.60±0.20

1.70±0.20

0.95±0.10

1.00±0.10

1.10±0.10

1.25±0.15

1.55±0.15

1.85±0.20

1.90±0.20

2.50±0.30

10,000

4,000

0

50,000

15,000

0

4,000

2,500

4,000

2,500

2,000

4,000

2,500

2,000

1,000

10,000

8,000

10,000

8,000

4,000

0

4,000

10,000

0

FG

FH

FJ

FT

FS

7" Reel

13" Reel

7" Reel

13" Reel

Thickness

Code

Case

Size1

Thickness ±

Range (mm)

Paper Quantity¹

Plastic Quantity

Package quantity based on ﬁnished chip thickness speciﬁcations.

¹If ordering using the 2 mm Tape and Reel pitch option, the packaging quantity outlined in the table above will be doubled. This option is limited to EIA

0603 (1608 metric) case size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.

C1005_Y5V_SMD • 7/21/2016

5

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Table 2B – Bulk Packaging Quantities

Loose Packaging

BulkꢀBagꢀ(default)

N/A²

Packaging Type

PackagingꢀC-Spec¹

Case Size

Packaging Quantities (pieces/unit packaging)

EIA (in)

Metric (mm)

Minimum

Maximum

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

50,000

1

20,000

¹The "Packaging C-Spec" is a 4 to 8 digit code which identiﬁes the packaging type and/or product grade. When ordering, the proper code must be

included in the 15th through 22nd character positions of the ordering code. See "Ordering Information" section of this document for further details.

Commercial Grade product ordered without a packaging C-Spec will default to our standard "Bulk Bag" packaging. Contact KEMET if you require a bulk

bag packaging option for Automotive Grade products.

²A packaging C-Spec (see note 1 above) is not required for "Bulk Bag" packaging (excluding Anti-Static Bulk Bag and Automotive Grade products). The

15th through 22nd character positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to our

standard "Bulk Bag" packaging.

C1005_Y5V_SMD • 7/21/2016

6

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC-7351

Density Level A:

Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

EIA

Size

Code

Metric

Size

Code

C

Y

X

V1

V2

C

Y

X

V1

V2

C

Y

X

V1

V2

0402

0603

0805

1206

1210

1210¹

1005

1608

2012

3216

3225

0.50

0.72

2.20

1.20

0.45

0.62

1.90

1.00

0.40

0.52

1.60

0.80

0.90

1.00

1.60

1.50

1.15

1.35

1.60

1.10

1.55

1.90

2.80

2.90

4.00

4.40

5.60

5.65

5.60

2.10

2.60

2.90

3.80

3.90

0.80

0.90

1.50

1.40

0.95

1.15

1.40

1.00

1.45

1.80

2.70

2.80

3.10

3.50

4.70

1.50

2.00

2.30

3.20

3.30

0.60

0.75

1.40

1.30

0.75

0.95

1.20

0.90

1.35

1.70

2.60

2.70

2.40

2.80

4.00

1.20

1.70

2.00

2.90

3.00

¹Only for capacitance values ≥ 22 µF

Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reﬂow

solder processes. KEMET only recommends wave soldering of EIA 0603, 0805, and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reﬂow solder processes.

Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform

qualiﬁcation testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).

Image below based on Density Level B for an EIA 1210 case size.

Vꢁ

Y

Vꢂ

ꢀ

C

Grid ꢃlacement Courtyard

C1005_Y5V_SMD • 7/21/2016

7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Soldering Process

Recommended Soldering Technique:

ꢀ •ꢀSolderꢀwaveꢀorꢀsolderꢀreﬂowꢀforꢀEIAꢀcaseꢀsizesꢀ0603,ꢀ0805ꢀandꢀ1206

ꢀ •ꢀAllꢀotherꢀEIAꢀcaseꢀsizesꢀareꢀlimitedꢀtoꢀsolderꢀreﬂowꢀonly

Recommended Reﬂow Soldering Proﬁle:

KEMET’sꢀfamiliesꢀofꢀsurfaceꢀmountꢀmultilayerꢀceramicꢀcapacitorsꢀ(SMDꢀMLCCs)ꢀareꢀcompatibleꢀwithꢀwaveꢀ(singleꢀorꢀdual),ꢀ

convection,ꢀIRꢀorꢀvaporꢀphaseꢀreﬂowꢀtechniques.ꢀPreheatingꢀofꢀtheseꢀcomponentsꢀisꢀrecommendedꢀtoꢀavoidꢀextremeꢀthermalꢀ

stress.ꢀKEMET’sꢀrecommendedꢀproﬁleꢀconditionsꢀforꢀconvectionꢀandꢀIRꢀreﬂowꢀreﬂectꢀtheꢀproﬁleꢀconditionsꢀofꢀtheꢀIPC/

J-STD-020ꢀstandardꢀforꢀmoistureꢀsensitivityꢀtesting.ꢀTheseꢀdevicesꢀcanꢀsafelyꢀwithstandꢀaꢀmaximumꢀofꢀthreeꢀreﬂowꢀpassesꢀ

atꢀtheseꢀconditions.

Termination Finish

ꢀ_ꢃ

ꢀ_L

t_ꢃ

Proﬁle Feature

Maꢂimum ꢄamp ꢅp ꢄate ꢆ 3ꢇCꢈsec

Maꢂimum ꢄamp Doꢉn ꢄate ꢆ 6ꢇCꢈsec

SnPb

100%ꢀMatteꢀSn

t_L

Preheat/Soak

TemperatureꢀMinimumꢀ(T_Smin

)

100°C

150°C

200°C

ꢀ_smaꢂ

ꢀ_smin

TemperatureꢀMaximumꢀ(T_Smax

)

Time (t_S) from T_Sminto T_Smax

60 – 120 seconds

t_s

3°C/secondꢀ

maximum

3°C/secondꢀ

maximum

Ramp-UpꢀRateꢀ(T_Lto T_P)

ꢁ5

ꢁ5ꢇC to ꢃeaꢊ

LiquidousꢀTemperatureꢀ(T_L)

TimeꢀAboveꢀLiquidousꢀ(t_L)

PeakꢀTemperatureꢀ(T_P)

183°C

60 – 150 seconds

235°C

217°C

60 – 150 seconds

260°C

Tiꢀe

TimeꢀWithinꢀ5°CꢀofꢀMaximumꢀ

20 seconds

maximum

30 seconds

maximum

PeakꢀTemperatureꢀ(t_P)

6°C/secondꢀ

maximum

6°C/secondꢀ

maximum

Ramp-Down Rate (T_Pto T_L)

Timeꢀ25°CꢀtoꢀPeakꢀ

Temperature

6ꢀminutes

maximum

8ꢀminutes

maximum

Note 1: All temperatures refer to the center of the package, measured on the

capacitor body surface that is facing up during assembly reﬂow.

C1005_Y5V_SMD • 7/21/2016

8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress

Reference

Test or Inspection Method

TerminalꢀStrength

JIS–C–6429

Appendixꢀ1,ꢀNote:ꢀForceꢀofꢀ1.8ꢀkgꢀforꢀ60ꢀseconds.

Appendixꢀ2,ꢀNote:ꢀStandardꢀterminationꢀsystemꢀ–ꢀ2.0ꢀmmꢀ(minimum)ꢀforꢀallꢀexceptꢀ3ꢀmmꢀ

forꢀC0G.ꢀFlexibleꢀterminationꢀsystemꢀ–ꢀ3.0ꢀmmꢀ(minimum).

BoardꢀFlex

JIS–C–6429

Magniﬁcationꢀ50ꢀX.ꢀConditions:

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀa)ꢀMethodꢀB,ꢀ4ꢀhoursꢀatꢀ155°C,ꢀdryꢀheatꢀatꢀ235°C

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀb)ꢀMethodꢀBꢀatꢀ215°Cꢀcategoryꢀ3

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀc)ꢀMethodꢀD,ꢀcategoryꢀ3ꢀatꢀ260°C

Solderability

J–STD–002

1,000ꢀCyclesꢀ(−55°Cꢀtoꢀ+125°C).ꢀMeasurementꢀatꢀ24ꢀhoursꢀ+/−ꢀ4ꢀhoursꢀafterꢀtestꢀ

conclusion.

LoadꢀHumidity:ꢀ1,000ꢀhoursꢀ85°C/85%ꢀRHꢀandꢀratedꢀvoltage.ꢀAddꢀ100ꢀKꢀohmꢀresistor.ꢀ

Measurementꢀatꢀ24ꢀhoursꢀ+/−ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

LowꢀVoltꢀHumidity:ꢀ1,000ꢀhoursꢀ85°C/85%ꢀRHꢀandꢀ1.5ꢀV.ꢀAddꢀ100ꢀKꢀohmꢀresistor.ꢀ

Measurementꢀatꢀ24ꢀhoursꢀ+/−ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

TemperatureꢀCycling

BiasedꢀHumidity

JESD22ꢀMethodꢀJA–104

MIL–STD–202ꢀMethodꢀ

103

MIL–STD–202ꢀMethodꢀ

tꢀ=ꢀ24ꢀhours/cycle.ꢀStepsꢀ7aꢀandꢀ7bꢀnotꢀrequired.

MoistureꢀResistance

ThermalꢀShock

Measurementꢀatꢀ24ꢀhoursꢀ+/−ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

106

MIL–STD–202ꢀMethodꢀ

−55°C/+125°C.ꢀNote:ꢀNumberꢀofꢀcyclesꢀrequiredꢀ–ꢀ300,ꢀmaximumꢀtransferꢀtimeꢀ–ꢀ20ꢀ

seconds,ꢀdwellꢀtimeꢀ–ꢀ15ꢀminutes.ꢀAirꢀ–ꢀAir.

107

MIL–STD–202ꢀMethodꢀ

108

HighꢀTemperatureꢀLife

1,000ꢀhoursꢀatꢀ125°Cꢀ(85°CꢀforꢀX5R,ꢀZ5UꢀandꢀY5V)ꢀwithꢀ2ꢀXꢀratedꢀvoltageꢀapplied.

/EIA–198

MIL–STD–202ꢀMethodꢀ

108

StorageꢀLife

150°C,ꢀ0ꢀVDCꢀforꢀ1,000ꢀhours.

5ꢀg'sꢀforꢀ20ꢀminutes,ꢀ12ꢀcyclesꢀeachꢀofꢀ3ꢀorientations.ꢀNote:ꢀUseꢀ8"ꢀXꢀ5"ꢀPCBꢀ0.031"ꢀthickꢀ

7ꢀsecureꢀpointsꢀonꢀoneꢀlongꢀsideꢀandꢀ2ꢀsecureꢀpointsꢀatꢀcornersꢀofꢀoppositeꢀsides.ꢀPartsꢀ

mountedꢀwithinꢀ2"ꢀfromꢀanyꢀsecureꢀpoint.ꢀTestꢀfromꢀ10ꢀ–ꢀ2,000ꢀHz

MIL–STD–202ꢀMethodꢀ

Vibration

204

MIL–STD–202ꢀMethodꢀ

MechanicalꢀShock

Figureꢀ1ꢀofꢀMethodꢀ213,ꢀConditionꢀF.

213

MIL–STD–202ꢀMethodꢀ

215

Resistance to Solvents

Addꢀaqueousꢀwashꢀchemical,ꢀOKEMꢀCleanꢀorꢀequivalent.

Storage and Handling

Ceramicꢀchipꢀcapacitorsꢀshouldꢀbeꢀstoredꢀinꢀnormalꢀworkingꢀenvironments.ꢀWhileꢀtheꢀchipsꢀthemselvesꢀareꢀquiteꢀrobustꢀinꢀ

otherꢀenvironments,ꢀsolderabilityꢀwillꢀbeꢀdegradedꢀbyꢀexposureꢀtoꢀhighꢀtemperatures,ꢀhighꢀhumidity,ꢀcorrosiveꢀatmospheres,ꢀ

andꢀlongꢀtermꢀstorage.ꢀInꢀaddition,ꢀpackagingꢀmaterialsꢀwillꢀbeꢀdegradedꢀbyꢀhighꢀtemperature–reelsꢀmayꢀsoftenꢀorꢀwarpꢀ

andꢀtapeꢀpeelꢀforceꢀmayꢀincrease.ꢀKEMETꢀrecommendsꢀthatꢀmaximumꢀstorageꢀtemperatureꢀnotꢀexceedꢀ40ºCꢀandꢀmaximumꢀ

storageꢀhumidityꢀnotꢀexceedꢀ70%ꢀrelativeꢀhumidity.ꢀTemperatureꢀﬂuctuationsꢀshouldꢀbeꢀminimizedꢀtoꢀavoidꢀcondensationꢀonꢀ

theꢀpartsꢀandꢀatmospheresꢀshouldꢀbeꢀfreeꢀofꢀchlorineꢀandꢀsulfurꢀbearingꢀcompounds.ꢀForꢀoptimizedꢀsolderabilityꢀchipꢀstockꢀ

shouldꢀbeꢀusedꢀpromptly,ꢀpreferablyꢀwithinꢀ1.5ꢀyearsꢀofꢀreceipt.

C1005_Y5V_SMD • 7/21/2016

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Construction (Typical)

ꢀeꢁaiꢂeꢃ ꢄrꢅꢆꢆ ꢇeꢈꢁiꢅꢉ

Dielectric Material

(ꢀaꢁiꢂ₃)

Dielectric

Material (ꢀaꢁiꢂ₃)

ꢀarrier Layer

(ꢃi)

ꢁermination

ꢆinish

(ꢇ00ꢈ Matte Sn)

ꢅnd ꢁerminationꢉ

ꢅꢊternal ꢅlectrode

(Cu)

ꢄnner ꢅlectrodes

(ꢃi)

ꢅnd ꢁerminationꢉ

ꢅꢊternal ꢅlectrode

(Cu)

ꢀarrier Layer

(ꢃi)

ꢁermination

ꢆinish

(ꢇ00ꢈ Matte Sn)

ꢄnner ꢅlectrodes

(ꢃi)

Capacitor Marking (Optional):

Laserꢀmarkingꢀoptionꢀisꢀnotꢀavailableꢀon:

•ꢀ C0G,ꢀUltraꢀStableꢀX8RꢀandꢀY5Vꢀdielectricꢀdevices

• EIA 0402 case size devices

•ꢀ EIAꢀ0603ꢀcaseꢀsizeꢀdevicesꢀwithꢀFlexibleꢀTerminationꢀoption.

•ꢀ KPSꢀCommercialꢀandꢀAutomotiveꢀgradeꢀstackedꢀdevices.

Theseꢀcapacitorsꢀareꢀsuppliedꢀunmarkedꢀonly.

C1005_Y5V_SMD • 7/21/2016 10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Tape & Reel Packaging Information

KEMETꢀoffersꢀmultilayerꢀceramicꢀchipꢀcapacitorsꢀpackagedꢀinꢀ8,ꢀ12ꢀandꢀ16ꢀmmꢀtapeꢀonꢀ7"ꢀandꢀ13"ꢀreelsꢀinꢀaccordanceꢀwithꢀ

EIAꢀStandardꢀ481.ꢀThisꢀpackagingꢀsystemꢀisꢀcompatibleꢀwithꢀallꢀtape-fedꢀautomaticꢀpickꢀandꢀplaceꢀsystems.ꢀSeeꢀTableꢀ2ꢀforꢀ

detailsꢀonꢀreelingꢀquantitiesꢀforꢀcommercialꢀchips.

ꢕar Code Laꢊel

ꢆntiꢇStatic ꢈeel

®

ꢉmꢊossed ꢋlasticꢌ or

ꢋunched ꢋaper Carrier.

Chip and ꢑꢋS ꢒrientation in ꢋocꢐet

(eꢏcept ꢁꢀꢂ5 Commercial, and ꢁꢀꢂ5 and ꢂꢂꢂ5 Military)

KEMET

Sprocꢐet ꢖoles

ꢉmꢊossment or ꢋunched Caꢍity

ꢀ mm, ꢁꢂ mm

or ꢁ6 mm Carrier ꢃape

ꢆntiꢇStatic Coꢍer ꢃape

(.ꢁ0 mm (.00ꢎꢅ) Maꢏimum ꢃhicꢐness)

ꢁꢄꢀ mm (ꢄ.00ꢅ)

or

330 mm (ꢁ3.00ꢅ)

ꢌꢉꢓꢆ 0ꢁ005, 0ꢂ0ꢁ, 0ꢎ0ꢂ and 0603 case siꢔes aꢍailaꢊle on punched paper carrier only.

Table 5 – Carrier Tape Conﬁguration, Embossed Plastic & Punched Paper (mm)

New 2 mm Pitch Reel Options*

Embossed Plastic Punched Paper

Tape

Packaging

Ordering Code

(C-Spec)

C-3190

7" Reel 13" Reel 7" Reel 13" Reel

EIA Case Size Size

(W)*

Packaging Type/Options

Pitchꢀ(P₁)* Pitchꢀ(P₁)*

01005 – 0402

0603

8

2

2/4

4

Automotiveꢀgradeꢀ7"ꢀreelꢀunmarked

Automotiveꢀgradeꢀ13"ꢀreelꢀunmarked

Commercialꢀgradeꢀ7"ꢀreelꢀunmarked

Commercialꢀgradeꢀ13"ꢀreelꢀunmarked

C-3191

2/4

4

C-7081

0805

8

4

C-7082

1206 – 1210

1805 – 1808

≥ꢀ1812

8

4

* 2 mm pitch reel only available for 0603 EIA case size.

2 mm pitch reel for 0805 EIA case size under development.

12

16

8

4

8

Beneﬁts of Changing from 4 mm to 2 mm Pitching Spacing

• Lower placement costs

•ꢀ Doubleꢀtheꢀpartsꢀonꢀeachꢀreelꢀresultsꢀinꢀfewerꢀreelꢀ

changesꢀandꢀincreasedꢀef ꢀciency

•ꢀ Fewerꢀreelsꢀresultꢀinꢀlowerꢀpackaging,ꢀshippingꢀandꢀ

storageꢀcosts,ꢀreducingꢀwaste

KPS 1210

8

KPSꢀ1812ꢀ&ꢀ2220

Arrayꢀ0508ꢀ&ꢀ0612

12

4

12

4

*Refer to Figures 1 & 2 for W and P₁carrier tape reference locations.

*Refer to Tables 6 & 7 for tolerance speciﬁcations.

C1005_Y5V_SMD • 7/21/2016 11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

ꢁ

ꢀ ꢋ

ꢑꢈ0 pitches cumulatiꢄe

tolerance on tape ꢒ 0.ꢋ mmꢓ

ꢋ

ꢍ

ꢈ

ꢀo

ꢌDo

ꢅo

ꢂ

ꢇo

ꢃ

ꢍ

ꢋ

ꢆ

ꢈ

ꢆo

S

ꢈ

ꢀ

ꢈ

ꢁ

ꢈ

ꢍmꢊossment

ꢂor caꢄity siꢎe,

see ꢏote ꢈ ꢁaꢊle ꢐ

Center Lines of Caꢄity

ꢌD

ꢈ

Coꢄer ꢁape

is for tape feeder reference only,

includinꢉ draft concentric aꢊout ꢆ

ꢆ

ꢈ

o

.

Uꢀer ꢁireꢂꢃiꢄꢅ ꢄꢆ Uꢅreeꢇiꢅꢈ

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

D₁ꢀMinimum

Note 1

1.0

(0.039)

R Reference S₁ꢀMinimum

T

T₁

Tape Size

8 mm

D₀

E₁

P₀

P₂

Note 2

Note 3

Maximum Maximum

25.0

(0.984)

1.5ꢀ+0.10/-0.0ꢀ

(0.059ꢀ+0.004/-

0.0)

1.75 ±0.10

4.0 ±0.10

2.0 ±0.05

0.600

(0.024)

0.100

(0.004)

12 mm

16 mm

(0.069 ±0.004) (0.157 ±0.004) (0.079 ±0.002)

(0.024)

1.5

(0.059)

30

(1.181)

Variable Dimensions — Millimeters (Inches)

B₁ꢀMaximum

E₂

T₂

W

Tape Size

8 mm

Pitchꢀ

Fꢀ

P₁

A₀,B₀ꢀ&ꢀK₀

Note 4

4.35

(0.171)

Minimum

6.25

(0.246)

Maximum Maximum

2.5

(0.098)

3.5 ±0.05

(0.138 ±0.002) (0.157 ±0.004)

4.0 ±0.10

8.3

(0.327)

Singleꢀ(4ꢀmm)

Singleꢀ(4ꢀmm)ꢀ&ꢀ

Doubleꢀ(8ꢀmm)

8.2

10.25

5.5 ±0.05

8.0 ±0.10

4.6

12.3

12 mm

16 mm

Note 5

(0.323)

(0.404)

(0.217 ±0.002) (0.315 ±0.004)

(0.181)

(0.484)

12.1

(0.476)

14.25

(0.561)

7.5 ±0.05 12.0 ±0.10

(0.138 ±0.002) (0.157 ±0.004)

4.6

(0.181)

16.3

(0.642)

Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment

location and hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 6).

3. If S₁< 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).

4. B₁dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with sufﬁcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3).

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see

Figure 4).

(e) for KPS Series product, A₀and B₀are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

C1005_Y5V_SMD • 7/21/2016 12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

ꢀ

ꢏꢃ0 pitches cumulatiꢁe

tolerance on tape ꢐ 0.ꢇ mmꢑ

ꢅ^ꢃ

ꢂo

ꢄDo

ꢉ⁰

ꢆ

ꢈ

ꢅ^ꢇ

ꢊ⁰

ꢊottom Coꢁer ꢀape

ꢂ^ꢃ

G

Caꢁity Siꢋe,

See

ꢀ^ꢃ

Center Lines of Caꢁity

ꢀop Coꢁer ꢀape

ꢌote ꢃ, ꢀaꢍle ꢎ

ꢊottom Coꢁer ꢀape

Uꢀer ꢁireꢂꢃiꢄꢅ ꢄꢆ Uꢅreeꢇiꢅꢈ

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

R Reference

Note 2

Tape Size

8 mm

D₀

E₁

P₀

P₂

T₁Maximum

GꢀMinimum

0.10

1.5ꢀ+0.10ꢀ-0.0ꢀ

(0.059ꢀ+0.004ꢀ-0.0)

1.75 ±0.10

(0.069 ±0.004)

4.0 ±0.10

(0.157 ±0.004)

2.0 ±0.05

(0.079 ±0.002)

0.75

(0.030)

25

(0.984)

(0.004)

Maximum

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

Pitch

E2ꢀMinimum

Fꢀ

P₁

TꢀMaximum

WꢀMaximum

A₀B₀

2.0 ±0.05

(0.079 ±0.002)

4.0 ±0.10

(0.157 ±0.004)

8.3

(0.327)

8.3

(0.327)

Half (2 mm)

Singleꢀ(4ꢀmm)

6.25

(0.246)

3.5 ±0.05

(0.138 ±0.002)

1.1

(0.098)

Note 1

8 mm

1. The cavity deﬁned by A₀, B₀and T shall surround the component with sufﬁcient clearance that:

a) the component does not protrude beyond either surface of the carrier tape.

b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

c) rotation of the component is limited to 20° maximum (see Figure 3).

d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).

e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 6).

C1005_Y5V_SMD • 7/21/2016 13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force:ꢀ1.0ꢀKgꢀminimum.

2. Cover Tape Peel Strength: Theꢀtotalꢀpeelꢀstrengthꢀofꢀtheꢀcoverꢀtapeꢀfromꢀtheꢀcarrierꢀtapeꢀshallꢀbe:ꢀ

Tape Width

8 mm

Peel Strength

0.1ꢀtoꢀ1.0ꢀNewtonꢀ(10ꢀtoꢀ100ꢀgf)

0.1ꢀtoꢀ1.3ꢀNewtonꢀ(10ꢀtoꢀ130ꢀgf)

12 and 16 mm

Theꢀdirectionꢀofꢀtheꢀpullꢀshallꢀbeꢀoppositeꢀtheꢀdirectionꢀofꢀtheꢀcarrierꢀtapeꢀtravel.ꢀTheꢀpullꢀangleꢀofꢀtheꢀcarrierꢀtapeꢀshallꢀbeꢀ

165°ꢀtoꢀ180°ꢀfromꢀtheꢀplaneꢀofꢀtheꢀcarrierꢀtape.ꢀDuringꢀpeeling,ꢀtheꢀcarrierꢀand/orꢀcoverꢀtapeꢀshallꢀbeꢀpulledꢀatꢀaꢀvelocityꢀofꢀ

300ꢀ±10ꢀmm/minute.

3. Labeling:ꢀBarꢀcodeꢀlabelingꢀ(standardꢀorꢀcustom)ꢀshallꢀbeꢀonꢀtheꢀsideꢀofꢀtheꢀreelꢀoppositeꢀtheꢀsprocketꢀholes.ꢀRefer to EIA

Standards 556 and 624.

Figure 3 – Maximum Component Rotation

°

ꢂ

ꢀaꢁiꢂꢃꢂ ꢄꢅꢂpꢅꢆeꢆꢇ ꢈꢅꢇaꢇiꢅꢆ

Tꢅp View

ꢀaꢁiꢂꢃꢂ ꢄꢅꢂpꢅꢆeꢆꢇ ꢈꢅꢇaꢇiꢅꢆ

ꢉiꢊe View

ꢂypical ꢇocꢈet Centerline

Tape

ꢀaꢁiꢂꢃꢂ

°

ꢂ

s

Wiꢊꢇꢋ ꢌꢂꢂꢍ ꢈꢅꢇaꢇiꢅꢆ ꢌ

)

ꢃ,ꢄꢅ

ꢄ6 – ꢅ00

ꢅ0

ꢄ0

ꢁo

Tape

ꢀaꢁiꢂꢃꢂ

°

S

Wiꢊꢇꢋ ꢌꢂꢂꢍ ꢈꢅꢇaꢇiꢅꢆ ꢌ

)

ꢃ,ꢄꢅ

ꢄ6 – 56

ꢆꢅ – ꢅ00

ꢅ0

ꢄ0

5

ꢂypical Component Centerline

ꢀo

Figure 4 – Maximum Lateral Movement

Figure 5 – Bending Radius

ꢃmꢄossed

Carrier

ꢅunched

Carrier

ꢁ mm ꢂ ꢃꢄ mm ꢅape

ꢃ6 mm ꢅape

0.5 mm maꢀimum

ꢃ.0 mm maꢀimum

ꢀ

ꢁendinꢂ

ꢀadius

ꢀ

C1005_Y5V_SMD • 7/21/2016 14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Figure 6 – Reel Dimensions

ꢂull ꢃadius,

ꢎ3 (ꢈncludes

flanꢏe distortion

at outer edꢏe)

ꢀccess ꢅole at

Slot Location

(ꢆ ꢇ0 mm minimum)

See ꢁote

ꢎꢊ (Measured at huꢐ)

D

(See ꢁote)

ꢀ

ꢁ

C

(ꢀrꢐor hole

ꢎꢍ (Measured at huꢐ)

diameter)

ꢈf present,

tape slot in core

for tape startꢉ

ꢊ.5 mm minimum ꢋidth ꢌ

ꢍ0.0 mm minimum depth

ꢄ

(see ꢁote)

ꢁoteꢉ Driꢑe spoꢒes optionalꢓ if used, dimensions ꢄ and D shall apply.

Table 8 – Reel Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

Tape Size

8 mm

A

BꢀMinimum

C

DꢀMinimum

178 ±0.20

(7.008 ±0.008)

or

1.5

(0.059)

13.0ꢀ+0.5/-0.2ꢀ

(0.521ꢀ+0.02/-0.008)

20.2

(0.795)

12 mm

16 mm

330 ±0.20

(13.000 ±0.008)

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

NꢀMinimum

W₁

W₂ꢀMaximum

W₃

8.4ꢀ+1.5/-0.0

(0.331ꢀ+0.059/-0.0)

14.4

(0.567)

50

(1.969)

12.4ꢀ+2.0/-0.0

18.4

Shallꢀaccommodateꢀtapeꢀ

widthꢀwithoutꢀinterference

12 mm

16 mm

(0.488ꢀ+0.078/-0.0)ꢀꢀ

(0.724)

16.4ꢀ+2.0/-0.0

(0.646ꢀ+0.078/-0.0)

22.4

(0.882)

C1005_Y5V_SMD • 7/21/2016 15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

ꢅmꢍossed Carrier

Carrier ꢀape

ꢊunched Carrier

ꢋ mm ꢌ ꢁꢇ mm only

ꢂound Sprocꢃet ꢄoles

ꢃTAꢄT

ꢀꢁꢂ

ꢀop Coꢉer ꢀape

ꢅlonꢆated Sprocꢃet ꢄoles

(3ꢇ mm tape and ꢈider)

ꢁ00 mm

Minimum Leader

ꢎ00 mm Minimum

ꢀrailer

Components

ꢁ60 mm Minimum

ꢀop Coꢉer ꢀape

Figure 8 – Maximum Camber

ꢇlonꢆated sprocꢂet holes

(3ꢈ mm ꢉ ꢊider tapes)

Carrier ꢀape

ꢁound Sprocꢂet ꢃoles

ꢄ mm Maꢅimum, either direction

Straiꢆht ꢇdꢆe

ꢈ50 mm

C1005_Y5V_SMD • 7/21/2016 16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

KEMET Electronic Corporation Sales Ofﬁces

Forꢀaꢀcompleteꢀlistꢀofꢀourꢀglobalꢀsalesꢀof ꢀces,ꢀpleaseꢀvisitꢀwww.kemet.com/sales.

Disclaimer

Allꢀproductꢀspeci ꢀcations,ꢀstatements,ꢀinformationꢀandꢀdataꢀ(collectively,ꢀtheꢀ“Information”)ꢀinꢀthisꢀdatasheetꢀareꢀsubjectꢀtoꢀchange.ꢀTheꢀcustomerꢀisꢀresponsibleꢀforꢀ

checkingꢀandꢀverifyingꢀtheꢀextentꢀtoꢀwhichꢀtheꢀInformationꢀcontainedꢀinꢀthisꢀpublicationꢀisꢀapplicableꢀtoꢀanꢀorderꢀatꢀtheꢀtimeꢀtheꢀorderꢀisꢀplaced.

AllꢀInformationꢀgivenꢀhereinꢀisꢀbelievedꢀtoꢀbeꢀaccurateꢀandꢀreliable,ꢀbutꢀitꢀisꢀpresentedꢀwithoutꢀguarantee,ꢀwarranty,ꢀorꢀresponsibilityꢀofꢀanyꢀkind,ꢀexpressedꢀorꢀimplied.

StatementsꢀofꢀsuitabilityꢀforꢀcertainꢀapplicationsꢀareꢀbasedꢀonꢀKEMETꢀElectronicsꢀCorporation’sꢀ(“KEMET”)ꢀknowledgeꢀofꢀtypicalꢀoperatingꢀconditionsꢀforꢀsuchꢀ

applications,ꢀbutꢀareꢀnotꢀintendedꢀtoꢀconstituteꢀ–ꢀandꢀKEMETꢀspeci ꢀcallyꢀdisclaimsꢀ–ꢀanyꢀwarrantyꢀconcerningꢀsuitabilityꢀforꢀaꢀspeci ꢀcꢀcustomerꢀapplicationꢀorꢀuse.ꢀ

TheꢀInformationꢀisꢀintendedꢀforꢀuseꢀonlyꢀbyꢀcustomersꢀwhoꢀhaveꢀtheꢀrequisiteꢀexperienceꢀandꢀcapabilityꢀtoꢀdetermineꢀtheꢀcorrectꢀproductsꢀforꢀtheirꢀapplication.ꢀAnyꢀ

technicalꢀadviceꢀinferredꢀfromꢀthisꢀInformationꢀorꢀotherwiseꢀprovidedꢀbyꢀKEMETꢀwithꢀreferenceꢀtoꢀtheꢀuseꢀofꢀKEMET’sꢀproductsꢀisꢀgivenꢀgratis,ꢀandꢀKEMETꢀassumesꢀnoꢀ

obligationꢀorꢀliabilityꢀforꢀtheꢀadviceꢀgivenꢀorꢀresultsꢀobtained.

AlthoughꢀKEMETꢀdesignsꢀandꢀmanufacturesꢀitsꢀproductsꢀtoꢀtheꢀmostꢀstringentꢀqualityꢀandꢀsafetyꢀstandards,ꢀgivenꢀtheꢀcurrentꢀstateꢀofꢀtheꢀart,ꢀisolatedꢀcomponentꢀ

failuresꢀmayꢀstillꢀoccur.ꢀAccordingly,ꢀcustomerꢀapplicationsꢀwhichꢀrequireꢀaꢀhighꢀdegreeꢀofꢀreliabilityꢀorꢀsafetyꢀshouldꢀemployꢀsuitableꢀdesignsꢀorꢀotherꢀsafeguardsꢀ

(suchꢀasꢀinstallationꢀofꢀprotectiveꢀcircuitryꢀorꢀredundancies)ꢀinꢀorderꢀtoꢀensureꢀthatꢀtheꢀfailureꢀofꢀanꢀelectricalꢀcomponentꢀdoesꢀnotꢀresultꢀinꢀaꢀriskꢀofꢀpersonalꢀinjuryꢀorꢀ

propertyꢀdamage.

Althoughꢀallꢀproduct–relatedꢀwarnings,ꢀcautionsꢀandꢀnotesꢀmustꢀbeꢀobserved,ꢀtheꢀcustomerꢀshouldꢀnotꢀassumeꢀthatꢀallꢀsafetyꢀmeasuresꢀareꢀindictedꢀorꢀthatꢀotherꢀ

measuresꢀmayꢀnotꢀbeꢀrequired.

KEMET is a registered trademark of KEMET Electronics Corporation.

C1005_Y5V_SMD • 7/21/2016 17


型号：	C0603C104Z3VACTU
厂家：	KEMET CORPORATION
描述：	Capacitor, Ceramic, Chip, General Purpose, 0.1uF, 25V, +80-20%, Y5V, 0603 (1608 mm), -30º ~ +85ºC, 7" Reel/Unmarked 电容器
文件：	总17页 (文件大小：1279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C0603C104Z3VACTU [KEMET]

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