Z86C3616PEC [IXYS]
Microcontroller, 8-Bit, MROM, Z8 CPU, 16MHz, CMOS, PDIP28,;型号: | Z86C3616PEC |
厂家: | IXYS CORPORATION |
描述: | Microcontroller, 8-Bit, MROM, Z8 CPU, 16MHz, CMOS, PDIP28, 时钟 微控制器 光电二极管 外围集成电路 |
文件: | 总70页 (文件大小:2256K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT SPECIFICATION
Z86C34/C35/C36
Z86C44/C45/C46
®
CMOS Z8 MCUS WITH ASCI UART
OFFER EFFICIENT, COST-EFFECTIVE
DESIGN FLEXIBILITY
FEATURES
• Expanded Register File (ERF)
• Full-Duplex UART (ASCI)
• Dedicated 16-Bit Baud Rate Generator
ROM
(KB)
RAM*
(Bytes)
Speed
(MHz)
Device
Z86C34
Z86C35
Z86C36
Z86C44
Z86C45
Z86C46
16
32
64
16
32
64
237
237
237
236
236
236
16
16
16
16
16
16
• 32 Input/Output Lines (C44/C45/C46)
24 Input/Output Lines (C34/C35/C36)
• Vectored, Prioritized Interrupts with Programmable Po-
larity
Note: *General-Purpose.
• Two Analog Comparators
• Two Programmable 8-Bit Counter/Timers, Each with
Two 6-Bit Programmable Prescaler
• 28-Pin DIP, 28-Pin SOIC and PLCC Packages (C34,
C35, C36)
• Watch-Dog Timer (WDT)/Power-On Reset (POR)
LQFP Packages (C44,
• 40-Pin DIP, 44-Pin PLCC and
• On-Chip Oscillator that Accepts a Crystal, Ceramic Res-
C45, C46)
onator, LC, RC, or External Clock
• 3.0- to 5.5-Volt Operating Range
• Clock Free Watch-Dog Timer (WDT) Reset
• RAM and ROM Protect
• Optional 32-kHz Oscillator
• Operating Temperature Ranges:
Standard: 0 °C to 70 °C
Extended: –40 °C to +105 °C
GENERAL DESCRIPTION
ZiLOG’s Z8® MCU single-chip family now includes the
Z86C34/C35/C36/C44/C45/C46productline,featuringen-
hanced wake-up circuitry, programmable Watch-Dog Tim-
ers (WDT), and low-noise/EMI options. Each of the new en-
hancements to the Z8 offer a more efficient, cost-effective
designandprovidetheuserwithincreaseddesignflexibility
over the standard Z8 microcontroller core. The low-power
consumption CMOS microcontroller offers fast execution,
efficient use of memory, sophisticated interrupts, input/out-
put bit manipulation capabilities, and easy hardware/soft-
ware system expansion.
The Z8 subfamily features an Expanded Register File (ERF)
to allow access to register-mapped peripheral and I/O cir-
cuits. Four basic address spaces are available to support this
wide range of configurations: Program Memory, Register
File, DataMemory, and ERF. TheRegisterFileiscomposed
of 236/237 bytes of general-purpose registers, four I/O port
registers, and 15 control and status registers. The ERF con-
sists of twelve control registers.
For applications demanding powerful I/O capabilities, the
Z86C34/C35/C36 offers 24 pins, and the Z86C44/C45/C46
offers 32 pins dedicated to input and output. These lines are
DS007601-Z8X0499
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
GENERAL DESCRIPTION (Continued)
configurable under software control to provide timing, sta-
tus signals, parallel I/O with or without handshake, and ad-
dress/data bus for interfacing external memory.
Note: All signals with an overline are active Low. For exam-
ple, B/W, for which WORD is active Low, and B/W, for
which BYTE is active Low.
To unburden the system from coping with real-time tasks
such as counting/timing and data communication, the Z8
offer two on-chip counter/timers with a large number of
user-selectable modes.
Power connections follow these conventional descriptions:
Connection
Power
Circuit
Device
With ROM/ROMless selectivity, the Z86C44/C45/C46
provide both external memory and preprogrammed ROM,
which enables this Z8® MCU to be used in high-volume ap-
plications, or where code flexibility is required.
V
V
V
CC
DD
SS
Ground
GND
(C44/C45/C46 Only)
Output Input
V
GND
CC
XTAL AS DS R/W RESET
Machine
Timing & Inst.
Control
Port 3
RESET
WDT, POR
Counter/
Timers (2)
ALU
Interrupt
Control
FLAG
Program
Memory
Two Analog
Comparators
Register
Pointer
Program
Counter
Full-Duplex
UART
Register File
16-Bit Baud
Rate Generator
Port 2
Port 0
Port 1
8
4
4
I/O
Address or I/O
(Nibble Programmable)
(Bit Programmable)
Address/Data or I/O
(Byte Programmable)
(C44/C45/C46 Only)
Figure 1. Functional Block Diagram
2
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN DESCRIPTION
1
P25
P26
P27
P04
P05
P06
P07
28
P24
P23
P22
P21
P20
P03
GND
P02
P01
P00
P30
P36
P37
P35
4
26
25
1
P21
P20
P03
GND
P02
P01
P00
P05
P06
P07
5
Z86C34/C35/C36
Z86C34/C35/C36
V
CC
V
CC
XTAL2
XTAL1
P31
XTAL2
XTAL1
P31
11
19
18
12
P32
P33
P34
14
15
Figure 2. 28-Pin DIP/SOIC Pin Configuration
Figure 3. 28-Pin PLCC Pin Configuration
Table 1. 28-Pin DIP/SOIC/PLCC Pin Identification
Pin #
Symbol
Function
Direction
1–3
4–7
8
P25–27
P04–07
Port 2, Bits 5,6,7
Port 0, Bits 4,5,6,7
Power Supply
In/Output
In/Output
V
CC
9
XTAL2
XTAL1
P31–33
P34–35
P37
Crystal Oscillator
Crystal Oscillator
Port 3, Bits 1,2,3
Port 3, Bits 4,5
Port 3, Bit 7
Output
10
Input
11–13
14–15
16
Fixed Input
Fixed Output
Fixed Output
Fixed Output
Fixed Input
In/Output
17
P36
Port 3, Bit 6
18
P30
Port 3, Bit 0
19–21
22
P00–02
GND
Port 0, Bits 0,1,2
Ground
23
P03
Port 0, Bit 3
In/Output
In/Output
24–28
P20–24
Port 2, Bits 0,1,2,3,4
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P R E L I M I N A R Y
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN DESCRIPTION (Continued)
1
R/W
P25
P26
P27
P04
P05
P06
P14
P15
P07
40
DS
P24
P23
P22
P21
P20
P03
P13
P12
GND
P02
P11
P10
P01
P00
P30
P36
P37
P35
RESET
Z86C44/C45/C46
V
CC
P16
P17
XTAL2
XTAL1
P31
P32
P33
P34
AS
20
21
Figure 4. 40-Pin DIP Configuration
Table 2. 40-Pin Dual-In-Line Package Pin Identification
Table 2. 40-Pin Dual-In-Line Package Pin Identification
Pin # Symbol Function
Direction
Pin # Symbol Function
Direction
1
R/W
READ/WRITE
Port 2, Bits 5,6,7
Port 0, Bits 4,5,6
Port 1, Bits 4,5
Port 0, Bit 7
Output
21
22
23
24
25
RESET
P35
Reset
Input
2–4
5–7
8–9
10
P25–27
P04–06
P14–15
P07
In/Output
In/Output
In/Output
In/Output
Port 3, Bit 5
Port 3, Bit 7
Port 3, Bit 6
Port 3, Bit 0
Port 0, Bit 0,1
Port 1, Bit 0,1
Port 0, Bit 2
Ground
Output
Output
Output
Input
P37
P36
P30
11
V
Power Supply
26–27 P00–01
28–29 P10–11
In/Output
In/Output
In/Output
CC
12–13 P16–17
Port 1, Bits 6,7
Crystal Oscillator
Crystal Oscillator
Port 3, Bits 1,2,3
Port 3, Bit 4
In/Output
Output
Input
30
31
P02
14
15
XTAL2
XTAL1
GND
32–33 P12–13
34 P03
35–39 P20–24
40 DS
Port 1, Bit 2,3
Port 0, Bit 3
Port 2, Bit 0,1,2,3,4
Data Strobe
In/Output
In/Output
In/Output
Output
16–18 P31–33
Input
19
20
P34
AS
Output
Output
Address Strobe
4
P R E L I M I N A R Y
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
6
1
40
39
7
P21
P22
P23
P24
DS
P30
P36
P37
P35
RESET
R/RL
AS
P34
P33
P32
P31
Z86C44/C45/C46
NC
R/W
P25
P26
P27
P04
17
29
28
18
Figure 5. 44-Pin PLCC Pin Configuration
Table 3. 44-Pin PLCC Pin Identification
Table 3. 44-Pin PLCC Pin Identification
Pin #
Symbol Function
Direction
Pin #
Symbol Function
Direction
1–2
3–4
5
GND
P12–13
P03
Ground
27
28
XTAL2
XTAL1
Crystal Oscillator
Output
Input
Port 1, Bits 2,3
Port 0, Bit 3
In/Output
In/Output
In/Output
Output
Crystal Oscillator
Port 3, Bits 1,2,3
Port 3, Bit 4
29–31 P31–33
Input
6–10
11
P20–24
DS
Port 2, Bits 0,1,2,3,4
Data Strobe
32
33
34
35
36
37
38
39
P34
Output
Output
AS
Address Strobe
12
NC
Not Connected
READ/WRITE
Port 2, Bits 5,6,7
Port 0, Bits 4,5,6
Port 1, Bits 4,5
Port 0, Bit 7
R/RL
RESET
P35
ROM/ROMless Control Input
13
R/W
Output
Reset
Input
14–16 P25–27
17–19 P04–06
20–21 P14–15
In/Output
In/Output
In/Output
In/Output
Port 3, Bit 5
Port 3, Bit 7
Port 3, Bit 6
Port 3, Bit 0
Port 0, Bits 0,1
Port 1, Bits 0,1
Port 0, Bit 2
Output
Output
Output
Input
P37
P36
22
P07
P30
23–24
V
Power Supply
40–41 P00–01
42–43 P10–11
In/Output
In/Output
In/Output
CC
25–26 P16–17
Port 1, Bits 6,7
In/Output
44
P02
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P R E L I M I N A R Y
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN DESCRIPTION (Continued)
33
34
23
22
P21
P22
P23
P24
DS
P30
P36
P37
P35
RESET
R/RL
AS
P34
P33
P32
P31
NC
Z86C44/C45/C46
R/W
P25
P26
P27
P04
44
1
12
11
Figure 6. 44-Pin LQFP Pin Configuration
Table 4. 44-Pin LQFP Pin Identification
Table 4. 44-Pin LQFP Pin Identification
Pin # Symbol Function Direction
Pin # Symbol Function
Direction
1–2
3–4
5
P05–06
P14–15
P07
Port 0, Bits 5,6
Port 1, Bits 4,5
Port 0, Bit 7
In/Output
In/Output
In/Output
21
22
P36
P30
Port 3, Bit 6
Output
Port 3, Bit 0
Input
23–24 P00–01
25–26 P10–11
Port 0, Bits 0,1
Port 1, Bits 0,1
Port 0, Bit 2
In/Output
In/Output
In/Output
6–7
V
Power Supply
CC
27
P02
8–9
10
P16–17
XTAL2
XTAL1
Port 1 Bits 6,7
In/Output
Output
Input
28–29 GND
Ground
Crystal Oscillator
Crystal Oscillator
Port 3, Bits 1,2,3
Port 3, Bit 4
30–31 P12–13
Port 1, Bits 2,3
Port 0, Bit 3
In/Output
In/Output
In/Output
Output
11
32
P03
12–14 P31–33
Input
33–37 P20–24
Port 2, Bits 0,1,2,3,4
Data Strobe
Not Connected
READ/WRITE
15
16
17
18
19
20
P34
Output
Output
38
39
40
DS
AS
Address Strobe
NC
R/RL
RESET
P35
ROM/ROMless Control Input
R/W
Output
Reset
Input
Port 3, Bit 5
Port 3, Bit 7
Output
Output
P37
6
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Units
Notes
Ambient Temperature under Bias
Storage Temperature
–40
–65
–0.6
+105
+150
+7
C
C
V
Voltage on any Pin with Respect to V
1
2
SS
Voltage on V Pin with Respect to V
–0.3
–0.6
+7
V
V
DD
SS
Voltage on XTAL1 and RESET Pins with Respect to V
Total Power Dissipation
V
+1
SS
DD
1.21
220
W
Maximum Allowable Current out of V
mA
SS
Maximum Allowable Current into V
180
mA
DD
Maximum Allowable Current into an Input Pin
–600
–600
+600
+600
25
µA
µA
3
4
Maximum Allowable Current into an Open-Drain Pin
Maximum Allowable Output Current Sunk by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
mA
mA
25
Notes:
1. Applies to all pins except XTAL pins and where otherwise noted.
2. There is no input protection diode from pin to V
3. Excludes XTAL pins.
and current into pin is limited to 600 µA.
DD
4. Device pin is not at an output Low state.
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
rating is a stress rating only. Functional operation of the de-
vice at any condition above those indicated in the opera-
tional sections of these specifications is not implied. Expo-
suretoabsolutemaximumratingconditionsforanextended
period may affect device reliability.
Total power dissipation should not exceed 1.21 W for the
package. Power dissipation is calculated as follows:
Total Power Dissipation = V x [I – (sum of I ),
DD
DD
OH
+ sum of [(V – V ) x I ]
OH
DD
OH
+ sum of (V x I
)
OL
OL
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P R E L I M I N A R Y
7
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
STANDARD TEST CONDITIONS
The characteristics listed in following pages apply for stan-
dard test conditions as noted. All voltages are referenced
to GND. Positive current flows into the referenced pin (see
Figure 7.)
From Output
Under Test
150 pF
Figure 7. Test Load Diagram
CAPACITANCE
TA = 25ºC, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins to GND
Parameter
Min
Max
Input capacitance
Output capacitance
I/O capacitance
0
0
0
12 pF
12 pF
12 pF
8
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
DC ELECTRICAL CHARACTERISTICS
Table 5. DC Characteristics
T =
T =
A
A
0°C to +70°C
–40°C to +105°C
2
Typical
1
V
Sym
Parameter
Min
Max
Min
Max
@25°C Units Conditions
Notes
CC
V
Clock Input 3.0V
High
Voltage
0.7 V
V
V
+0.3 0.7 V
V
V
+0.3
1.8
2.6
1.2
2.1
V
V
V
V
Driven by
External Clock
Generator
CH
CC
CC
CC
CC
5.5V
0.7 V
+0.3 0.7 V
+0.3
Driven by
External Clock
Generator
CC
CC
CC
CC
V
Clock Input 3.0V GND–0.3 0.2 V
Low
Voltage
GND–0.3 0.2 V
GND–0.3 0.2 V
Driven by
External Clock
Generator
CL
CC
CC
5.5V GND–0.3 0.2 V
Driven by
CC
CC
External Clock
Generator
V
V
V
Input High
Voltage
3.0V
5.5V
0.7 V
0.7 V
V
V
+0.3 0.7 V
+0.3 0.7 V
V
V
+0.3
+0.3
1.8
2.6
1.1
1.6
3.1
4.8
V
V
V
V
V
V
IH
CC
CC
CC
CC
CC
CC
CC
CC
Input Low
Voltage
3.0V GND–0.3 0.2 V
5.5V GND–0.3 0.2 V
GND–0.3 0.2 V
GND–0.3 0.2 V
IL
CC
CC
CC
CC
Output
High
Voltage
(Low-EMI
Mode)
3.0V
5.0V
V
V
–0.4
–0.4
V
V
–0.4
–0.4
I
I
= –0.5 mA
= –0.5 mA
OH
CC
CC
CC
CC
OH
OH
V
V
Output
High
Voltage
3.0V
5.5V
V
V
–0.4
–0.4
V
V
–0.4
–0.4
3.1
4.8
V
V
I
I
= –2.0 mA
= –2.0 mA
3
3
OH1
OL
CC
CC
CC
OH
OH
CC
Output Low 3.0V
Voltage
(Low-EMI
0.6
0.6
0.2
0.1
V
V
I
I
= 1.0 mA
= 1.0 mA
OL
OL
5.0V
0.4
0.4
Mode)
V
Output Low 3.0V
0.6
0.4
0.6
0.4
0.2
0.1
V
V
I
I
= +4.0 mA
= +4.0 mA
3
3
OL1
OL
OL
Voltage
5.5V
Notes:
1. The V voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at V = 3.3V, and the V voltage
CC
CC
CC
specification of 5.5V guarantees 5.0V 0.5V with typicals at V = 5.0V.
CC
2. Typicals are at V = 5.0V and 3.3V.
CC
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at V
.
CC
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0ºC to 70ºC (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The V voltage increases as the temperature decreases and overlaps lower V operating region.
LV
CC
12. –40˚C to 150˚C (extended temperature).
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P R E L I M I N A R Y
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
DC ELECTRICAL CHARACTERISTICS (Continued)
Table 5. DC Characteristics (Continued)
T =
T =
A
A
0°C to +70°C
–40°C to +105°C
2
Typical
@25°C Units Conditions
1
V
Sym
Parameter
Min
Max
Min
Max
1.2
Notes
CC
V
Output Low 3.0V
1.2
1.2
0.3
0.4
1.8
2.6
V
V
V
V
I
I
= +6 mA
3
3
4
4
OL2
OL
OL
Voltage
5.5V
1.2
= +12 mA
V
Reset Input 3.0V
.8 V
V
.8 V
V
V
RH
CC
CC
CC
CC
CC
CC
High
Voltage
5.5V
.8 V
V
.8 V
CC
CC
V
V
V
Reset Input 3.0V GND–0.3 0.2 V
GND–0.3 0.2 V
GND–0.3 0.2 V
1.1
1.6
V
V
4
4
Rl
CC
CC
Low
5.5V GND–0.3 0.2 V
Voltage
CC
CC
Reset
Output Low
Voltage
3.0V
5.5V
0.6
0.6
0.6
0.3
0.3
V
V
I
I
= +1.0 mA
= +1.0 mA
4
4
OLR
OL
OL
0.6
Comparator 3.0V
25
25
25
25
10
10
mV
mV
5
5
OFFSET
Input Offset
5.5V
Voltage
I
I
Input
Leakage
3.0V
5.5V
3.0V
5.5V
–1
–1
–1
–1
2
2
1
1
–1
–1
–1
–1
2
2
2
2
0.004
0.004
0.004
0.004
µA
µA
µA
µA
V
V
V
V
= 0V, V
= 0V, V
= 0V, V
= 0V, V
IL
IN
IN
IN
IN
CC
CC
CC
CC
Output
Leakage
OL
IIR
Reset Input 3.0V
–20
–20
–130
–180
20
–18
–18
–130
–180
20
–60
–85
7
µA
µA
Current
5.5V
I
Supply
Current
3.0V
5.5V
3.0V
5.5V
mA @ 16 MHz
mA @ 16 MHz
mA @ 12 MHz
mA @ 12 MHz
6
6
6
6
CC
25
25
20
5
15
15
20
20
15
Notes:
1. The V voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at V = 3.3V, and the V voltage
CC
CC
CC
specification of 5.5V guarantees 5.0V 0.5V with typicals at V = 5.0V.
CC
2. Typicals are at V = 5.0V and 3.3V.
CC
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at V
.
CC
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0ºC to 70ºC (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The V voltage increases as the temperature decreases and overlaps lower V operating region.
LV
CC
12. –40˚C to 150˚C (extended temperature).
10
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Table 5. DC Characteristics (Continued)
T =
T =
A
A
0°C to +70°C
–40°C to +105°C
2
Typical
1
V
Sym
Parameter
Min
Max
Min
Max
@25°C Units Conditions
Notes
CC
I
Standby
Current
(HALT
3.0V
5.5V
3.0V
4.5
4.5
2.0
3.7
1.5
mA V = 0V, V
6
CC1
IN
CC
@ 16 MHz
8
8
mA V = 0V, V
6
6
IN
CC
Mode)
@ 16 MHz
3.4
3.4
mA Clock Divide-
by-16 @ 16
MHz
5.5V
3.0V
7.0
8
7.0
8
2.9
2
mA Clock Divide-
by-16 @ 16
MHz
6
I
Standby
Current
(STOP
µA
µA
µA
µA
V
= 0V, V
CC
7,8
CC2
IN
WDT is not
Running
Mode)
5.5V
3.0V
5.5V
10
10
4
V
= 0V, V
7,8
IN
CC
WDT is not
Running
500
800
600
310
600
V
= 0V, V
7,8,9
7,8,9
IN
CC
WDT is
Running
1000
V
= 0V, V
IN
CC
WDT is
Running
V
Input
Common
Mode
3.0V
5.5V
0
0
V
V
–1.0V
0
0
V
V
–1.5V
V
V
5
5
ICR
CC
CC
CC
–1.0V
–1.5V
CC
Voltage
Range
I
I
Auto Latch
Low
Current
3.0V
5.5V
0.7
1.4
8
0.7
1.4
10
20
3
5
µA 0V < V < V
10
10
ALL
IN
CC
15
µA 0V < V < V
IN
CC
Auto Latch
High
Current
3.0V
5.5V
–0.6
–1.0
–5
–8
–0.6
–1.0
–7
–3
–6
µA 0V < V < V
10
10
ALH
IN
CC
–10
µA 0V < V < V
IN
CC
Notes:
1. The V voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at V = 3.3V, and the V voltage
CC
CC
CC
specification of 5.5V guarantees 5.0V 0.5V with typicals at V = 5.0V.
CC
2. Typicals are at V = 5.0V and 3.3V.
CC
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at V
.
CC
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0ºC to 70ºC (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The V voltage increases as the temperature decreases and overlaps lower V operating region.
LV
CC
12. –40˚C to 150˚C (extended temperature).
DS007601-Z8X0499
P R E L I M I N A R Y
11
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
DC ELECTRICAL CHARACTERISTICS (Continued)
Table 5. DC Characteristics (Continued)
T =
T =
A
A
0°C to +70°C
–40°C to +105°C
2
Typical
@25°C Units Conditions
1
V
Sym
Parameter
Low
Min
Max
Min
Max
Notes
CC
V
V
2.0
3.3
2.8
V
4 MHz max
11,12
LV
CC
Int. CLK Freq.
Voltage
Protection
Voltage
2.2
3.1
2.8
6 MHz max
Int. CLK Freq.
9,11
Notes:
1. The V voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at V = 3.3V, and the V voltage
CC
CC
CC
specification of 5.5V guarantees 5.0V 0.5V with typicals at V = 5.0V.
CC
2. Typicals are at V = 5.0V and 3.3V.
CC
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at V
.
CC
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0ºC to 70ºC (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The V voltage increases as the temperature decreases and overlaps lower V operating region.
LV
CC
12. –40˚C to 150˚C (extended temperature).
12
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
AC ELECTRICAL CHARACTERISTICS
External I/O or Memory READ and WRITE Timing
R/W
13
19
12
Port 0, DM
16
20
3
18
1
Port 1
AS
D7–D0 IN
A7–A0
2
9
8
11
4
5
6
DS
(Read)
17
10
Port1
A7–A0
D7–D0 OUT
14
15
7
DS
(Write)
Figure 8. External I/O or Memory READ and WRITE Timing
DS007601-Z8X0499
P R E L I M I N A R Y
13
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
AC ELECTRICAL CHARACTERISTICS (Continued)
Table 6. External I/O or Memory READ and WRITE Timing (C44/C45/C46 Only)
(SCLK/TCLK = XTAL/2)
T = –0ºC to 70ºC
T = –40ºC to +105ºC
A
A
12 MHz
16 MHz
12 MHz
16 MHz
1
V
No Symbol
Parameter
Min Max Min Max Min Max Min Max Units Notes
CC
1
2
3
4
5
6
7
8
9
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
Address Valid to AS
Rise Delay
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
35
35
45
45
25
25
35
35
35
35
45
45
25
25
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
AS Rise to Address
Float Delay
2
2
AS Rise to Read
Data Req’d Valid
250
250
180
180
250
250
180
180
2,3
2
AS Low Width
55
55
40
40
0
55
55
40
40
0
2
2
TdAS(DS)
TwDSR
Address Float to DS
Fall
0
0
0
0
0
0
DS (Read) Low
Width
200
200
110
110
135
135
80
80
200
200
110
110
135
135
80
80
2,3
2,3
2,3
2,3
2,3
2,3
2
TwDSW
DS (WRITE) Low
Width
TdDSR(DR) DS Fall to Read Data 3.0
150
150
75
75
150
150
75
75
Req’d Valid
5.5
ThDR(DS)
Read Data to DS
Rise Hold Time
3.0
5.5
3.0
5.5
3.0
5.5
0
0
0
0
0
0
0
0
2
10 TdDS(A)
DS Rise to Address
Active Delay
45
55
30
45
45
45
45
45
55
55
50
50
35
35
25
25
35
35
25
25
45
55
30
45
45
45
45
45
55
55
50
50
35
55
25
25
35
35
25
25
2
2
11 TdDS(AS)
DS Rise to AS Fall
Delay
2
2
12 TdR/W(AS) R/W Valid to AS Rise 3.0
2
Delay
5.5
2
13 TdDS(R/W) DS Rise to R/W Not
Valid
3.0
5.5
2
2
14 TdDW(DSW) WRITE Data Valid to 3.0
2
DS Fall (WRITE)
Delay
5.5
2
15 TdDS(DW) DS Rise to WRITE
Data Not Valid Delay
3.0
5.5
3.0
5.5
45
45
35
35
45
45
35
35
ns
ns
ns
ns
2
2
16 TdA(DR)
Address Valid to
Read Data Req’d
Valid
310
310
230
230
310
310
230
230
2,3
2,3
Notes:
1. The V voltage specification of 3.0V guarantees 3.3V 0.3V, and the V voltage specification of 5.5V guarantees 5.0V
CC
CC
0.5V.
2. Timing numbers provided are for minimum TpC.
3. When using extended memory timing add 2 TpC.
14
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Table 6. External I/O or Memory READ and WRITE Timing (C44/C45/C46 Only)
(SCLK/TCLK = XTAL/2) (Continued)
T = –0ºC to 70ºC
T = –40ºC to +105ºC
A
A
12 MHz
16 MHz
12 MHz
16 MHz
1
V
No Symbol
Parameter
Min Max Min Max Min Max Min Max Units Notes
CC
17 TdAS(DS)
AS Rise to DS Fall
Delay
3.0
5.5
3.0
5.5
65
65
35
35
45
45
30
30
65
65
35
35
45
45
30
30
ns
ns
ns
ns
2
2
2
2
18 TdDM(AS) DM Valid to AS Fall
Delay
19 TdDs(DM)
20 ThDS(AS)
Notes:
DS Rise to DM Valid 3.0
45
45
35
35
45
45
35
35
ns
ns
2
2
Delay
5.5
DS Valid to Address
Valid Hold Time
3.0
5.5
45
45
35
35
45
45
35
35
ns
ns
2
2
1. The V voltage specification of 3.0V guarantees 3.3V 0.3V, and the V voltage specification of 5.5V guarantees 5.0V
CC
CC
0.5V.
2. Timing numbers provided are for minimum TpC.
3. When using extended memory timing add 2 TpC.
DS007601-Z8X0499
P R E L I M I N A R Y
15
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
AC ELECTRICAL CHARACTERISTICS (Continued)
Additional Timing Diagram
3
1
Clock
2
2
3
7
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 9. Additional Timing
16
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Table 7. Additional Timing (SCLK/TCLK = XTAL/2)
T = 0ºC to +70ºC T = –40ºC to +105ºC
A
A
12 MHz
16 MHz
12 MHz
16 MHz
1
No Symbol Parameter
Min Max Min Max Min Max Min Max Units Notes D1,D0
V
CC
1
TpC
Input Clock
Period
3.0V
5.5V
83
83
DC
DC
DC
DC
15
62.5
62.5
250
250
DC
DC
DC
DC
15
83
83
DC
DC
DC
DC
15
62.5
62.5
250
250
DC
DC
DC
DC
15
ns
ns
ns
ns
ns
ns
2,3,4
2,3,4
2,3
3.0V 250
5.5V 250
3.0V
250
250
2,3
2
3
TrC,TfC Clock Input
Rise & Fall
2,3
5.5V
15
15
15
15
2,3
Times
TwC
Input Clock
Width
3.0V
5.5V
41
41
31
31
41
41
31
31
ns
ns
ns
ns
ns
ns
2,3,4
2,3,4
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
3.0V 125
5.5V 125
3.0V 100
125
125
125
125
125
125
4
5
6
7
TwTinL
Timer Input
Low Width
100
100
100
5.5V
70
70
70
70
TwTinH Timer Input
High Width
3.0V 5TpC
5.5V 5TpC
3.0V 8TpC
5.5V 8TpC
3.0V
5TpC
5TpC
8TpC
8TpC
5TpC
5TpC
8TpC
8TpC
5TpC
5TpC
8TpC
8TpC
TpTin
Timer Input
Period
TrTin,
TfTin
Timer Input
Rise & Fall
Timer
100
100
100
100
100
100
100
100
ns
ns
5.5V
8A TwIL
8B TwIL
Int. Request
Low Time
3.0V 100
100
70
100
70
100
70
ns
ns
2,3,5
2,3,5
2,3,6
2,3,6
2,3,5
2,3,5
5.5V
70
Int. Request
Low Time
3.0V 5TpC
5.5V 5TpC
3.0V 5TpC
5.5V 5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
9
TwIH
Int. Request
Input High
Time
10 Twsm
Stop-Mode
Recovery
Width Spec
3.0V
5.5V
12
12
12
12
12
12
12
12
ns
ns
7
7
11 Tost
Oscillator
Startup Time
3.0V
5.5V
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
7,8
7,8
Notes:
1. The V voltage specification of 3.0V guarantees 3.3V 0.3V, and the V voltage specification of 5.5V guarantees 5.0V
CC
CC
0.5V.
2. Timing Reference uses 0.7 V for a logic 1and 0.2 V for a logic 0.
CC
CC
3. SMR D1 = 0.
4. Maximum frequency for external XTAL clock is 4 MHz when using low-EMI Oscillator mode PCON Reg.D7 = 0.
5. Interrupt request via Port 3 (P31–P33).
6. Interrupt request via Port 3 (P30).
7. SMR–D5 = 1, POR STOP Mode Delay is on.
8. For RC and LC oscillator, and for oscillator driven by clock driver.
9. Register WDTMR.
DS007601-Z8X0499
P R E L I M I N A R Y
17
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
AC ELECTRICAL CHARACTERISTICS (Continued)
Table 7. Additional Timing (SCLK/TCLK = XTAL/2) (Continued)
T = 0ºC to +70ºC T = –40ºC to +105ºC
A
A
12 MHz
16 MHz
12 MHz
16 MHz
1
No Symbol Parameter
Min Max Min Max Min Max Min Max Units Notes D1,D0
V
CC
12 Twdt
Watch-Dog
Timer Delay
Timer before
time-out
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
7
3.5
14
7
7
3.5
14
7
7
3.5
14
7
7
3.5
14
7
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
9
9
9
9
9
9
9
9
0,0
0,0
0,1
0,1
1,0
1,0
1,1
1,1
28
14
28
14
112
56
3
28
14
112
56
3
28
14
112
56
3
3.0V 112
5.5V
3.0V
5.5V
56
3
13 TPOR
Power-On
Reset Delay
24
13
24
13
25
14
25
14
1.5
1.5
1
1
Notes:
1. The V voltage specification of 3.0V guarantees 3.3V 0.3V, and the V voltage specification of 5.5V guarantees 5.0V
CC
CC
0.5V.
2. Timing Reference uses 0.7 V for a logic 1and 0.2 V for a logic 0.
CC
CC
3. SMR D1 = 0.
4. Maximum frequency for external XTAL clock is 4 MHz when using low-EMI Oscillator mode PCON Reg.D7 = 0.
5. Interrupt request via Port 3 (P31–P33).
6. Interrupt request via Port 3 (P30).
7. SMR–D5 = 1, POR STOP Mode Delay is on.
8. For RC and LC oscillator, and for oscillator driven by clock driver.
9. Register WDTMR.
18
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Table 8. Additional Timing
(Divide-By-One Mode, SCLK/TCLK = XTAL)
T = 0ºC to
T = 40ºC to
A
A
+70ºC
+105ºC
1
V
8 MHz
8 MHz
CC
No Symbol Parameter
Min
Max
Min
Max
Units Notes
1
TpC
Input Clock Period
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
250
250
125
125
DC
DC
DC
DC
25
250
250
125
125
DC
DC
DC
DC
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2,3,4
2,3,4
2,3
2,3
2
3
TrC,TfC Clock Input Rise
& Fall Times
2,3
25
25
2,3
TwC
Input Clock Width
125
125
125
125
2,3,4
2,3,4
2,3
62
62
62
62
2,3
4
5
6
7
TwTinL Timer Input Low Width
TwTinH Timer Input High Width
100
100
2,3
70
70
2,3
3TpC
3TpC
4TpC
4TpC
3TpC
3TpC
4TpC
4TpC
2,3
2,3
TpTin
Timer Input Period
2,3
2,3
TrTin,
TfTin
Timer Input Rise
& Fall Timer
100
100
100
100
ns
ns
ns
ns
2,3
2,3
8A TwIL
Int. Request Low Time
100
70
100
70
2,3,5
2,3,5
2,3,6
2,3,6
2,3,5
2,3,5
7
8B TwIL
Int. Request Low Time
3TpC
3TpC
3TpC
3TpC
12
3TpC
3TpC
3TpC
2TpC
12
9
TwIH
Int. Request Input
High Time
10 Twsm
11 Tost
Notes:
Stop-Mode Recovery
Width Spec
ns
ns
12
12
7
Oscillator Startup Time
5TpC
5TpC
5TpC
5TpC
7,8
7,8
1. The V voltage specification of 3.0V guarantees 3.3V 0.3V, and the V voltage specification of 5.5V guarantees 5.0V
CC
CC
0.5V.
2. Timing Reference uses 0.7 V for a logic “1” and 0.2 V for a logic “0”.
CC
CC
3. SMR D1 = 0.
4. Maximum frequency for external XTAL clock is 4 MHz when using low-EMI Oscillator mode PCON Reg.D7 = 0.
5. Interrupt request via Port 3 (P31–P33).
6. Interrupt request via Port 3 (P30).
7. SMR–D5 = 1, POR STOP Mode Delay is on.
8. For RC and LC oscillator, and for oscillator driven by clock driver.
DS007601-Z8X0499
P R E L I M I N A R Y
19
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
AC ELECTRICAL CHARACTERISTICS (Continued)
Handshake Timing Diagrams
Data In
Data In Valid
Next Data In Valid
2
1
3
Delayed DAV
DAV
(Input)
6
5
4
RDY
(Output)
Delayed RDY
Figure 10. Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
DAV
(Output)
Delayed DAV
9
11
8
10
RDY
(Input)
Delayed RDY
Figure 11. Output Handshake Timing
20
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
1
Table 9. Handshake Timing
T = 0°C to +70°C
T = –40°C to +105°C
A
A
12 MHz
16 MHz
12 MHz
16 MHz
Data
2
V
No Symbol
Parameter
Min Max Min Max Min Max Min Max Direction
CC
1
2
3
4
5
6
7
8
9
TsDI(DAV)
ThDI(RDY)
TwDAV
Data In Setup Time
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
0
0
0
0
0
0
0
0
IN
IN
Data In Hold Time
0
0
0
0
IN
0
0
0
0
IN
Data Available Width
155
110
155
110
155
110
155
110
IN
IN
TdDAVI(RDY) DAV Fall to RDY Fall
Delay
0
0
0
0
0
0
0
IN
0
IN
TdDAVId(RDY) DAV Out to DAV Fall
Delay
120
80
120
80
120
80
120
80
IN
IN
RDY0d(DAV)
RDY Rise to DAV Fall
Delay
0
0
0
0
0
0
0
0
IN
IN
TdD0(DAV)
Data Out to DAV Fall
Delay
42
42
0
31
31
0
42
42
0
31
31
0
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
TdDAV0(RDY) DAV Fall to RDY Fall
Delay
0
0
0
0
TdRDY0(DAV) RDY Fall to DAV Rise
Delay
160
115
160
115
160
115
160
115
10 TwRDY
RDY Width
3.0V 110
110
80
110
80
110
80
5.5V
3.0V
5.5V
80
11 TdRDY0d(DAV) RDY Rise to DAV Fall
Delay
110
80
110
80
110
80
110
80
Note:
1. Timing Reference uses 0.7 V for a logic 1and 0.2 V for a logic 0.
CC
CC
2. The V voltage specification of 3.0V guarantees 3.3V 0.3V. The V voltage specification of 5.5V guarantees 5.0V 0.5V.
CC
CC
DS007601-Z8X0499
P R E L I M I N A R Y
21
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN FUNCTIONS
R/RL (input, active Low). The ROM/ROMless pin, when
connected to GND, disables the internal ROM and forces
the device to function as a ROMless Z8. (Not available for
devices in the 28-pin package.)
AS (output, active Low). Address Strobe is pulsed one
time at the beginning of each machine cycle for external
memory transfer. Address output is from Port 0/Port 1 for
all external programs. Memory address transfers are valid
at the trailing edge of AS. Under program control, AS is
placed in the high-impedance state along with Ports 0 and
1, Data Strobe, and READ/WRITE. (Not available for de-
vices in the 28-pin package.)
Notes: When left unconnected or pulled High to VCC, the
device functions normally as a Z8 ROM version.
When using in ROM Mode in a high-EMI (noisy)
environment, the ROMless pins should be connected
XTAL1 Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, or RC net-
work, or an external single-phase clock to the on-chip os-
cillator input.
directly to V
.
CC
DS (output, active Low). Data Strobe is activated one
time for each external memory transfer. For a READ oper-
ation, data must be available prior to the trailing edge of DS.
For WRITE operations, the falling edge of DS indicates that
output data is valid. (Not available for devices in the 28-
pin package.)
XTAL2 Crystal 2 (time-based output). This pin connects
a parallel-resonant crystal, ceramic resonant, LC, or RC net-
work to the on-chip oscillator output.
R/W (output, WRITE Low). The READ/WRITE signal is
Low when the Z8 is writing to the external program or data
memory. (Not available for devices in the 28-pin package.)
22
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Port 0 (P00–P07). Port 0 is an 8-bit, bidirectional, CMOS-
compatible port. These eight I/O lines are configured under
software control as a nibble I/O port (P03–P00 input/output
and P07–P04 input/output), or as an address port for inter-
facingexternalmemory. TheinputbuffersareSchmitt-trig-
gered and nibble-programmed as outputs and can be glo-
bally programmed as either push-pull or open-drain. Low-
EMIoutputbufferscanbegloballyprogrammedbythesoft-
ware. Port 0 is placed under handshake control. In this con-
figuration, Port 3, lines P32 and P35 are used as the hand-
shake control DAV0 and RDY0. Handshake signal direction
is dictated by the I/O direction (input or output) of Port 0
of the upper nibble P04–P07. The lower nibble must indi-
cate the same direction as the upper nibble.
nibble) depending on the required address space. If the ad-
dress range requires 12 bits or less, the upper nibble of Port
0 can be programmed independently as I/O while the lower
nibble is used for addressing. If one or both nibbles are re-
quired for I/O operation, they are configured by writing to
the Port 0 mode register.
In ROMless mode, after a hardware RESET, Port 0 is con-
figured as address lines A15–A8, and extended timing is set
to accommodate slow memory access. The initialization
routine can include reconfiguration to eliminate this ex-
tended timing mode. (In ROM mode, Port 0 is defined as
input after RESET.)
Port 0 can be placed in a high-impedance state along with
Port 1, AS, DS and R/W, allowing the Z8 to share common re-
sources in multiprocessor and DMA applications (Figure 12).
For external memory references, Port 0 provides address
bits A11–A8 (lower nibble) or A15–A8 (lower and upper
4
Port 0
(I/O or A15–A8)
4
Z8
Handshake Controls
DAV0 and RDY0
(P32 and P35)
Open-Drain
OE
Pull-Up
Transistor Enable
(Mask Option)
PAD
Out
In
1.5
2.3 Hysteresis @ VCC = 5.0V
Auto Latch
(mask option)
R ≈ 500KΩ
Figure 12. Port 0 Configuration
DS007601-Z8X0499
P R E L I M I N A R Y
23
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN FUNCTIONS (Continued)
Port 1 (P17–P10). Port 1 is an 8-bit, bidirectional, CMOS-
compatible port (Figure 13), with multiplexed Address
(A7–A0) and Data (D7–D0) ports. For the ROM device,
these eight I/O lines are programmed as inputs or outputs,
or can be configured under software control as an Ad-
dress/Data port for interfacing external memory. The input
buffers are Schmitt-triggered and byte-programmed as out-
puts and can be globally programmed as either push-pull
oropen-drain.Low-EMIoutputbufferscanbegloballypro-
grammed by the software.
Port 1 may be placed under handshake control. In this con-
figuration, Port 3, lines P33 and P34 are used as the hand-
shake controls RDY1 and DAV1 (Ready and Data Avail-
able). Memory locations greater than the internal ROM
address are referenced through Port 1, except for Z86C46.
To interface external memory, Port 1 must be programmed
for the multiplexed Address/Data mode. If more than 256
externallocationsarerequired, Port0outputstheadditional
lines.
Port 1 can be placed in the high-impedance state along with
Port 0, AS, DS, and R/W, allowing the Z8 to share common
resources in multiprocessor and DMA applications.
Note: Port 1 is not available on the devices in the 28-pin pack-
age, and P01M Register must set Bit D4,D3 as 00. Low-
EMI mode is not supported on the emulator for Port1.
PCON register D4 must be 1.
Port 1
(I/O or AD7–AD0)
8
Z8
Handshake Controls
DAV1 and RDY1
(P33 and P34)
Open Drain
OE
Pull-Up
Transistor Enable
(Mask Option)
PAD
Out
1.5
2.3 Hysteresis @ VCC = 5.0V
In
Auto Latch
(mask option)
R ≈ 500 KΩ
Figure 13. Port 1 Configuration
24
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Port 2 (P27–P20). Port 2 is an 8-bit, bidirectional, CMOS-
compatible I/O port. These eight I/O lines are configured
under software control as an input or output, independently.
Port 2 is always available for I/O operation. The input buff-
ers are Schmitt-triggered. Bits programmed as outputs may
be globally programmed as either push-pull or open-drain.
Low-EMI output buffers can be globally programmed by
the software.
Port 2 may be placed under handshake control. In this Hand-
shake Mode, Port 3 lines P31 and P36 are used as the hand-
shake controls lines DAV2 and RDY2. The handshake signal
assignment for Port 3 lines P31 and P36 is dictated by the di-
rection (input or output) assigned to Bit 7, Port 2 (Figure 14).
Port 2 (I/O)
Z8
Handshake Controls
DAV2 and RDY2
(P31 and P36)
Open Drain
OE
Pull-Up
Transistor Enable
(Mask Option)
PAD
Out
1.5
2.3 Hysteresis @ VCC
= 5.0V.
In
Auto Latch
(mask option)
R ≈ 500 KΩ
Figure 14. Port 2 Configuration
DS007601-Z8X0499
P R E L I M I N A R Y
25
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN FUNCTIONS (Continued)
Port 3 (P37–P30). Port 3 is an 8-bit, CMOS-compatible
port, with four fixed inputs (P33–P30) and four fixed out-
puts (P34–P37). It is configured under software control for
Input/Output, Counter/Timers, interrupt, port handshake,
and Data Memory functions. Port 3, bit 0input is Schmitt-
triggered, and pins P31, P32, and P33 are standard CMOS
inputs (no Auto Latches). Pins P34, P35, P36, P37are push-
pull output lines. Low-EMI output buffers can be globally
programmed by the software.
(TOUT). Handshake lines for Ports 0, 1, and 2 are available
on P31 through P36.
Port 3 also provides the following control functions: hand-
shake for Ports 0, 1, and 2 (DAV and RDY); four external
interrupt request signals (IRQ3–IRQ0); timer input and out-
put signals (TIN and TOUT); Data Memory Select (DM, see
Table 10 and Figure 15).
P34 output can be software-programmed to function as a
Data Memory Select (DM). The Port 3 mode register (P3M)
Bit D3,D4 selects this function. When accessing external
Data Memory, the P34 goes active Low; when accessing
external Program Memory, the P34 goes High.
Two onboard comparators can process analog signals on
P31 and P32 with reference to the voltage on P33. The an-
alog function is enabled by programming Port 3 Mode Reg-
ister (P3M bit 1). For Interrupt functions, Port 3, bit 0and
pin 3 are falling edge interrupt inputs. P31 and P32 are pro-
grammable as rising, falling, or both edge triggered inter-
rupts (IRQ register Bits 6and 7). P33 is the comparator ref-
erence voltage input when in Analog mode. Access to
An onboard UART (ASCI) can be enabled by software by
setting the RE and TE bits of the ASCI Control Register A
(CNTLA). When enabled, P30 is the receive input and P37
is the transmit output.
Counter/Timers 1 is made through P31 (T ) and P36
IN
Table 10. Port 3 Pin Assignments
Analog Int. P0 HS P1 HS
Pin
I/O
CTC1
P2 HS
Ext
UART
P30
P31
IN
IN
IRQ3
IRQ2
RX
T
AN1
D/R
IN
P32
P33
P34
P35
P36
IN
AN2
REF
IRQ0
IRQ1
D/R
R/D
IN
D/R
R/D
OUT
OUT
OUT
AN1–OUT
DM
T
R/D
OUT
P37
OUT
AN2–OUT
TX
Notes:
HS = Handshake Signals
D = DAV
R = RDY
Comparator Inputs and Outputs. Port 3, pins P31 and
P32 each feature a comparator front end. The comparator
reference voltage, pin P33, is common to both comparators.
In analog mode, the P31 and P32 are the positive inputs to
the comparators and P33 is the reference voltage supplied
to both comparators. In digital mode, pin P33 can be used
as a P33 register input or IRQ1 source. P34 and P37 outputs
the comparator outputs by software-programming the
PCON Register Bit D0 to 1(see Figure 16).
Note: The user must add a two-NOP delay after selecting the
P3M bit D1 to 1before the comparator output is valid.
IRQ0, IRQ1, and IRQ2 should be cleared in the IRQ reg-
ister when the comparator is enabled or disabled.
26
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
P30
P31
P32
P33
Port 3
(I/O or Control)
Z8
P34
P35
P36
P37
Auto Latch
(mask option)
R ≈ 500KΩ
P30 Data
Latch IRQ3
P30
R247 = P3M
1 = Analog
0 = Digital
D1
DIG.
AN.
P31 (AN1)
IRQ2,T , P31 Data Latch
IN
+
–
P32 (AN2)
P33 (REF)
IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
+
–
From Stop-Mode
Recovery Source
Figure 15. Port 3 Configuration
DS007601-Z8X0499
P R E L I M I N A R Y
27
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN FUNCTIONS (Continued)
P34
P34 OUT
PAD
P31
+
–
REF (P33)
P37
P37 OUT
PAD
P32
+
–
REF (P33)
PCON
0 P34, P37 Standard Output
1 P34, P37 Comparator Output
D0
Figure 16. Port 3 Configuration
Auto Latch. The Auto Latch places valid CMOS levels on
all CMOS inputs (except P33–P31) that are not externally
driven. Whether this level is 0or 1cannot be determined.
A valid CMOS level, rather than a floating node, reduces
excessive supply current flow in the input buffer. Auto
Latches are available on Port 0, Port 1, Port 2, and P30.
There are no Auto Latches on P31, P32, and P33.
ditions. RESET depends on oscillator operation to achieve
full reset conditions, except for conditions wherein a WDT
resetispermanentlyenabled.Pull-upisprovidedinternally.
Note: The RESET pin is not available on devices in the 28-pin
package.
After the POR time, RESET is a Schmitt-triggered input.
During the RESET cycle, DS is held active Low while AS
Note: Deletion of all Port Auto Latches is available as a ROM
Mask option. The Auto Latch Delete option is selected
by the customer when the ROM code is submitted.
cycles at a rate of T C/2. Program execution begins at lo-
P
cation 000Ch, after the RESET is released. For Power-On
Reset, the reset output time is TPOR ms.
RESET (input, active Low). Initializes the MCU. Reset is
accomplished either through Power-On Reset, Watch-Dog
Timerreset, Stop-ModeRecovery, orexternalreset. During
Power-On Reset and Watch-Dog Reset, the internally-gen-
erated reset is driving the RESET pin Low for the POR time.
Any devices driving the RESET line must be open-drain to
avoid damage from a possible conflict during RESET con-
When program execution begins, AS and DS toggles only
for external memory accesses. The Z8 does not reset
WDTMR, SMR, P2M, PCON, and P3M registers on a Stop-
ModeRecoveryoperationorfroma WDTresetoutof STOP
mode.
28
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION
The Z8 MCU incorporates the following special functions
®
toenhancethestandardZ8 architecturetoprovidetheuser
with increased design flexibility.
65535
External/Internal
ROM and RAM
RESET. The device is reset in one of the following condi-
tions:
16383/32767
16382/32766
• Power-On Reset
Location of
On-Chip
ROM
First Byte of
Instruction
Executed
• Watch-Dog Timer
• Stop-Mode Recovery Source
• External Reset
12
11
10
9
After RESET
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
• Low Voltage Recovery
Auto Power-On Reset circuitry is built into the Z8, elimi-
nating the requirement for an external reset circuit to reset
upon power-up. The internal pull-up resistor is on the Reset
pin, so a pull-up resistor is not required; however, in a high-
EMI (noisy) environment, it is recommended that a small
value pull-up resistor be used.
8
7
Interrupt
Vector
(Lower Byte)
6
Note: The RESET pin is not available on devices in the 28-pin
5
package.
4
Interrupt
Vector
(Upper Byte)
Program Memory. The first 12 bytes of program memory
are reserved for the interrupt vectors. These locations con-
tain six 16-bit vectors that correspond to the six available
interrupts. For ROM mode, address 12 to address 65535
(C36/C46)/32767(C35/C45)/16383(C34/C44) consists
of on-chip mask-programmed ROM. The Z86C44/C45 can
access external program and data memory from addresses
16384/32768 to 65535.
3
2
1
0
Figure 17. Program Memory Map
for Z86C34/35/44/45
The 65535 (C36/C46)/32767 (C35/C45)/16383
(C34/C44) program memory is mask programmable. A
ROM protect feature prevents dumping of the ROM con-
tents by inhibiting execution of LDC, LDCI, LDE, and LDEI
instructions to Program Memory in external program
mode. ROM look-up tables can be used with this feature.
Data Memory (DM). The ROMless version can address up
to 64 KB of external data memory. External data memory
may be included with, or separated from, the external pro-
gram memory space. DM, an optional I/O function that can
be programmed to appear on pin P34, is used to distinguish
between data and program memory space (Figure 18). The
stateoftheDMsignaliscontrolledbythetypeofinstruction
being executed. An LDC Op Code references PROGRAM
(DM inactive) memory, and an LDE instruction references
data (DM active Low) memory. The user must configure
Port 3 Mode Register (P3M) bits D3 and D4 for this mode.
This feature is not usable for devices in 28-pin package.
When used in ROM mode, the Z86C46 cannot access any
external data memory. The Z86C44/C45 can access exter-
The ROM Protect option is mask-programmable, to be se-
lected by the customer when the ROM code is submitted.
DS007601-Z8X0499
P R E L I M I N A R Y
29
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
nal program and data memory from addresses
16384/32768to 65535.
knownastheExpandedRegisterFile(ERF).Bits7–4ofreg-
ister RP select the working register group. Bits 3–0 of reg-
ister RP select the expanded register group. Three system
configuration registers reside in the Expanded Register File
at Bank F (PCON, SMR, WDTMR). The rest of the Expand-
ed Register is not physically implemented, and is open for
future expansion.
Expanded Register File (ERF). The Z8 register file is ex-
panded to allow for additional system control registers, and
for mapping of additional peripheral devices along with I/O
ports into the register address area. The Z8 register address
space R0 through R15 is implemented as 16 groups of 16
registers per group (Figure 19). These register groups are
65535
65535
External
Data
Memory
External
Data
Memory
16384/32768
16383/32767
NotAddressable
0
0
ROM Mode
ROMless Mode
Figure 18. Data Memory Map
30
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Z8® STANDARD CONTROL REGISTERS
RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER
% FF
SPL
0
0
0
0
0
0
0
0
0
0
0
REGISTER POINTER
0
0
0
0
0
% FE
% FD
% FC
% FB
% FA
% F9
SPH
RP
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
FLAGS
IMR
IRQ
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
orkingRegister
ExpandedRegister
Group Pointer
W
Group Pointer
0
IPR
U
0
U
1
U
0
U
0
U
1
U
1
U
0
U
1
†
% F8
P01M
P3M
P2M
0
0
0
0
0
0
0
0
% F7
*
*
% F6
1
1
1
1
1
1
1
1
% F5
PRE0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
0
0
% F4
T0
U
0
Z8 Reg. File
% F3
PRE1
T1
%FF
%FO
% F2
U
0
U
0
% F1
TMR
Reserved
% F0
EXPANDED REG. GROUP (F)
REGISTER
RESET CONDITION
% (F) 0F
% (F) 0E
% (F) 0D
WDTMR
U
U
U
0
1
1
0
0
1
0
*
*
Reserved
U
U
U
U
U
U
SMR2
%7F
Reserved
SMR
% (F) 0C
% (F) 0B
**
0
0
1
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCON
% (F) 0A
% (F) 09
% (F) 08
% (F) 07
Reserved
% (F) 06
% (F) 05
% (F) 04
%0F
%00
% (F) 03
% (F) 02
% (F) 01
% (F) 00
*
*
1
1
1
1
1
1
1
0
EXPANDED REG. GROUP(0)
REGISTER
Notes:
RESET CONDITION
U = Unknown
†For ROMless Reset condition: “10110110”.
*Will not be reset with a STOP-Mode Recovery.
**Will not be reset with a STOP-Mode Recovery, except bit D0.
XNot available on 28-pin packages.
1
1
1
1
U
U
U
U
U
U
U
U
% (0) 03
% (0) 02
% (0) 01
P3
P2
P1
P0
*
U
U
U
U
X
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
% (0) 00
Figure 19. Expanded Register File Architecture
Register File. TheregisterfileconsistsoffourI/Oportreg-
isters, 236 general-purpose registers and 15 control and sta-
tusregisters(R0–R3, R4–R239andR240–R255, respective-
ly), plus three system configuration registers in the
expanded register group. The instructions access registers
directly or indirectly through an 8-bit address field. As a re-
sult, a short, 4-bit register address can use the Register
Pointer (Figure 20). In the 4-bit mode, the register file is
divided into 16 working register groups, each occupying 16
DS007601-Z8X0499
P R E L I M I N A R Y
31
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
continuous locations. The Register Pointer addresses the
starting location of the active working register group.
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Group
Working Register Group
Default setting after RESET = 00000000
Figure 20. Register Pointer
r7 r6 r5 r4
r3 r2 r1 r0
R253
(Register Pointer)
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
F0
R15 to R0
Register Group F
7F
70
6F
60
5F
50
4F
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register
40
3F
Specified Working
Register Group
30
2F
20
1F
Register Group 1
R15 to R0
10
0F
Register Group 0
I/O Ports
R15 to R4
R3 to R0
00
Figure 21. Register Pointer—Detail
32
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
General-Purpose Registers (GPR). These registers are
undefinedafterthedeviceispoweredup. Theregisterskeep
their most recent value after any RESET, as long as the RE-
Note: R254 and R255 are set to 00hafter any RESET or Stop-
Mode Recovery.
SET occurs in the V voltage-specified operating range.
CC
These do not keep their most recent state from a Low Volt-
Counter/Timers. There are two 8-bit programmable
counter/timers (T0–T1), each driven by its own 6-bit pro-
grammable prescaler. The T1 prescaler is driven by internal
or external clock sources; however, the T0 prescaler is driv-
en by the internal clock only (Figure 22).
age Protection (V ) RESET if the VCC drops below 1.8V.
LV
Note: Register Bank E0–EF is only accessed through working
register and indirect addressing modes.
The 6-bit prescalers can divide the input frequency of the
clocksourcebyanyintegernumberfrom1to64. Eachpres-
caler drives its counter, which decrements the value (1to
256) that is loaded into the counter. When the counter
reaches the end of the count, a timer interrupt request, IRQ4
(T0) or IRQ5 (T1), is generated.
RAM Protect. The upper portion of the RAM’s address
spaces %80Fto %EF(excluding the control registers) are
protected from writing. The RAM Protect bit option is
mask-programmable and is selected by the customer when
the ROM code is submitted. After the mask option is se-
lected, the user activates this feature from the internal ROM
code to turn off/on the RAM Protect by loading either a 0
or 1into the IMR register, bit D6. A 1in D6 enables RAM
Protect.
The counters can be programmed to START, STOP, restart
toCONTINUE,orrestartfromtheinitialvalue.Thecounters
can also be programmed to STOP upon reaching 0(single
pass mode) or to automatically reload the initial value and
continue counting (modulo–n continuous mode).
Stack. TheZ8internalregisterfileisusedforthestack. The
16-bit Stack Pointer (R254–R255) is used for the external
stack, which can reside anywhere in the data memory for
ROMless mode. An 8-bit Stack Pointer (R255) is used for
the internal stack that resides within the 236 general-pur-
pose registers (R4–R239). Stack Pointer High (SPH) is used
as a general-purpose register when using internal stack
only. The devices in 28-pin packages use the 8-bit stack
pointer (R255) for internal stack only.
The counters, but not the prescalers, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and is either the internal mi-
croprocessor clock divide-by-four, or an external signal in-
put through Port 3. The Timer Mode register configures the
external timer input (P31) as an external clock, a trigger in-
putthatcanberetriggerableornonretriggerable, orasagate
input for the internal clock. The counter/timers can be cas-
caded by connecting the T0 output to the input of T1. T
Mode is enabled by setting R243 PRE1 bit D1 to 0.
IN
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ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
OSC
Internal Data Bus
Write
D1 (SMR)
Write
Read
2
PRE0
T0
T0
Initial Value
Register
Initial Value
Register
Current Value
Register
D0 (SMR)
6-Bit
Down
8-bit
Down
16
÷4
Counter
Counter
IRQ4
Internal
Clock
TOUT
P36
÷2
External Clock
Clock
Logic
6-Bit
Down
Counter
8-Bit
Down
Counter
IRQ5
÷4
Internal Clock
Gated Clock
Triggered Clock
PRE1
Initial Value
Register
T1
T1
Initial Value
Register
Current Value
Register
TIN P31
Write
Write
Read
Internal Data Bus
Figure 22. Counter/Timer Block Diagram
Interrupts. TheZ8featuressixdifferentinterruptsfromsix
differentsources. Theseinterruptsaremaskable, prioritized
(Figure 23) and the six sources are divided as follows: four
sources are claimed by Port 3 lines P33–P30, and two in
counter/timers(Table11). TheInterruptMaskRegisterglo-
bally or individually enables or disables the six interrupt re-
quests.
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ZiLOG
IRQ0 IRQ2
IRQ1, 3, 4, 5
Interrupt
Edge
IRQ (D6, D7)
Select
IRQ
IMR
IPR
6
Global
Interrupt
Enable
Interrupt
Request
PRIORITY
LOGIC
Vector Select
Figure 23. Interrupt Block Diagram
Table 11. Interrupt Types, Sources, and Vectors
Vector
Name
Source
Location
Comments
IRQ0
IRQ1,
IRQ2
DAV0, IRQ0
IRQ1
0, 1
2, 3
4, 5
External (P32), Rise Fall Edge Triggered
External (P33), Fall Edge Triggered
External (P31), Rise Fall Edge Triggered
DAV2, IRQ2, T
IN
IRQ3
IRQ4
IRQ5
UART (ASCI)
6, 7
External (P30), Fall Edge Triggered
T0
T1
8, 9
Internal
Internal
10, 11
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. An interrupt ma-
chine cycle activates when an interrupt request is granted.
Thisactiondisablesallsubsequentinterrupts,savesthePro-
gram Counter and Status Flags, and then branches to the
programmemoryvectorlocationreservedforthatinterrupt.
All Z8 interrupts are vectored through locations in the pro-
grammemory. Thismemorylocationandthenextbytecon-
tain the 16-bit address of the interrupt service routine for
thatparticularinterruptrequest. Toaccommodatepolledin-
terrupt systems, interrupt inputs are masked and the Inter-
rupt Request register is polled to determine which of the in-
terrupt requests require service.
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CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
Clock. The Z8 on-chip oscillator features a high-gain, par-
allel-resonant amplifier for connection to a crystal, LC, RC,
ceramic resonator, or any suitable external clock source
(XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should
be AT-cut, 16 MHz maximum, with a series resistance (RS)
of less than or equal to 100 Ohms when counting from
1 MHz to 16 MHz.
An interrupt resulting from AN1 maps to IRQ2, and an in-
terrupt from AN2 maps to IRQ0. Interrupts IRQ2 and IRQ0
may be rising, falling, or both edge-triggered, and are pro-
grammable by the user. The software may poll to identify
the state of the pin. When in analog mode, the IRQ1 gener-
ates by the Stop-Mode Recovery source selected by SMR
Reg. bits D4, D3, D2, or SMR2 D1 or D0.
The crystal should be connected across XTAL1 and XTAL2
using the vendor’s recommended capacitor values from
eachpindirectlytothedeviceGroundpintoreduceground-
noise injection into the oscillator. The RC oscillator option
is mask-programmable on the Z8 and is selected by the cus-
tomer at the time when the ROM code is submitted.
Programming bits for the Interrupt Edge Select are located
in the IRQ register (R250), bits D7 and D6. The configura-
tion is indicated in Table 12.
Table 12. IRQ Register
IRQ
Interrupt Edge
P31 P32
D7
0
D6
0
Notes: The RC option is available up to 8 MHz. The RC
oscillator configuration must be an external resistor
connected from XTAL1 to XTAL2, with a frequency-
setting capacitor from XTAL1 to Ground (Figure 24).
F
F
0
1
F
R
R
F
1
0
1
1
R/F
R/F
For better noise immunity, the capacitors should be tied
Notes:
F = Falling Edge
R = Rising Edge
directly to the device Ground pin (VSS).
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XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
C1
VSS**
C1
C1
VSS**
VSS**
L
R
C2
VSS**
C2
VSS**
Ceramic Resonator or
Crystal
LC
RC
External Clock
C1, C2 = 22 pF
@ 5V VCC (TYP)
C1, C2 = 47 pF TYP *
f = 8 MHz
L = 130 uH *
f = 3 MHz *
C1 = 33 pF *
R = 1K *
f = 6 MHz *
*Preliminary value including pin parasitics
**Device ground pin
Figure 24. Oscillator Configuration
Power-On-Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for the Power-On Re-
set (POR) timer function. The POR time allows VCC and the
oscillator circuit to stabilize before instruction execution
begins.
aNOP(OpCode=FFH)immediatelybeforetheappropriate
sleep instruction. For example:
FF
6F
NOP
STOP
; clear the pipeline
; enter STOP mode
or
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
FF
7F
NOP
HALT
; clear the pipeline
; enter HALT Mode
1. Power fail to Power OK status.
2. Stop-Mode Recovery (if D5 of SMR = 1).
3. WDT time-out.
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation. It also reduces the standby current
to 10 µA or less. The STOP mode is terminated by a RESET
only, either by WDT time-out, POR, SMR recovery, or ex-
ternal reset. As a result, the processor restarts the applica-
tion program at address 000Ch. A WDT time-out in STOP
mode affects all registers the same as if a Stop-Mode Re-
covery occurred via a selected Stop-Mode Recovery source
except that the POR delay is enabled even if the delay is se-
lected for disable.
The POR time is specified as TPOR. Bit 5of the Stop-Mode
Register determines whether the POR timer is bypassed af-
ter Stop-Mode Recovery (typical for external clock, RC/LC
oscillators).
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external inter-
rupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The de-
vices are recovered by interrupts and are either externally
or internally generated. An interrupt request must be en-
abled and executed to exit HALT mode. After the interrupt
service routine, the program continues from the instruction
after the HALT.
Note: If a permanent WDT is selected, the WDT runs in all
modes and cannot be stopped or disabled if the onboard
RC oscillator is selected to drive the WDT.
In order to enter STOP (or HALT) mode, it is necessary to
first flush the instruction pipeline to avoid suspending ex-
ecutioninmid-instruction.Therefore,theusermustexecute
Port Configuration Register (PCON). The PCON regis-
ter configures the ports individually; comparator output on
Port 3, open-drain on Port 0 and Port 1, low EMI on Ports
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CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
0, 1, 2, and 3, and low-EMI oscillator. The PCON register
is located in the expanded register file at Bank F, location
00h(Figure 25).
Note: For emulator, this bit must be set to 1.
Low-EMI Port 2 (D5). Port 2 can be configured as a low-
EMI port by resetting this bit (D5 = 0) or configured as a
Standard Port by setting this bit (D5 = 1). The default value
is 1.
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
Low-EMI Port 3 (D6). Port 3 can be configured as a low-
EMI port by resetting this bit (D6 = 0) or configured as a
Standard Port by setting this bit (D6 = 1). The default value
is 1.
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
0 Port 1 Open Drain
1 Port 1 Push-pull Active*†
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
Low-EMI OSC (D7). This bit of the PCON Register con-
trols the low-EMI noise oscillator. A 1in this location con-
figures the oscillator, DS, AS and R/W with standard drive,
while a 0configures the oscillator, DS, AS and R/W with
low noise drive. The low-EMI mode reduces the drive of
the oscillator (OSC). The default value is 1.
0
1
Port 0 Low EMI
Port 0 Standard*†
0 Port 1 Low EMI
1 Port 1 Standard*
0
1
Port 2 Low EMI
Port 2 Standard*
0
1
Port 3 Low EMI
Port 3 Standard*
LowEMI Oscillator
Note: Maximum external clock frequency of 4 MHz when run-
0
1
Low EMI
Standard*
ning in the low-EMI oscillator mode.
*Default Setting After Reset
† Must be set to one for devices
in 28-pin packages
Low-EMI Emission. TheZ8canbeprogrammedtooperate
in a low-EMI emission mode in the PCON register. The os-
cillator and all I/O ports can be programmed as low-EMI
emissionmodeindependently. Useofthisfeatureresultsin:
Figure 25. Port Configuration Register (PCON)
(WRITE ONLY)
• The pre-drivers slew rate reduced to 10 ns (typical)
Comparator Output Port 3 (D0). Bit 0controls the com-
parator use in Port 3. A 1in this location brings the com-
parator outputs to P34 and P37, and a 0releases the Port to
its standard I/O configuration. The default value is 0.
• Low-EMI output drivers exhibit resistance of 200 Ohms
(typical)
• Low-EMI Oscillator
Port 1 Open-Drain (D1). Port 1 can be configured as an
open-drain by resetting this bit (D1 = 0) or configured as
push-pull active by setting this bit (D1 = 1). The default val-
ue is 1. The user must set D1 = 1 for devices in 28-pin pack-
ages.
• Internal SCLK/TCLK = XTAL operation limited to a
maximum of 4 MHz–250 ns cycle time, when LOW
EMI OSCILLATOR is selected and system clock (SCLK
= XTAL, SMR REGISTER BIT D1 = 1)
Stop-Mode Recovery Register (SMR). This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figures 26 and 27). All bits are
WRITE ONLY, except bit 7, which is READ ONLY. Bit 7
is a flag bit that is hardware set on the condition of STOP
recovery and RESET by a power-on cycle. Bit 6controls
whether a low level or a high level is required from the re-
covery source. Bit 5controls the reset delay after recovery.
Bits 2, 3, and 4, or the SMR register, specify the source of
the Stop-Mode Recovery signal. Bits 0and 1determine the
time-out period of the WDT. The SMR is located in Bank
F of the Expanded Register Group at address 0BH.
Port 0 Open-Drain (D2). Port 0 can be configured as an
open-drain by resetting this bit (D2 = 0) or configured as
push-pull active by setting this bit (D2 = 1). The default val-
ue is 1.
Low-EMI Port 0 (D3). Port 0 can be configured as a low-
EMI port by resetting this bit (D3 = 0) or configured as a
Standard Port by setting this bit (D3 = 1). The default value
is 1.
Low-EMI Port 1 (D4). Port 1 can be configured as a low-
EMI port by resetting this bit (D4 = 0) or configured as a
Standard Port by setting this bit (D4 = 1). The default value
is1.TheusermustsetD4=1fordevicesin28-pinpackages.
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ZiLOG
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The pur-
pose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT mode (where TCLK sources
counter/timers and interrupt logic). This bit is reset to D0
= 0 after a Stop-Mode Recovery.
SMR (FH) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0
1
OFF * *
ON
External Clock Divide by 2
0
1
SCLK/TCLK =XTAL/2*
SCLK/TCLK =XTAL
External Clock Divide-by-Two (D1). This bit can elimi-
nate the oscillator divide-by-two circuitry. When this bit is
0, the System Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock frequency divided by 2. The
SCLK/TCLK is equal to the external clock frequency when
this bit is set (D1 = 1). Using this bit together with D7 of
PCON further helps lower EMI (that is, D7 (PCON) = 0, D1
(SMR) = 1). The default setting is 0. Maximum external
clock frequency is 4 MHz when SMR BIT D1 = 1 where
SCLK/TCLK = XTAL.
STOP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0
1
OFF
ON*
Stop Recovery Level
0
1
Low*
High
Stop Flag (Read only)
0
1
POR*
Stop Recovery
Stop-Mode Recovery Source (D2, D3, and D4). These
three bits of the SMR specify the wake-up source of the
STOP recovery (Figure 28 and Table 13). When the Stop-
Mode Recovery Sources are selected in this register, then
SMR2 register bits D0,D1 must be set to 0.
Note: Not used in conjunction with SMR2 Source
* Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
Figure 26. Stop-Mode Recovery Register
(WRITE ONLY Except Bit D7, Which Is READ ONLY)
Note: If the Port 2 pin is configured as an output, this output
level is read by the SMR circuitry.
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
Figure 27. Stop-Mode Recovery Register 2
(0F) DH: WRITE ONLY
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CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
SMR2 D1 D0
0
0
VDD
SMR2 D1 D0
SMR2 D1 D0
1
1
1
1
P20
P23
P20
P27
SMR D4 D3 D2
0
0
0
VDD
SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2
SMR D4 D3 D2
SMR D4 D3 D2
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
1
1
0
1
1
1
P20
P20
P30
P31
P32
P33
P27
P23
P27
To POR
RESET
Stop-Mode Recovery Edge
Select (SMR)
To P33 Data
Latch and IRQ1
MUX
P33 From Pads
Digital/Analog Mode
Select (P3M)
Figure 28. Stop-Mode Recovery Source
Table 13. Stop-Mode Recovery Source
wake up is selected, the Stop-Mode Recovery source must
be kept active for at least 5 TpC.
SMR:432
D4 D3 D2
Operation
Description of Action
Stop-Mode Recovery Edge Select (D6). A 1 in this bit
position indicates that a high level on any one of the recov-
ery sources wakes the Z8 from STOP mode. A 0indicates
low-level recovery. The default is 0on POR (Figure 28).
This bit is used for either SMR or SMR2.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
POR and/or external reset recovery
P30 transition
P31 transition (not in Analog Mode)
P32 transition (not in Analog Mode)
P33 transition (not in Analog Mode)
P27 transition
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP mode. A 0in this bit (cold) indicates
that the device resets by POR/WDT RESET. A 1in this bit
(warm) indicates that the device awakens by a Stop-Mode
Recovery source.
Logical NOR of P20 through P23
Logical NOR of P20 through P27
Note: If the Port 2 pin is configured as an output, this output
level is read by the SMR2 circuitry.
Stop-Mode Recovery Delay Select (D5). This bit, if
High, enables the T RESET delay after Stop-Mode Re-
POR
covery. The default configuration of this bit is 1. If the fast
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ZiLOG
Stop-Mode Recovery Register 2 (SMR2). This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this reg-
ister then SMR Register. Bits D2, D3, and D4 must be 0.
es its terminal count. The WDT is initially enabled by exe-
cutingtheWDTinstructionandrefreshedonsubsequentex-
ecutions of the WDT instruction. The WDT circuit is driven
by an onboard RC oscillator or external oscillator from the
XTAL1 pin. The POR clock source is selected with bit 4of
the WDT register (Figure 29).
Table 14. Stop-Mode Recovery Source
WDTinstructionaffectstheZ(Zero),S(Sign),andV(Over-
flow) flags. The WDTMR must be written to within 64 in-
ternalsystemclocks.Afterthat,the WDTMRisWRITE-pro-
tected.
SMR:10
D1 D0
Operation
Description of Action
0
0
1
0
1
0
POR and/or external reset recovery
Logical AND of P20 through P23
Logical AND of P20 through P27
Note: WDT time-out while in STOP mode does not reset SMR,
PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers,
but the POR delay counter is still enabled even though
the SMR stop delay is disabled.
Watch-Dog Timer Mode Register (WDTMR). The WDT
isaretriggerableone-shottimerthatresetstheZ8ifitreach-
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC External Clock
00
01*
10
3.5 ms
7 ms
14 ms
56 ms
128 TpC
256 TpC
512 TpC
2048 TpC
11
WDT During HALT
0
1
OFF
ON*
WDT During STOP
0
1
OFF
ON*
XTAL1/INT RC Select for WDT
0
1
On-Board RC*
XTAL
Reserved (must be 0)
*Default setting after RESET
Figure 29. Watch-Dog Timer Mode Register (WRITE ONLY)
Table 15. WDT Time Select
WDT Time Select. (D0,D1). Selects the WDT time period
and is configured as indicated in Table 15.
Timeout of
Timeout of
D1
D0
Internal RC OSC
System Clock
0
0
1
0
1
3.5 ms min
7 ms min
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
0
1
1
14 ms min
56 ms min
Notes:
SCLK = system bus clock cycle.
The default on RESET is 7 ms.
Values provided are for V = 5.0V.
CC
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ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
WDTMR During HALT (D2). This bit determines whether
or not the WDT is active during HALT mode. A 1indicates
active during HALT. The default is 1.
WDTMR Register Accessibility. The WDTMR register is
accessible only during the first 60 internal system clock cy-
cles from the execution of the first instruction after Power-
On Reset, Watch-Dog Reset, or Stop-Mode Recovery. Af-
ter this point, the register cannot be modified by any means,
intentional or otherwise. The WDTMR cannot be read and
is located in bank F of the Expanded Register Group at ad-
dress location 0FH(Figure 30).
WDTMR During STOP (D3). This bit determines whether
ornottheWDTisactiveduring STOPmode. Because XTAL
clock is stopped during STOP mode, the on-board RC must
be selected as the clock source to the POR counter. A 1in-
dicates active during STOP. The default is 1.
Note: The WDT can be permanently enabled (automatically
enabled after RESET) through a mask programming op-
tion. The option is selected by the customer at the time
of ROM code submission. In this mode, WDT is always
activated when the device comes out of RESET. Execu-
tion of the WDT instruction serves to refresh the WDT
time-out period. WDT operation in the HALT and STOP
Modes is controlled by WDTMR programming. If this
mask option is not selected at the time of ROM code sub-
mission, the WDT must be activated by the user through
the WDT instruction and is always disabled by any reset
to the device.
Note: If permanent WDT is selected, the WDT runs in all
modes and can not be stopped or disabled if the on board
RC oscillator is selected as the clock source for WDT.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and WDT
counter chain. If the bit is a 1, the internal RC oscillator is
bypassedandthe PORandWDTclocksourceisdrivenfrom
the external pin, XTAL1. The default configuration of this
bit is 0which selects the internal RC oscillator.
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CMOS Z8® MCUs with ASCI UART
ZiLOG
Reset
4 Clock
Filter
Clear
CLK
18 Clock RESET
Generator
RESET
Internal
RESET
WDT Select
(WDTMR)
WDT TAP SELECT
CLK Source
Select
(WDTMR)
15ms 25ms 100ms
5ms
5ms POR
CK
XTAL
M
U
X
WDT/POR Counter Chain
CLR
Internal
RC OSC.
2V Operating
Voltage Det.
VDD
VLV
+
–
WDT
From Stop
Mode
Recovery
Source
Stop Delay
Select (SMR)
Figure 30. Resets and WDT
Low Voltage Protection. An onboard Voltage Compara-
tor checks that VCC is at the required level to ensure correct
operation of the device. RESET is globally driven if VCC is
below the specified voltage (Low Voltage Protection). The
minimumoperatingvoltageisvaryingwiththetemperature
and operating frequency, while the Low Voltage Protection
Note: The internal clock frequency relationship to the XTAL
clock is dependent on SMR BIT 0 1 setting.
The device functions normally at or above 3.0V under all
conditions. Below 3.0V, the device functions normally until
the Low Voltage Protection trip point (VLV) is reached, for
(V ) varies with temperature only.
LV
the temperatures and operating frequencies in Case 1 and
Case2,above.Thedeviceisguaranteedtofunctionnormally
at supply voltages above the Low Voltage Protection trip
point. TheactualLowVoltageProtectiontrippointisafunc-
tion of temperature and process parameters (Figure 36).
The Low Voltage Protection trip voltage (V ) is less than
3V and more than 1.4V under the following conditions.
LV
Table 16. Maximum (V ) Conditions:
LV
Case 1:
Case 2:
T = –40ºC, +105ºC, Internal Clock
A
Frequency equal or less than 4 MHz
T = –40ºC, +85ºC, Internal Clock
A
Frequency equal or less than 6 MHz
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CMOS Z8® MCUs with ASCI UART
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (ASCI)
Key features of the ASCI include:
ceive Data Register Full Flag also goes active during this
time. If there is no space in the FIFO at the time that the
RSRattemptstotransferthereceiveddataintoit, anoverrun
error occurs.
• Full-duplex operation
• Programmable data format
• 7 or 8 data bits with optional ninth bit for multiprocessor
Receive Data FIFO. When a complete incoming data byte
is assembled in the RSR, it is automatically transferred to
the 4-byte FIFO, which serves to reduce the incidence of
overrun errors. The top (oldest) character in the FIFO (if
any) can be read via the Receive Data Register (RDR).
communication
•
P30 and P37 can be used as general-purpose I/O as long
as the ASCI channels are disabled
• One or two STOP bits
• Odd, even or no parity
The next incoming data byte can be shifted into the RSR
while the FIFO is full, thus providing an additional level of
buffering. However, an overrun occurs if the receive FIFO
is still full when the receiver completes assembly of that
character and is ready to transfer it to the FIFO. If this sit-
uation occurs, the overrun error bit associated with the pre-
viousbyteintheFIFOisset. Thelatestdatabyteisnottrans-
ferred from the shift register to the FIFO in this case, and
is lost. When an overrun occurs, the receiver does not place
any further data in the FIFO until the most recent good byte
received arrives at the top of the FIFO and sets the Overrun
latch, and software then clears the Overrun latch by a
WRITE of 0to the EFR bit. Assembly of bytes continues in
the shift register, but this data is ignored until the byte with
the overrun error reaches the top of the FIFO and the status
is cleared.
• Programmable interrupt conditions
• Four level data/status FIFOs for the receiver
• Receive parity, framing and overrun error detection
• Break detection and generation
Transmit Data Register. Data written to the ASCI Trans-
mit Data Register (TDR) is transferred to the Transmit Shift
Register(TSR) as soon as the TSR is empty. Data can be
written while the TSR is shifting out the previous byte of
data, providing double buffering for the transmit data. The
TDR is READ- and WRITE-accessible. Reading from the
TDR does not affect the ASCI data transmit operation cur-
rently in progress.
When a break occurs (defined as a framing error with the
data equal to all zeros), the all-zero byte with its associated
error bits are transferred to the FIFO if it is not full and the
Break Detect bit in the ASEXT register is set. If the FIFO
is full, an overrun is generated, but the break, framing error
and data are not transferred to the FIFO. Any time a break
isdetected, thereceiverdoesnotreceiveanymoredatauntil
the RX pin returns to a high state.
Transmit Shift Register. When the ASCI Transmit Shift
Register (TSR) receives data from the ASCI Transmit Data
Register, the data is shifted out to the TX (P37) pin. When
transmission is completed, the next byte (if available) is au-
tomatically loaded from the TDR into the TSR and the next
transmission starts. If no data is available for transmission,
the TSR idles at a continuous High level. This register is
not program-accessible.
If the channel is set in multiprocessor mode and the MPE
bit of the CNTLA register is set to 1,then break, errors and
data are ignored unless the MP bit in the received character
isa 1. Thetwoconditionslistedabovecouldcausethemiss-
ing of a break condition if the FIFO is full and the break
occurs or if the MP bit in the transmission is not a one with
the conditions specified above.
Receive Shift Register. When the RE bit is set in the
CNTLA register, the RX (P30) pin is monitored for a Low.
One-half bit-time after a Low is sensed at RX, the ASCI
samples RX again. If RX goes back to High, the ASCI
ignores the previous Low and resumes looking for a new
Low, but if RX is still Low, it considers RX a START bit
and proceeds to clock in the data based upon the selected
baud rate. The number of data bits, parity, multiprocessor
and STOP bits are selected by the MOD2, MOD1, MOD0
and multiprocessor mode (MP) bits in the CNTLA and
CNTLB registers.
ASCI Status FIFO/Registers. This FIFO contains Parity
Error, Framing Error, RX Overrun, and Break status bits as-
sociated with each character in the receive data FIFO. The
status of the oldest character (if any) can be read from the
ASCI status register, which also provides several other,
non-FIFOed status conditions.
After the data is received, the appropriate MP, parity and
one STOP bit are checked. Data and any errors are clocked
into the receive data and status FIFO during the STOP bit
if there is an empty position available. Interrupts and Re-
The outputs of the error FIFO go to the set inputs of soft-
ware-accessible error latches in the status register. Writing
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CMOS Z8® MCUs with ASCI UART
ZiLOG
a 0to the EFR bit in CNTLA is the only way to clear these
latches. In other words, when an error bit reaches the top
of the FIFO, it sets an error latch. If the FIFO contains more
data and the software reads the next byte out of the FIFO,
the error latch remains set until the software writes a 0to
the EFR bit. The error bits are cumulative, so if additional
errorsareintheFIFOtheysetanyunseterrorlatchesasthey
reach the top.
main processor clock frequency. The BRG can also be dis-
abled in favor of the SCLK.
The Receiver and Transmitter subsequently divide the out-
put of the Baud rate Generator (or the signal from the CLK
pin) by 1, 16 or 64 under the control of the DR bit in the
CNTLB register and the X1 bit in the ASCI Extension Con-
trol Register (ASEXT).
RESET. During RESET, the ASCI is forced to the following
conditions:
Baud Rate Generator. The baud rate generator features
two modes. The first provides a dual set of fixed clock di-
vide ratios as defined in CNTLB. In the second mode, the
BRGisconfiguredasasixteen-bitdowncounterthatdivides
the processor clock by the value in a software accessible,
sixteen-bit, time-constant register. As a result, virtually any
frequency can be created by appropriately selecting the
• FIFO Empty
• All Error Bits Cleared (including those in the FIFO)
• Receive Enable Cleared (CNTLA BIT 6 = 0)
• Transmit Enable Cleared (CNTLA BIT 5 = 0)
Internal Address/Data Bus
ASCI Transmit Data Register
TDR (Bank:Ah,Addr :01h)
IRQ3
Interrupt Request
**
**
ASCI Transmit Shift Register
TSR
(P37) TX
(P30) RX
ASCI Receive Data FIFO
RDR (Bank:Ah,Addr:02h)
ASCI Receive Shift Register
RSR
ASCI
ASCI Control Register A
CNTLA (Bank:Ah,Addr:03h)
Accessible
Control
ASCI Control Register B
CNTLB (Bank:Ah,Addr:04h)
ASCI Status FIFO/Register
STAT (Bank:Ah,Addr:08h)
ASCI Extension Control Reg.
ASEXT (Bank:Ah,Addr:05h)
ASCI Time Constant High
ASTCH (Bank:Ah,Addr:07h)
ASCI Time Constant Low
ASTCL (Bank:Ah,Add:06h)r
SCLK
Baud Rate Generator
Note: **Not Program
Figure 31. ASCI Interface Diagram
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INTERRUPTS
The ASCI channel generates one interrupt (IRQ3) from two
sources of interrupts: a receiver and a transmitter. In addi-
tion, there are several conditions that may cause these in-
terrupts to trigger. Figure 32 illustrates the different condi-
tions for each interrupt source enabled under program
control.
FIFO full
Overrun error
Framing Error
Parity Error
Start Bit
Receiver
Interrupt
Sources
ASCI
Interrupt
(IRQ3)
Transmitter
Interrupt
Sources
Buffer Empty
Figure 32. ASCI Interrupt Conditions and Sources
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EXPANDED REGISTER GROUP (A)
B7 B6 B5 B4 B3 B2 B1 B0
%(A)0F
%(A)0E
%(A)0D
%(A)0C
%(A)0B
%(A)0A
%(A)09
%(A)08
%(A)07
%(A)06
%(A)05
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
GEN PURPOSE
STAT
u
0
1
1
0
0
0
u
u
u
0
1
1
0
0
0
u
u
u
0
1
1
0
0
0
u
u
u
0
1
1
0
0
1
u
u
u
0
1
1
0
0
0
u
u
u
0
1
1
0
1
0
u
u
u
1
1
1
0
1
0
u
u
u
0
1
1
0
1
0
u
u
*
*
*
*
*
*
*
*
ASTCH
ASTCL
ASEXT
%(A)04
CNTLB
%(A)03
%(A)02
CNTLA
RDR
%(A)01
%(A)00
TDR
RESERVED
* Not reset with a STOP-Mode Recovery.
Figure 33. Expanded Register Group (A) Registers
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CMOS Z8® MCUs with ASCI UART
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ASCI TRANSMIT DATA REGISTER (TDR)
(%(A)01H: READ/WRITE)
Table 17. TDR Register Bit Functions
Bit
R
7
6
5
4
3
2
1
0
Transmit Data
W
Reset
U
U
U
U
U
U
U
U
Data written to the ASCI Transmit Data Register (TDR) is
transferred to the Transmit Shift Register (TSR) as soon as
the TSR is empty. The TSR is not not software-accessible.
The ASCI transmitter is double-buffered so data can be
writtentothe TDRwhilethe TSRisshiftingouttheprevious
byte.Datacanbewrittenintoandreadoutofthe TDR.When
the TDR is read, the data transmit operation is not affected.
ASCI RECEIVE DATA REGISTER (RDR)
(%(A)02H: READ/WRITE)
Table 18. RDR Register Bit Functions
Bit
R
7
6
5
4
3
2
1
0
Receive Data
W
Reset
U
U
U
U
U
U
U
U
When a complete incoming data byte is assembled in the
ReceiveShiftRegister(RSR),itisautomaticallytransferred
to the highest available location in the Receive Data FIFO.
The Receive Data Register (RDR) is the highest location in
the Receive Data FIFO. The RDRF bit in the STAT register
is set when one or more bytes is available from the FIFO.
The FIFO status for the character in the RDR is available
in the STAT register via bits 6, 5and 4. STAT should be
read before reading the RDR. The data in both FIFO loca-
tions is popped when the character is read from the RDR.
ASCI CONTROL REGISTER A (CNTLA)
(%(A)03H: READ/WRITE)
Table 19. CNTLA Register Bit Functions
Bit
R
7
6
5
4
Reserved
1
3
2
1
0
Multiprocessor
Bit Received
(MPBR)
MOD2 MOD1 MOD0
Multiprocessor
Enable
Receiver
Enable
(RE)
Transmitter
Enable
(TE)
Mode Select
Error Flag
Receive
(EFR)
(MPE)
W
Reset
0
0
0
0
0
0
0
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Bit 7 is the Multiprocessor Enable
Bit 4 is Reserved
The ASCI features a multiprocessor communication mode
that utilizes an extra data bit for selective communication
when a number of processors share a common serial bus.
Multiprocessor data format is selected when the MP bit in
the corresponding register is set to 1. If multiprocessor
modeisnotselected(MPbitinCNTLB = 0), multiprocessor
enable (MPE) has no effect. If multiprocessor mode is se-
lected (MP bit in CNTLB = 1), MPE enables or disables the
wake-up feature as follows. If MPE is set to 1, only received
bytes in which the multiprocessor bit (MPB) = 1 are treated
as valid data characters and loaded into the receiver FIFO
with corresponding error flags in the status FIFO. Bytes
with MPB = 0 are ignored by the ASCI. If MPE is reset to
0, all bytes are received by the ASCI, regardless of the state
of the MPB data bit.
Bit 3 is the Multiprocessor Bit Receive
(Read only)
When multiprocessor mode is enabled (MP in CNTLB = 1),
this bit, when read, contains the value of the MPB bit for
the data byte currently available at the Receive Data Reg-
ister (the top of the receiver FIFO).
Bit 3 is the Error Flag Reset (WRITE ONLY)
When written to 0, the error flags (OVRN, FE; PE in STAT
and BRK in ASEXT) are cleared to 0. This command self-
resets, and as a result, writing EFR to a 1is not required.
Bits 2–0 are the ASCI Data Format Mode 2,1,0
These bits program the ASCI data format.
Bit 6 is the Receiver Enable
Table 20. Format Mode Control Bits
When Receiver Enable(RE) is set to 1,the ASCI receiver is
enabled. When RE is reset to 0, the receiver is disabled and
any receive operation in progress is aborted. However, the
previous contents of the receiver data and status FIFO are
not affected.
Bit Name Function
Bit = 0 Bit = 1
2
1
MOD2 Number of Data Bits
MOD1 Parity Enabled
7
8
No
With
Parity
Parity
0
MOD0 Number of Stop Bits
1
2
Bit 5 is the Transmitter Enable
When Transmitter Enable(TE) is set to 1,the ASCI trans-
mitter is enabled. When TE is reset to 0, the transmitter is
disabled and any transmit operation in progress is aborted.
However, the previous contents of the transmitter data reg-
ister and the TDRE flag are not affected.
If MOD1 = 1, parity is checked on received data and a parity
bit is appended to the data bits in the transmitted data. Parity
Even/Odd (PEO) in CNTLB selects even or odd parity.
The ASCI serial data format is illustrated in Figure 34.
7 or 8 bits Data Field
1 or 2
Stop Bit(s)
Start
Bit
Parity
Bit
Figure 34. ASCI Serial Data Format
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ASCI CONTROL REGISTER B (CNTLB)
(%(A)04H: READ/WRITE)
Table 21. CNTLB Register Bit Functions
Bit
R
7
6
5
4
3
2
1
0
SS2
SS1
SS0
Multiprocessor
Bit
Transmitter
(MPBT)
Multiprocessor
Mode
Parity
Even/Odd
(PEO)
Divide Ratio
(DR)
Clock Source
and Speed
Prescale
(PR)
(MP)
W
Reset
0
0
0
0
0
1
1
1
position whose value is specified in MPBT immediately af-
ter the specified number of data bits and preceding the spec-
ified number of STOP bits.
BIT 7 is the Multiprocessor Bit Transmit
When multiprocessor format is selected (MP BIT = 1), Mul-
tiprocessorBitTransmit(MPBT)isusedtospecifythe MPB
databitfortransmission.IfMPBT=1,thena1istransmitted
in the MPB bit position. If MPBT = 0, a 0is transmitted.
Note: The multiprocessor format does not provide parity. The
serial data format while in MP mode is illustrated in Fig-
ure 35.
BIT 6 is the Multiprocessor Mode
When Multiprocessor Mode (MP) is set to 1, the serial data
format is configured for multiprocessor mode, adding a bit
7 or 8 bits Data Field
Start Bit
MPB
1 or 2
Stop Bit(s)
Figure 35. MP Mode Serial Data Format
If MP = 0, the data format is based on MOD2–0 in CNTLA
and may include parity.
Bit 4 is the Parity Even/Odd
Parity Even/Odd (PEO) controls the parity bit transmitted
on the serial output and the parity check on the serial input.
IfPEOisclearedto0,evenparityistransmittedandchecked
If PEO is set to 1, odd parity is transmitted and checked.
Bit 5 is the BRG Prescaler
The Prescale bit specifies the baud rate generator prescale
factor when using the SS2–0 bits to define the ASCI baud
rate (BRG MODE = 0). Writing a 0to this bit sets the BRG
Prescaler to divide by 10. Setting this bit to a 1sets the BRG
Prescaler to divide by 30. See the Baud Rate Generation
Summary for more information on setting the ASCI baud
rate.
Bit 3 is the Divide Ratio
The Divide Ratio bit specifies the divider used to obtain the
baud rate from the data sampling clock when using the
SS2–0 bits to define the ASCI baud rate (BRG MODE = 0).
If DR is 0, then DIVIDE-BY-16 is used. If DR is set to a 1,
then DIVIDE-BY-64 is used. See the Baud Rate Generation
Summary for more information on setting the ASCI baud
rate.
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Table 22. Clock Source and Speed Bits
DR
Sampling Clock
0
1
Divide by 16
Divide by 64
SS2
SS1
SS0
Divider (DIV)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷1
÷2
÷4
Bit 2,1 are the Clock Source and Speed Select
÷8
When the BRG mode bit in the ASEXT register is set to 0,
these 3 bits, along with DR and PR in this register define
the ASCI baud rate. Bits 2, 1and 0specify a power-of-two
divider of the SCLK as defined in Table 22. These bits
should never be set to all 1s or erratic results may occur.
See the Baud Rate Generation Summary for more informa-
tion on setting the ASCI baud rate.
÷16
÷32
÷64
Reserved
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ASCI EXTENSION CONTROL REGISTER (ASEXT)
(%(A)05H: READ/WRITE)
Table 23. ASEXT Register Bit Functions
Bit
R
7
6
Reserved
0
5
Reserved
0
4
3
2
1
0
Break
Detect
(BD)
RX State
(RX)
RX
Reserved BRG Mode Interrupton
(must be 0) (BRGM)
Send Break
(SB)
Start Bit
(RIS)
W
Reset
P30
0
0
0
0
0
on RX. Such a receive interrupt is always followed by the
settingofRDRFinthemiddleoftheSTOPbit.Thisinterrupt
request must be cleared by writing this bit back to a 0. Writ-
ing a 1to this bit has no effect. One function of this feature
is to wake the part from Sleep mode when a character ar-
rives, so that the ASCI receives clocking with which to pro-
cess the character. Another function is to ensure that the as-
sociated interrupt service routine is activated in time to
sense the setting of RDRF in the status register, and to start
a timer for baud rate measurement at that time.
BIT 7 is the RX State (READ ONLY)
Providestherealtimestateof RX,thechannel’sreceivedata
input pin—P30.
BIT 6 is Reserved
When read, this bit reflects the default value 0. When
WRITE, this bit is ignored.
Bit 5 is Reserved
When read, this bit reflects the default value 0. When
WRITE, this bit is ignored.
Bit 1 is the Break Detect (READ ONLY)
This status bit is set to a 1when a Break is detected, defined
as a framing error with the data bits all equal to 0. The all-
zero byte with its associated error bits are transferred to the
FIFO if it is not full. If the FIFO is full, an overrun is gen-
erated, but the break, framing error and data are not trans-
ferredtotheFIFO.Anytimeabreakisdetected,thereceiver
do not receive any more data until the RX pin returns to a
High state. When set, this bit remains set until it is cleared
by writing a 0to the EFR bit in the CNTLA register.
Bit 4 is the X1 Bit Clock
Reserved—must be set to 0or erratic results may occur.
Bit 3 is the BRG Mode
When this bit is set to a 1, the ASCI’s baud rate is set by
the 16-bit programmable divider programmed in ASCI
TimeConstantHigh(ASTH)andASCITimeConstantLow
(ASTL). If this bit is set to a 0, the baud rate is defined by
the PR bit, the DR bit, and the SS2–0 bits in the CNTLB reg-
ister. In either case, the source for the baud rate generator
is the SCLK. See the Baud Rate Generation Summary for
more information on setting the ASCI baud rate.
Bit 0 is the Send Break
Setting this bit to a 1forces the channel’s transmitter data
output pin, TX, to a Low for as long as it remains set. Before
starting the break, any character(s) in the TSR and in the
TDRarecompletelytransmitted. Ifacharacterisloadedinto
the TDR while a break is being generated, that character is
held until the break is terminated and transmitted.
Bit 2 is the Rx Interrupt on Start
If software sets this bit to 1,a receive interrupt is requested
(in a combinatorial fashion) when a START bit is detected
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ASCI TIME CONSTANT REGISTER (ASTL)
(%(A)06H: READ/WRITE)
Table 24. ASTL Register Bit Functions
Bit
R
7
1
6
1
5
4
3
2
1
1
1
0
1
ASCI Time Constant Low
W
Reset
1
1
1
ASCI TIME CONSTANT REGISTER (ASTH)
(%(A)07H: READ/WRITE)
Table 25. ASTH Register Bit Functions
Bit
R
7
6
5
4
3
2
1
1
1
0
1
ASCI Time Constant High
W
Reset
1
1
1
1
1
The ASTL and ASTH registers are only used when the BRG
mode bit in the ASEXT register is set to a 1. These two 8-
bit registers form a 16-bit counter with a flip-flop logic cir-
cuit (DIVIDE-BY-2) on the output so that the final BRG out-
put is symmetrical. The values written to these registers de-
termine the time constant from which the baud rate is
generated.
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ASCI STATUS REGISTER (STAT)
(%(A)08H: READ/WRITE)
Table 26. ASCI Status Register (STAT)
Bit
R
7
6
5
4
3
2
Reserved
0
1
0
Receive
Data
Register
Full
Transmit
Data
Register
Empty
TDRE)
Overrun
Error
(OE)
Framing
Error
Parity Error
(PE)
(FE)
Receiver
Interrupt
Enable
(RIE)
Transmitter
Interrupt
Enable
(RDRF)
(TIE)
W
Reset
0
0
0
0
0
0
0
BIT 7 is the Receive Data Register Full
Bit 5 is the Parity Error
RDRFissetto1whenthereceivertransfersacharacterfrom
the RSR into an empty Rx FIFO.
Aparityerrorisdetectedwhenparitygenerationandcheck-
ing is enabled by the MOD1 bit in the CNTLA register and
a character has been assembled in which the parity does not
match that specified by the PEO bit in CNTLB.
Note: If a framing or parity error occurs, RDRF is still set and
the receive data (which generated the error) is still load-
ed into the FIFO.
Note: PE is FIFOed and the error bit is not actually set until the
associated data becomes available for reading in the
RDR.
WhenthereismorethanonecharacterintheFIFO, andsoft-
warereadsacharacter, RDRFeitherremainssetoriscleared
and immediately set again. RDRF is cleared to 0when the
FIFO becomes empty after reading the RDR and during
Power-On Reset.
When set, the bit remains set until it is cleared by writing
a 0to the EFT bit in the CNTLA register. The bit is cleared
at Power-On Reset.
Bit 6 is the Overrun Error
Bit 4 is the Framing Error
An overrun occurs if the receive FIFO is still full when the
receiver completes assembly of a character and is ready to
transfer it to the FIFO. If this situation occurs, the overrun
error bit associated with the previous byte in the FIFO is
set. In this case, the latest data byte is not transferred from
the shift register to the FIFO and is lost.
Aframingerrorisdetectedwhenthe STOPbitofacharacter
is sampled as a 0(space). Like PE, FE is FIFOed and the
error bit is not actually set until the associated data becomes
available for reading in the RDR. When set, the bit remains
set until it is cleared by writing a 0to the EFR bit in the
CNTLA register. The bit is cleared at Power-On Reset.
When an overrun occurs, the receiver does not place any
further data in the FIFO until the most recent good byte
received (the byte with the associated overrun error bit set)
moves to the top of the FIFO and sets the Overrun latch,
and software then clears the Overrun latch. Assembly of
bytes continues in the shift register, but this data is ignored
until the byte with the overrun error reaches the top of the
FIFO and the status is cleared. When set, the bit remains
set until it is cleared by writing a 0to the EFR bit in the
CNTLA register. The bit is also cleared during Power-On
Reset.
Bit 3 is the Receiver Interrupt Enable
RIE should be set to a 1to enable ASCI receive interrupt
requests. An interrupt (IRQ3) is generated when RDRF (bit
7of the STAT register) is a 1. A receive interrupt is also
generated if this bit is set to a 1, bit 2of the ASEXT register
(RX interrupt on the START bit) is set to a 1, and a START
bit is detected by the receiver.
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ZiLOG
Bit 2 is Reserved
SCLK
Baud Rate =
When read, this bit reflects the default value 0. When
WRITE, this bit is ignored.
(10 + 20 x PS) x DIV x Divide Ratio
Bit 1 is the Transmit Data Register Empty
Where:
TDRE = 1 indicates that the Transmit Data Register (TDR)
is empty and that the next data byte to be transmitted can
be written into the TDR. TDRE is cleared to 0after the byte
is written to TDR, until the ASCI transfers the byte from the
TDR to the Transmit Shift Register (TSR), and then TDRE
is again set to 1. TDRE is set to 1at Power-On Reset.
1. SCLK is the system clock.
2. PS = 1or 0 and is bit 5of CNTLB.
3. DIV = 1, 2, 4, 8, 16, 32or 64as reflected by SS2–0 in
CNTLB.
4. DIVIDE RATIO = 16 or 64, as defined by DR in
CNTLB.
Bit 0 is the Transmit Interrupt Enable
If BRG mode = 1:
TIE should be set to a 1to enable ASCI transmit interrupt
requests. An interrupt (IRQ3) is generated when TDRE (bit
1of the STAT register) is a 1. TIE is cleared to 0at Power-
On Reset.
SCLK
Baud Rate =
(2 x (TC + 2) x Divide Ratio
An anomaly exists that requires setting of the RIE bit to al-
low the generation of transmit interrupts. If RIE is not set,
transmit interrupts are not generated, even if TIE is set. See
Precautions.
or
SCLK
TC =
– 2
2 x Baud Rate x Divide Ratio
Baud Rate Generation Summary
The application can select between one of two baud rate
generatorsfortheASCI. IftheBRGModebitintheASEXT
register is set to a 0, the SS2,1,0 bits, the DR, bit and the
PRbitinCNTLBareusedtoselectthebaudrate. IftheBRG
Mode bit is set to a 1, the ASTL and ASTH registers are
used to select the baud rate.
Where:
1. SCLK is the system clock.
2. TC is the 16-bit value programmed into ASTL and
ASTH.
3. DIVIDE RATIO = 16 or 64, as defined by DR in
CNTLB.
The following formulas are used to calculate the baud rate
from the two baud rate generators:
4. Baud Rate is the desired baud rate.
If BRG mode = 0:
DS007601-Z8X0499
P R E L I M I N A R Y
55
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
ASCI STATUS REGISTER (STAT) (Continued)
Table 27. Baud Rate List (BRG Mode = 0)
Sampling
Rate
Prescaler
Divide
Baud Rate
Example Baud Rate (bps)
SCLK = SCLK = SCLK =
Divide
Ratio
General
Divide Ratio
6.144
MHz
4.608
MHz
3.072
MHz
PS
Ratio
DR
Rate
SS2
SS1
SS0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
÷1
÷2
SCLK ÷ 160
SCLK ÷ 320
38400
19200
9600
4800
2400
1200
600
19200
9600
4800
2400
1200
600
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
÷4
SCLK ÷ 640
0
16
64
16
64
÷8
SCLK ÷ 1280
SCLK ÷ 2560
SCLK ÷ 5120
SCLK ÷ 10240
SCLK ÷ 640
÷16
÷32
÷64
÷1
300
SCLK
÷ 10
0
9600
4800
2400
1200
600
4800
2400
1200
600
÷2
SCLK ÷ 1280
SCLK ÷ 2560
SCLK ÷ 5120
SCLK ÷ 10240
SCLK ÷ 20480
SCLK ÷ 40960
SCLK ÷ 480
÷4
1
0
1
÷8
÷16
÷32
÷64
÷1
300
300
150
150
75
4800
2400
1200
600
300
150
75
÷2
SCLK ÷ 960
÷4
SCLK ÷ 1920
SCLK ÷ 3840
SCLK ÷ 7680
SCLK ÷ 15360
SCLK ÷ 30720
SCLK ÷ 1920
SCLK ÷ 3840
SCLK ÷ 7680
SCLK ÷ 15360
SCLK ÷ 30720
SCLK ÷ 61440
SCLK ÷ 122880
÷8
÷16
÷32
÷64
÷1
SCLK
÷ 30
1
2400
1200
600
300
150
75
÷2
÷4
÷8
÷16
÷32
÷64
37.5
56
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
LOW VOLTAGE PROTECTION
VCC
(Volts)
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
A
B
RUN/HALT Mode
STOP Mode
V
(Typical)
LV
B
A
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (ºC)
Figure 36. Typical Low Voltage Protection vs. Temperature
DS007601-Z8X0499
P R E L I M I N A R Y
57
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
MASK OPTIONS
Below is an example of the ROM mask bit option selection
for this product.
Options
Option Selections
Enable ROM Protect
ROM Protect
Disable ROM Protect
Disable RAM Protect
RC Oscillator Enable
RAM Protect
Enable RAM Protect
System Clock Source
Oscillator Operational Mode
Crystal/Other Clock Source
Normal High-Frequency Operation
Enabled
32-kHz Crystal Operation Enabled
(Limits High-Frequency Operation)
WDT Mode
WDT Enabled by Software Only
WDT Enabled Automatically After
RESET
Auto Latch Mode
Port 0 Pull-Ups
Port 1 Pull-Ups
Port 2 Pull-Ups
Disable Auto Latches
Disable Pull-Ups
Disable Pull-Ups
Disable Pull-Ups
Enable Auto Latches
Enable Pull-Ups
Enable Pull-Ups
Enable Pull-Ups
ROM Protect. SelectingtheDISABLEROMPROTECTop-
tion READs the software program that is in the program
memory using ZiLOG’s internal factory test mode. How-
ever, none of the standard methods for reading or verifying
the code in the microcontroller uses an EPROM program-
mer. With this option disabled, ZiLOG is able to fully test
the ROM memory and provides its standard warranty for
the part. Selecting the ENABLE ROM PROTECT option ne-
gates the possibility of reading the code out of the part using
atester, programmer, oranyotherstandardmethod. ZiLOG
will be unable to test the ROM memory at any time prior
to customer delivery.
allows protection (under software control) of a portion of
the RAM’s address space from being read or written.
System Clock Source. Selecting the RC OSCILLATOR
ENABLE option, configures the oscillator circuit on the mi-
crocontroller to work with an external RC circuit. Selecting
the CRYSTAL/OTHER CLOCK SOURCE option configures
the oscillator circuit to work with an external crystal, ce-
ramic resonator, or LC oscillator.
Oscillator Operational Mode. Selecting the NORMAL
HIGH FREQUENCY OPERATION ENABLED option en-
ables the part to operate using a standard crystal or resona-
tor, but it does not operate using a 32-kHz crystal. Selecting
the 32-KHZ OPERATION ENABLED option enables the mi-
crocontroller to work with a 32-kHz crystal and an external
feedback resistor—these must be supplied between the
XTAL1 and XTAL2 pins. (If RC OSCILLATOR ENABLED
is selected in the SYSTEM CLOCK SOURCE option, this
option defaults to the NORMAL HIGH FREQUENCY OP-
ERATION ENABLED bit.)
The ROM PROTECT option bit only affects the ability to
read the code and does not affect the operation of the part
in an application. If the ROM PROTECT option is disabled,
ZiLOG tests the part for ROM fallout and parts which fail
are not shipped to the customer. When the ROM PROTECT
option is enabled, ZiLOG cannot perform these tests on the
ROM. When ROM PROTECT is enabled, except for the im-
proper transfer of the code by ZiLOG, all ROM memory
software errors shall be the responsibility of the Buyer and
ZiLOG shall have no obligation to repair or replace product
containing software errors. Selecting the ENABLE ROM
PROTECT option waives all warranties of ZiLOG, ex-
pressed or implied, on microcontrollers containing ROM
failures including, but not limited to, the implied warranty
of merchantability and fitness for a particular purpose.
WDT Mode. Selecting the WDT ENABLED BY SOFT-
WAREONLYoptionoperatestheWatchDogTimer(WDT)
when turned on under software control. Selecting the WDT
ENABLEDAUTOMATICALLYAFTERRESEToptionstarts
the WDT automatically at RESET.There is no way to dis-
able or stop this mode, making it necessary in the code to
periodically clear the WDT to prevent it from resetting the
microcontroller. If the WDT ENABLED AUTOMATICAL-
LY AFTER RESET option and the WDT DRIVEN BY SYS-
TEM CLOCK option (if offered) are selected, the WDT nev-
RAM Protect. Selecting the DISABLE RAM PROTECT op-
tion does not affect the RAM memory. RAM memory op-
eratesasdefinedinthisProductSpecificationforalladdress
locations. Selecting the ENABLE RAM PROTECT option,
58
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
er operates in STOP mode, and cannot be enabled, by any
means, to operate in STOP mode.
Port 0 pins. This option bit does not affect any of the other
port pins on the part.
Auto Latch Mode. Selecting the DISABLE AUTOLATCH-
ES option disables the autolatches on the Port pins. These
pins will float rather than be pulled to a valid CMOS level
when they are inputs and not connected to an external sig-
nal. SelectingtheENABLEAUTOLATCHESoptionenables
the autolatches on the Port pins and pulls the pins to a valid
CMOSlevelwhentheyarenotconnectedtoanexternalsig-
nal.
Port 1 Pull-Ups. Selecting DISABLE PULL-UPS disables
the input pull-up circuitry on all Port 1 pins. Selecting EN-
ABLE PULL-UPS enables the input pull-up circuitry on all
Port 1 pins. This option bit does not affect any of the other
port pins on the part.
Port 2 Pull-Ups. Selecting DISABLE PULL-UPS disables
the input pull-up circuitry on all Port 2 pins. Selecting EN-
ABLE PULL-UPS enables the input pull-up circuitry on all
Port 2 pins. This option bit does not affect any of the other
port pins on the part.
Port 0 Pull-Ups. Selecting DISABLE PULL-UPS disables
the input pull-up circuitry on all Port 0 pins. Selecting EN-
ABLE PULL-UPS enables the input pull-up circuitry on all
DS007601-Z8X0499
P R E L I M I N A R Y
59
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
EXPANDED REGISTER FILE CONTROL REGISTERS
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
SMR (FH) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
WDT TAP INT RC OSC System Clock
0
1
OFF * *
ON
00
01
10
11
3.5 ms
10 ms
14 ms
56 ms
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
*
External Clock Divide by 2
0
1
SCLK/TCLK =XTAL/2*
SCLK/TCLK =XTAL
WDT During HALT
0
1
OFF
ON *
STOP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
WDT During STOP
0
1
OFF
ON
*
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
XTAL1/INT RC Select for WDT
0
1
On-Board RC
XTAL
*
Reserved (Must be 0)
Stop Delay
0
1
OFF
ON*
* Default setting after RESET
Stop Recovery Level
0
1
Low*
High
Figure 39. Watch-Dog Timer Mode Register
(WRITE ONLY)
Stop Flag (Read only)
0
1
POR*
Stop Recovery
Note: Not used in conjunction with SMR2 Source
* Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
Figure 37. Stop-Mode Recovery Register
(WRITE ONLY, except Bit D7, which is READ ONLY)
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
Figure 38. Stop-Mode Recovery Register2
60
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Z8 CONTROL REGISTERS
R242 T1
D7 D6 D5 D4 D3 D2 D1 D0
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
T
1
Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
Current Value
(When Read)
0 Port 1 Open Drain
T
1 Port 1 Push-pull Active*†
1
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
0
1
Port 0 Low EMI
Figure 42. Counter/Timer 1 Register
(F2 : READ/WRITE)
Port 0 Standard*†
H
0 Port 1 Low EMI
1 Port 1 Standard*
0
1
Port 2 Low EMI
Port 2 Standard*
0
1
Port 3 Low EMI
Port 3 Standard*
R243 PRE1
D7 D6 D5 D4 D3 D2 D1 D0
LowEMI Oscillator
0
1
Low EMI
Standard*
*Default Setting After Reset
† Must be set to one for devices
in 28-pin packages
Count Mode
0
1
T1 Single Pass
T1 Modulo N
Figure 40. Port Configuration Register (PCON)
(WRITE ONLY)
Clock Source
1
0
T1Internal
T1External Timing Input
(TIN) Mode
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R241 TMR
D7 D6 D5 D4 D3 D2 D1 D0
Figure 43. Prescaler 1 Register
(F3 : WRITE ONLY)
H
0
1
No Function
Load T0
0
1
Disable T0 Count
Enable T0 Count
R244 T0
D7 D6 D5 D4 D3 D2 D1 D0
0
1
No Function
Load T1
0
1
Disable T1 Count
Enable T1 Count
T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T0 Current Value
(When Read)
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
Figure 44. Counter/Timer 0 Register
(F4 : READ/WRITE)
TOUT Modes
00 Not Used
01 T0 Out
H
10 T1 Out
11 Internal Clock Out
Figure 41. Timer Mode Register
(F1 : READ/WRITE)
H
DS007601-Z8X0499
P R E L I M I N A R Y
61
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Z8 CONTROL REGISTERS (Continued)
R245 PRE0
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
P00–P03 Mode
00 Output
01 Input
Count Mode
0
1
T0 Single Pass
T0 Modulo N
1X A11–A8
Stack Selection
Reserved (Must be 0)
0
1
External
Internal†
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
P10 - P17 Mode
00 Byte Output†
01 Byte Input
10 AD7 -AD0
Figure 45. Prescaler 0 Register
(F5 : WRITE ONLY)
11 High-Impedance AD7–AD0,
AS, DS, R/W, A11–A8,
A15–A12, If Selected
H
External Memory Timing
0
1
Normal
Extended
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
P04–P07 Mode
00 Output
01 Input
†For 28 pin device, the user must set:
D2=1
D3=0
D4=0
1X A15–A12
P20 - P27 I/O Definition
0
1
Defines Bit as Output
Defines Bit as Input
Figure 48. Port 0 and 1 Mode Register
(F8 : WRITE ONLY)
H
Figure 46. Port 2 Mode Register
(F6 : WRITE ONLY)
H
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
R247 P3M
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
0 Port 2 Pull-Ups Open Drain
1 Port 2 Push-Pull Active
0 P31, P32 Digital Mode
1 P31, P32Analog Mode
0 P32 = Input
P35 = Output
1 P32 = DAV0/RDY0
P35 = RDY0/DAV0
IRQ1, IRQ4 Priority (Group C)
0
1
IRQ1 > IRQ4
IRQ4 > IRQ1
00 P33 = Input
P34 = Output
IRQ0, IRQ2 Priority (Group B)
0
1
IRQ2 > IRQ0
IRQ0 > IRQ2
01 P33 = Input
10 P34 = DM
IRQ3, IRQ5 Priority (GroupA)
11 P33 = DAV0/RDY0
P34 = RDY1/DAV1
0
1
IRQ5 > IRQ3
IRQ3 > IRQ5
0 P31 = Input (T
)
IN
Reserved (Must be 0)
P36 = Output (T )
OUT
1 P31 = DAV2/RDY2
P36 = RDY2/DAV2
0 P30 = Input
P37 = Output
Figure 49. Interrupt Priority Register
(F9 : WRITE ONLY)
¬
H
Reserved (must be 0)
Figure 47. Port 3 Mode Register
(F7 : WRITE ONLY)
H
62
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
R250 IRQ
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = P30 Input
IRQ4 = T0
Expanded Register File
Working Register Pointer
IRQ5 = T1
Figure 53. Register Pointer
(FD : READ/WRITE)
Inter Edge
H
P31 ↓ P32 ↓ = 00
P31 ↓ P32 ↑ = 01
P31 ↑ P32 ↓ = 10
P31 ↑↓ P32 ↑↓ = 11
R254 SPH
D7 D6 D5 D4 D3 D2 D1 D0
Figure 50. Interrupt Request Register
(FA : READ/WRITE)
H
Stack Pointer Upper
Byte (SP8 - SP15)
R251 IMR
D7 D6 D5 D4 D3 D2 D1 D0
Figure 54. Stack Pointer High
(FE : READ/WRITE)
H
1
Enables IRQ0-IRQ5
(D0 = IRQ0)
1
1
Enables RAM Protect *
Enables Interrupts
R255 SPL
D7 D6 D5 D4 D3 D2 D1 D0
* This option must be selected when ROM code is
submitted for ROM Masking, otherwise this control bit
is disabled permanently.
Stack Pointer Lower
Byte (SP0 - SP7)
Figure 51. Interrupt Mask Register
(FB : READ/WRITE)
H
Figure 55. Stack Pointer Low
(FF : READ/WRITE)
H
R252 FLAGS
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1 *
User Flag F2 *
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
* Not affected by reset
Figure 52. Flag Register
(FC : READ/WRITE)
H
DS007601-Z8X0499
P R E L I M I N A R Y
63
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PACKAGE INFORMATION
Figure 56. 28-Pin DIP Package Diagram
Figure 57. 28-Pin SOIC Package Diagram
64
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Figure 58. 28-Pin PLCC Package Diagram
Figure 59. 40-Pin DIP Package Diagram
DS007601-Z8X0499
P R E L I M I N A R Y
65
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Figure 60. 44-Pin PLCC Package Diagram
Figure 61. 44-Pin LQFP Package Diagram
66
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
ORDERING INFORMATION
Z86C34
Standard Temperature
Extended Temperature
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
Z86C3416PSC
Z86C3416SSC
Z86C3416VSC
Z86C3416PEC
Z86C3416SEC
Z86C3416VEC
Z86C35
Standard Temperature
Extended Temperature
28-Pin DIP
Z86C3516PSC
28-Pin SOIC
Z86C3516SSC
28-Pin PLCC
Z86C3516VSC
28-Pin DIP
Z86C3516PEC
28-Pin SOIC
Z86C3516SEC
28-Pin PLCC
Z86C3516VEC
Z86C36
Standard Temperature
Extended Temperature
28-Pin DIP
Z86C3616PSC
28-Pin SOIC
Z86C3616SSC
28-Pin PLCC
Z86C3616VSC
28-Pin DIP
Z86C3616PEC
28-Pin SOIC
Z86C3616SEC
28-Pin PLCC
Z86C3616VEC
Z86C44
Standard Temperature
Extended Temperature
40-Pin DIP
Z86C4416PSC
44-Pin PLCC
Z86C4416VSC
Z86C4416FSC
40-Pin DIP
Z86C4416PEC
44-Pin PLCC
Z86C4416VEC
Z86C4416FEC
44-Pin LQFP
44-Pin LQFP
Z86C45
Standard Temperature
Extended Temperature
40-Pin DIP
Z86C4516PSC
44-Pin PLCC
Z86C4516VSC
44-Pin QFP
Z86C4516FSC
40-Pin DIP
Z86C4516PEC
44-Pin PLCC
Z86C4516VEC
44-Pin QFP
Z86C4516FEC
44-Pin LQFP
44-Pin LQFP
Z86C46
Standard Temperature
Extended Temperature
40-Pin DIP
Z86C4616PSC
44-Pin PLCC
Z86C4616VSC
44-Pin QFP
Z86C4616FSC
40-Pin DIP
Z86C4616PEC
44-Pin PLCC
Z86C4616VEC
Z86C4616FEC
44-Pin LQFP
44-Pin LQFP
For fast results, contact your local ZiLOG sales office for
assistance in ordering the part required.
DS007601-Z8X0499
P R E L I M I N A R Y
67
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PRECAUTIONS (Continued)
PRECAUTIONS
1. Enabling the transmit interrupt (bit 0 in the ASCI
STAT register) does not make the device ready for
transmitter-related interrupts. The receiver interrupt
(bit 3in the ASCI STAT register) must also be enabled.
terrupt may be lost. This situation occurs when an in-
terrupt is generated by one side (either the transmitter
or receiver) and, before the interrupt is serviced, an-
other interrupt is generated by the other side. The sec-
ond interrupt may be lost.
Workaround: For transmit interrupts to be generated,
the RIE bit must also be set. When IRQ3 is generated,
the software should check the STAT register for
details on the interrupt source.
Workaround: The only workaround is not to use
transmitter interrupts when using the ASCI in full-
duplex mode. Use the transmitter in polled mode and
the receiver in interrupt mode for full duplex
operation. In half-duplex operation, this anomaly does
not create a problem.
2. When using the device in full-duplex mode under in-
terrupts (both transmit and receive interrupts enabled),
a small window exists where a transmit or receive in-
68
P R E L I M I N A R Y
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
CODES
For fast results, contact your local ZiLOG sales office for
assistance in ordering the part required.
Preferred Package
Longer Lead Time
P = Plastic DIP
V = Plastic Chip Carrier
F = Plastic Quad Flat Pack
S = Small Outline
Integrated Chip
Preferred Temperature
Longer Lead Time
Speed
S = 0°C to +70°C
E = –40°C to +105°C
16 = 16 MHz
Environmental
C = Plastic Standard
Example:
The Z86C36 is a 16-MHz PLCC, 0ºC to 70ºC, with Plastic
Standard Flow.
Z
ZiLOG Prefix
Product Number
Speed
86C36
16
P
Package
S
C
Temperature
Environmental Flow
Pre-Characterization Product
The product represented by this document is newly introduced
and ZiLOG has not completed the full characterization of the
product. The document states what ZiLOG knows about this
product at this time, but additional features or nonconformance
with some aspects of the document may be found, either by
ZiLOG or its customers in the course of further application and
characterization work. In addition, ZiLOG cautions that delivery
may be uncertain at times, due to start-up yield issues.
DS007601-Z8X0499
P R E L I M I N A R Y
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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Customer Support
For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings,
please visit Zilog’s Knowledge Base at http://www.zilog.com/kb.
For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at
http://support.zilog.com.
70
P R E L I M I N A R Y
DS007601-Z8X0499
相关型号:
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