PDM4M4060S25M [IXYS]
SRAM Module, 256KX32, 25ns, CMOS, SIMM-72;
| 型号： | PDM4M4060S25M |
| 厂家： | 
IXYS CORPORATION |
| 描述： | SRAM Module, 256KX32, 25ns, CMOS, SIMM-72 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PDM4M4060
256K x 32 CMOS
Static RAM Module
1
The PDM4M4060 is packaged in a 72-lead SIMM
(Single In-line Memory Module). The SIMM
configuration allows 72 leads to be placed on a
Features
■ High-density 8 megabit Static RAM module)
■ Low profile 72-lead SIMM and Angled SIMM
(Single In-line Memory Module)
■ Very fast access time: 10 ns (max.)
■ Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
■ Single 5V (±10%) power supply
■ Multiple V pins and decoupling capacitors for
maximum noise immunity
■ Inputs/outputs directly TTL compatible
package 4.25” long and 0.35” wide. At only 0.650” 2
high, this low-profile package is ideal for systems
with minimum board spacing. The SIMM
configuration allows use of angled sockets to reduce
the effective module height further. The Angled 3
SIMM configuration allows 72 leads to be placed on a
package 4.255” long and 0.35” wide. At only 0.680”
high, this low-profile package is ideal for systems
SS
4
with minimum board spacing.
All inputs and outputs of the PDM4M4060 are TTL
compatible and operate from a single 5V supply. Full
Description
asynchronous circuitry requires no clock or refresh for
operation and provides equal access and cycle times 5
The PDM4M4060 is a 256K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate
using eight 256K x 4 static RAMs in plastic SOJ pack-
ages. Availability of four chip select lines (one for
each of two RAMs) provides byte access. The
PDM4M4060 is available with access times as fast as
15 ns with minimal power consumption.
for ease of use.
Four identification pins (PD3-PD0) are provided for
applications in which different density versions of the
module are used. In this way, the target system can
read the respective levels of PD3-PD0 to determine a
256K depth.
6
7
Functional Block Diagram
CS1
CS2
CS3
CS4
9
18
ADDRESS
WE
2
PD
256K x 32
10
11
12
OE
8
8
8
8
I/O31-I/O0
Rev 2.2
PDM4M4060
(1)
Pin Configuration
Pin Assignment
Pin
Signal
1
3
NC
PD0 - Vss
2
NC
PD3
PD0
I/O0
I/O1
I/O2
I/O3
Vcc
A7
PD2
Vss
PD1 - Vss
I/O31-I/O0
A17-A0
CS4-CS1
WE
Data Inputs/Outputs
Addresses
4
5
PD2 - OPEN
PD3 - OPEN
6
Chip Selects
Write Enable
Output Enable
Depth Identification
Power
7
PD1
I/O8
I/O9
I/O10
I/O11
A0
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
OE
11
13
15
17
19
21
23
25
27
29
31
33
35
PD3-PD0
V
CC
V
Ground
SS
NC
No Connect
A1
A8
A2
A9
I/O12
I/O13
I/O14
I/O15
Vss
I/O4
I/O5
I/O6
I/O7
WE
A15
CS2
A14
CS1
SIMM
TOP VIEW
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CS4
A17
OE
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CS3
A16
Vss
I/O24
I/O25
I/O26
I/O27
A3
I/O16
I/O17
I/O18
I/O19
A10
A4
A11
A5
A12
Vcc
A13
A6
I/O20
I/O21
I/O22
I/O23
Vss
I/O28
I/O29
I/O30
I/O31
NC
NC
NC
NC
NOTE: 1. Pins 3, 4, 5, and 7 (PD3-PD0) are read by the
user to determine the density of the module. If
PD0, PD1 reads V and PD2, PD3 reads
SS
OPEN then the module has a 256K depth.
Rev 2.2
PDM4M4060
Truth Table
CS
OE
WE
Mode
Output
Power
1
2
Deselect/
Power-down
H
X
X
High-Z
Standby
Read
L
L
L
L
X
H
H
L
DATA
Active
Active
Active
OUT
Write
DATA
IN
Deselect
H
High-Z
3
(1)
Absolute Maximum Ratings
4
Symbol
Rating
Com’l.
Ind.
Unit
V
Terminal Voltage with Respect to V
Temperature Under Bias
Storage Temperature
–0.5 to +7.0
–10 to +85
–55 to +125
0 to +70
1.0
–0.5 to +7.0
–10 to +85
–65 to +150
0 to +70
1.0
V
°C
°C
°C
W
TERM
BIAS
STG
A
SS
T
T
T
5
Operating Temperature
Power Dissipation
P
T
6
I
DC Output Current
50
50
mA
OUT
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device.This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
7
Recommended DC Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
9
V
V
Supply Voltage
4.75
0
5.0
0
5.25
0
V
V
CC
Supply Voltage
SS
Commercial
Ambient Temperature
0
25
70
°C
10
11
12
Rev 2.2
PDM4M4060
DC Electrical Characteristics (V = 5.0V ± 5%, T = 0°C to 70°C)
CC
A
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
I
I
Input Leakage Current
(Address WE, and OE)
V
V
V
= Max.,V = V to V
CC
—
80
µA
LI
CC
IN
SS
Input Leakage Current
(Data and CS)
= Max., V = V to V
CC
—
—
10
10
µA
µA
LI
CC
IN
SS
Output Leakage Current
= V to V , V = Max.,
SS CC CC
LO
OUT
CS = V
IH
V
V
V
V
Output Low Voltage
Output High Voltage
Input High Voltage
Input Low Voltage
I
I
= 8 mA, V = Min.
—
0.4
—
V
V
V
V
OL
OH
IH
OL
OL
CC
= –4 mA, V = Min.
2.4
2.2
CC
6.0
0.8
(1)
–0.5
IL
NOTE 1. V = –3.0V for pulse widths less than 10 ns, once per cycle.
IL
Power Supply Characteristics
20 ns - 25
(1)
10 ns - 15 ns
Max
(1)
ns
Max
Unit
Symbol
Parameter
I
I
I
Operating Current
1600
480
1360
mA
mA
mA
CC
CS = V , V = Max., f = f , Outputs Open
IL
CC
MAX
Standby Current
CS ≥ V , V = Max., f = f , Outputs Open
MAX
480
120
SB
IH
CC
Full Standby Current CS ≥ V – 0.2V,
320
SB1
CC
f = 0, V > V – 0.2V or < 0.2V, Outputs Open
IN
CC
NOTE 1. Preliminary specification only.
Capacitance(1) (T = +25°C, f = 1.0 MHz)
A
Symbol
Parameter
Input Capacitance, (CS) V = 0V
Max.
Unit
C
C
C
20
70
12
pF
pF
pF
IN(D)
IN(A)
I/O
IN
Input Capacitance, (Address and Control) V = 0V
IN
I/O Capacitance, V
= 0V
OUT
NOTE 1. This parameter is determined by device characteristics but is not production tested.
Rev 2.2
PDM4M4060
AC Test Conditions
Input Pulse Levels
V
to 3.0V
SS
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5 ns
1.5V
1.5V
1
2
See Figures 1 and 2
3
+5V
+5V
480Ω
480Ω
4
DATAOUT
255Ω
DATAOUT
255Ω
5 pF*
30 pF*
5
* Including scope and jig capacitances
* Including scope and jig capacitances
6
Figure 2. Output Load
(for tOHZ, tCHZ, tOLZ, and tCLZ)
Figure 1. Output Load
7
9
10
11
12
Rev 2.2
PDM4M4060
AC Electrical Characteristics (Vcc = 5V ± 5%, T = 0°C to +70°C)
A
PDM4M4060SXXZ, PDM4M4060SXXM
(2)
(2)
(2)
-10 ns
-12 ns
-15 ns
-20 ns
-25 ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Symbol
Parameter
Unit
Read Cycle
t
t
t
t
t
t
t
t
t
Read Cycle Time
10
—
—
2
—
10
10
—
5
12
—
—
2
—
12
12
—
7
15
—
—
2
—
15
15
—
8
20
—
—
5
—
20
20
—
10
—
10
10
—
25
—
—
5
—
25
25
—
12
—
12
10
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address Access Time
AA
Chip Select Access Time
ACS
(1)
Chip Select to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Deselect to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
CLZ
—
0
—
0
—
0
—
0
—
0
OE
(1)
(1)
—
6
—
7
—
8
OLZ
—
—
3
—
—
3
—
—
3
—
—
3
—
—
3
CHZ
OHZ
OH
(1)
6
7
8
—
—
—
Write Cycle
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
10
8
—
—
—
—
—
—
5
12
10
10
0
—
—
—
–
15
12
12
0
—
—
—
—
—
—
7
—
20
—
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AW
AS
Chip Select to End of Write
Address Valid to End of Write
Address Setup Time
8
20
15
15
0
—
—
—
–
25
20
20
0
—
—
—
—
—
—
15
—
0
Write Pulse Width
8
10
1
—
—
6
12
1
WP
WR
WHZ
DW
DH
Write Recovery Time
1
(1)
Write Enable to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
—
6
—
7
—
8
15
0
—
—
13
—
20
0
—
—
—
—
—
—
—
—
—
1
1
1
—
12
—
15
(1)
OW
1
1
1
NOTES 1. This parameter is determined by device characteristics but is not production tested.
2. Preliminary specifications only.
Rev 2.2
PDM4M4060
(1)
Timing Waveforms of Read Cycle No.1
t
RC
1
2
ADDRESS
t
AA
OE
CS
t
t
OH
(5)
OE
(5)
t
OLZ
3
t
t
OHZ
ACS
(5)
(5)
t
t
CHZ
CLZ
D
OUT
4
5
(1,2,4)
Timing Waveforms of Read Cycle No.2
t
RC
6
ADDRESS
t
AA
t
t
OH
OH
7
D
OUT
Previous Data Valid
Data Valid
(1,3,4)
Timing Waveforms of Read Cycle No.3
9
CS
t
ACS
10
11
12
(5)
(5)
t
t
CLZ
CLZ
D
OUT
NOTES 1 WE is HIGH for Read Cycle.
2. Device is continuously selected. CS = V .
IL
3. Address valid prior to or coincident with CS transition LOW.
4. OE = V .
5. Transition is measured ±200 mV for steady state. This parameter is
IL
determined by device characteristics but is not production tested.
Rev 2.2
PDM4M4060
(1,2,3,7)
WE
Timing Waveforms of Write Cycle No.1 (
Controlled)
t
WC
ADDRESS
OE
t
AW
CS
(7)
t
t
t
WR
AS
WP
WE
(6)
t
WHZ
(6)
(6)
(6)
t
t
t
OHZ
OHZ
OW
D
OUT
(4)
(4)
t
t
DH
DW
D
IN
Data Valid
(1,2,3,5)
CS
Timing Waveforms of Write Cycle No.2 (
Controlled)
t
WC
ADDRESS
t
AW
CS
t
t
t
WR
AS
CW
WE
t
t
DH
DW
D
IN
Data Valid
NOTES 1 WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (t ) of a LOW CS and a LOW WE.
WP
3. t
is measured from the earlier of CS or WE going HIGH to end the write cycle.
WR
4. During this period, I/O pins are in the output state, and input signals must be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs
remain in a high-impedance state.
6. Transition is measured ±200 mV for steady state with a 5 pF load (including scope and jig). This
parameter is determined by device characteristics but is not production tested.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
or
WP
(t
+ t ) to allow the I/O drivers to turn off and data to be placed on the bus for the required t
.
WHZ
DW
DW
If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write
pulse width can be as short as the specified t
.
WP
Rev 2.2
PDM4M4060
Package Dimensions
SIMM Version
1
2
SIDE VIEW
FRONT VIEW
4.250
3.979
0.350
COMPONENTS THIS SIDE
(NOT SHOWN)
0.650
0.250
0.400
3
0.250
0.050
PIN 1
0.050
0.080
4
BACK VIEW
5
COMPONENTS THIS SIDE
(NOT SHOWN)
6
PIN 1
Angled SIMM Version
7
SIDE VIEW
4.255
Max.
3.988
3.980
0.350
Max.
COMPONENTS BOTH SIDES
(NOT SHOWN)
0.680
Max.
9
0.403
0.397
.220 ref
.130 ref
0.251
0.249
0.255
0.245
PIN 1
0.050
Typical
10
11
12
0.630 R
0.610 R
0.085
0.075
0.255
0.245
3.752
3.748
Rev 2.2
PDM4M4060
Ordering Information
PDM4M XXXXX
S
XX
X
X
Device Power Speed Package Temp
Blank Commercial (0 to 70°C)
AM
M
72-Lead Angled SIMM
72-lead SIMM
10
12
15
20
25
Commercial
S
Standard Power
256K x 32
4060
Rev 2.2
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