CPC7584BA-TR_技术文档

CPC7584

Line Card Access Switch

sary functions to replace two 2-Form-C electro-

mechanical relays on analog line cards found in Cen-

tral Office, Access, and PBX equipment. The device

contains solid state switches for tip and ring line break,

ring injection/ring return and test access. The

CPC7584 requires only a +5V supply and offers

“break-before-make” or “make-before-break” switch

operation using simple logic-level input control.

Features

• Small 16-pin surface-mount SOIC package and very

small micro-leadframe package (MLP) available

• Monolithic IC reliability

• Low matched RDS

ON

• Eliminates the need for zero cross switching

• Flexible switch timing to transition from ringing mode

to idle/talk mode.

• Clean, bounce free switching

The CPC7584xC differs from the CPC7584xA/B with

the addition of a logic state. See “Functional Descrip-

tion” on page 10 for more information. The

CPC7584xC also has a higher hold current for the pro-

tection SCR.

• Tertiary protection consisting of integrated current

limiting, thermal shutdown, and SLIC protection

• 5 V operation with power consumption less than

10 mW

• Intelligent battery monitor

• Latched logic level inputs, no drive circuitry

Ordering Information

Applications

Part Number Description

• Central office (CO)

CPC7584BA

CPC7584BB

SOIC 6-pole LCAS with protection SCR

SOIC 6-pole LCAS without protection SCR

• Digital Loop Carrier (DLC)

• PBX Systems

SOIC 6-pole LCAS with protection SCR and

added logic state

• Digitally Added Main Line (DAML)

• Hybrid Fiber Coax (HFC)

• Fiber in the Loop (FITL)

• Pair Gain System

CPC7584BC

CPC7584MA

CPC7584MB

MLP 6-pole LCAS with protection SCR

MLP 6-pole LCAS without protection SCR

• Channel Banks

MLP 6-pole LCAS with protection SCR and

added logic state

CPC7584MC

Description

The CPC7584 is a monolithic solid state switch in a

16-pin surface-mount package. It provides the neces-

Add -TR to the part number when ordering

tape and reel packaging

CPC7584xx-TR

Figure 1. CPC7584 Block Diagram

V_BAT

TRING (4)

TTEST-IN (5)

Reference (16)

SW3

Ringing

SW5

Test-In

Return

TLINE

TBAT(2)

R1

TIP

(3)

SW1

Break

Secondary

Protection

SCR

and Trip

Circuit

SLIC

R2

Ring

SW4

Ringing

Access

SW6

Test-In

RBAT (15)

SW2

Break

RLINE

(14)

CPC7584

Ring Generator

R^Test-In(12)

-

+

RRING (13)

Battery

DS-CPC7584-R0.A

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1

CPC7584

1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1 Absolute Maximum Ratings (at 25° C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Electrical Characteristics, TA = -40° C to +85° C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2.3 Ring Return Switch, SW3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2.4 Ringing Access Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.5 Test-In Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 Alternate Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.5 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.6 CPC7584xA/B Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.7 CPC7584xC Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Package Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Switch Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3 Ring Access Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.4 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.5 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6.2 Current Limiting function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.7 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.8 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.9 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4.1 Moisture Reflow Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1

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R0.A

CPC7584

1. Specifications

Absolute maximum ratings are stress ratings. Stresses in

excess of these ratings can cause permanent damage to

the device. Functional operation of the device at these or

any other conditions beyond those indicated in the opera-

tional sections of this data sheet is not implied. Exposure of

the device to the absolute maximum ratings for an

extended period may degrade the device and affect its reli-

ability.

1.1 Absolute Maximum Ratings (at 25° C)

Parameter

Minimum Maximum

Unit

Operating temperature

Storage temperature

-40

5

+110

+150

95

°C

%

Operating relative humidity

Pin soldering temperature

(10 seconds max)

-

+260

°C

1.2.1 Power Supply Specifications

+5 V power supply

Battery Supply

-

7

-85

7

V

Supply

Minimum Typical Maximum Unit

V

+4.5

-19

+5.0

-

+5.5

-72

V

DD

Logic input voltage

1

Logic input to switch output

isolation

V

BAT

-

330

V

1

V

is used only as a reference for internal protection circuitry. If V

rises above

BAT

-10 V, the device will enter the all-off state and will remain in the all-off state until the

battery drops below -15 V.

Switch isolation (SW1,

SW2, SW3, SW5, SW6)

-

330

480

V

Switch Isolation (SW4)

ESD Rating (Human Body Model)

1.2 Electrical Characteristics, T = -40° C to +85° C

A

1000 V

Unless otherwise specified, minimum and maximum

values are production testing requirements. Typical

values are characteristic of the device and are the

result of engineering evaluations. Typical values are

provided for information purposes only and are not

part of the testing requirements.

1.2.2 Break Switches, SW1 and SW2

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Off-state leakage current

V

(differential) = -320 V to GND

(differential) = -60 V to +260 V

SW

I

+25° C

+85° C

-40° C

-

0.1

0.3

0.1

1

µA

SW

V

(differential) = -330 V to GND

(differential) = -60 V to +270 V

SW

I

SW

V

(differential) = -310 V to GND

(differential) = -60 V to +250 V

SW

I

SW

RDS

ON

T

= 10 mA, 40 mA, T = -2 V

BAT

+25° C

+85° C

-40° C

∆ V

-

14.5

20.5

10.5

-

28

-

Ω

LINE

T

= 10 mA, 40 mA, T = -2 V

BAT

= 10 mA, 40 mA, T = -2 V

BAT

Per on-resistance test condition of

SW1, SW2R SW1-R SW2

RDS match

ON

Magnitude

-

0.15

0.8

Ω

ON

DC current limit

+25° C

V

(on) = 10 V

I

-

80

-

300

160

400

-

mA

SW

I

+85° C

SW

I

-40° C

425

SW

Rev. 0.A

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2

CPC7584

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Break switches in on state, ringing

access switches off, apply 1 kV at

10/1000 ms pulse, with appropriate

secondary protection in place.

Dynamic current limit

(t = <0.5 µs)

I

-

2.5

-

A

SW

Logic input to switch output isolation

V

(T , R ) = 320 V, logic

SW LINE LINE

I

+25° C

-

0.1

0.3

0.1

200

1

-

µA

SW

inputs = gnd

(T , R ) = 330 V, logic

V

SW LINE LINE

I

+85° C

SW

inputs = gnd

(T , R ) = 310 V, logic

V

SW LINE LINE

I

-40° C

µA

SW

inputs = gnd

Applied voltage = 100 V p-p square

wave at 100 Hz

dv/dt sensitivity

-

V/µs

1.2.3 Ring Return Switch, SW3

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Off-state leakage current

V

(differential) = -320 V to GND

(differential) = -60 V to +260 V

SW

I

+25° C

+85° C

-40° C

-

0.1

0.3

0.1

1

µA

SW

V

(differential) = -330 V to GND

(differential) = -60 V to +270 V

SW

I

SW

V

(differential) = -310 V to GND

(differential) = -60 V to +250 V

SW

I

SW

RDS

ON

I

(on) = 0 mA, 10 mA

+25° C

∆ V

-

60

85

45

-

100

-

Ω

SW

I

+85° C

SW

-40° C

DC current limit

+25° C

V

(on) = 10 V

I

-

135

85

-

mA

SW

(on) = 10 V

I

+85° C

SW

I

-40° C

210

SW

Break switches in on state, ringing

access switches off, apply 1 kV at

10/1000 ms pulse, with appropriate

secondary protection in place.

Dynamic current limit

(t = <0.5 µs)

I

-

2.5

-

A

SW

Logic input to switch output isolation

(T

V

, T ) = 320 V, logic

SW RING LINE

I

+25° C

+85° C

-40° C

-

0.1

0.3

0.1

1

µA

SW

inputs = gnd

(T , T ) = 330 V, logic

V

SW RING LINE

I

SW

inputs = gnd

(T , T ) = 310 V, logic

V

SW RING LINE

I

SW

inputs = gnd

3

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Rev. 0.A

CPC7584

1.2.4 Ringing Access Switch, SW4

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Off-state leakage current

V

(differential) = -255 V to +210 V

(differential) = +255 V to -210 V

SW

I

+25° C

+85° C

-

0.05

0.1

1

µA

SW

V

(differential) = -270 V to +210 V

(differential) = +270 V to -210 V

SW

I

SW

V

(differential) = -245 V to +210 V

(differential) = +245 V to -210 V

SW

I

-40° C

0.05

SW

I

(on) = 1 mA

On Voltage

-

1.5

0.1

3

V

SW

Ring generator current

during ring

V

= 5 V, INaccess = 0

I

0.25

mA

CC

R

Surge current

-

I

-

2

-

A

µA

Ω

Release current

300

8.5

RDS

(on) = 70 mA, 80 mA

SW

∆ V

12

ON

Logic input to switch output isolation

(R

V

, R ) = 320 V, logic

SW RING LINE

I

+25° C

+85° C

-40° C

-

0.05

0.1

1

µA

SW

inputs = gnd

(R , R ) = 330 V, logic

V

SW RING LINE

I

SW

inputs = gnd

(R , R ) = 310 V, logic

V

SW RING LINE

I

0.05

SW

inputs = gnd

1.2.5 Test-In Switches, SW5 and SW6

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Off-state leakage current

V

(differential) = -320 V to GND

(differential) = -60 V to +260 V

SW

I

+25° C

+85° C

-40° C

-

0.1

0.3

0.1

1

µA

SW

V

(differential) = -330 V to GND

(differential) = -60 V to +270 V

SW

I

SW

V

(differential) = -310 V to GND

(differential) = -60 V to +250 V

SW

I

SW

RDS

ON

T

= 10 mA, 40 mA, T = -2 V

BAT

+25° C

∆ V

-

38

46

28

-

70

-

Ω

LINE

T

= 10 mA, 40 mA, T = -2 V

BAT

+85° C

= 10 mA, 40 mA, T = -2 V

BAT

-40° C

DC current limit

+25° C

V

(on) = 10 V

I

-

80

-

175

110

210

-

mA

SW

I

+85° C

SW

I

-40° C

250

SW

Break switches in on state, ringing

access switches off, apply 1 kV at

10/1000 ms pulse, with appropriate

secondary protection in place.

Dynamic current limit

(t = <0.5 µs)

I

-

2.5

-

A

SW

Rev. 0.A

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4

CPC7584

Parameter

Logic input to switch output isolation

(T

Conditions

Symbol

Minimum

Typical

Maximum

Unit

V

, T ) = 320 V, logic

SW ACCESS LINE

I

+25° C

+85° C

-40° C

-

0.1

0.3

0.1

1

µA

SW

inputs = gnd

(T

V

, T ) = 330 V, logic

SW ACCESS LINE

I

SW

inputs = gnd

(T

V

, T ) = 310 V, logic

SW ACCESS LINE

I

SW

inputs = gnd

1.3 Additional Electrical Characteristics

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Digital input characteristics

-

Input low voltage

Input high voltage

-

1.5

-

V

3.5

Input leakage current

(high)

V

= 5.5 V, V = -75 V, V = 5 V

BAT log

I

-

0.1

1

DD

log

µA

Input leakage current

(low)

V

= 5.5 V, V = -75 V, V = 0 V

BAT log

I

log

Power requirements

Power dissipation in

idle/talk and all-off

states

V

= 5 V, V = -48 V

BAT

I

, I

DD BAT

-

5.5

6.5

10

DD

mW

Power dissipation in

ringing and access

states

(on) = 10 V

I

SW

DD

V

current in idle/talk

DD

I

-

1.1

1.3

0.1

2.0

10

DD

and all off states

current in ringing

V

= 5 V

mA

DD

V

DD

I

DD

and access states

current in idle/talk

V

BAT

I

BAT

and all off states

current in ringing

V

= -48 V

µA

BAT

V

BAT

I

10

BAT

and access states

Temperature Shutdown Requirements (temperature shutdown flag is active low)

Shutdown activation

temperature

-

110

10

125

-

150

25

°C

Shutdown circuit hyster-

esis

-

5

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Rev. 0.A

CPC7584

1.3.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition)

Line

Break

Ring

Switches Return

Ring

Access

1 and 2 Switch 3 Switch 4

Access

Switches

5 and 6

Test-In

Input

TSD

State

Timing

0 V

5 V

Floating

Ringing

-

Open

Closed

Open

Closed

Open

SW4 waiting for next zero-current crossing

to turn off. Maximum time is one-half of ring-

ing. In this transition state, current that is

limited to the dc break switch current limit

value will be sourced from the ring node of

the SLIC.

Make-

before-

break

0 V

Floating

Floating Idle/Talk

Zero-cross current has occurred

1.3.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition)

Line

Break

Ring

Switches Return

Ring

Access

1 and 2 Switch 3 Switch 4

Access

Switches

5 and 6

Test-In

Input

TSD

State

Timing

0 V

5 V

Floating

Ringing

All-off

-

Open

Closed

Open

Closed

Open

Hold this state for at least 25 ms. SW4 wait-

ing for zero current to turn off.

5 V

0 V

5 V

0 V

SW4 has opened.

Open

Floating Idle/Talk

Release Break Switches

Closed

1.4 Alternate Break-Before-Make Operation

Break-before-make operation can also be achieved

using TSD as an input. In lines 2 and 3 of “Break-

Before-Make Operation (Ringing to Idle/Talk Transi-

tion)” on page 6, instead of using the logic input pins to

force the all-off state, force TSD to ground. This over-

rides the logic inputs and also forces the all off state.

Hold this state for 25 ms. During this 25 ms all-off

state, toggle the inputs from the ringing state (Ring =

5 V, Test-In = 0 V) to the idle/talk state

(Ring = 0 V, Test-In=0 V). After 25 ms, release TSD to

return switch control to the input pins which will set the

idle talk state.

When using the CPC7584 in this mode, forcing TSD

to ground overrides the input pins and force an all off

state. Setting TSD to +5 V allows switch control via the

logic input pins. However, setting TSD to +5 V also

disables the thermal shutdown mechanism. This is not

recommended. Therefore, to allow switch control via

the logic input pins, allow TSD to float.

When using TSD as an input, the two recommended

states are 0 (overrides logic input pins and forces all

off state) and float (allows switch control via logic input

pins and the thermal shutdown mechanism is active).

This may require use of an open-collector buffer.

Rev. 0.A

www.clare.com

6

CPC7584

1.5 Protection Circuitry Electrical Specifications

Parameter

Conditions

Symbol

Minimum

Typical

Maximum Unit

Parameters Related to the Diodes in the Diode Bridge

Voltage drop at continu- Apply dc current limit of break

ous current (50/60 Hz) switches

Forward

Voltage

-

2.1

5

3

V

-

Voltage drop at surge Apply dynamic current limit of break Forward

current

Parameters Related to the Protection SCR

Surge current

Trigger current (+25° C) -

Hold current (+25° C)

Trigger current (+85° C) -

switches

Voltage

-

60

100

35

70

-

*

-

A

I

mA

V

TRIG

I

-

HOLD

I

-

TRIG

I

Hold current (+85° C)

Gate trigger voltage

-

60

HOLD

V

-4

V

-2

Trigger current

-

BAT

Reverse leakage cur-

rent

V

-

1.0

µA

BAT

V

0.5 A, t = 0.5 ms

2.0 A, t = 0.5 ms

-

-3

-5

-

V

ON

On-state voltage

-

*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.

1.6 CPC7584xA/B Truth Table

Tip

Break

Switch

Ring

Break

Switch

Ringing

Return

Switch

Ring

Switch

Tip Test-In Ring Test-

In Switch

1

State

Ring

Test-In

TSD

Switch

Idle/Talk

0 V

5 V

0 V

On

Off

On

Off

On

Off

On

Off

Power Ring-

ing

Off

5 V/Floating

0 V

Test-In

All Off

0 V

5 V

Off

On

Off

On

Off

All off

Don’t care Don’t care

1

If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled.

1.7 CPC7584xC Truth Table

Tip

Break

Switch

Ring

Break

Switch

Ringing

Return

Switch

Ring

Switch

Tip Test-In Ring Test-

In Switch

1

State

Ring

Test-In

TSD

Switch

Idle/Talk

0 V

5 V

0 V

On

Off

On

Off

On

Off

On

Off

Power Ring-

ing

5 V/Floating

0 V

Test Monitor

All Off

0 V

5 V

On

Off

On

Off

On

Off

On

Off

All off

Don’t care Don’t care

1

If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled.

7

www.clare.com

Rev. 0.A

CPC7584

2.1 Pinout

2. Package Pinout

1

Name

Description

Tip lead test input

Fault ground

1 T_TEST-IN

2 F_GND

3 T_BAT

R

16

15

14

TEST-IN

T

TEST-IN

V

BAT

R

BAT

F

2

GND

T

3

Connect to tip lead on SLIC side

Connect to tip lead on the line side

Connect to ring generator return

+5 V supply

BAT

T

4 T_LINE

5 T_RING

6 V_DD

R_LINE13

R_RING12

LATCH 11

IN_RING10

4

LINE

5

RING

V

6

DD

Temperature shutdown pin. Can be used

as a logic-level input or output. See “Make-

Before-Break Operation (Ringing to Idle/

Talk Transition)” on page 6, “Break-

Before-Make Operation (Ringing to Idle/

Talk Transition)” on page 6, and

7 T_SD

8 D_GND

IN_TEST-IN

9

7

TSD

“CPC7584xA/B Truth Table” on page 7 for

details. As an output, TSD will read +5 V

when the device is in the operational mode

and 0 V in the thermal shutdown mode. To

disable thermal shutdown, tie this pin to +5

V (not recommended)

D

8

9

Digital ground

GND

IN

Logic-level switch control input

TEST-IN

IN

10

RING

Data latch control, active high, transparent

low

11

LATCH

R

12

13

14

15

16

Test access

ACCESS

R

Connect to ring generator

Connect to ring lead on the line side

Connect to ring lead on the SLIC side

Test-in access on ring

RING

R

LINE

R

BAT

V

TEST-IN

Rev. 0.A

www.clare.com

8

CPC7584

3. Functional Description

3.1 Introduction

The CPC7584xA/B has four states:

mum breakdown voltage of the switches. To minimize

the stress on the solid-state contacts, use of a fold-

back or crowbar type secondary protector is recom-

mended. With proper selection of the secondary

protector, a line card using the CPC7582BC will meet

all relevant ITU, LSSGR, FCC and UL protection

requirements.

• Idle/Talk. Line break switches SW1 and SW2

closed, ringing switches SW3 and SW4 open, and

test-in switches SW5 and SW6 open.

• Ringing. Line break switches SW1 and SW2 open,

ringing switches SW3 and SW4 closed, and test-in

switches SW5 and SW6 open.

• Test-In. Line break switches SW1 and SW2 open,

ringing switches SW3 and SW4 open, and test-in

switches SW5 and SW6 closed.

• All off. Line break switches SW1 and SW2 open,

ringing switches SW3 and SW4 open, and loop test

switches SW5 and SW6 open.

The CPC7584 operates from a +5 V supply only. This

gives the device extremely low idle and active power

dissipation and allows use with virtually any range of

battery voltage. A battery voltage is also used by the

CPC7584 as a reference for the integrated protection

circuit. In the event of a loss of battery voltage, the

CPC7584 enters the all-off state.

In the CPC7584xC, the test-in state is replaced with

the test monitor state, defined as: line break switches

SW1 and SW2 closed, Ringing switches SW3 and

SW4 open, and test-in switches SW5 and SW6

closed.

3.2 Switch Timing

The CPC7584 provides, when switching from the ring-

ing state to the idle/talk state, the ability to control the

release timing of the ringing access switches SW3

and SW4 relative to the state of the line break

switches SW1 and SW2 using simple logic-level input.

This is referred to a make-before-break or break-

before-make operation. When the line break switch

contacts (SW1 and SW2) are closed (or made) before

the ringing access switch contacts (SW3 and SW4)

are opened (or broken), this is referred to make-

before-break operation. Break-before-make operation

occurs when the ringing access contacts (SW3 and

SW4) are opened (broken) before the line break

switch contacts (SW1 and SW2) are closed (made).

With the CPC7584, the make-before-break and break-

before-make operations can easily be selected by

The CPC7584 offers break-before-make and make-

before-break switching with simple logic-level input

control. Solid-state switch construction means no

impulse noise is generated when switching during ring

cadence or ring trip, eliminating the need for external

zero-cross switching circuitry. State-control is via

logic-level input so no additional driver circuitry is

required. The line break switches SW1 and SW2 are

linear switches that have exceptionally low RDS

ON

and excellent matching characteristics. The ringing

access switch SW4 has a breakdown voltage rating of

greater than 480 V. This is sufficiently high, with

proper protection, to prevent breakdown in the pres-

ence of a transient fault condition (i.e., passing the

transient on to the ring generator).

applying logic-level inputs to pins 9 and 10 (IN

RING

and IN

) of the device.

TEST-IN

The logic sequences for either mode of operation are

given in “Make-Before-Break Operation (Ringing to

Idle/Talk Transition)” on page 6 and “Break-Before-

Make Operation (Ringing to Idle/Talk Transition)” on

page 6. Logic states and explanations are given in

“CPC7584xA/B Truth Table” on page 7.

Integrated into the CPC7584 is a diode bridge/SCR

clamping circuit, current limiting, and a thermal shut-

down mechanism to provide protection to the SLIC

device during a fault condition. Positive and negative

surges are reduced by the current limiting circuitry and

steered to ground via diodes and the integrated SCR.

Power-cross transients are also reduced by the cur-

rent limiting and thermal shutdown circuits. Note that

only the CPC7584xA and CPC7584xC parts include

the integrated protection SCR.

Break-before-make operation can also be achieved

using pin 7 (TSD) as an input. In “Break-Before-Make

Operation (Ringing to Idle/Talk Transition)” on page 6

lines 2 and 3, it is possible to induce the switches to

the all-off state by grounding pin 7 (TSD) instead of

apply logic input to the pins. This has the effect of

overriding the logic inputs and forcing the device to the

all-off state. Hold this input state for 25 ms. During this

hold period, toggle the inputs from the ringing state

To protect the CPC7584 from an overvoltage fault

condition, use of a secondary protector is required.

The secondary protector must limit the voltage seen at

the tip and ring terminals to a level below the maxi-

9

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Rev. 0.A

CPC7584

(10) to the idle/talk state (00). After the 25 ms, release

pin 7 (TSD) to return the switch control to the input

pins 9 and 10 and reset the device to the idle/talk

state.

restored. The device also enters the all-off state if the

battery voltage rises above –10 V and remains in the

all-off state until the battery voltage drops below

–15 V. This battery monitor feature draws a small cur-

rent from the battery (less than 1 mA typical) and will

add slightly to the device’s overall power dissipation.

Setting TSD to +5 V allows switch control using the

logic pins 9 and 10. This setting, however, also dis-

ables the thermal shutdown circuit and is therefore not

recommended. When using logic controls via the input

pins 9 and 10, pin 7 (TSD) should be allowed to float.

As a result, the two recommended states when using

pin 7 (TSD) as a control are 0, which forces the device

to the all-off state, or float, which allows logic inputs to

pins 9 and 10 to remain active. This may require the

use of an open-collector buffer.

3.6 Protection

3.6.1 Diode Bridge/SCR

The CPC7584 uses a combination of current limited

break switches, a diode bridge/SCR clamping circuit,

and a thermal shutdown mechanism to protect the

SLIC device or other associated circuitry from damage

during line transient events such as lightning. During a

positive transient condition, the fault current is con-

ducted through the diode bridge to ground. Voltage is

clamped to the diode drop above ground. During a

negative transient of 2 to 4 V more negative than the

battery, the SCR conducts and faults are shunted to

ground via the SCR and diode bridge.

3.3 Ring Access Switch Zero-Cross Current Turn Off

After the application of a logic input to turn SW4 off,

the ring access switch is designed to delay the change

in state until the next zero-crossing. Once on, the

switch requires a zero-current cross to turn off, and

therefore should not be used to switch a pure DC sig-

nal. The switch will remain in the on state no matter

what logic input until the next zero crossing. For

In order for the SCR to crowbar or foldback, the on

voltage (see “Protection Circuitry Electrical Specifica-

tions” on page 7) of the SCR must be less negative

than the battery reference voltage. If the battery volt-

age is less negative the SCR on voltage, the SCR will

not crowbar, however it will conduct fault currents to

ground.

proper operation, pin 12 (R

) should be connected

RING

using proper impedance to a ring generator or other

AC source. These switching characteristics will reduce

and possibly eliminate overall system impulse noise

normally associated with ringing access switches. The

attributes of ringing access switch SW4 may make it

possible to eliminate the need for a zero-cross switch-

ing scheme. A minimum impedance of 300 Ω in series

with the ring generator is recommended.

For power induction or power-cross fault conditions,

the positive cycle of the transient is clamped to the

diode drop above ground and the fault current directed

to ground. The negative cycle of the transient will

cause the SCR to conduct when the voltage exceeds

the battery reference voltage by two to four volts,

steering the current to ground.

3.4 Power Supplies

Both a +5 V supply and battery voltage are connected

to the CPC7584. CPC7584 switch state control is

powered exclusively by the +5 V supply. As a result,

the CPC7584 exhibits extremely low power dissipation

during both active and idle states.

3.6.2 Current Limiting function

If a lightning strike transient occurs when the device in

the talk/idle state, the current is passed along the line

to the integrated protection circuitry and limited by the

dynamic current limit response of break switches SW1

and SW2. When a 1000V 10/1000 pulse (LSSGR

lightning) is applied to the line though a properly

clamped external protector, the current seen at pins 2

The battery voltage is not used for switch control but

rather as a reference for the integrated secondary pro-

tection circuitry. The integrated SCR is designed to

trigger when pin 3 (T ) or pin 14 (R ) drops 2 to

BAT

4 V below the battery. This trigger prevents a fault

(T ) and pin 15 (R ) will be a pulse with a typical

BAT

induced overvoltage event at the T

or R

nodes.

magnitude of 2.5 A and a duration of less than 0.5 ms.

BAT

If a power-cross fault occurs with the device in the talk/

idle state, the current is passed though break switches

SW1 and SW2 on to the integrated protection circuit

and is limited by the dynamic DC current limit

response of the two break switches. The DC current

limit, specified over temperature, is between 80 mA

3.5 Battery Voltage Monitor

The CPC7584 also uses the voltage reference to

monitor battery voltage. If battery voltage is lost, the

CPC7582BC immediately enters the all-off state. It

remains in this state until the battery voltage is

Rev. 0.A

www.clare.com

10

CPC7584

and 425 mA, and the circuitry has a negative tempera-

ture coefficient. As a result, if the device is subjected

to extended heating due to power cross fault, the mea-

to the specifications of external secondary protectors,

fused resistors and PTCs.

sured current at pin 2 (T ) and pin 15 (R ) will

BAT

3.9 Data Latch

The CPC7584 has an integrated data latch. The latch

operation is controlled by logic-level input pin 11

decrease as the device temperature increases. If the

device temperature rises sufficiently, the temperature

shutdown mechanism will activate and the device will

default to the all-off state.

(LATCH). The data input of the latch is pin 10 (IN

)

RING

and pin 9 (IN

) of the device while the output of

TEST-IN

the data latch is an internal node used for state con-

trol. When LATCH control pin is at logic 0, the data

latch is transparent and data control signals flow

3.7 Temperature Shutdown

The thermal shutdown mechanism will activate when

the device temperature reaches a minimum of 110° C,

placing the device in the all-off state regardless of

logic input. During thermal shutdown mode, pin 7

directly through to state control. A change in input will

be reflected in a change is switch state. When LATCH

control pin is at logic 1, the data latch is active and a

change in input control will not affect switch state. The

switches will remain in the position they were in when

the LATCH changed from logic 0 to logic 1 and will not

respond to changes in input as long as the latch is at

logic 1. The TSD input is not tied to the data latch.

Therefore, TSD is not affected by the LATCH input

and the TSD input will override state control via pin 10

(TSD) will read 0 V. Normal output of TSD is +V

.

DD

If presented with a short duration transient such as a

lightning event, the thermal shutdown feature will typi-

cally not activate. But in an extended power-cross

transient, the device temperature will rise and the ther-

mal shutdown will activate forcing the switches to the

all-off state. At this point the current measured at pin 3

(IN

) and pin 9 (IN

) and the LATCH.

RING

TEST-IN

(T ) and pin 14 (R ) will drop to zero. Once the

BAT

device enters thermal shutdown it will remain in the

all-off state until the temperature of the device drops

below the activation level of the thermal shutdown cir-

cuit. This will return the device to the state prior to

thermal shutdown. If the transient has not passed, cur-

rent will flow at the value allowed by the dynamic DC

current limiting of the switches and heating will begin

again, reactivating the thermal shutdown mechanism.

This cycle of entering and exiting the thermal shut-

down mode will continue as long as the fault condition

persists. If the magnitude of the fault condition is great

enough, the external secondary protector could acti-

vate and shunt all current to ground.

The thermal shutdown mechanism of the CPC7584

can be disable by applying +V to pin 7 (TSD).

DD

3.8 External Protection Elements

The CPC7584 requires only one overvoltage second-

ary protector on the loop side of the device. The inte-

grated protection feature described above negates the

need for protection on the line side. The secondary

protector limits voltage transients to levels that do not

exceed the breakdown voltage or input-output isola-

tion barrier of the CPC7584. A foldback or crowbar

type protector is recommended to minimize stresses

on the device.

Consult Clare’s application note, AN-100, “Designing

Surge and Power Fault Protection Circuits for Solid

State Subscriber Line Interfaces” for equations related

11

www.clare.com

Rev. 0.A

CPC7584

4. Manufacturing Information

4.1 Mechanical Dimensions

4.1.1 SOIC

16 Pin SOIC (JEDEC Package)

10.11 MIN / 10.31 MAX

(.398 MIN / .406 MAX)

1.27

(.050)

0.23 MIN / 0.32 MAX

(.0091 MIN / .0125 MAX)

2.44 MIN / 2.64 MAX

(.096 MIN / .104 MAX)

10.11 MIN / 10.51 MAX

(.398 MIN / .414 MAX)

7.40 MIN / 7.60 MAX

(.291 MIN / .299 MAX)

0.51 MIN / 1.01 MAX

(.020 MIN / .040 MAX)

0.36 MIN / 0.46 MAX

(.014 MIN / .018 MAX)

4.1.2 MLP

7

6

INDEX AREA

TOP VIEW

0.2

0.80

(±0.10)

SEATING

PLANE

SIDE VIEW

0.02

(+0.05, -0)

0.33

(+0.07, -0.05)

1

2

EXPOSED PAD

0.55

4.0

(±0.05)

0.55

(±0.1)

16

6.0

(±0.05)

Terminal Tip

0.80

BOTTOM VIEW

Dimensions in mm

Rev. 0.A

www.clare.com

12

CPC7584

4.2 Printed-Circuit Board Layout

4.2.2 MLP

5.75

0.75 on center

4.2.1 SOIC

0.65

PC Board Pattern

(Top View)

0.38

1.270

(.050)

5.35 on center

6.1

Detail A

9.728 ± .051

(.383 ± .002)

1.193

(.047)

6.13

Detail A

0.65

.787

(.031)

All dimensions in mm

Not drawn to scale

0.66

0.47

0.38

4.3 Tape and Reel Packaging

4.3.1 SOIC

A0

6.50

3.00

R = .50

2.00

2.30

K1

K0

B0

6.80

2.70

1.30

16.00

7.50

12.00

4.00

2.00

1.50

NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA

STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS

LISTED ON PAGE 5 OF EIA-481-2.

A0 =

B0 =

K0 =

K1 =

6.5 mm

10.3 mm

2.3 mm

2.7 mm

4.4 Soldering

4.4.1 Moisture Reflow Sensitivity

Clare has characterized the moisture reflow sensitivity

of LCAS products using IPC/JEDEC standard J-STD-

020A. Moisture uptake from atmospheric humidity

occurs by diffusion. During the solder reflow process,

in which the component is attached to the PCB, the

whole body of the component is exposed to high pro-

cess temperatures. The combination of moisture

uptake and high reflow soldering temperatures may

13

www.clare.com

Rev. 0.A

lead to moisture induced delamination and cracking of

the component. To prevent this, this component must

be handled in accordance with IPC/JEDEC standard

J-STD-020A per the labeled moisture sensitivity level

(MSL), level 1 for the SOIC package, and level 2 for

the MLP package.

4.4.2 Reflow Profile

The maximum ramp rates, dwell times, and tempera-

tures of the assembly reflow profile should not exceed

those specified in IPC/JEDEC standard J-STD-020A,

which were used to determine the moisture sensitivity

level of this component.

4.5 Washing

Clare does not recommend ultrasonic cleaning of

LCAS parts.

For additional information please visit www.clare.com

Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make

changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set

forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its

products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.

The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into

the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a

person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.

Specifications: DS-CPC7584-R0.A

5/6/2002


型号：	CPC7584BA-TR
厂家：	IXYS CORPORATION
描述：	Telecom Circuit, 1-Func, PDSO16, SOIC-16 电信光电二极管电信集成电路
文件：	总15页 (文件大小：401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CPC7584BA-TR [IXYS]

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