PM25LQ512B-SCE_技术文档

Pm25LQ040B

Pm25LQ020B

Pm25LQ010B

Pm25LQ512B

4/2M/1M/512KBIT

3V QUAD SERIAL FLASH MEMORY WITH

MULTI-I/O SPI

DATA SHEET

Pm25LQ040B/020B/010B/512B

4M/2M/1M/512KBIT

3V QUAD SERIAL FLASH MEMORY WITH MULTI-I/O SPI

FEATURES

 Industry Standard Serial Interface

 Low Power with Wide Temp. Ranges

- Single 2.3V to 3.6V Voltage Supply

- 10 mA Active Read Current

- 8 µA Standby Current

- Deep Power Down

- Pm25LQ040B: 4Mbit/512Kbyte

- Pm25LQ020B: 2Mbit/256Kbyte

- Pm25LQ010B: 1Mbit/128Kbyte

- Pm25LQ512B: 512Kbit/64Kbyte

- 256-bytes per Programmable Page Standard

- Standard SPI/Dual/Quad Multi-I/O SPI

- Supports Serial Flash Discoverable Parameters

(SFDP)

- Temp Range:

-40°C to +85°C

 Advanced Security Protection

- Software and Hardware Write Protection

- 4x256-Byte dedicated security area with

user-lockable bits, (OTP) One Time

Programmable Memory

 High Performance Serial Flash (SPI)

- 104 MHz SPI/Dual/Quad Multi-I/O SPI

- 416 MHz equivalent Quad SPI

- 52MB/S Continuous Data Throughput

- Supports SPI Modes 0 and 3

- More than 100,000 erase/program cycles

- More than 20-year data retention

- 128 bit Unique ID for each device

 Industry Standard Pin-out & Pb-Free Packages¹

- S = 8-pin SOIC 150mil

- D = 8-pin TSSOP

 Efficient Read and Program modes

Note1: Pm25LQ040B (not available in D)

- Low Instruction Overhead Operations

- Continuous data read with Byte Wrap around

- Allows XIP operations (execute in place)

- Outperforms X16 Parallel Flash

 Flexible & Cost Efficient Memory Architecture

- Uniform 4 Kbyte Sectors or 32/64 Kbyte Blocks

- Flexible 4, 32, 64 Kbytes, or Chip Erase

- Standard Page Program 1 to 256 bytes

- Program/Erase Suspend and Resume

GENERAL DESCRIPTION

The Pm25LQ040B/020B/010B/512B (4M/2M/1M/512Kbit) Serial Flash memory offers a storage solution with flexibility

and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” is for systems that have

limited space, pins, and power. The device is accessed through a 4-wire SPI Interface consisting of a Serial Data

Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which also serve as multi-

function I/O pins in Dual and Quad modes (see pin descriptions). The Pm25xQ series of Flash is ideal for code

shadowing to RAM, execute in place (XIP) operations, and storing non-volatile data.

The memory array is organized into programmable pages of 256-bytes each. The device supports page program

mode where 1 to 256 bytes of data can be programmed into the memory with one command. Pages can be erased in

groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sectors and blocks

allow greater flexibility for a variety of applications requiring solid data retention.

The device supports the standard Serial Peripheral Interface (SPI), Dual/Quad output (SPI), and Dual/Quad I/O (SPI).

Clock frequencies of up to 104MHz for all read modes allow for equivalent clock rates of up to 416MHz (104MHz x 4)

which equates to 52Mbytes/S of throughput. These transfer rates can outperform 16-bit Parallel Flash memories

allowing for efficient memory access for a XIP (execute in place) operation. The device is manufactured using

industry leading non-volatile memory technology and offered in industry standard lead-free packages. See Ordering

Information for the density and package combinations available.

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TABLE OF CONTENTS

FEATURES..........................................................................................................................................................2

GENERAL DESCRIPTION ..................................................................................................................................2

TABLE OF CONTENTS.......................................................................................................................................3

1. PIN CONFIGURATION ................................................................................................................................5

2. PIN DESCRIPTIONS ...................................................................................................................................6

3. BLOCK DIAGRAM .......................................................................................................................................7

4. SPI MODES DESCRIPTION........................................................................................................................8

5. SYSTEM CONFIGURATION .....................................................................................................................10

5.1 BLOCK/SECTOR ADDRESSES ..........................................................................................................10

6. REGISTERS...............................................................................................................................................12

6.1. STATUS REGISTER ...........................................................................................................................12

6.2. FUNCTION REGISTER.......................................................................................................................15

7. PROTECTION MODE................................................................................................................................16

7.1 HARDWARE WRITE PROTECTION....................................................................................................16

7.2 SOFTWARE WRITE PROTECTION ....................................................................................................16

8. DEVICE OPERATION................................................................................................................................17

8.1 READ DATA OPERATION (RD, 03h) ..................................................................................................18

8.2 FAST READ DATA OPERATION (FR, 0Bh)........................................................................................20

8.3 HOLD OPERATION..............................................................................................................................21

8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ...........................................................................21

8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) ..................................................................24

8.6 FAST READ QUAD OUTPUT (FRQO, 6Bh) ........................................................................................26

8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh) ..........................................................................28

8.8 PAGE PROGRAM OPERATION (PP, 02h)..........................................................................................30

8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) ........................................................31

8.10 ERASE OPERATION .........................................................................................................................32

8.11 SECTOR ERASE OPERATION (SER, D7h/20h) ...............................................................................32

8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................33

8.13 CHIP ERASE OPERATION (CER, C7h/60h) .....................................................................................34

8.14 WRITE ENABLE OPERATION (WREN, 06h) ....................................................................................35

8.15 WRITE DISABLE OPERATION (WRDI, 04h).....................................................................................35

8.16 READ STATUS REGISTER OPERATION (RDSR, 05h) ...................................................................36

8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h).................................................................36

8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h)...............................................................37

8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h).............................................................37

8.20 PROGRAM/ERASE SUSPEND & RESUME......................................................................................38

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8.21 DEEP POWER DOWN (DP, B9h) ......................................................................................................40

8.22 RELEASE DEEP POWER DOWN (RDPD, ABh)...............................................................................41

8.23 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................42

8.24 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh)...........................44

8.25 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ........................45

8.26 READ UNIQUE ID NUMBER (RDUID, 4Bh) ......................................................................................46

8.27 READ SFDP OPERATION (RDSFDP, 5Ah) ......................................................................................47

8.28 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h) ............................48

8.29 SECURITY INFORMATION ROW (OTP AREA)................................................................................49

8.30 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) .............................................................49

8.31 INFORMATION ROW READ OPERATION (IRRD, 68h) ...................................................................51

8.32 SECTOR LOCK/UNLOCK FUNCTIONS............................................................................................52

9. ELECTRICAL CHARACTERISTICS..........................................................................................................54

9.1 ABSOLUTE MAXIMUM RATINGS ⁽¹⁾...................................................................................................54

9.2 OPERATING RANGE...........................................................................................................................54

9.3 DC CHARACTERISTICS......................................................................................................................54

9.4 AC MEASUREMENT CONDITIONS ....................................................................................................55

9.5 AC CHARACTERISTICS......................................................................................................................56

9.6 SERIAL INPUT/OUTPUT TIMING........................................................................................................57

9.7 POWER-UP AND POWER-DOWN ......................................................................................................58

9.8 PROGRAM/ERASE PERFORMANCE.................................................................................................59

9.9 RELIABILITY CHARACTERISTICS .....................................................................................................59

10. PACKAGE TYPE INFORMATION .............................................................................................................60

10.1 8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package (S)............................60

10.2 8-Pin TSSOP Package (D) .................................................................................................................61

11. ORDERING INFORMATION......................................................................................................................62

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1. PIN CONFIGURATION

CE#

1

Vcc

8

7

SO (IO1)

2

HOLD# (IO3)

SCK

WP# (IO2)

GND

3

4

6

5

SI (IO0)

8-pin SOIC 150mil (Package: S)

8-pin TSSOP (Package: D)

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2. PIN DESCRIPTIONS

SYMBOL

TYPE

DESCRIPTION

Chip Enable: The Chip Enable (CE#) pin enables and disables the devices

operation. When CE# is high the device is deselected and output pins are in a high

impedance state. When deselected the devices non-critical internal circuitry power

down to allow minimal levels of power consumption while in a standby state.

When CE# is pulled low the device will be selected and brought out of standby

mode. The device is considered active and instructions can be written to, data read,

and written to the device. After power-up, CE# must transition from high to low

before a new instruction will be accepted.

CE#

INPUT

Keeping CE# in a high state deselects the device and switches it into its low power

state. Data will not be accepted when CE# is high.

Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):

This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI

instructions use the unidirectional SI (Serial Input) pin to write instructions,

addresses, or data to the device on the rising edge of the Serial Clock (SCK).

Standard SPI also uses the unidirectional SO (Serial Output) to read data or status

from the device on the falling edge of the serial clock (SCK).

SI (IO0),

SO (IO1)

INPUT/OUTPUT

In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write

instructions, addresses or data to the device on the rising edge of the Serial Clock

(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI

instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.

Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from

being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the

WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) are

write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the

Status Register is not write-protected regardless of WP# state.

WP# (IO2)

INPUT/OUTPUT

When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available

since this pin is used for IO2.

Hold/Serial Data IO (IO3): Pauses serial communication by the master device

without resetting the serial sequence. When the QE bit of Status Register is set to

“1”, HOLD# pin is not available since it becomes IO3.

The HOLD# pin allows the device to be paused while it is selected. The HOLD# pin

HOLD# (IO3)

INPUT/OUTPUT is active low. When HOLD# is in a low state, and CE# is low, the SO pin will be at

high impedance.

Device operation can resume when HOLD# pin is brought to a high state. When the

QE bit of Status Register is set for Quad I/O, the HOLD# pin function is not available

and becomes IO3 for Multi-I/O SPI mode.

Serial Data Clock: Synchronized Clock for input and output timing operations.

SCK

Vcc

INPUT

Power: Device Core Power Supply

POWER

Ground: Connect to ground when referenced to Vcc

GND

NC

GROUND

NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.

Unused

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3. BLOCK DIAGRAM

Control Logic

High Voltage Generator

Status

Register

I/O Buffers and

Data Latches

256 Bytes

Page Buffer

CE#

SCK

WP#

(IO2)

Y-Decoder

SI

(IO0)

SO

(IO1)

HOLD#

(IO3)

Memory Array

Address Latch &

Counter

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4. SPI MODES DESCRIPTION

Multiple devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as

shown in Figure 4.1 the devices support either of two SPI modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the

serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer

to Figure 4.2 for SPI mode. In SPI mode, the input data is latched on the rising edge of Serial Clock (SCK), and

the output data is available from the falling edge of SCK.

Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

SDO

SDI

SPI interface with

(0,0) or (1,1)

SCK

SCK SO SI

SPI Master

(i.e. Microcontroller)

SPI

Memory

Device

Memory

Device

Memory

Device

CS3

CS2

CS1

CE#

HOLD#

WP#

WP# HOLD#

Notes:

1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as necessary.

2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively

during Multi-IO mode.

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Figure 4.2 SPI Mode Support

SCK

Mode 0 (0,0)

SCK

Mode 3 (1,1)

MSB

SI

Input

mode

SO

MSB

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5. SYSTEM CONFIGURATION

The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI)

microcontrollers or any SPI interface-equipped system controllers.

The memory array of Pm25LQ512B is divided into uniform 4 Kbyte sectors or uniform 32 Kbyte blocks (a block

consists of eight adjacent sectors). The memory array of Pm25LQ040/020/010B is divided into uniform 4 Kbyte

sectors or uniform 32/64 Kbyte blocks (a block consists of eight/sixteen adjacent sectors respectively).

Table 5.1 and Table 5.2 illustrate the memory map of the device. The Status Register controls how the memory

is protected.

5.1 BLOCK/SECTOR ADDRESSES

Table 5.1 Block/Sector Addresses of Pm25LQ512B

Memory

Density

Block No.

(32Kbyte)

Sector Size

(Kbyte)

Sector No.

Address Range

Sector 0

Sector 1

:

4

:

000000h - 000FFFh

001000h - 001FFFh

:

Block 0

Block 1

Sector 7

Sector 8

Sector 9

:

4

:

007000h - 007FFFh

008000h - 008FFFh

009000h - 009FFFh

:

512Kb

Sector 15

4

00F000h - 00FFFFh

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Table 5.2 Block/Sector Addresses of Pm25LQ010/020/040B

Block No.

(64Kbyte)

Block No.

(32Kbyte)

Sector Size

(Kbyte)

Memory Density

Sector No.

Address Range

Block 0

Sector 0

4

:

000000h - 000FFFh

:

Block 0

Block 1

Block 2

Block 3

Block 4

Block 5

Block 6

Block 7

:

Block 1

Block 2

Block 3

Block 4

Block 5

Block 6

Block 7

Block 8

Block 9

Block 10

Block 11

Block 12

Block 13

Block 14

Block 15

Sector 15

4

:

00F000h - 00FFFFh

1 Mb

Sector 16

010000h - 010FFFh

:

Sector 31

4

:

01F000h - 01FFFFh

2 Mb

Sector 32

020000h - 020FFFh

:

Sector 47

4

:

02F000h - 02FFFFh

Sector 48

030000h - 030FFFh

:

Sector 63

4

:

03F000h - 03FFFFh

4 Mb

Sector 64

040000h - 040FFFh

:

Sector 79

4

:

04F000h - 04FFFFh

Sector 80

050000h - 050FFFh

:

Sector 95

4

:

05F000h - 05FFFFh

Sector 96

060000h - 060FFFh

:

Sector 111

4

:

06F000h - 06FFFFh

Sector 112

070000h - 070FFFh

:

Sector 127

4

07F000h - 07FFFFh

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6. REGISTERS

The device has two sets of Registers: Status, Function.

6.1. STATUS REGISTER

Status Register Format and Status Register Bit Definitions are described in Tables 6.1 & 6.2.

Table 6.1 Status Register Format

Bit 7

SRWD

0

Bit 6

QE

0

Bit 5

BP3

0

Bit 4

BP2

0

Bit 3

BP1

0

Bit 2

BP0

0

Bit 1

WEL

0

Bit 0

WIP

0

Default

Table 6.2 Status Register Bit Definition

Read-

/Write

Bit

Name

Definition

Type

Write In Progress Bit:

"0" indicates the device is ready (default)

"1" indicates a write cycle is in progress and the device is busy

Write Enable Latch:

"0" indicates the device is not write enabled (default)

"1" indicates the device is write enabled

Bit 0

WIP

R

Volatile

Bit 1

WEL

R/W¹

Bit 2

Bit 3

Bit 4

Bit 5

BP0

BP1

BP2

BP3

Block Protection Bit: (See Tables 6.4 for details)

"0" indicates the specific blocks are not write-protected (default)

"1" indicates the specific blocks are write-protected

R/W

Non-Volatile

Quad Enable bit:

Bit 6

Bit 7

QE

“0” indicates the Quad output function disable (default)

“1” indicates the Quad output function enable

Status Register Write Disable: (See Table 7.1 for details)

"0" indicates the Status Register is not write-protected (default)

"1" indicates the Status Register is write-protected

R/W

Non-Volatile

SRWD

Note1: WEL bit can be written by WREN and WRDI commands, but cannot by WRSR command.

The BP0, BP1, BP2, BP3, QE, and SRWD are non-volatile memory cells that can be written by a Write Status

Register (WRSR) instruction. The default value of the BP0, BP1, BP2, BP3, QE, and SRWD bits were set to “0”

at factory. The Status Register can be read by the Read Status Register (RDSR).

The function of Status Register bits are described as follows:

WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a

program or erase operation. When the WIP bit is “0”, the device is ready for write Status or Function Register,

program or erase operation. When the WIP bit is “1”, the device is busy.

WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the

WEL is “0”, the write enable latch is disabled and all write operations described in Table 6.3 are inhibited. When

the WEL bit is “1”, write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each

write register, program and erase instruction must be preceded by a WREN instruction. The WEL bit can be

reset by a Write Disable (WRDI) instruction. It will automatically be reset after the completion of any write

operation.

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Table 6.3 Instructions requiring WREN instruction ahead

Instructions must be preceded by the WREN instruction

Operation

Name

Hex Code

02h

PP

Serial Input Page Program

Quad Input Page Program

Sector Erase 4KB

PPQ

32h/38h

D7h/20h

52h

SER

BER32 (32Kbyte)

BER64 (64Kbyte)

BER32 (32Kbyte)

BER64 (64Kbyte)

CER

Block Erase 32KB

Pm25LQ040/020/010B

D8h

Block Erase 64KB

52h/D8h

NA

Block Erase 32KB

Pm25LQ512B

Block Erase 64KB

C7h/60h

01h

Chip Erase

WRSR

Write Status Register

Write Function Register

Program Information Row

WRFR

42h

IRP

62h

BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of

the memory area to be protected. Refer to Tables 6.4 for the Block Write Protection (BP) bit settings. When a

defined combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any

program or erase operation to that area will be inhibited.

Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.

SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection

(WP#) signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not

write-protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register

(SRWD, QE, BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is

set to “1” and WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.

QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the

QE bit is set to “0”, the pin WP# and HOLD# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins

are enabled.

WARNING: The QE bit must be set to 0 if WP# or HOLD# pin is tied directly to the power supply.

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Table 6.4 Block (64Kbyte) assignment by Block Write Protect (BP) Bits.

Status Register Bits Protected Memory Area

BP3

0

BP2

0

BP1

0

BP0

0

4Mb

2Mb

None

1Mb

None

512Kb

None

0

1

1 block : 7

2 blocks : 6 - 7

4 blocks : 4 - 7

1 block : 3

2 blocks : 2 - 3

1 block : 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

All Blocks

1

0

1

0

1

0

1

0

1

0

1

0

4 blocks 0 - 3

2 blocks : 0 - 1

1 block : 0

None

1

0

1

2 blocks : 0 - 1

1 block : 0

None

1

0

1 block : 0

None

1

None

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6.2. FUNCTION REGISTER

Function Register Format and Bit definition are described in Table 6.5 and 6.6.

Table 6.5 Function Register Format

Bit 7

IRL3

0

Bit 6

IRL2

0

Bit 5

IRL1

0

Bit 4

IRL0

0

Bit 3

ESUS

0

Bit 2

PSUS

0

Bit 1

Bit 0

Reserved Reserved

Default

0

Table 6.6 Function Register Bit Definition

Read-

/Write

Bit

Name

Definition

Type

Bit 0

Bit 1

Reserved Reserved

R

Reserved

Program suspend bit:

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

PSUS

ESUS

“0” indicates program is not suspend

“1” indicates program is suspend

Erase suspend bit:

"0" indicates Erase is not suspend

"1" indicates Erase is suspend

Lock the Information Row 0:

R

Volatile

R

Volatile

IR Lock 0 “0” indicates the Information Row can be programmed

“1” indicates the Information Row cannot be programmed

Lock the Information Row 1:

IR Lock 1 “0” indicates the Information Row can be programmed

“1” indicates the Information Row cannot be programmed

Lock the Information Row 2:

IR Lock 2 “0” indicates the Information Row can be programmed

“1” indicates the Information Row cannot be programmed

Lock the Information Row 3:

IR Lock 3 “0” indicates the Information Row can be programmed

“1” indicates the Information Row cannot be programmed

R/W

Non-Volatile

Note: Function Register bits are only One Time Programmable (OTP) and cannot be modified.

PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The

PSUS changes to “1” after a suspend command is issued during the program operation. Once the suspended

Program resumes, the PSUS bit is reset to “0”.

ESUS bit: The Erase Suspend Status indicates when an Erase operation has been suspended. The ESUS bit is

“1” after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the

ESUS bit is reset to “0”.

IR Lock bit 0 ~ 3: The Information Row Lock bits are programmable. If the bit set to “1”, the Information Row

can’t be programmed.

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7. PROTECTION MODE

The device supports hardware and software write-protection mechanisms.

7.1 HARDWARE WRITE PROTECTION

The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0 and

SRWD in the Status Register. Refer to the section 6.1 STATUS REGISTER.

Write inhibit voltage (V_WI) is specified in the section 9.7 POWER-UP AND POWER-DOWN. All write sequence

will be ignored when Vcc drops to V_WI.

Table 7.1 Hardware Write Protection on Status Register

SRWD

WP#

Low

High

Status Register

Writable

0

1

0

1

Protected

Writable

Note: Before the execution of any program, erase or write Status/Function Register instruction, the Write Enable

Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not

enabled, the program, erase or write register instruction will be ignored.

7.2 SOFTWARE WRITE PROTECTION

The device also provides a software write protection feature. The Block Protection (BP3, BP2, BP1, and BP0)

bits allow part or the whole memory area to be write-protected.

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8. DEVICE OPERATION

The device utilizes an 8-bit instruction register. Refer to Table 8.1. Instruction Set for details on Instructions and

Instruction Codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on

Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is latched on the rising

edge of Serial Clock (SCK) after Chip Enable (CE#) is driven low (V_IL). Every instruction sequence starts with a

one-byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes,

depending on the type of instruction. CE# must be driven high (V_IH) after the last bit of the instruction sequence

has been shifted in to end the operation.

Table 8.1 Instruction Set

Instruction Name Hex Code Operation

Maximum

Frequency

Mode

RD

03h

Read Data Bytes from Memory at Normal Read Mode

Read Data Bytes from Memory at Fast Read Mode

Fast Read Dual I/O

SPI

33MHz

FR

0Bh

104MHz

FRDIO

BBh

FRDO

3Bh

Fast Read Dual Output

FRQIO

EBh

Fast Read Quad I/O

FRQO

6Bh

Fast Read Quad Output

PP

02h

Page Program Data Bytes into Memory

Page Program Data Bytes into Memory with Quad Interface

Sector Erase 4KB

PPQ

32h/38h

D7h/20h

52h

SER

BER32 (32Kbyte)

BER64 (64Kbyte)

BER32 (32Kbyte)

BER64 (64Kbyte)

CER

Block Erase 32KB

Pm25LQ040B/020B/010B

Block Erase 64KB

D8h

52h/D8h

NA

Block Erase 32KB

Pm25LQ512B

Block Erase 64KB

C7h/60h

06h

Chip Erase

WREN

Write Enable

WRDI

04h

Write Disable

RDSR

05h

Read Status Register

WRSR

01h

Write Status Register

RDFR

48h

Read Function Register

Write Function Register

Suspend during the Program/Erase

Resume Program/Erase

Deep Power Down Mode

Read Manufacturer and Product ID/Release Deep Power Down

Read Unique ID Number

Read Manufacturer and Product ID by JEDEC ID Command

Read Manufacturer and Device ID

SFDP Read

WRFR

42h

PERSUS

PERRSM

DP

75h/B0h

7Ah/30h

B9h

RDID, RDPD

RDUID

ABh

4Bh

RDJDID

RDMDID

RDSFDP

RSTEN

RST

9Fh

90h

5Ah

66h

Software Reset Enable

99h

Reset

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Maximum

Mode

Instruction Name Hex Code Operation

Frequency

IRP

62h

68h

26h

24h

Program Information Row

Read Information Row

Sector Unlock

SPI

104MHz

IRRD

SECUNLOCK

SECLOCK

Sector Lock

8.1 READ DATA OPERATION (RD, 03h)

The Read Data (RD) instruction is used to read memory contents of the device at a maximum frequency of

33MHz.

The RD instruction code is transmitted via the Sl line, followed by three address bytes (A23 - A0) of the first

memory location to be read. A total of 24 address bits are shifted in, but only AMSB (Most Significant Bit) - A₀are

decoded. The remaining bits (A23 – AMSB+1) are ignored. The first byte address can be at any memory location.

Upon completion, any data on the Sl will be ignored. Refer to Table 8.2 for the related Address Key.

The first byte data (D7 - D0) address is shifted out on the SO line, MSB first. A single byte of data, or up to the

whole memory array, can be read out in one READ instruction. The address is automatically incremented after

each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH)

after the data comes out. When the highest address of the device is reached, the address counter will roll over

to the 000000h address, allowing the entire memory to be read in one continuous READ instruction.

If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction

is ignored and will not have any effects on the current cycle.

Table 8.2 Address Key

Address

Pm25LQ040B

Pm25LQ020B

Pm25LQ010B

Pm25LQ512B

A18-A0

(A23-A19=X)

A17-A0

(A23-A18=X)

A16-A0

(A23-A17=X)

A15-A0

(A23-A16=X)

A_MSB–A₀

Note: X=Don’t Care

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Figure 8.1 Read Data Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

SI

3-byte Address

...

3

Instruction = 03h

2

1

0

23

22

High Impedance

SO

CE#

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

SCK

SI

Data Out 1

Data Out 2

SO

1

0

1

0

3

6

5

4

3

2

7

6

5

4

2

7

t_V

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8.2 FAST READ DATA OPERATION (FR, 0Bh)

The Fast Read instruction is used to read memory data at up to a 104MHZ clock.

The Fast Read instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks),

transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte from

the address is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling

edge of SCK.

The first byte addressed can be at any memory location. The address is automatically incremented after each

byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single Fast Read instruction. The Fast Read

instruction is terminated by driving CE# high (VIH).

If a Fast Read instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction

is ignored and will not have any effects on the current cycle.

Figure 8.2 Fast Read Data Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

SI

3-byte Address

...

3

Instruction = 0Bh

2

1

0

23

22

High Impedance

SO

CE#

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

SCK

SI

Dummy Byte

Data Out

t_V

SO

...

1

0

3

7

6

5

4

2

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8.3 HOLD OPERATION

HOLD# is used in conjunction with CE# to select the device. When the device is selected and a serial sequence

is underway, HOLD# can be used to pause the serial communication with the master device without resetting

the serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial

communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs

to SI will be ignored while SO is in the high impedance state, during HOLD.

Timing graph can be referenced in AC Parameters Figure 9.3.

8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh)

The FRDIO instruction allows the address bits to be input two bits at a time. This may allow for code to be

executed directly from the SPI in some applications.

The FRDIO instruction code is followed by three address bytes (A23 – A0) and a mode byte, transmitted via the

IO1 and IO0 lines, with each pair of bits latched-in during the rising edge of SCK. The address MSB is input on

IO1, the next bit on IO0, and continue to shift in alternating on the two lines. If AXh (where X is don’t care) is

input for the mode byte, the device will enter AX read mode. In the AX read mode, the next instruction expected

from the device will be another FRDIO instruction and will not need the BBh instruction code so that it saves

cycles as described in Figure 8.4. If the following mode byte is not set to AXh, the device will exit AX read mode.

To avoid any I/O contention problem, X should be Hi-Z.

Once address and mode byte are input the device will read out data at the specified address. The first data byte

addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency fCT,

during the falling edge of SCK. The first bit (MSB) is output on IO1, while simultaneously the second bit is output

on IO0. Figure 8.3 illustrates the timing sequence.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is

terminated by driving CE# high (VIH).

If a FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is

ignored and will not have any effects on the current cycle.

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Figure 8.3 Fast Read Dual I/O Sequence (with command decode cycles)

CE#

0

1

2

3

4

5

6

7

8

9

10

...

18

19

20

21

Mode 3

Mode 0

SCK

Mode Bits

4

3-byte Address

...

IO0

IO1

2

3

Instruction = BBh

0

1

6

7

22

23

20

21

18

High Impedance

...

5

19

CE#

SCK

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

t_V

...

IO0

IO1

2

3

0

1

0

1

0

1

2

6

7

6

7

6

7

4

2

0

1

4

Data Out 1

Data Out 2

Data Out 3

...

3

5

3

5

3

Notes:

1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). Anything but

AXh in the mode byte cycle will keep the same sequence.

2. To avoid I/O contention, X should be Hi-Z.

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Figure 8.4 Fast Read Dual I/O Sequence (without command decode cycles)

CE#

...

0

1

2

3

11

12

13

14

15

16

17

18

19

20

21

22

Mode 3

Mode 0

SCK

Mode Bits

t_V

3-byte Address

Data Out 1

Data Out 2

4

...

IO0

IO1

2

3

6

7

2

3

6

7

2

0

1

4

5

0

1

4

0

1

6

7

22

23

20

21

18

...

3

5

19

Notes:

1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When

the mode bits are different from AXh, the device will exit the AX read operation.

2. To avoid I/O contention, X should be Hi-Z.

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8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)

The FRDO instruction is used to read memory data on two output pins each at up to a 104MHZ clock.

The FRDO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks),

transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the first data byte

addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency fCT,

during the falling edge of SCK. The first bit (MSB) is output on IO1. Simultaneously the second bit is output on

IO0.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDO instruction. FRDO instruction is

terminated by driving CE# high (VIH).

If a FRDO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is

ignored and will not have any effects on the current cycle.

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Figure 8.5 Fast Read Dual-Output Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

11

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

3

IO0

IO1

Instruction = 3Bh

2

1

0

23

22

High Impedance

CE#

SCK

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

t_V

IO0

IO1

0

1

...

2

6

7

4

6

7

4

2

0

1

8 Dummy Cycles

Data Out 1

Data Out 2

3

5

3

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8.6 FAST READ QUAD OUTPUT (FRQO, 6Bh)

The FRQO instruction is used to read memory data on four output pins each at up to a 104 MHz clock.

The FRQO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks),

transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the first data byte

addressed is shifted out on the IO3, IO2, IO1, and IO0 lines, with each group of four bits shifted out at a

maximum frequency f_CT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while

simultaneously the second bit is output on IO2, the third bit is output on IO1, etc.

The first byte addressed can be at any memory location. The address is automatically incremented after each

byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is

terminated by driving CE# high (VIH).

If a FRQO instruction is issued while an Erase, Program or Wri

ignored and will not have any effects on the current cycle.

te cycle is in process (WIP=1) the instruction is

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Figure 8.6 Fast Read Quad-Output Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

11

28

29

30

31

Mode 3

Mode 0

SCK

IO0

3-byte Address

...

3

Instruction = 6Bh

2

1

0

23

22

High Impedance

IO1

IO2

IO3

High Impedance

CE#

SCK

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

t_V

...

IO0

IO1

IO2

IO3

0

4

0

4

0

4

0

8 Dummy Cycles

Data Out 1 Data Out 2 Data Out 3 Data Out 4

1

...

5

1

5

1

5

1

2

6

2

6

2

6

2

3

...

7

3

7

3

7

3

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8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh)

The FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to be

executed directly from the SPI in some applications.

The FRQIO instruction code is followed by three address bytes (A23 – A0), a mode byte, and 4 dummy cycles,

transmitted via the IO3, IO2, IO0 and IO1 lines, with each group of four bits latched-in during the rising edge of

SCK. The address of MSB inputs on IO3, the next bit on IO2, the next bit on IO1, the next bit on IO0, and

continue to shift in alternating on the four. The mode byte contains the value AXh (where X is don’t care). After

four dummy clocks, the first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each

group of four bits shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is

output on IO3, while simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.7

illustrates the timing sequence.

If the mode byte is AXh, the AX read mode is enabled. In the mode, the device expects that the next operation

will be another FRQIO and subsequent FRQIO execution skips command code. It saves command cycles as

described in Figure 8.8. The device will remain in this mode until the mode byte is different from AXh.

The first byte addressed can be at any memory location. The address is automatically incremented after each

byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is

terminated by driving CE# high (VIH).

If a FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is

ignored and will not have any effects on the current cycle.

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Figure 8.7 Fast Read Quad I/O Sequence (with command decode cycles)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

3-byte Address

Mode Bits

IO0

IO1

4

5

6

7

Instruction = EBh

High Impedance

0

1

2

3

4

5

6

7

0

1

2

3

20

21

22

23

16

17

18

19

12

13

14

15

8

9

IO2

10

11

IO3

CE#

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

SCK

4 Dummy Cycles

Data Out 1 Data Out 2 Data Out 3 Data Out 4

Data Out 5 Data Out 6

t_V

IO0

IO1

0

1

2

3

0

1

2

3

...

4

5

6

7

4

5

6

7

4

5

6

7

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

0

1

2

3

4

5

6

7

0

1

2

3

IO2

IO3

Note: If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). Anything

but AXh in the mode byte cycle will keep the same sequence.

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8.8 PAGE PROGRAM OPERATION (PP, 02h)

The Page Program (PP) instruction allows up to 256 bytes data to be programmed into memory in a single

operation. The destination of the memory to be programmed must be outside the protected memory area set by

the Block Protection (BP2, BP1, BP0) bits. The PP instruction which attempts to program into a page that is

write-protected will be ignored. Before the execution of PP instruction, the Write Enable Latch (WEL) must be

enabled through a Write Enable (WREN) instruction.

The PP instruction code, three address bytes and program data (1 to 256 bytes) are input via the SI line.

Program operation will start immediately after the CE# is brought high, otherwise the PP instruction will not be

executed. The internal control logic automatically handles the programming voltages and timing. During a

program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of

the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If

the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has

completed.

If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the

previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. The

starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap

around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all

other bytes on the same page will remain unchanged.

Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.

A byte cannot be reprogrammed without first erasing the whole sector or block.

Figure 8.8 Page Program Sequence

CE#

0

1

...

7

8

9

...

31

32

33

...

39

...

Mode 3

Mode 0

SCK

3-byte Address

Data In 1

Data In 256

...

SI

...

6

0

7

0

Instruction = 02h

7

23

22

High Impedance

SO

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8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h)

The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a

single operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must

be outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input

Page Program instruction which attempts to program into a page that is write-protected will be ignored. Before

the execution of Quad Input Page Program instruction, the QE bit in the Status Register must be set to “1” and

the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.

The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are

input via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought

high, otherwise the Quad Input Page Program instruction will not be executed. The internal control logic

automatically handles the programming voltages and timing. During a program operation, all instructions will be

ignored except the RDSR instruction. The progress or completion of the program operation can be determined

by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is

still in progress. If WIP bit is “0”, the program operation has completed.

If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the

previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page.

The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap

around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all

other bytes on the same page will remain unchanged.

Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.

A byte cannot be reprogrammed without first erasing the whole sector or block.

Figure 8.9 Quad Input Page Program Operation

CE#

0

1

2

3

4

5

6

7

8

9

...

31

32

33

34

35

Mode 3

Mode 0

SCK

3-byte Address

Data In 1

Data In 2

...

IO0

IO1

...

4

5

6

7

Instruction = 32h/38h

High Impedance

0

1

2

3

4

5

6

7

0

1

2

3

23

22

0

IO2

IO3

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8.10 ERASE OPERATION

The memory array of the Pm25LQ512B is organized into uniform 4Kbyte sectors or 32Kbyte uniform blocks (a

block consists of eight adjacent sectors). The memory array of the Pm25LQ010/020/040B is organized into

uniform 4Kbyte sectors or 32/64Kbyte uniform blocks (a block consists of eight/sixteen adjacent sectors

respectively).

Before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to

“1”). In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase

(BER) and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without

affecting the data in other sectors. A block erase operation erases any individual block. A chip erase operation

erases the whole memory array of a device. A sector erase, block erase or chip erase operation can be

executed prior to any programming operation.

8.11 SECTOR ERASE OPERATION (SER, D7h/20h)

A Sector Erase (SER) instruction erases a 4Kbyte sector. Before the execution of a SER instruction, the Write

Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is reset automatically after

the completion of Sector Erase operation.

A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire

instruction sequence. The SER instruction code, and three address bytes are input via SI. Erase operation will

start immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and

timing.

During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction.

The progress or completion of the erase operation can be determined by reading the WIP bit in the Status

Register using a RDSR instruction.

If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been

completed.

Figure 8.10 Sector Erase Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

SI

3

Instruction = D7h/20h

High Impedance

2

1

0

23

22

SO

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8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h)

A Block Erase (BER) instruction erases a 32/64Kbyte block. Before the execution of a BER instruction, the Write

Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after

the completion of a block erase operation.

The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after

the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic

automatically handles the erase voltage and timing.

Figure 8.11 Block Erase (64K) Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

SI

3

Instruction = D8h

2

1

0

23

22

High Impedance

SO

Figure 8.12 Block Erase (32K) Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

SI

3

Instruction = 52h

2

1

0

23

22

High Impedance

SO

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8.13 CHIP ERASE OPERATION (CER, C7h/60h)

A Chip Erase (CER) instruction erases the entire memory array. Before the execution of CER instruction, the

Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically

after completion of a chip erase operation.

The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,

otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase

voltage and timing.

Figure 8.13 Chip Erase Sequence

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

Instruction = C7h/60h

High Impedance

SI

SO

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8.14 WRITE ENABLE OPERATION (WREN, 06h)

The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit is reset to

the write-protected state after power-up. The WEL bit must be write enabled before any write operation,

including Sector Erase, Block Erase, Chip Erase, Page Program, Write Status Register, and Write Function

Register operations. The WEL bit will be reset to the write-protected state automatically upon completion of a

write operation. The WREN instruction is required before any above operation is executed.

Figure 8.14 Write Enable Sequence

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

Address

Instruction = 06h

High Impedance

SI

SO

8.15 WRITE DISABLE OPERATION (WRDI, 04h)

The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI

instruction is not required after the execution of a write instruction, since the WEL bit is automatically reset.

Figure 8.15 Write Disable Sequence

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

Instruction = 04h

SI

High Impedance

SO

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8.16 READ STATUS REGISTER OPERATION (RDSR, 05h)

The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a

program, erase or write Status Register operation, all other instructions will be ignored except the RDSR

instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of

Status Register.

Figure 8.16 Read Status Register Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

SI

Instruction = 05h

t_V

Data Out

SO

3

2

1

0

7

6

5

4

8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h)

The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and

Status Register write protection features by writing “0”s or “1”s into the non-volatile BP3, BP2, BP1, BP0, and

SRWD bits. Also WRSR instruction allows the user to disable or enable quad operation by writing “0” or “1” into

the non-volatile QE bit.

Figure 8.17 Write Status Register Sequence

CE#

0

1

2

3

4

5

6

7

8

7

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

Data In

SI

Instruction = 01h

2

1

0

3

6

5

4

High Impedence

SO

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8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h)

The Read Function Register (RDFR) instruction provides access to the Function Register. Refer to Table 6.6

Function Register Bit Definition for more detail.

Figure 8.18 Read Function Register Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

SI

Instruction = 48h

t_V

Data Out

SO

3

2

1

0

7

6

5

4

8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)

The Write Function Register (WRFR) instruction allows the user to lock the Information Row by bit 0. (IR Lock)

Figure 8.19 Write Function Register Sequence

CE#

0

1

2

3

4

5

6

7

8

7

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

Data In

SI

Instruction = 42h

2

1

0

3

6

5

4

High Impedence

SO

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8.20 PROGRAM/ERASE SUSPEND & RESUME

The device allows the interruption of Sector-Erase, Block-Erase or Page-Program operations to conduct other

operations. 75h/B0h command for suspend and 7Ah/30h for resume will be used. Function Register bit2 (PSUS)

and bit3 (ESUS) are used to check whether or not the device is in suspend mode.

Suspend to read ready timing: 100µs.

Resume to another suspend timing: 400µs (recommendation).

PROGRAM/ERASE SUSPEND DURING SECTOR-ERASE OR BLOCK-Erase (PERSUS 75h/B0h)

The Program/Erase Suspend allows the interruption of Sector Erase and Block Erase operations. After the

Program/Erase Suspend, WEL bit will be disabled, therefore only read related, resume and reset commands

can be accepted (Refer to Table 8.3 for more detail).

To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend

command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the erase has been

suspended by changing the ESUS bit from “0” to “1”, but the device will not accept another command until it is

ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or wait

the specified time t_SUS. When ESUS bit is issued, the Write Enable Latch (WEL) bit will be reset.

PROGRAM/ERASE SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)

The Program/Erase Suspend allows the interruption of all program operations. After the Program/Erase

Suspend command, WEL bit will be disabled, therefore only read related, resume and reset commands can be

accepted (Refer to Table 8.3 for more detail).

To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend

command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the programming has

been suspended by changing the PSUS bit from “0” to “1”, but the device will not accept another command until

it is ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or

wait the specified time t_SUS

.

PROGRAM/ERASE RESUME (PERRSM 7Ah/30h)

The Program/Erase Resume restarts a Program or Erase command that was suspended, and changes the

suspend status bit in the Function Register (ESUS or PSUS bits) back to “0”. To execute the Program/Erase

Resume operation, the host drives CE# low, sends the Program/Erase Resume command cycle (7Ah/30h), then

drives CE# high. A cycle is two nibbles long, most significant nibble first. To determine if the internal, self-timed

Write operation completed, poll the WIP bit in the Status Register, or wait the specified time t_SE, t_BEor t_PPfor

Sector Erase, Block Erase, or Page Programming, respectively. The total write time before suspend and after

resume will not exceed the uninterrupted write times t_SE, t_BEor t_PP.

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Table 8.3 Instructions accepted during Suspend

Operation

Instruction Allowed

Suspended

Name

RD

Hex Code

03h

Operation

Read Data Bytes from Memory at Normal Read Mode

Read Data Bytes from Memory at Fast Read Mode

Fast Read Dual I/O

Program or Erase

FR

0Bh

FRDIO

FRDO

FRQIO

FRQO

RDSR

RDFR

PERRSM

RDID

BBh

3Bh

Fast Read Dual Output

EBh

6Bh

Fast Read Quad I/O

Fast Read Quad Output

05h

Read Status Register

48h

Read Function Register

7Ah/30h

ABh

4Bh

Resume program/erase

Read Manufacturer and Product ID

Read Unique ID Number

RDUID

RDJDID

RDMDID

RDSFDP

RSTEN

RST

9Fh

Read Manufacturer and Product ID by JEDEC ID Command

Read Manufacturer and Device ID

SFDP Read

90h

5Ah

66h

Software reset enable

99h

Reset (Only along with 66h)

Read Information Row

IRRD

68h

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8.21 DEEP POWER DOWN (DP, B9h)

The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (enter

into Power-down mode), and the standby current is reduced from I_sb1to I_sb2. During the Power-down mode, the

device is not active and all Write/Program/Erase instructions are ignored. The instruction is initiated by driving

the CE# pin low and shifting the instruction code “B9h” as show in the figure 8.20. The CE# pin must be driven

high after the instruction has been latched. If this is not done the Power-Down will not be executed. After CE#

pin driven high, the power-down state will be entered within the time duration of t_DP. While in the power-down

state only the Release from Power-down/RDID instruction, which restores the device to normal operation, will be

recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is

always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful

condition for securing maximum write protection. It can support in SPI and Multi-IO mode.

Figure 8.20 Enter Deep Power Down Mode Operation. (SPI)

CE#

t_DP

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

SI

...

Instruction = B9h

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8.22 RELEASE DEEP POWER DOWN (RDPD, ABh)

The Release from Power-down/Read Device ID instruction is a multi-purpose instruction. To release the device

from the deep power-down mode, the instruction is issued by driving the CE# pin low, shifting the instruction

code “ABh” and driving CE# high as shown in Figure 8.21.

Release from power-down will take the time duration of tRES1 before the device will resume normal operation

and other instructions are accepted. The CE# pin must remain high during the tRES1 time duration.

If the Release from Power-down/RDID instruction is issued while an Erase, Program or Write cycle is in process

(when WIP equals 1) the instruction is ignored and will not have any effects on the current cycle.

Figure 8.21 Release Power Down Sequence (SPI)

CE#

t_RES1

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

SI

...

Instruction = ABh

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8.23 READ PRODUCT IDENTIFICATION (RDID, ABh)

The Release from Power-down/Read Device ID instruction is a multi-purpose instruction. It can support both SPI

and Multi-IO mode. The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit

Electronic Signature, whose values are shown as table of Product Identification.

For Pm25LQ020B/010B/512B:

The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising

SCK edge. Then the Device ID1 is shifted out on SO with the MSB first, each bit been shifted out during the

falling edge of SCK. The RDID instruction is ended by CE# going high. The Device ID1 outputs repeatedly if

additional clock cycles are continuously sent on SCK while CE# is at low.

For Pm25LQ040B:

The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SIO during the rising

edge of SCK. Then the first byte Manufacturer ID (9Dh) is shifted out on SO with the MSB first, followed by the

Device ID1 (7Eh) and the second byte Manufacturer ID (7Fh), each bit been shifted out during the falling edge

of SCK. If the CE# stays low after the last bit of second byte Manufacturer ID is shifted out, the Manufacturer

IDs and Device ID1 will be looping until the pulled high of CE# signal.

Table 8.4 Product Identification

Instruction (ABh, 90h, 9Fh)

Manufacturer ID

Data

9Dh

ISSI Serial Flash First Byte

ISSI Serial Flash Second Byte

7Fh

Device Density

Device ID1

7Eh

Device ID2

7Eh

4Mb

2Mb

1Mb

512K

11h

42h

10h

21h

05h

20h

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Figure 8.22 Read Product Identification Sequence

For Pm25LQ020B/010B/512B:

CE#

0

1

...

7

8

9

...

31

32

...

39

40

...

47

48

...

55

Mode 3

Mode 0

SCK

SI

Instruction = ABh

3 Dummy Bytes

t_V

SO

Device ID1

For Pm25LQ040B:

CE#

0

1

...

7

8

9

...

31

32

...

39

40

...

47

48

...

55

Mode 3

SCK

Mode 0

SI

Instruction = ABh

3 Dummy Bytes

t_V

SO

Manufacturer ID1

Device ID1

Manufacturer ID2

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8.24 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh)

The JEDEC ID READ instruction allows the user to read the Manufacturer and Product ID of devices. Refer to

Table 8.4 Product Identification for Manufacturer ID and Device ID. After the JEDEC ID READ command is

input, the second byte Manufacturer ID (Manufacturer ID2) is shifted out on SO with the MSB first, followed by

the first byte Manufacturer ID (Manufacturer ID1) and the Device ID2, each bit shifted out during the falling edge

of SCK. If CE# stays low after the last bit of the Device ID2 is shifted out, the Manufacturer IDs and Device ID2

will loop until CE# is pulled high.

Figure 8.23 Read Product Identification by JEDEC ID READ Sequence

CE#

0

1

...

7

8

9

...

15

16

17

...

23

24

25

...

31

Mode 3

Mode 0

SCK

SI

Instruction = 9Fh

t_V

SO

Manufacturer ID2

Device ID2

Manufacturer ID1

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8.25 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h)

The Read Device Manufacturer and Device ID (RDMDID) instruction allows the user to read the Manufacturer

and product ID of devices. Refer to Table 8.4 Product Identification for Manufacturer ID and Device ID. The

RDMDID command is input, followed by a 24-bit address (A23~A0) pointing to an ID table, each bit being

latched-in on SI during the rising edge of SCK. The table contains the first byte Manufacturer ID (Manufacturer

ID1), the second byte Manufacturing ID (Manufacturer ID2) and Device ID1. If A0 = 0 (A23-A1 bits are don’t

care), then Manufacturer ID1 is shifted out on SO with the MSB first, followed by Device ID1 and Manufacturer

ID2, each bit shifted out during the falling edge of SCK. If A0 = 1 (A23-A1 bits are don’t care), then Device ID1

will be read first, followed by Manufacturer ID1 and Manufacturing ID2. If CE# stays low after the last bit of

Manufacturer ID2 is shifted out, the Manufacturer IDs and Device ID1 will loop as the sequence determined by

A0 until CE# is pulled high.

Figure 8.24 Read Product Identification by RDMDID READ Sequence

CE#

0

1

...

7

8

9

...

31

32

...

39

40

...

47

48

...

55

Mode 3

Mode 0

SCK

SI

Instruction = 90h

3 Byte Address

t_V

SO

Manufacturer ID1

Device ID1

Manufacturer ID2

Notes:

1. ADDRESS A0 = 0, will output Manufacture ID1 first  Device ID1 next  Manufacture ID2 next

ADDRESS A0 = 1, will output Device ID1 first  Manufacture ID1 next  Manufacture ID2 next

2. The Manufacture IDs and Device ID1 can be read continuously and will alternate between the three until CE# pin

is pulled high.

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8.26 READ UNIQUE ID NUMBER (RDUID, 4Bh)

The Read Unique ID Number (RDUID) instruction accesses a factory-set read-only 16-byte number that is

unique to the device. The ID number can be used in conjunction with user software methods to help prevent

copying or cloning of a system. The RDUID instruction is instated by driving the CE# pin low and shifting the

instruction code (4Bh) followed by 3 address bytes and a dummy byte. After which, the 16-byte ID is shifted out

on the falling edge of SCK as shown below.

Note: 16-byte of data will repeat as long as CE# is low and SCK is toggling.

Figure 8.25 Read Product Identification Sequence

CE#

0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

Mode 3

Mode 0

SCK

SI

Instruction = 4Bh

3 Byte Address

Dummy Byte

t_V

SO

Data Out

Table 8.5 Unique ID Addressing

A[23:16]

XXh

A[15:9]

XXh

A[8:4]

00h

A[3:0]

0h Byte address

1h Byte address

2h Byte address

XXh

00h

XXh

00h

XXh

00h

XXh

00h

Fh Byte address

Note: XX means “don’t care”.

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8.27 READ SFDP OPERATION (RDSFDP, 5Ah)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the

functional and feature capabilities of serial Flash devices in a standard set of internal parameter tables. These

parameter tables can be interrogated by host system software to enable adjustments needed to accommodate

divergent features from multiple vendors. For more details please refer to the JEDEC Standard JESD216A

(Serial Flash Discoverable Parameters).

The sequence of issuing RDSFDP instruction is same as Fast Read instruction: CE# goes low  send RDSFDP

instruction (5Ah)  send 3 address bytes on SI pin  send 1 dummy byte on SI pin  read SFDP code on SO

 to end RDSFDP operation can use CE# high at any time during data out. Refer to ISSI’s Application note for

SFDP table. The data at the addresses that are not specified in SFDP table are undefined.

Figure 8.26 RDSFDP COMMAND (Read SFDP) OPERATION

CE#

0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

Mode 3

Mode 0

SCK

SI

Instruction = 5Ah

3 Byte Address

Dummy Byte

t_V

SO

Data Out

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8.28 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)

The Reset operation is used as a system (software) reset that puts the device in normal operating mode. This

operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). The Reset operation requires

the Reset-Enable command followed by the Reset command. Any command other than the Reset command

after the Reset-Enable command will disable the Reset-Enable.

Execute the CE# pin low  sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives

CE# low again, sends the Reset command (99h), and drives CE# high.

The Software Reset during an active Program or Erase operation aborts the operation, which can result in

corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset timing

may vary. Recovery from a Write operation requires more latency time than recovery from other operations.

Note: The Status and Function Registers remain unaffected.

Figure 8.27 SOFTWARE RESET ENABLE, SOFTWARE RESET OPERATIONS (RSTEN, 66h + RST, 99h)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCK

Instruction = 66h

High Impedance

Instruction = 99h

SI

SO

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8.29 SECURITY INFORMATION ROW (OTP AREA)

The security Information Row is comprised of an additional 4 x 256 bytes of programmable information. The

security bits can be reprogrammed by the user. Any program security instruction issued while program cycle is

in progress is rejected without having any effect on the cycle that is in progress.

Table 8.6 Information Row Valid Address Range

Address Assignment

A[23:16]

00h

A[15:8]

00h

A[7:0]

IRL0 (Information Row Lock0)

Byte address

IRL1

IRL2

IRL3

00h

10h

00h

20h

00h

30h

Bit 7~4 of the Function Register is used to permanently lock the programmable memory array.

-When Function Register bit IRLx = “0”, the 256 bytes of the programmable memory array can be programmed.

-When Function Register bit IRLx = “1”, the 256 bytes of the programmable memory array function as read only.

8.30 INFORMATION ROW PROGRAM OPERATION (IRP, 62h)

The Information Row Program (IRP) instruction allows up to 256 bytes data to be programmed into the memory

in a single operation. Before the execution of IRP instruction, the Write Enable Latch (WEL) must be enabled

through a Write Enable (WREN) instruction.

The IRP instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input

via the SI line. Three address bytes has to be input as specified in the Table 8.6 Information Row Valid Address

Range. Program operation will start once the CE# goes high, otherwise the IRP instruction will not be executed.

The internal control logic automatically handles the programming voltages and timing. During a program

operation, all instructions will be ignored except the RDSR instruction. The progress or completion of the

program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the

WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed.

If more than 256 bytes data are sent to a device, the address counter rolls over within the same page. The

previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. The

starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap

around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all

other bytes on the same page will remain unchanged.

Note: Information Row is only One Time Programmable (OTP). Once an Information Row is programmed, the data

cannot be altered.

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Figure 8.28 IRP COMMAND (Information Row Program) OPERATION

CE#

0

1

...

7

8

9

...

31

32

33

...

39

...

Mode 3

Mode 0

SCK

3-byte Address

Data In 1

Data In 256

...

SI

...

6

0

7

0

Instruction = 62h

7

23

22

High Impedance

SO

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8.31 INFORMATION ROW READ OPERATION (IRRD, 68h)

The IRRD instruction is used to read memory data at up to a 104MHZ clock.

The IRRD instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks),

transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte

addressed is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling

edge of SCK.

The address is automatically incremented by one after each byte of data is shifted out. Once the address

reaches the last address of each 256 byte Information Row, the next address will not be valid and the data of

the address will be garbage data. It is recommended to repeat four times IRRD operation that reads 256 byte

with a valid starting address of each Information Row in order to read all data in the 4 x 256 byte Information

Row array. The IRRD instruction is terminated by driving CE# high (VIH).

If a IRRD instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is

ignored and will not have any effects on the current cycle

Figure 8.29 IRRD COMMAND (Information Row Read) OPERATION

CE#

0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

Mode 3

Mode 0

SCK

SI

Instruction = 68h

3 Byte Address

Dummy Byte

t_V

SO

Data Out

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8.32 SECTOR LOCK/UNLOCK FUNCTIONS

SECTOR UNLOCK OPERATION (SECUNLOCK, 26h)

The Sector Unlock command allows the user to select a specific sector to allow program and erase operations.

This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2, and

BP3 bits in the Status Register. Only one sector can be enabled at any time. If many SECUNLOCK commands

are input, only the last sector designated by the last SECUNLOCK command will be unlocked. The instruction

code is followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The

remaining sectors within the same block remain as read-only.

Figure 8.59 Sector Unlock Sequence

CE#

0

1

2

3

4

5

6

7

8

9

10

21

...

28

29

30

31

Mode 3

Mode 0

SCK

3-byte Address

...

SI

Instruction = 26h

3

2

1

0

23

22

High Impedance

SO

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SECTOR LOCK OPERATION (SECLOCK, 24h)

The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The

instruction code does not require an address to be specified, as only one sector can be enabled at a time. The

remaining sectors within the same block remain in read-only mode.

Figure 8.60 Sector Lock Sequence

CE#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCK

SI

Instruction = 24h

High Impedance

SO

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9. ELECTRICAL CHARACTERISTICS

9.1 ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

Storage Temperature

-65°C to +150°C

Standard Package

Lead-free Package

240°C 3 Seconds

260°C 3 Seconds

-0.5V to V_CC+ 0.5V

-0.5V to +6.0V

Surface Mount Lead Soldering Temperature

Input Voltage with Respect to Ground on All Pins

All Output Voltage with Respect to Ground

V_CC

Electrostatic Discharge Voltage (Human Body Model)⁽²⁾

-2000V to +2000V

Note:

1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. ANSI/ESDA/JEDEC JS-001

9.2 OPERATING RANGE

Part Number

Pm25LQ040B/020B/010B/512B

-40°C to 85°C

Operating Temperature

V_CCPower Supply

2.3V (VMIN) – 3.6V (VMAX); 3.0V (Typ)

9.3 DC CHARACTERISTICS

(Under operating range)

Symbol

Parameter

Condition

Min

Typ⁽²⁾

Max

Units

I_CC1

V_CCActive Read Current

V_CC= VMAX at 33MHz, SO = Open

10

15

mA

V_CCProgram/Erase

Current

I_CC2

I_SB1

V_CC= VMAX at 33MHz, SO = Open

15

30

mA

25°C

10

µA

V

V_CCStandby Current

CMOS

V_CC= VMAX, CE# = V_CC

85°C

25°C

85°C

15

5

I_SB2

Deep power down current V_CC= VMAX, CE# = V_CC

7

I_LI

Input Leakage Current

Output Leakage Current

Input Low Voltage

V_IN= 0V to V_CC

1

I_LO

(1)

V_IL

-0.5

0.3V_CC

V_CC+ 0.3

0.2

(1)

V_IH

Input High Voltage

0.7V_CC

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 100 µA

I_OH= -100 µA

V

VMIN < V_CC< VMAX

V_CC- 0.2

V

Notes:

1. Maximum DC voltage on input or I/O pins is V_CC+ 0.5V. During voltage transitions, input or I/O pins may

overshoot V_CCby +2.0V for a period of time not to exceed 20ns. Minimum DC voltage on input or I/O pins is -0.5V.

During voltage transitions, input or I/O pins may undershoot GND by -2.0V for a period of time not to exceed 20ns.

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at

V_CC= V_CC(Typ), TA=25°C.

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9.4 AC MEASUREMENT CONDITIONS

Symbol Parameter

Min

Max

30

5

Units

pF

ns

V

CL

Load Capacitance

TR,TF

VIN

Input Rise and Fall Times

Input Pulse Voltages

0.2V_CCto 0.8V_CC

VREFI

VREFO

Input Timing Reference Voltages

Output Timing Reference Voltages

0.3V_CCto 0.7V_CC

0.5V_CC

V

Figure9.1 Output test load & AC measurement I/O Waveform

0.8V_CC

AC

Input

V_CC/2

Measurement

Level

1.8k

0.2V_CC

OUTPUT PIN

1.2k

30pf

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9.5 AC CHARACTERISTICS

(Under operating range, refer to section 9.4 for AC measurement conditions)

Symbol

Parameter

Min

Typ

Max

104

33

8

Units

MHz

ns

f_CT

Clock Frequency for fast read mode

Clock Frequency for read mode

Input Rise Time

0

f_C

0

t_RI

t_FI

Input Fall Time

8

ns

t_CKH

t_CKL

t_CEH

t_CS

SCK High Time

4

ns

SCK Low Time

ns

CE# High Time

7

ns

CE# Setup Time

10

5

ns

t_CH

CE# Hold Time

ns

t_DS

Data In Setup Time

2

ns

t_DH

Data in Hold Time

2

ns

t_HS

Hold Setup Time

ns

15

t_HD

Hold Time

ns

t_V

Output Valid

8

ns

t_OH

Output Hold Time

2

ns

t_DIS

t_HLCH

t_CHHH

t_HHCH

t_CHHL

t_LZ

Output Disable Time

ns

HOLD Active Setup Time relative to SCK

HOLD Active Hold Time relative to SCK

HOLD Not Active Setup Time relative to SCK

HOLD Not Active Hold Time relative to SCK

HOLD to Output Low Z

HOLD to Output High Z

Sector Erase Time (4Kbyte)

Block Erase Time (32Kbyte)

Block Erase time (64Kbyte)⁽¹⁾

5

ns

12

300

500

1000

1

ns

t_HZ

ns

70

130

200

0.25

0.4

ms

t_EC

512Kb

1Mb

2Mb

4Mb

1.5

2

Chip Erase Time

s

0.75

1.5

3

t_PP

Page Program Time

0.5

0.8

3

ms

µs

ms

µs

t_res1

t_DP

Release deep power down

Deep power down

3

t_W

Write Status Register time

Suspend to read ready

Software Reset cover time

2

10

100

t_SUS

t_SRST

Note1: 64Kbyte Block Erase time is not applicable to Pm25LQ512B.

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9.6 SERIAL INPUT/OUTPUT TIMING

Figure 9.2 SERIAL INPUT/OUTPUT TIMING ⁽¹⁾

t_CEH

CE#

t_CS

t_CH

t_CKH

t_CKL

SCK

SI

t_DS

t_DH

VALID IN

t_V

t_OH

t_DIS

HI-Z

SO

VALID OUTPUT

Note1: For SPI Mode 0 (0,0)

Figure 9.3 HOLD TIMING

CE#

t_HLCH

t_CHHL

t_HHCH

SCK

t_CHHH

t_HZ

t_LZ

SO

SI

HOLD#

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9.7 POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must be NOT SELECTED until Vcc reaches at the right level. (Adding

a simple pull-up resistor on CE# is recommended.)

Power up timing

V_CC

V_CC(max)

All Write Commands are Rejected

Chip Selection Not Allowed

V_CC(min)

Reset State

Device fully

accessible

t_VCE

Read Access Allowed

V(write inhibit)

t_PUW

Symbol

tVCE⁽¹⁾

tPUW⁽¹⁾

Parameter

Min.

1

Max

Unit

ms

V

Vcc(min) to CE# Low

Power-up time delay to write instruction

Write Inhibit Voltage

1

10

(1)

V_WI

2.1

Note1: These parameters are characterized and are not 100% tested.

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9.8 PROGRAM/ERASE PERFORMANCE

Unit

ms

Parameter

Typ

70

Max

300

500

1000

1

Remarks

Sector Erase Time (4KB)

Block Erase Time (32KB)

Block Erase Time (64KB)

512Kb

130

200

0.25

0.4

ms

From writing erase command to erase

completion

1.5

2

1Mb

s

Chip Erase Time

2Mb

0.75

1.5

3

4Mb

Page Programming Time

Byte Program

ms

µs

0.5

8

0.8

25

From writing program command to

program completion

Note: These parameters are characterized and are not 100% tested.

9.9 RELIABILITY CHARACTERISTICS

Parameter

Endurance

Min

100,000

20

Max

Unit

Test Method

-

Cycles

Years

mA

JEDEC Standard A117

JEDEC Standard 78

Data Retention

Latch-Up

-100

+100

Note: These parameters are characterized and are not 100% tested.

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10.PACKAGE TYPE INFORMATION

10.1 8-PIN JEDEC 150MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (S)

Note: Lead co-planarity is 0.08mm.

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10.2 8-PIN TSSOP PACKAGE (D)

Note: Lead co-planarity is 0.08mm

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11.ORDERING INFORMATION

Pm25LQ040B

-

S

C

E

ENVIRONMENTAL ATTRIBUTE

E = Lead-free (Pb-free) and Halogen-free package

TEMPERATURE RANGE

C = -40°C to +85°C

PACKAGE TYPE

S = 8-pin SOIC 150mm

D = 8-pin TSSOP

DIE REVISION

B = Revision B

DENSITY

040 = 4 Mbit

020 = 2 Mbit

010 = 1 Mbit

512 = 512 Kbit

BASE PART NUMBER

Pm = pFLASH

25LQ = FLASH, 2.3V ~ 3.6V, Quad SPI

Density

4Mb

Frequency (MHz)

Order Part Number

Pm25LQ040B-SCE

Pm25LQ020B-SCE

Pm25LQ020B-DCE

Pm25LQ010B-SCE

Pm25LQ010B-DCE

Pm25LQ512B-SCE

Pm25LQ512B-DCE

Package

Temp Range

8-pin SOIC 150mil

8-pin TSSOP

2Mb

1Mb

104

8-pin SOIC 150mil

8-pin TSSOP

-40°C to +85°C

8-pin SOIC 150mil

8-pin TSSOP

512K

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APPENDIX 1. : SAFEGUARD FUNCTION

SAFEGUARD offers an alternative way to protect the memory array. When SAFEGUARD is implemented every

single 4Kbyte sector can be locked (protected) or unlocked (unprotected). Each sector is protected by setting a

“0” or “1” to max 4K bits of SAFEGUARD Register. When set to “0” the corresponding sector is protected and

vice versa.

SAFEGUARD has lower priority than BP bits. This means SAFEGUARD will be effective only if BP bits are all “0”

so that all blocks are unprotected. If any block is protected by BP bits, SAFEGUARD will be ignored. To unlock

all blocks, please make sure that BP bits are set to all “0” and also SAFEGUARD Register is set to all “1”.

The mapping table (Table A.1) represents sector assignment for each bit of data out/in of Read/Program

SAFEGUARD Register commands respectively according to an address.

D7-D0 for each address group is mapped to a single sector. For instance, if the output of the address 000h is

00001010b (Ah), then only the sectors 1 and 3 are unlocked while the remaining are locked.

If Block Erase commands (32Kbyte Block and 64K byte Block) are executed for the block which has at least a

sector protected by SAFEGUARD, it will be ignored so that it does not erase any data in the block.

As to Chip Erase command, all other blocks are erased except for the blocks which has at least a sector

protected by SAFEGUARD.

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Table A.1. Mapping table for SAFEGUARD Register¹

Block No.

Sector Assignment

Address

64Kbyte²32Kbyte

D7

D6

D5

D4

D3

D2

D1

D0

decimal

Sector

7

Sector

15

Sector

6

Sector

14

Sector

5

Sector

13

Sector

4

Sector

12

Sector

3

Sector

11

Sector

2

Sector

10

Sector

1

Sector

9

Sector

0

Sector

8

Block 0

0

1

Block 1

Sector

23

Sector

31

Sector

22

Sector

30

Sector

21

Sector

29

Sector

12

Sector

28

Sector

19

Sector

27

Sector

18

Sector

26

Sector

17

Sector

25

Sector

16

Sector

24

Block 2

Block 1

2

Block 3

3

Sector

39

Sector

47

Sector

38

Sector

46

Sector

37

Sector

45

Sector

36

Sector

44

Sector

35

Sector

43

Sector

34

Sector

42

Sector

33

Sector

41

Sector

32

Sector

40

Block 4

Block 2

4

Block 5

5

Sector

55

Sector

63

Sector

54

Sector

62

Sector

53

Sector

61

Sector

52

Sector

60

Sector

51

Sector

59

Sector

50

Sector

58

Sector

49

Sector

57

Sector

48

Sector

56

Block 6

Block 3

6

Block 7

7

:

Sector

16N+7

Sector

16N+6

Sector

16N+5

Sector

16N+4

Sector

16N+3

Sector

16N+2

Sector

16N+1

Sector

16N+9

Sector

16N

Sector

16N+8

Block 2N

2N

2N+1

Block N³

Block

2N+1

16N+15 16N+14 16N+13 16N+12 16N+11 16N+10

Notes:

1. The SAFEGUARD Register is non-volatile and the default value of all the SAFEGUARD Register bit is “1”.

2. 64Kbyte Block is not available for Pm25LQ512B.

3. N is dependent to device density as following.

Density

4M

2M

1M

512K

N

7

3

1

0

(Decimal)

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READ SAFEGUARD REGISTER (2Fh)

The Read SAFEGUARD Register instruction will be operated in normal read mode.

Normal Read SAFEGUARD Register instruction code 2Fh is transmitted via the SI pin, followed by three

address bytes (A23 - A0), but only A7-A0 will be decoded. The first byte of data (D7 - D0) shifts out on the SO

line, MSB first. The address is automatically incremented after each byte of data is shifted out. The data is valid

only for the valid address range dependent to the device density. The operation can be terminated at any time

by driving CE# high (VIH). See Figure A.1 for the Normal Read SAFEGUARD Register sequence.

Table A.2. Valid Address Range

Device

Density

Decoding

Address

Valid Address

Range

4M

A7-A0

A3-A0 (0-Fh)

A2-A0 (0-7h)

A1-A0 (0-3h)

A0 (0-1h)

2M

1M

512K

Example: To find out which sectors are locked or unlocked for IS25LQ040B, enter the 2Fh command followed

by (A23-A0) = XXXX XXXX XXXX 0000 0000b (where X is don’t care), D7-D0 will output for Sector 7-Sector 0

(MSB first), followed by D7-D0 for sector 15-sector 8, and so on until CE# is pulled high.

After Program/Erase suspend, the Read SAFEGUARD Register command (2Fh) can be accepted.

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Figure A.1. Normal Read SAFEGUARD Register Sequence

CE#

...

0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

Mode 3

Mode 0

SCK

3-byte Address

SI

...

0

Instruction = 2Fh

23

22

1^stByte Data Out

2^ndByte Data Out

t_V

High Impedance

SO

...

6

...

6

...

7

0

7

ERASE SAFEGUARD REGISTER (2Bh)

Erasing the SAFEGUARD Register will reset the mapping table and unprotect all sectors. Four continuous

instruction sequence (55h-AAh-80h-AAh) shall be required for write enable before the Erase SAFEGUARD

Register command as Figure A.2. Four continuous instruction sequence can be replaced by WREN (06h)

command. If the number of clocks is not match 8 for the command, then the instruction will be regarded as an

incorrect instruction so that it will be ignored.

The Erase SAFEGUARD Register instruction is entered, after CE# is pulled low to select the device and stays

low during the entire instruction sequence. The Erase SAFEGUARD Register instruction code is input via SI.

Erase operation will start immediately after CE# is pulled high, otherwise the Erase SAFEGUARD Register

instruction will not be executed. The internal control logic automatically handles the programming voltages and

timing. See Figure A.3 for the Erase SAFEGUARD Register sequence.

During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction.

The progress or completion of the erase operation can be determined by reading the WIP bit in the Status

Register using a RDSR instruction. If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is

“0”, the erase operation has been completed.

Program/Erase Suspend command is not applied to the Erase SAFEGUARD Register command.

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Figure A.2. Four Continuous Instruction Sequence before the Erase SAFEGUARD Register Command

CE#

0

1

...

7

8

9

...

31

Mode 3

Mode 0

SCK

SI

3-byte Address

...

0

Instruction = 55h

23

22

CE#

SCK

0

1

...

7

8

9

...

31

Mode 3

Mode 0

3-byte Address

SI

...

0

Instruction = AAh

23

22

CE#

0

1

...

7

8

9

...

31

Mode 3

Mode 0

SCK

SI

3-byte Address

...

0

Instruction = 80h

23

22

CE#

SCK

0

1

...

7

8

9

...

31

Mode 3

Mode 0

3-byte Address

SI

...

0

Instruction = AAh

23

22

Notes:

1. The sequence can be replaced by WREN (06h).

2. The 3-bye address (A23 – A0) is don’t care.

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Figure A.3. Erase SAFEGUARD Register Sequence

CE#

SCK

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SI

Instruction = 2Bh

High Impedance

SO

PROGRAM SAFEGUARD REGISTER (23h)

The Program SAFEGUARD Register command is similar to the Erase SAFEGUARD Register command. To

program SAFEGUARD Register, four continuous instruction sequence (55h-AAh-A0h-AAh) is needed for write

enable before the Program SAFEGUARD Register command as Figure A.4. Four continuous instruction

sequence can be replaced by WREN (06h) command. If the number of clocks is not match 8 (command) + 24

(address) + 8 x n (n=the number of data), then the instruction will be regarded as an incorrect instruction so that

it will be ignored.

The Program SAFEGUARD Register instruction code 23h is transmitted via the SI pin, followed by three

address bytes (A23 - A0) and program data (1 to 256 bytes) like Page Program sequence. The first byte of data

(D7 - D0) shifts in on the SI line, MSB first. The address is automatically incremented after each byte of data is

shifted in. The data is valid only for the valid address range.

Program operation will start immediately after the CE# is brought high, otherwise the Program SAFEGUARD

Register instruction will not be executed. The internal control logic automatically handles the programming

voltages and timing. During a program operation, all instructions will be ignored except the RDSR instruction.

The progress or completion of the program operation can be determined by reading the WIP bit in Status

Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”,

the program operation has completed. See Figure A.5 for how to program the SAFEGUARD Register.

Program/Erase Suspend command is not applied to Program SAFEGUARD Register command.

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Figure A.4. Four Continuous Instruction Sequence before the Program SAFEGUARD Register Command

CE#

0

1

...

7

8

9

...

31

Mode 3

Mode 0

SCK

SI

3-byte Address

...

0

Instruction = 55h

23

22

CE#

SCK

0

1

...

7

8

9

...

31

Mode 3

Mode 0

3-byte Address

SI

...

0

Instruction = AAh

23

22

CE#

0

1

...

7

8

9

...

31

Mode 3

Mode 0

SCK

SI

3-byte Address

...

0

Instruction = A0h

23

22

CE#

SCK

0

1

...

7

8

9

...

31

Mode 3

Mode 0

3-byte Address

SI

...

0

Instruction = AAh

23

22

Notes:

1. The sequence can be replaced by WREN (06h).

2. The 3-bye address (A23 – A0) is don’t care.

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Figure A.5. Program SAFEGUARD Register Sequence

CE#

...

0

1

...

7

8

9

...

31

32

33

...

39

40

...

41

...

47

Mode 3

Mode 0

SCK

1^stByte Data In

2^ndByte Data In

3-byte Address

SI

...

6

...

7

...

0

7

0

Instruction = 23h

23

22

High Impedance

SO

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型号：	PM25LQ512B-SCE
厂家：	INTEGRATED SILICON SOLUTION, INC
描述：	Flash, 64KX8, PDSO8, SOIC-8 时钟光电二极管内存集成电路
文件：	总70页 (文件大小：838K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PM25LQ512B-SCE [ISSI]

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