IS61LV25616AL-10B [ISSI]
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY; 256K ×16高速异步静态CMOS与3.3V供电的RAM
| 型号： | IS61LV25616AL-10B |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY |
| 文件： | 总12页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV25616AL
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
ISSI
FEBRUARY2003
DESCRIPTION
FEATURES
The ISSI IS61LV25616AL is a high-speed, 4,194,304-bit
static RAM organized as 262,144 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS technol-
ogy. This highly reliable process coupled with innovative
circuitdesigntechniques,yieldshigh-performanceandlow
powerconsumptiondevices.
• High-speed access time:
— 10, 12 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 mA (typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
The IS61LV25616AL is packaged in the JEDEC standard
44-pin400-milSOJ,44-pinTSOPTypeII,44-pinLQFPand
48-pin Mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
256K x 16
MEMORY ARRAY
A0-A17
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
CIRCUIT
COLUMN I/O
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
1
02/21/03
®
IS61LV25616AL
ISSI
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
ISB1, ISB2
ICC
Not Selected
OutputDisabled
X
H
X
X
X
High-Z
High-Z
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
A0
A1
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
OE
2
A2
3
WE
A3
4
A4
5
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
NoConnection
CE
6
UB
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
7
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
8
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VDD
Power
GND
Ground
A6
A7
A8
A9
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/21/03
®
IS61LV25616AL
ISSI
PIN CONFIGURATIONS
44-Pin LQFP
48-Pin mini BGA
1
1
2
3
4
5
6
2
44 43 42 41 40 39 38 37 36 35 34
1
33
32
31
30
29
28
27
26
25
24
23
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
A0
A3
A1
A4
A2
2
LB
I/O
OE
UB
N/C
A
B
C
D
E
F
3
3
CE
I/O
0
8
4
I/O
I/O
A5
A6
I/O
I/O
2
9
10
1
5
TOP VIEW
GND
A7
I/O
I/O
A17
NC
A14
A12
I/O
I/O
I/O
VDD
11
3
4
5
6
4
7
GND
V
DD
A16
A15
A13
A10
12
8
I/O
I/O
I/O
I/O
6
14
13
9
NC
WE
I/O
7
15
5
G
H
10
11
I/O8
NC
NC
A8
A9
A11
NC
12 13 14 15 16 17 18 19 20 21 22
6
7
PIN DESCRIPTIONS
8
A0-A17
I/O0-I/O15
CE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
9
OE
WE
10
11
12
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
NoConnection
UB
NC
VDD
Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
3
02/21/03
®
IS61LV25616AL
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to VDD+0.5
–65 to +150
1.0
Unit
V
VTERM
TSTG
PT
Terminal Voltage with Respect to GND
StorageTemperature
°C
W
PowerDissipation
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE
VDD
Range
AmbientTemperature
0°C to +70°C
10ns
12ns
Commercial
Industrial
3.3V +10%, -5%
3.3V +10%, -5%
3.3V + 10%
3.3V + 10%
–40°Cto+85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
—
0.4
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
—
V
2.0
VDD + 0.3
0.8
V
–0.3
V
GND ≤ VIN ≤ VDD
Com.
Ind.
–2
–5
2
5
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD
OutputsDisabled
Com.
Ind.
–2
–5
2
5
µA
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/21/03
®
IS61LV25616AL
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
1
-10
Min. Max.
-12
Min. Max.
Symbol Parameter
ICC VDD Dynamic Operating
Test Conditions
Unit
VDD = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
100
110
—
—
90
100
mA
Supply Current
2
ISB
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = fMAX.
Com.
Ind.
—
—
50
55
—
—
45
50
mA
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
20
25
—
—
20
25
mA
mA
3
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
Com.
Ind.
—
—
15
20
—
—
15
20
4
CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
5
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Shaded area product in development
6
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
7
InputCapacitance
Input/OutputCapacitance
6
8
COUT
VOUT = 0V
pF
Note:
8
1. Tested initially and after any design or process changes that may affect these parameters.
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
5
02/21/03
®
IS61LV25616AL
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10
Min. Max.
-12
Min. Max.
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
10
—
2
—
10
—
10
4
12
—
2
—
12
—
12
5
tAA
t
t
t
t
OHA
ACE
—
—
—
0
—
—
—
0
DOE
HZOE
OE Access Time
(2)
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
Power Up Time
4
5
(2)
t
t
t
LZOE
—
4
—
6
(2
HZCE
0
0
(2)
LZCE
BA
3
—
4
3
—
5
t
—
0
—
0
(2)
t
t
t
t
HZB
3
4
(2)
LZB
PU
PD
0
—
—
10
0
—
—
12
0
0
Power Down Time
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels
of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
AC TEST LOADS
319 Ω
319 Ω
3.3V
OUTPUT
3.3V
OUTPUT
353 Ω
5 pF
Including
jig and
353 Ω
30 pF
Including
jig and
scope
scope
Figure 1
Figure 2
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Level
OutputLoad
1.5V
See Figures 1 and 2
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/21/03
®
IS61LV25616AL
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
1
t
RC
2
ADDRESS
t
AA
t
OHA
t
OHA
3
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
4
READ CYCLE NO. 2(1,3)
5
tRC
ADDRESS
OE
6
tAA
tOHA
tHZOE
t
DOE
LZOE
ACE
7
t
CE
t
t
HZCE
tLZCE
8
LB, UB
tBA
tHZB
t
RC
tLZB
HIGH-Z
DOUT
DATA VALID
9
I
CC
SB
V
DD
Supply
Current
50%
50%
tPD
tPU
I
UB_CEDR2.eps
10
11
12
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
7
02/21/03
®
IS61LV25616AL
ISSI
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
OE
tAA
tOHA
tHZOE
t
DOE
LZOE
ACE
t
CE
t
t
HZCE
tLZCE
LB, UB
tBA
tHZB
t
RC
t
LZB
HIGH-Z
DOUT
DATA VALID
I
CC
SB
V
DD
Supply
Current
50%
50%
tPD
tPU
I
UB_CEDR2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10
-12
Symbol
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tSCE
tAW
t
HA
Write Cycle Time
10
8
—
—
—
—
—
—
—
—
—
—
5
12
8
—
—
—
—
—
—
—
—
—
—
6
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
8
8
0
0
tSA
0
0
t
t
t
t
t
t
t
PWB
PWE
PWE
SD
LB, UB Valid to End of Write
WE Pulse Width
8
8
1
2
8
8
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
10
6
12
6
HD
0
0
(2)
HZWE
—
2
—
2
(2)
LZWE
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold
timing are referenced to the rising or falling edge of the signal that terminates the write.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/21/03
®
IS61LV25616AL
ISSI
AC WAVEFORMS
(1 )
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW)
1
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
2
t
SA
t
t
HA
t
AW
t
PWE1
PWE2
3
t
WE
t
PBW
UB, LB
4
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
5
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
6
7
(1,2)
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle)
8
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
9
LOW
CE
t
AW
t
PWE1
WE
10
11
12
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
9
02/21/03
®
IS61LV25616AL
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 3(WE Controlled. OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
t
PBW
UB, LB
HZWE
tLZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
tHD
DATAIN VALID
DIN
UB_CEWR3.eps
WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write) (1,3)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
tHA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
tHD
t
SD
tSD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/21/03
®
IS61LV25616AL
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS (LL)
1
Symbol
VDR
Parameter
Test Condition
Options
Min.
Typ.(1)
Max.
Unit
V
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 2.0V, CE ≥ VDD – 0.2V
2.0
—
3.6
IDR
Com.
Ind.
—
—
5
10
15
mA
—
2
tSDR
tRDR
Data Retention Setup Time See Data Retention Waveform
0
—
—
—
—
ns
ns
Recovery Time
See Data Retention Waveform
tRC
O
Note 1: Typical values are measured at VDD = 3.0V, T
A
= 25 C and not 100% tested.
3
4
DATA RETENTION WAVEFORM (CE Controlled)
5
t
SDR
Data Retention Mode
t
RDR
VDD
1.65V
6
1.4V
VDR
CE ≥ VDD - 0.2V
7
CE
GND
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11
02/21/03
®
IS61LV25616AL
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
10
IS61LV25616AL-10T
IS61LV25616AL-10K
IS61LV25616AL-10LQ
IS61LV25616AL-10B
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
12
IS61LV25616AL-12T
IS61LV25616AL-12K
IS61LV25616AL-12B
TSOP (Type II)
400-mil SOJ
Mini BGA (8mm x 10mm)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
10
IS61LV25616AL-10TI
IS61LV25616AL-10KI
IS61LV25616AL-10LQI
IS61LV25616AL-10BI
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
12
IS61LV25616AL-12TI
IS61LV25616AL-12KI
TSOP (Type II)
400-mil SOJ
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/21/03
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