IS27HC010-70TI [ISSI]
131,072 x 8 HIGH-SPEED CMOS EPROM; 131,072 ×8高速CMOS EPROM
| 型号： | IS27HC010-70TI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 131,072 x 8 HIGH-SPEED CMOS EPROM |
| 文件： | 总11页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ISSI
IS27HC010
131,072 x 8 HIGH-SPEED CMOS EPROM
JULY 1997
FEATURES
DESCRIPTION
The ISSI IS27HC010 is an ultra-high-speed 1 megabit (128K-
word by 8-bit) Ultraviolet Erasable CMOS Programmable
Read-Only Memory. It utilizes the standard JEDEC pinout
making it functionally compatible with the IS27C010, but with
significantly faster access capability. This superior random
access capability results from a focused high-speed design.
This offers users bipolar speeds with higher density, lower
cost, and proven reliability.
• Fast read access time: 30 ns
• Pin compatible with the IS27C010
• High-speed write programming
— Typically less than 30 seconds
• Industrial and commercial temperature ranges
available
• ±10% power supply tolerance
The device is ideal for use with the faster processors. Design-
ers may take full advantage of high-speed digital signal
processors and microprocessors by allowing code to be
executed at full speed directly out of EPROM. Typical applica-
tions include laser printers, switching networks, graphics,
workstations,high-speedmodems,anddigitalsignalprocess-
ing.
• JEDEC-approved pinout
• Standard 32-pin DIP, PLCC, and TSOP
packages
The IS27HC010 uses ISSI's write programming algorithm
which allows the entire chip to be programmed in typically less
than 30 seconds.
This product is available inOne-Time Programmable (OTP)
PDIP, PLCC, and TSOP packages over commercial and
industrial temperature ranges.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
VPP
DQ0-DQ7
8
OE
OUTPUT ENABLE
CHIP ENABLE
AND
PROG LOGIC
CE
OUTPUT
BUFFERS
PGM
Y
Y
GATING
DECODER
17
A0-A16
1,048,576-BIT
CELL MATRIX
X
DECODER
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
1
EP009-1F
07/18/97
®
IS27HC010
ISSI
PIN CONFIGURATIONS
32-Pin DIP
PIN DESCRIPTIONS
A0-A16
CE (E)
DQ0-DQ7
OE (G)
PGM (P)
Vcc
Address Inputs
VPP
A16
A15
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
PGM (P)
NC
Chip Enable Input
Data Inputs/Outputs
Output Enable Input
Program Enable Input
Power Supply Voltage
Program Supply Voltage
Ground
2
3
4
A14
5
A13
A6
6
A8
A5
7
A9
VPP
A4
8
A11
GND
A3
9
OE (G)
A10
A2
10
11
12
13
14
15
16
NC
No Internal Connection
A1
CE (E)
DQ7
DQ6
DQ5
DQ4
DQ3
A0
DQ0
DQ1
DQ2
GND
32-Pin TSOP
32-Pin PLCC
INDEX
A11
A9
A8
A13
A14
NC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE (G)
A10
4
3
2
1
32 31 30
2
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
5
6
7
8
9
A14
3
CE (E)
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
4
A13
5
A8
6
PGM (P)
VCC
VPP
A16
A15
A12
A7
7
A9
8
A11
9
10
11
12
13
14
15
16
A2 10
A1 11
OE (G)
A10
A0 12
CE (E)
DQ7
A6
A5
A4
A1
A2
A3
DQ0 13
14 15 16 17 18 19 20
2
Integrated Silicon Solution, Inc.
EP009-1F
07/18/97
®
IS27HC010
ISSI
FUNCTIONAL DESCRIPTION
Erasing the IS27HC010
Program Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The
verify should be performed with OEand CEat VIL, PGM at
VIH, and VPP between 12.5V and 13.0V.
Inordertoclearalllocationsoftheirprogrammedcontents,
it is necessary to expose the IS27HC010 to an ultraviolet
light source. A dosage of 30W - sec/cm2 is required to
completely erase the IS27HC010. This dosage can be
obtained by exposure to an ultraviolet lamp-wavelength of
2537 Angstroms (Å)—with intensity of 12,000 µW/cm2 for
30to40minutes. TheIS27HC010shouldbedirectlyunder
andaboutoneinchfromthesourceandallfiltersshouldbe
removed from the UV light source prior to erasure.
Auto Select Mode
The auto select mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and type. This mode is intended for use by programming
equipment for the purpose of automatically matching the
device to be programmed with its corresponding program-
ming algorithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when pro-
gramming the IS27HC010.
It is important to note that the IS27HC010, and similar
devices, will erase with light sources having wavelengths
shorter than 4000Å. The exposure to fluorescent light and
sunlight will eventually erase the IS27HC010 and expo-
sure to them should be prevented to realize maximum
system reliability. If used in such an environment, the
package window should be covered by an opaque label or
substance.
To activate this mode, the programming equipment must
force 12.0 ± 0.5V on address line A9 of the IS27HC010.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to VIH.
All other address lines must be held at VIL during auto
select mode.
Programming the IS27HC010
Upon delivery, or after each erasure, the IS27HC010 has
1,048,576 bits in the "ONE", or HIGH state. "ZEROs" are
loaded into the IS27HC010 through the procedure of
programming.
Byte 0 (A0 = VIL) represents the manufacturer code, and
byte 1 (A0 = VIH), the device identifier code. For the
IS27HC010, these two identifier bytes are given in the
Mode Select table. All identifiers manufacturer and device
codeswillpossessoddparity, withtheMSB(DQ7)defined
as the parity bit.
The programming mode is entered when 12.75 ± 0.25V is
applied to the VPP pin, VCC = 6.25V, CEand PGM is at VIL,
and OE is at VIH. For programming, the data to be pro-
grammed is applied eight bits in parallel to the data output
pins.
Read Mode
The IS27HC010 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and should
beusedfordeviceselection. Assumingthataddressesare
stable, address access time (tACC) is equal to the delay
from CE to output (tCE). Output Enable (OE) is the output
control and should be used to get data to the output pins,
independent of device selection. Data is available at the
outputs tOE after the falling edge of OE assuming that CE
has been LOW and addresses have been stable for at
least tACC – tOE.
The write programming algorithm reduces programming
time by using 100 µs programming pulses followed by a
byte verification to determine whether the byte has been
successfully programmed. If the data does not verify, an
additional pulse is applied for a maximum of 25 pulses.
This process is repeated while sequencing through each
address of the EPROM.
The write programming algorithm programs and verifies at
VCC = 6.25V and VPP = 12.75V. After the final address is
completed, all byte are compared to the original data with
VCC = 5.25V.
Standby Mode
The IS27HC010 has a standby mode which reduces the
maximum VCC active current. It is placed in standby mode
when CEis at VIH. The amount of current drawn in standby
mode depends on the frequency and the number of
address pins switching. The IS27HC010 is specified with
50% of the address lines toggling at 10 MHz. A reduction
of the frequency or quantity of address lines toggling will
significantly reduce the actual standby current.
Program Inhibit
Programming of multiple IS27HC010s in parallel with
different data is also easily accomplished. Except for CE,
all like inputs of the parallel IS27HC010 may be common.
A TTL low-level program pulse applied to an IS27HC010
CE input with VPP = 12.75 ± 0.25V, PGM LOW and OE
HIGH will program that IS27HC010. A high-level CEinput
inhibits the other IS27HC010 from being programmed.
Integrated Silicon Solution, Inc.
3
EP009-1F
07/18/97
®
IS27HC010
ISSI
Output OR-Tieing
System Applications
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
During the switch between active and standby conditions,
transient current peaks are produced on the rising and
falling edges of Chip Enable. The magnitude of these
transientcurrentpeaksisdependentontheoutputcapaci-
tanceloadingofthedeviceataminimum, a0.1µFceramic
capacitor(high-frequency,lowinherentinductance)should
be used on each device between VCC and GND to mini-
mizetransienteffects. Inaddition, toovercomethevoltage
drop caused by the inductive effects of the printed circuit
board traces on EPROM arrays, a 4.7 µF bulk electrolytic
capacitor should be used between VCC and GND for each
eight devices. The location of the capacitor should be
close to where the power supply is connected to the array.
1. Low memory power dissipation, and
2. Assurance that output bus contention will not
occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and con-
nected to the READ line from the system control bus. This
assures that all deselected memory devices are in their
low-power standby mode and that the output pins are only
active when data is desired from a particular memory
device.
TRUTH TABLE(1,2)
Mode
CE
OE
PGM
A0
A9
VPP
Outputs
Read
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VCC
VCC
VCC
VPP
VPP
VPP
DOUT
Hi-Z
Hi-Z
DIN
Output Disable
Standby
X
Program
VIH
VIL
X
VIL
VIH
X
Program Verify
Program Inhibit
DOUT
Hi-Z
Auto Select(3,5) Manufacturer Code
Device Code
VIL
VIL
VIL
VIL
X
X
VIL
VIH
VH
VH
VCC
VCC
D5H
0EH
Notes:
1. VH = 12.0V ± 0.5V.
2. X = Either VIH or VIL.
3. A1-A8 = A10-A16 = VIL.
4. See DC Programming Characteristics for VPP voltage during programming.
5. The IS27HC010 can use the same write algorithm during program as other IS27C010 or IS27010 devices.
LOGIC SYMBOL
17
A0-A16
8
DQ0-DQ7
CE (E)
PGM (P)
OE (G)
4
Integrated Silicon Solution, Inc.
EP009-1F
07/18/97
®
IS27HC010
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
VTERM
Terminal Voltage with Respect to GND
All pins except A9 and VPP
–0.6 to VCC + 0.5(2)
VCC – 0.3 to 13.5(2,3)
–0.6 to 13.5(2,3)
V
V
V
V
VPP
A9
VCC
–0.6 to 7.0(2)
TA
Ambient Temperature with Power Applied
Storage Temperature (OTP)
–65 to +125
–65 to +125
–65 to +150
°C
°C
°C
TSTG
TSTG
Storage Temperature (All others)
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods less than 10
ns. Maximum DC voltage on output pins is VCC + 0.5V which may overshoot to VCC + 2.0V for periods less than
10 ns.
3. Maximum DC voltage on A9 or VPP may overshoot to +13.5V for periods less than 10 ns.
OPERATING RANGE
Range
Ambient Temperature
0°C to +70°C
VCC
Commercial
Industrial(1)
5V ± 10%
5V ± 10%
–40°C to +85°C
Note:
1. Operating ranges define those limits between which the
functionally of the device is guaranteed.
DC ELECTRICAL CHARACTERISTICS(1,2,3) (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
—
Max.
—
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –4 mA
VCC = Min., IOL = 12 mA
Output LOW Voltage
Input HIGH Voltage(4)
Input LOW Voltage(4)
Input Load Current
0.45
VCC + 0.5
0.8
V
2.0
–0.3
—
V
V
VIN = 0V to +VCC
5.0
µA
µA
ILO
Output Leakage Current
VOUT = 0V to +VCC
—
10
Notes:
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Never try to force VPP LOW to 1V
below VCC. Manufacturer suggests to tie VPP and Vcc together during the READ operation.
2. Caution: the IS27HC010 must not be removed from (or inserted into) a socket when VCC or VPP is applied.
3. Minimum DC input voltage is –0.5V. During transitions, the inputs may undershoot to –2.0V for periods less than 10 ns.
Maximum DC voltage on output pins is VCC + 0.5V which may overshoot to VCC + 2.0V for periods less than 10 ns.
4. Tested under static DC conditions.
Integrated Silicon Solution, Inc.
5
EP009-1F
07/18/97
®
IS27HC010
ISSI
POWER SUPPLY CHARACTERISTICS(1,2,5) (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
ICC1
Vcc Operating
VCC = Max., CE = VIL
IOUT = 0 mA, f = 10 MHz
(Open outputs)
Commercial
Industrial
—
—
75
90
mA
Supply Current(3)
IPP1
VPP Current During
Read(4)
VCC = Max., CE = OE = VIL
VPP = VCC
—
—
1.0
20
µA
ICCSB0
Vcc CMOS Standby
Current
CE ≥ VCC – 0.3V
All pins ≥ VCC – 0.3V or ≤ 0.3V toggling
f ≤ 10 MHz
mA
ICCSB1
Vcc TTL Standby
Current
CE ≥ VIH
—
35
mA
All pins = VIH or VIL (TTL Level) toggling
f ≤ 10 MHz
Notes:
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Never try to force VPP LOW to 1V
below VCC. Manufacturer suggests to tie VPP and Vcc together during the READ operation.
2. Caution: the IS27HC010 must not be removed from (or inserted into) a socket when VCC or VPP is applied.
3. ICC1 is tested with OE = VIH to simulate open outputs.
4. Maximum active power usage is the sum of ICC and IPP.
5. Minimum DC input voltage is –0.5V. During transitions, the inputs may undershoot to –2.0V for periods less than 10 ns.
Maximum DC voltage on output pins is VCC + 0.5V which may overshoot to VCC + 2.0V for periods less than 10 ns.
CAPACITANCE(1,2,3)
DIP
PLCC/TSOP
Symbol Parameter
Conditions
VIN = 0V
Typ.
6
Max.
10
Typ.
Max.
Unit
pF
CIN1
CIN2
CIN3
COUT
Address Input Capacitance
6
7
7
6
9
9
9
9
OE Input Capacitance
CE Input Capacitance
Output Capacitance
VIN = 0V
10
10
8
10
pF
VIN = 0V
10
pF
VOUT = 0V
12
pF
Notes:
1. Typical values are for nominal supply voltage.
2. This parameter is only sampled, but not 100% tested.
3. Test conditions: TA = 25°C, f = 1 MHz.
SWITCHING TEST WAVEFORM
SWITCHING TEST CIRCUIT
3V
Device
Under
Test
OUT
1.5V
TEST POINTS
1.5V
0V
R
L
= 121Ω
INPUT
OUTPUT
CL1 = 30 pF
L2 = 5 pF
CL
C
V
L
= 1.9V
Notes:
AC Testing:
1. Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
2. Input pulse rise and fall skew rate ≥ 1.5V/ns.
6
Integrated Silicon Solution, Inc.
EP009-1F
07/18/97
®
IS27HC010
ISSI
SWITCHING CHARACTERISTICS(1,3,4) (Over Operating Range)
JEDEC
Symbol
Std.
Symbol
-30
-45
-70
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tAVQA
tELQV
tGLQV
tACC
tCE
Address to
Output Delay
CE = OE = VIL
CL = CL1
—
30
—
45
—
70
ns
Chip Enable to
Output Delay
OE = VIL
CL = CL1
—
—
0
30
10
10
—
—
0
45
20
20
—
—
0
70
35
35
ns
ns
ns
tOE
Output Enable to
Output Delay
CE = VIL
CL = CL1
(2)
tEHOZ,
tGHQZ
tDF
Chip Enable HIGH or
Output Enable HIGH,
whichever comes first,
to Output Float
CL = CL2
tAVOX
tOH
Output Hold from
Address, CE or OE
whichever occured first
0
—
0
—
0
—
ns
Notes:
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. This parameter is only sampled, not 100% tested.
3. Caution: The IS27HC010 must not be removed from (or inserted into) a socket or board when VPP or VCC applied.
4. Output Load: 1 TTL gate and C = CL.
Input Rise and Fall times: 2 ns.
Input Pulse Levels: 0 to 3V.
Timing Measurement Reference Level: 1.5V for inputs and outputs.
SWITCHING WAVEFORMS
3V
1.5V
1.5V
ADDRESS
ADDRESS VALID
0V
CE
OE
tCE
tOE
tDF(2)
tACC(1)
tOH
Hi-Z
Hi-Z
OUTPUT
VALID OUTPUT
Notes:
1. OE may be delayed up to tACC – tOE after the falling edge of CE without impact on tACC.
2. tDF is specified from OE or CE, whichever occurs first.
Integrated Silicon Solution, Inc.
7
EP009-1F
07/18/97
®
IS27HC010
ISSI
DC PROGRAMMING CHARACTERISTICS(1,2,3,4) (TA = +25°C ± 5°C)
Symbol Parameter
Test Conditions
IOH = –400 µA
IOL = 2.1 mA
Min.
2.4
—
Max.
—
Unit
V
VOH
VOL
VIH
VIL
Output HIGH Voltage During Verify
Output LOW Voltage During Verify
Input HIGH Voltage
0.45
VCC + 0.5
0.8
V
2.0
–0.3
11.5
—
V
Input LOW Voltage (All Inputs)
A9 Auto Select Voltage
Input Current (All Inputs)
VCC Supply Current (Program & Verify)
VPP Supply Current
V
VH
12.5
10.0
50
V
ILI
VIN = VIL or VIH
µA
mA
mA
V
ICC
IPP
—
CE = VIL, OE = VIH
—
30
VCC
VPP
Supply Voltage
6.0
12.5
6.5
Programming Voltage
13.0
V
SWITCH PROGRAMMING CHARACTERISTICS(1,2,3,4) (TA = +25°C ± 5°C)
JEDEC
Symbol
Std.
Symbol
Parameter
Min.
2
Max.
—
Unit
µs
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
tAVEL
tDZGL
tDVEL
tGHAX
tEHDX
tGHQZ
tVPS
tAS
tOES
tDS
Address Setup Time
OE Setup Time
2
—
Data Setup Time
Address Hold Time
Data Hold Time
2
—
tAH
0
—
tDH
2
—
tDFP
tVPS
tPW
tVCS
tCES
tOE
OE HIGH to Output Float Delay
VPP Setup Time
0
130
—
2
tELEH1
tVCS
PGM Program Pulse Width
VCC Setup Time
95
2
105
—
tELPL
tGLQV
CE Setup Time
2
—
Data Valid from OE
—
150
Notes:
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. VPP must be ≥ VCC during the entire programming and verifying procedure.
3. When programming IS27HC010, a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage transients
which may damage the device.
4. Programming characteristics are sampled but not 100% tested at worst-case conditions.
8
Integrated Silicon Solution, Inc.
EP009-1F
07/18/97
®
IS27HC010
ISSI
PROGRAMMING ALGORITHM WAVEFORM(1,2)
PROGRAM
VERIFY
PROGRAM
ADDRESS
tAS
tAH
Hi-Z
DATA
DATAIN STABLE
DATAOUT VALID
tDFP
tDS
tVPS
tVCS
tDH
12.75V
VPP
VCC
≥Vcc–0.3V
5V±10%
6.0V-6.5V
CE
tCES
PGM
OE
tPW
tOES
tOE
Max
Notes:
1. The timing reference level is 1.5V for inputs and outputs.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
Integrated Silicon Solution, Inc.
9
EP009-1F
07/18/97
®
IS27HC010
ISSI
PROGRAMMING FLOW CHART
Start
Address = First Location
Vcc = 6.25V
V
PP = 12.75V
X = 0
Interactive
programming
Section
Program One 100 µs Pulse
Increment X
Yes
X = 25?
No
Fail
Verify
Byte
Pass
Last
No
Increment Address
Address?
Yes
Vcc = VPP = 5.25V
Fail
Verify Section
Verify All
Bytes
Device Failed
Pass
Device Passed
10
Integrated Silicon Solution, Inc.
EP009-1F
07/18/97
®
IS27HC010
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part Number Package
30
IS27HC010-30W
IS27HC010-30PL
IS27HC010-30T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP
45
70
IS27HC010-45W
IS27HC010-45PL
IS27HC010-45T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP
IS27HC010-70W
IS27HC010-70PL
IS27HC010-70T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part Number Package
30
IS27HC010-30PLI
IS27HC010-30TI
PLCC – Plastic Leaded Chip Carrier
TSOP
45
70
IS27HC010-45PLI
IS27HC010-45TI
PLCC – Plastic Leaded Chip Carrier
TSOP
IS27HC010-70PLI
IS27HC010-70TI
PLCC – Plastic Leaded Chip Carrier
TSOP
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Fax: (408) 588-0806
Toll Free: 1-800-379-4774
http://www.issiusa.com
Integrated Silicon Solution, Inc.
11
EP009-1F
07/18/97
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