IR3522MPBF_技术文档

IR3522

DATA SHEET

XPHASE3^TMDDR & VTT CONTROL IC

DESCRIPTION

The IR3522 Control IC combined with IR3506 xPHASE3^TMPhase ICs implements a full featured DDR3

power solution. The IR3522 provides control functions for both the VTT (single phase) and VDDR

(multiphase) power rails which can interfaces with any number of IR3506 ICs each driving and monitoring

a single phase to power any number of DDR3 DIMMs. The xPHASE3^TMarchitecture delivers a power

supply that is smaller, more flexible, and easier to design while providing higher efficiency than

conventional approaches.

FEATURES

•

I²C interface programs 1.025V< VREF1<1.612V, the VDD output voltage reference

•

I²C also programs the VTT tracking ratio 25 %, and provides digital ON/OFF control

Four different I²C addresses are selectible using 2 ADDR pins

Four different VREF1 voltages are selectible using 2 VID pins if I²C communication is not available

VTT tracking defaults to ½ the VDD Remote Sense Amp output voltage

Power Good output driven by an external bias input

VDD to VTT overvoltage protection

Soft-Stop turn-off to ensure VDDR and Vtt tracking

Fault activated Crowbar pin to drive external NMOS devices for external output voltage protection

Pin programmable slew rate of I²C programmed VREF1 voltage transitions

0.5% overall VDD system set point accuracy

Remote sense amplifiers provide differential sensing and requires less than 50uA bias current

Pin programmable per phase switching frequency of 250kHz to 1.5MHz

Complete protection including over-current, over-voltage, open remote sense, and open control

APPLICATION CIRCUIT

12V

To Converters

12V

VCCL

To Phase IC

VCCL & GATE

DRIVE BIAS

CVCCL

Phase Clock Input to

Last Phase IC of VDD

PGOOD

PHSIN

2 wire Digital

Daisy Chain Bus

to Phase ICs

PHSOUT

CLKOUT

SCL

SDA

RPGBIAS

1

2

3

4

5

6

7

8

24

SDA

LGND

ROSC

23

22

21

20

19

18

17

PGBIAS

ENABLE

IIN2

Drives NMOS crowbar

ENABLE

devices at VTT and

VDDR rails

CROWBAR

IIN1

IR3522

CONTROL

IC

CSS/DEL

CVREF

ADDR1

ADDR2

OCSET2

EAOUT2

SS/DEL1

VREF1

RVREF

ROCSET1

ROCSET2

OCSET1

EAOUT1

RCP2 CCP21

RFB22 CFB2

RFB21

CFB1

RFB12

CCP11

RCP1

ISHARE1

EAOUT1

VREF1

CCP22

RFB11

CCP12

5 Wire Analog

Phase IC

Control Bus

EAOUT2

ISHARE2

To Vtt

Remote

Sense

To VDD

Remote

Sense

VTT SENSE +

VTT SENSE -

DDR SENSE +

DDR SENSE -

Figure 1 – IR3522 Application Circuit

Page 1

V3.01

IR3522

ORDERING INFORMATION

Device

Package

Order Quantity

IR3522MTRPBF

* IR3522MPBF

32 Lead MLPQ (5 x 5 mm body)

3000 per reel

100 piece strips

* Samples only

PIN DESCRIPTION

PIN# PIN SYMBOL

PIN DESCRIPTION

1

SDA

SDA (Serial Data) is a bidirectional signal that is an input and open drain output for

both master (I²C controller) and slave (IR3522). SDA requires a pull resistor to a

bias voltage and should not be floated.

2

PGBIAS

Input to provide bias to the Power Good output transistor directly from the converter

input voltage. Enables the Power Good output to assert even if there is no bias

supplied to the VCCL pin. Internal voltage clamp protects the pin. Do not exceed

100 uA of pull-up current.

3

ENABLE

Enable input. A logic low applied to this pin puts the IC into fault mode. A logic high

on the pin resets and enables the converter. Do not float this pin as the logic state

will be undefined.

4

5

IIN2

Output 2 average current input from the output 2 phase IC(s).

Digital input to program bit 1 of the 2 bit address code with internal pull-up. Connect

to LGND for logic “0”, float for logic “1”

ADDR1

6

7

ADDR2

Digital input to program bit 2 of the 2 bit address code with internal pull-up. Connect

to LGND for logic “0”, float for logic “1”

OCSET2

Programs the output 2 constant converter output current limit through an external

resistor tied to VREF1 and an internal current source from this pin. Over-current

protection can be disabled by over sizing the resistor value to program the threshold

higher than IIN2 pin possible signal amplitude, but no greater than 5V (do not float

this pin as improper operation will occur).

8

EAOUT2

FB2

Output of the output 2 error amplifier.

9

Inverting input to the output 2 error amplifier.

10

11

12

13

14

15

16

17

18

VOUT2

Output 2 remote sense amplifier output.

VOSEN2+

VOSEN2-

VOSEN1-

VOSEN1+

VOUT1

Output 2 remote sense amplifier input. Connect to output at the load.

Output 2 remote sense amplifier input. Connect to ground at the load.

Output 1 remote sense amplifier input. Connect to ground at the load.

Output 1 remote sense amplifier input. Connect to output at the load.

Output 1 remote sense amplifier output. Provides reference to Error Amp2.

Inverting input to the output 1 error amplifier.

FB1

EAOUT1

OCSET1

Output of the output 1 error amplifier.

Programs the output 1 constant converter output current limit through an external

resistor tied to VREF1 and an internal current source from this pin. Over-current

protection can be disabled by over sizing the resistor value to program the threshold

higher than IIN2 pin possible signal amplitude, but no greater than 5V (do not float

this pin as improper operation will occur).

Reference voltage programmed by the I²C inputs and error amplifier non-inverting

input. Connect an external RC network to LGND to program dynamic VID slew rate

and provide compensation for the internal buffer amplifier.

19

20

VREF1

SS/DEL1

Connect an external capacitor to LGND to program startup and Fault delay timing

Page 2

V3.01

IR3522

PIN# PIN SYMBOL

PIN DESCRIPTION

21

IIN1

Output 1 average current input from the output 1 phase IC(s). This pin is also used

to initialize Diode Emulation Mode in the phase IC(s).

Drives NMOS crowbar devices at VTT and VDDR rails.

22

23

CROWBAR

ROSC

Connect a resistor to LGND to program oscillator frequency and OCSET1, OCSET2,

and VREF bias currents. Oscillator frequency equals switching frequency per phase.

The pin voltage is 0.6V during normal operation.

24

25

LGND

Local Ground for internal circuitry and IC substrate connection.

Clock output at switching frequency multiplied by phase number. Connect to CLKIN

pins of phase ICs.

CLKOUT

26

PHSOUT

Phase clock output at switching frequency per phase. Connect to PHSIN pin of the

first phase IC.

27

28

PHSIN

VCCL

Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.

Output of the voltage regulator, and power input for clock oscillator circuitry. Connect

a decoupling capacitor to LGND.

29

30

31

VID0

VID1

Digital input to program one of four power-up VREF1 VDD reference values.

Connect to LGND for logic “0”, float for logic “1”

Digital input to program one of four power-up VREF1 VDD reference values.

Connect to LGND for logic “0”, float for logic “1”

PGOOD

Open collector output that drives low during startup and under any external fault

condition. The Power Good function also monitors output voltages and this pin will

drive low if any of the voltage planes are outside of the specified limits. Connect

external pull-up.

SCL (Serial Clock) is an open drain output of the I²C controller and input to IR3522.

This pin requires an external bias voltage and should not be floated.

32

SCL

Page 3

V3.01

IR3522

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications are not implied. All voltages are absolute voltages referenced to the

LGND pin.

Operating Junction Temperature……………..0 to 150^oC

Storage Temperature Range………………….-65^oC to 150^oC

ESD Rating………………………………………HBM Class 1C JEDEC Standard

MSL Rating………………………………………2

Reflow Temperature…………………………….260^oC

PIN #

1

PIN NAME

SDA

V_MAX

V_MIN

I_SOURCE

1mA

5mA

1mA

25mA

1mA

5mA

1mA

25mA

1mA

5mA

35mA

1mA

20mA

100mA

10mA

1mA

I_SINK

10mA

1mA

10mA

1mA

25mA

1mA

25mA

1mA

10mA

1mA

100mA

10mA

1mA

20mA

1mA

20mA

1mA

8V

-0.3V

-0.5V

-0.3V

n/a

2

PGBIAS

ENABLE

IIN2

8V

3

3.5V

4

8V

5

ADDR1

ADDR2

OCSET2

EAOUT2

FB2

3.5V

6

3.5V

7

8V

8

8V

9

8V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

VOUT2

VOSEN2+

VOSEN2-

VOSEN1-

VOSEN1+

VOUT1

FB1

8V

1.0V

8V

EAOUT1

OCSET1

VREF1

SS/DEL1

IIN1

8V

3.5V

8V

V(VCCL) + 1.1 V

8V

CROWBAR

ROSC

8V

LGND

n/a

CLKOUT

PHSOUT

PHSIN

8V

-0.3V

8V

VCCL

8V

VID0

8V

VID1

PGOOD

SCL

VCCL + 0.3V

8V

Page 4

V3.01

IR3522

RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN

4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN-x ≤ 0.3V, 0 ^oC ≤ T_J≤ 100 ^oC, 7.75 kΩ ≤ ROSC ≤ 50 kΩ, CSS/DEL1 = 0.1uF

ELECTRICAL CHARACTERISTICS

The electrical characteristics table list the spread of critical values that are guaranteed to be within the recommended

operating conditions (unless otherwise specified). Typical values represent the median values, which are related to 25°C.

PARAMETER

SVID Interface

SCL & SDA Input Thresholds

TEST CONDITION

MIN

TYP

MAX UNIT

Threshold Increasing

1.265

1.04

150

-5

1.325

1.1

225

0

1.385

1.16

300

5

V

Threshold Decreasing

Threshold Hysteresis

0V ≤ V(x) ≤ 3.5V, SDA not asserted

I(SDA)= 3mA

mV

uA

mV

ns

Bias Current

SDA Low Voltage

SDA Output Fall Time

20

300

250

0.7 x VDD to 0.3 x VDD, 1.425V ≤ VDD ≤

1.9V, 10 pF ≤ Cb ≤ 400 pF,

Cb=capacitance of one bus line (Note 1)

20+ 0.1

xCb(pF)

Pulse width of spikes suppressed Note 1

by the input filter

85

260

550

ns

ADDRx Internal Pull-up

ADDRx Threshold Voltage

ADDRx Float Voltage

Pull-up to 3.3 V typical

50

1.38

3.1

100

1.65

3.3

250

1.94

3.5

kΩ

V

Oscillator

PHSOUT Frequency

-10%

See

Figure 2

0.600

+10%

kHz

ROSC Voltage

0.57

0.630

1

V

CLKOUT High Voltage

I(CLKOUT)= -10 mA, measure V(VCCL) –

V(CLKOUT).

I(CLKOUT)= 10 mA

CLKOUT Low Voltage

PHSOUT High Voltage

1

V

I(PHSOUT)= -1 mA, measure V(VCCL) –

V(PHSOUT)

I(PHSOUT)= 1 mA

PHSOUT Low Voltage

1

V

PHSIN Threshold Voltage

Compare to V(VCCL)

30

50

70

%

Remote Sense Differential Amplifiers

Unity Gain Bandwidth

Input Offset Voltage

Note 1

3.0

6.4

9.0

MHz

mV

1.025 V ≤ V(VOSEN1+) - V(VOSEN1-) ≤

1.6125 V, 385mV ≤ V(VOSEN2+) -

V(VOSEN2-) ≤ 1.021 V, Note 2

-3

0

3

Source Current

Sink Current

1.025 V ≤ V(VOSEN1+) - V(VOSEN1-) ≤

1.6125 V, 385mV ≤ V(VOSEN2+) -

V(VOSEN2-) ≤ 1.021 V

1.025 V ≤ V(VOSEN1+) - V(VOSEN1-) ≤

1.6125 V, 385mV ≤ V(VOSEN2+) -

V(VOSEN2-) ≤ 1.021 V

3

300

2

7

450

4

15

650

8

mA

uA

Slew Rate

1.025 V ≤ V(VOSEN1+) - V(VOSEN1-) ≤

1.6125 V, 385mV ≤ V(VOSEN2+) -

V/us

uA

V(VOSEN2-) ≤ 1.021 V

Note 1.

VOSEN+ Bias Current

VOSEN- Bias Current

1.025 V ≤ V(VOSEN1+) - V(VOSEN1-) ≤

1.6125 V, 385mV ≤ V(VOSEN2+) -

V(VOSEN2-) ≤ 1.021 V

1.025 V ≤ V(VOSEN1+) - V(VOSEN1-) ≤

1.6125 V, 385mV ≤ V(VOSEN2+) -

V(VOSEN2-) ≤ 1.021 V, All VID Codes

V(VCCL) =7V

30

50

uA

Low Voltage

High Voltage

40

mV

V

V(VCCL) – V(VOUTx)

1.2

1.8

2.3

Page 5

V3.01

IR3522

PARAMETER

Soft Start and Soft Stop

Start Delay

TEST CONDITION

MIN

TYP

MAX UNIT

Measure Enable to EAOUT1 activation

Measure Enable activation to PGOOD

1

3

2.9

8

3.5

13

ms

V

Start-up Time

SS/DEL1 to FB1 Input Offset

Voltage

Charge Current

With FB1 = 0V, adjust V(SS/DEL1) until

EAOUT1 drives high

0.7

1.4

1.9

-20

25

-45

55

4

-90

105

4.2

µA

V

Soft Stop Discharge Currents

Charge Voltage

3.7

150

Discharge Comp. Threshold

Delay Comparator Threshold

220

80

300

mV

Relative to Charge Voltage, SS/DELx

rising Note 1

Delay Comparator Threshold

Relative to Charge Voltage, SS/DELx

falling Note 1

Note 1

120

mV

Delay Comparator Hysteresis

IINx Bias Current

40

0

mV

uA

mV

V

-1

330

310

15

1

SRD Comp. Rise Threshold

SRD Comp. Fall Threshold

SRD Comp Hysteresis

IIN1 High Voltage

390

360

30

440

425

50

Measure V(VCCL)-V(IIN1)

0

1.2

Error Amplifiers

VOUT1 System Set-Point

Accuracy

VOUT2 Tracking Accuracy

(Deviation from Table 2 and per test

circuit in Figures 2A)

-0.5

-1.0

-1

0.5

1.0

1

%

(Deviation from Table 2, and 3 per test

circuit in Figures 2B)

Input Offset Voltage

Measure V(FB1) – V(VREF1).

Measure V(FB2) – V(VOUT1)/2. Note 2

0

mV

FB1, FB2 Bias Currents

DC Gain

-1

100

20

0

1

µA

dB

Note 1

110

30

135

40

Bandwidth

MHz

V/µs

mA

mV

Slew Rate

5.5

0.4

5.0

500

12

20

Sink Current

0.85

8.5

780

120

300

1.2

12.0

950

250

600

Source Current

Maximum Voltage

Minimum Voltage

Measure V(VCCL) – V(EAOUTx)

Open Control Loop Detection

Threshold

Measure V(VCCL) - V(EAOUTx),

Relative to Error Amplifier maximum

voltage.

125

Open Control Loop Detection

Delay

FB2 Activation Voltage

Measure PHSOUT pulse numbers from

V(EAOUTx)=V(VCCL) to PGOOD = low.

With FB2 grounded, V(VOUT1)/2 when

EAOUT2 drives high

8

Pulses

mV

40

70

100

VREF1 Reference

2000*Vrosc(V)

/ ROSC(kΩ)

Source and Sink Currents

Includes I(OCSET1) and I(OCSET2)

-8%

+8%

µA

POWER GOOD (PGOOD) Output

Under Voltage Threshold - Voutx

Decreasing

VOUT1 referenced to VREF1

VOUT2 referenced to VOUT1/2

VOUT1 referenced to VREF1

VOUT2 referenced to VOUT1/2

-365

-325

5

-315

-275

53

-265

-225

110

mV

Under Voltage Threshold - Voutx

Increasing

Under Voltage Threshold

Hysteresis

Output Voltage

I(PGOOD) = 3mA

150

0

300

10

mV

µA

V

Leakage Current

V( PGOOD ) = 5.5V

PGBIAS Activation Threshold

PGBIAS Clamp Voltage

I(PGBIAS)max

I( PGOOD )=2mA, V(PGOOD) = 300mV

I(PGBIAS) = 100uA

2

3.5

6.5

100

3

4.5

V

uA

Page 6

V3.01

IR3522

PARAMETER

TEST CONDITION

MIN

230

TYP

MAX

UNIT

Over Voltage Protection (OVP) Comparators

VOUT1 Threshold Voltage

VOUT2 Threshold Voltage

CROWBAR

Compare to V(VREF1)

260

0

300

20

mV

Compare to V(VREF1)

-20

VOUT1 Propagation Delay to

CROWBAR

Measure time from V(VOUT1) >

V(VREF1) (500 mV overdrive) to

V(CROWBAR) transition to > 2 V with

1nF.

40

100

ns

VOUT2 Propagation Delay to

CROWBAR

Measure time from V(VOUT2) >

V(VREF1) (250 mV overdrive) to

V(CROWBAR) transition to > 2 V with

1nF.

CROWBAR Pull-up Resistance,

Active

To VCCL

5

15

65

60

Ω

kΩ

Ω

CROWBAR Passive Pull Down

Resistance

12

25

20

CROWBAR Active Pull Down

Resistance to LGND

Track Fault Comparator

Threshold Voltage

Compare VOUT1 to VOUT2

0.99

1.06

1.13

V

Propagation Delay to CROWBAR

Measure time from V(VOUT1) >

V(VOUT1) (1.2V overdrive) to

V(CROWBAR) transition to > 0.9 *

V(VCCL).

90

180

ns

Open Sense Line Detection

Sense Line Detection Active

Comparator Threshold Voltage

Sense Line Detection Active

Comparator Offset Voltage

VOSEN+ Open Sense Line

Comparator Threshold

150

35

200

62.5

89.0

0.40

500

250

90

mV

%

V(VOUTx) < [V(VOSENx+) – V(LGND)] /

2

Compare to V(VCCL)

86.5

0.36

200

91.5

0.44

700

VOSEN- Open Sense Line

Comparator Threshold

V

Sense Line Detection Source

Currents

V(VOUTx) = 100mV

uA

VIDx

VID0 & VID1 Input Thresholds

Internal Pull-up

Float Voltage

1.38

50

1.65

100

3.3

1.94

250

3.5

V

kΩ

V

Pull-up to 3.3 V typical

3.1

ENABLE

Threshold Increasing

Threshold Decreasing

Threshold Hysteresis

Bias Current

1.38

0.8

470

-5

1.65

0.99

620

0

1.94

1.2

770

5

V

mV

uA

ns

0V ≤ V(x) ≤ 3.5V

Blanking Time

Noise Pulse < 100ns will not register an

ENABLE state change. Note 1

75

250

400

Over-Current Comparators

Input Offset Voltage

1V ≤ V(OCSETx) ≤ 3.3V

-35

0

Vrosc(V)*1000/

Rosc(KΩ)

35

mV

OCSET Bias Current

-5%

+5

%

µA

2048-4096 Count Threshold

1024-2048 Count Threshold

ROSC value, Note 1

11.3

14.4

16

20

23.1

kΩ

29.1

Page 7

V3.01

IR3522

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

VCCL

Supply Current

3.5

4.20

3.8

7

15

4.7

mA

V

UVLO Start Threshold

UVLO Stop Threshold

Hysteresis

4.43

3.99

0.42

4.3

V

0.36

0.46

V

Note 1: Guaranteed by design, but not tested in production

Note 2: VDACx Outputs are trimmed to compensate for Error & Amp Remote Sense Amp input offsets

Bold Letters: Critical specs

SYSTEM SET POINT TEST

Converter output voltage is determined by the system set point voltage which is the voltage that appears at the

FBx pins when the converter is in regulation. The set point voltage includes error terms for the VDAC digital-to-

analog converters, the Error Amp input offsets, and the Remote Sense input offsets. The voltage appearing at

the VDACx pins is not the system set point voltage. System set point voltage test circuits for Outputs 1 and 2 are

shown in Figures 2A and 2B.

ERROR

IR3522

AMPLIFIER

+

VREF1

EAOUT1

FB1

BUFFER

-

AMPLIFIER

+

ISOURCE

ISINK

"FAST"

VDAC

VREF1

OCSET1

-

ROCSET1

IOCSET1

IROSC

RVREF1

CVREF1

ROSC BUFFER

AMPLIFIER

CURRENT

SOURCE

IROSC

0.6V

LGND

+

-

GENERATOR

RROSC

ROSC

VOUT1

EAOUT

SYSTEM

REMOTE SENSE

SET POINT

VOSNS-

VOLTAGE

AMPLIFIER

+

VOSEN1+

VOSEN1-

-

Figure 2A - Output 1 System Set Point Test Circuit

ERROR

IR3522

AMPLIFIER

+

2

VOUT1

EAOUT2

FB2

-

VREF_TRACK

VOUT2

EAOUT

SYSTEM

REMOTE SENSE

SET POINT

VOSNS-

VOLTAGE

AMPLIFIER

2

VOSEN2+

VOSEN2-

+

-

Figure 2B - Output 2 System Set Point Test Circuit

Page 8

V3.01

IR3522

SYSTEM THEORY OF OPERATION

PWM Control Method

The PWM block diagram of the xPHASE3^TMarchitecture is shown in Figure 3. Feed-forward voltage mode control

with trailing edge modulation is used to provide system control. A voltage type error amplifier with high-gain and

wide-bandwidth, located in the Control IC, is used for the voltage control loop. The feed-forward control is

performed by the phase ICs as a result of sensing the Input voltage (FET’s drain voltage). The PWM ramp slope

will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage

can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related

to changes in load current.

.

GATE DRIVE

VOLTAGE

VIN

IR3522 CONTROL IC

PHSOUT

IR3506 PHASE IC

CLOCK GENERATOR

CLKOUT

CLKIN

PHSIN

CLK

D

Q

VCCH

PWM

LATCH

GATEH

CBST

PHSOUT

PHSIN

VOSNS1+

VOUT1

S

PWM

SW

RESET

COMPARATOR DOMINANT

COUT

-

R

VCCL

EAIN

+

GND

GATEL

PGND

ENABLE

REMOTE SENSE

AMPLIFIER

+

-

+

-

VID6

VOSNS1-

RAMP

VOUT1

VREF1

LGND

DISCHARGE

CLAMP

SHARE ADJUST

ERROR AMPLIFIER

ERROR

+

AMPLIFIER

VREF1_FAST

CURRENT

SENSE

+

-

EAOUT1

IOUT

VID6

-

CSIN+

CSIN-

-

AMPLIFIER

+

3K

RCP1

CCS RCS

VID6

VID6₊

+

-

CCP12

RFB12

CFB1

RFB11

CCP11

FB1

DACIN

PHSOUT

CLKIN

IR3506 PHASE IC

CLK

D

Q

VCCH

PWM

LATCH

GATEH

CBST

PHSIN

EAIN

S

PWM

RESET

COMPARATOR DOMINANT

SW

-

R

VCCL

+

GATEL

PGND

ENABLE

+

-

VID6

RAMP

DISCHARGE

CLAMP

SHARE ADJUST

ERROR AMPLIFIER

+

CURRENT

SENSE

IOUT

VID6

-

CSIN+

CSIN-

-

AMPLIFIER

+

3K

CCS RCS

VID6

VID6₊

+

-

DACIN

Figure 3 - PWM Block Diagram

Frequency and Phase Timing Control

The system oscillator is located in the Control IC and is programmable from 250 kHz to 9 MHZ by an external

resistor. The control IC clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the

phase ICs is controlled by a daisy chain loop. The control IC phase clock output (PHSOUT) is connected to the

phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the

second phase IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to complete the

loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects

the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 4

shows the phase timing for a four phase converter.

Page 9

V3.01

IR3522

Control IC CLKOUT

(Phase IC CLKIN)

Control IC PHSOUT

(Phase IC1 PHSIN)

Phase IC1

PWM Latch SET

Phase IC 1 PHSOUT

(Phase IC2 PHSIN)

Phase IC 2 PHSOUT

(Phase IC3 PHSIN)

Phase IC 3 PHSOUT

(Phase IC4 PHSIN)

Phase IC4 PHSOUT

(Control IC PHSIN)

Figure 4 Four Phase Oscillator Waveforms

PWM Operation

The PWM comparator is located in the phase IC. Upon receiving a clock falling edge and PHSIN high, the PWM

latch is set and the PWM ramp voltage begins to increase and turning off the low side driver The high side driver is

then turned on once GATEL falls below 1.0V (non-overlap time). When the PWM ramp voltage exceeds the error

amplifier’s output voltage, the PWM latch is reset and the internal ramp capacitor is quickly discharged to the output

voltage of share adjust amplifier. And, the ramp will remains discharged until the next clock pulse. This reset turns

off the high side driver and enables the low side driver after the non-overlap time ((GATEH-SW) < 1.0V).

The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in

response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step

increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode

input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This

arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required.

It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of

most systems. The inductor current will increase much more rapidly than decrease in response to load transients.

This control method is designed to provide “single cycle transient response” where the inductor current changes in

response to load transients within a single switching cycle maximizing the effectiveness of the power train and

minimizing the output capacitor requirements. An additional advantage of this architecture is that differences in

ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.

Figure 5 depicts PWM operating waveforms under various conditions.

Page 10

V3.01

IR3522

PHASE IC

CLOCK

PULSE

EAIN

PWMRMP

GATEH

GATEL

VDAC

STEADY-STATE

OPERATION

DUTY CYCLE INCREASE

DUE TO LOAD

DUTY CYCLE DECREASE

DUE TO VIN INCREASE

(FEED-FORWARD)

DUTY CYCLE DECREASE DUE TO LOAD

DECREASE (BODY BRAKING) OR FAULT

(VCC UV, OCP, VID FAULT)

STEADY-STATE

OPERATION

INCREASE

Figure 5 PWM Operating Waveforms

Lossless Average Inductor Current Sensing

Inductor current can be sensed by connecting a series RC network in parallel with the inductor and measuring the

voltage across the capacitor, as shown in Figure 6. The equation of this sensing network is,

(

)

1+ s L R_L

^L1+ sR_CSC_CS

1

v_C(s) = v_L(s)

= i_L(s)R

.

1+ sR_CSC_CS

Usually, the resistor Rcs and capacitor Ccs are chosen so that the RC time constant equals the time constant of the

inductor which is the inductance L divided by the inductor’s DCR (RL). If the two time constants match, the voltage

across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor

with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC

current, but affects the AC component of the inductor current.

L

v

L

R

L

i

O

V

CS

C

O

C

Current

Sense Amp

c

vCS

CSOUT

Figure 6 Inductor Current Sensing and Current Sense Amplifier

The advantage of sensing the inductor current versus high side or low side sensing is that actual output current

being delivered to the load is obtained rather than peak or sampled information about the switch currents. The

output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in

series with the inductor, this is the only sense method that can support a single cycle transient response. Other

methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).

Page 11

V3.01

IR3522

An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer

from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency

variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and

the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier

bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional

sources of peak-to-average errors.

Current Sense Amplifier

A high speed differential current sense amplifier is located in the IR3506 phase IC, as shown in Figure 7. Its gain is

nominally 32.5 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be considered when setting the

controller’s current limit.

The current sense amplifier can accept positive differential input up to 50 mV and negative up to -10 mV before

clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and

other phases through an on-chip 3KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are

tied together and the voltage on the share bus represents the average current through all the inductors and is used

by the control IC for current limit protection.

Average Current Share Loop

Current sharing between phases of the converter is achieved by the average current share loop in each phase IC.

The output of the current sense amplifier is compared with average current at the share bus. If a single phase

current is smaller than the average current, the phase IC share adjust amplifier will pull down the starting point of

the PWM ramp thereby increasing its duty cycle and output current. Conversely, a phase current larger than the

average current will pull up the PWM starting point decreasing its duty cycle and output current. The current share

amplifier is internally compensated so that the crossover frequency, of the current share loop, is much slower than

that of the voltage loop and the two loops do not interact.

Page 12

V3.01

IR3522

IR3522 THEORY OF OPERATION

Block Diagram

The Block diagram of the IR3522 is shown in Figure 7. The following discussions are applicable to either output

plane unless otherwise specified.

ENABLE COMPARATOR

OPEN DAISY

-

ENABLE

250nS

OPEN SENSE

+

BLANKING

1.65V

1V

OPEN CONTROL

TRACK_FLT

OV1-2

2

1

VCCL

DIS

INTERNAL VCCL UVL

CIRCUIT BIASCOMPARATOR

+

VCCL

CROWBAR

VCCL

LGND

VCCL UVLO

-

SVI_OFF

25k

4.43V

3.99V

ENABLE

INTERNAL_CROWBAR

Fault Latch

PGBIAS

PGOOD

OC TIMEOUT

DLY_OUT

Control Logic

VCCL

SOFT STOP

UV2

UV1

SS_DISCHARGED

SRD_PRESET#

3.9V

ICHG

45uA

OC LIMIT COMPARATOR 1

+

IIN1

OC1

SS Comparators

-

OC DELAY

COUTER

OCSET1

SS/DEL1

IDCHG

55uA

IROSC

OC2

SRD_PRESET#

SRD PRESET

DLY_OUT

PHSOUT

IROSC

OC LIMIT COMPARATOR2

+

IIN2

-

OCSET2

VCCL

OPEN CONTROL

1

IROSC

OPEN CONTROL

2

Open Control

Loop

ERROR

AMPLIFIER 1

AMPLIFIER 2

INTERNAL_CROWBAR

SOFT ST ART

CLAMP

+

DIS

VREF_TRACK

-

+

DIS

T RACK FAULT

EAOUT2

FB2

+

COMPARAT OR

EAOUT1

FB1

+

-

70mV

1.4V

VREF1

-

TRACK_FLT

-

VOUT1

SS/DEL

+

275mV

315mV

VOUT2 UV

OV1

COMPARATOR

+

-

OV1_2

OVER VOLT AGE

COMPARATOR 1

VOUT1 UV

COMPARATOR

+

UV2

275mV

315mV

260mV

-

+

1.06V

UV1

-

OVER VOLTAGE

COMPARAT OR 2

VREF1

-

OV2

REMOTE SENSE

AMPLIFIER 1

+

25k

OPEN SENSE

VOUT2

VOUT1

25k

+

-

VOSEN1+

VOSEN1-

REMOTE SENSE

+

-

VOSEN2+

VOSEN2-

AMPLIFIER 2

25k

OPEN

DETECT PULSE1

SS_DISCHARGED

OPEN SENSE

LINE DETECT

CIRCUIT 1

SENSE LINE

DETECT

DETECT PULSE1

SS_DISCHARGED

CIRCUIT 2

VREF BUFFER

AMPLIFIER

D/A CONVERT ER

+

VOUT1

SVI (Serial VID Interface)

+

VID7

VID3

ISOURCE

TRACK

VID3

IROSC

SCL

SDA

VREF1

CONTROL

VREF_TRACK

-

ISINK

VID7

VREF

VID3

+

-

CONTROL

VREF1_FAST

-

.

950mV

650mV

VID7

SVI ADDRESS

3.3V

2X IROSC

VID7

VID1 OFF

VID2 OFF

SVI_OFF

VALID I2C

COMMAND

OVERRIDE

ARRIVED

+

-

ADDR1

ADDR2

VID7

+

-

OPEN

VCCL UVLO

^DAISYFAULT

POWER-UP VREF1

CONTROL

ROSC BUFFER

AMPLIFIER

+

VID0

IROSC

CURRENT

SOURCE

VREF1 CODE

+

-

VID1 VID0 VREF1

STORAGE LATCH

VID1

VID0

GENERATOR

PHSIN

PHSOUT

0

1

0

1

0

1

1.05V

1.2V

-

0.6V

+

-

VID7

R

1.35V

1.5V

CLKOUT

Q

D

ROSC

ENABLE

1.65V

VID7

CLK

CLKOUT PHSIN PHSOUT

Figure 7 Block Diagram

Page 13

V3.01

IR3522

Serial VID Control

The IR3522 outputs can be controlled via a serial VID Interface (SVID) which employs a Fast Mode I²C protocol.

VREF1, which is the reference for VOUT1, can also be programmed to boot-up to one of four codes through pins

VID0 and VID1 prior to ENABLE rising if SVID communication is not available prior to power-up. Refer to Table 4.

Pins VID0 and VID1 have internal 100K pull-up resistors to an internal 3.3V. The SVID controls both the VOUT1

and VOUT2 margining (see Table 2 or 3) depending on which serial address precedes the data string. See Table 1

for proper address codes. If the top address is used, then both outputs will coincide with the values in Table 2

depending on data code used, where VOUT2 is always half the value of VOUT1. The second address will only

have an effect on VOUT2’s amplitude (margining +26.67 % and -25 %) as defined in Table 3. Since there is no

internal compensation for Vref_track (VOUT2 reference), It is recommended that VOUT2 be incremented to its

final value to prevent possible output overshoot. If no serial command is received before an enable event (ENABLE

pin going high), the controller’s VOUT1 will startup in a default state as indicated in Table 4 and VOUT2 to 0.75 V

(half of VDAC).

Addresses and data are serially transmitted in 8-bit words. The first data bit of the SVID data word represents the

PSI_L bit and will be ignored by the IR3522 therefore this system will never enter a power-saving mode. The

remaining data bits SVID[6:0] select the desired VOUTx regulation voltage as defined in Table 2 or Table 3

depending address chosen. VOUT1 is divided in half by an internal resistor divider to provide a reference voltage

(Vref_track) for VOUT2. This allows VOUT2 to track VOUT1 maintaining a desired differential voltage. SVID [6:0]

are the inputs to the Digital-to-Analog Converter (VREF) which then provides an analog reference voltage to the

transconductance type buffer amplifier. This VREF buffer provides a system reference on the VREF1 pin. The

VREF1 voltage along with error amplifier and remote sense differential amplifier input offsets are post-package

trimmed to provide a 0.5% system set-point accuracy, as measured in Figures 2A and 2B. VREF1 slew rates are

programmable by properly selecting external series RC compensation networks located between the VREF1 and

the LGND pins. The VREF1 source and sink currents are derived off the external oscillator frequency setting

resistor, R_ROSC

.

The programmable slew rate enables the IR3522 to smoothly transition the regulated output

voltage throughout VID transitions resulting in a power supply input and output capacitor inrush currents, along with

output voltage overshoot, to be well controlled.

The ADDR1 and ADDR2 pins (5, 6) are reserved for controller addressing. These pins have internal 100K pull-up

resistors to an internal 3.3V. By floating or shorting to ground these two pins, four different controller identification

address states can be made. By setting bit 2 and 3 of the SVI address codes (see Figure 8) to the desired controller

address, a CPU can communicate with one controller while ignoring other controllers sharing the same SVID bus.

SVI Address [6:0] + Wr

6

5

4

ADDR1 ADDR2

1

0

WR

Figure 8 Bit 2 and 3 are use for Controller addressing

The SCL and SDA pins require external pull-up biasing and should not be floated. Biasing of pins SDA, SCL, VID0,

VID1, ADDR1 and ADDR2 prior to applying VCCL is acceptable. For Write, WR=0.

SVI Address

SVI Address [6:0] + Wr

[bit6 :bit5 : bit4 : ADDR1 _ ADDR2 : bit1 : bit0 : WR]

Description

1101_1100 in binary or D_C in hex if ADDR1 and ADDR2 pins are high

1101_1010 in binary or D_A in hex if ADDR1 and ADDR2 pins are high

BOLD indicates the pin states of ADDR1 and ADDR2, in this case high or floating.

Set VID only Output 1

Set VID only Output 2

Table 1 – SVI Address

Page 14

V3.01

IR3522

VDDR (VREF1) SVID Codes and Resulting VTT Default (50%) Voltage

Hex

VDDR SVID Codes

VDDR, VREF1, VOUT1

Typical Target

1.6125

1.6

VOUT2

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

X000_0000

X000_0001

X000_0010

X000_0011

X000_0100

X000_0101

X000_0110

X000_0111

X000_1000

X000_1001

X000_1010

X000_1011

X000_1100

X000_1101

X000_1110

X000_1111

X001_0000

X001_0001

X001_0010

X001_0011

X001_0100

X001_0101

X001_0110

X001_0111

X001_1000

X001_1001

X001_1010

X001_1011

X001_1100

X001_1101

X001_1110

X001_1111

X010_0000

X010_0001

X010_0010

X010_0011

X010_0100

X010_0101

X010_0110

X010_0111

X010_1000

X010_1001

X010_1010

X010_1011

X010_1100

X010_1101

X010_1110

X010_1111

x1xx_xxxx

0.80625

0.8

1.5875

1.575

1.5625

1.55

1.5375

1.525

1.5125

1.5

1.4875

1.475

1.4625

1.45

1.4375

1.425

1.4125

1.4

1.3875

1.375

1.3625

1.35

1.3375

1.325

1.3125

1.3

1.2875

1.275

1.2625

1.25

1.2375

1.225

1.2125

1.2

0.79375

0.7875

0.78125

0.775

0.76875

0.7625

0.75625

0.75

0.74375

0.7375

0.73125

0.725

0.71875

0.7125

0.70625

0.7

0.69375

0.6875

0.68125

0.675

0.66875

0.6625

0.65625

0.65

0.64375

0.6375

0.63125

0.625

0.61875

0.6125

0.60625

0.6

1.1875

1.175

1.1625

1.15

1.1375

1.125

1.1125

1.1

1.0875

1.075

1.0625

1.05

0.59375

0.5875

0.58125

0.575

0.56875

0.5625

0.55625

0.55

0.54375

0.5375

0.53125

0.525

1.0375 0.51875

1.025 0.5125

VID OFF, no change in VREF or VTT

Table 2: VDDR Margin Codes and resulting 50% Vtt Tracking

(VIDX pin controlled codes are in Gray)

Page 15

V3.01

IR3522

VTT Margining Range Codes

Hex VTT SVID

Codes

% Change % Change

from Default from VOUT1

0

1

x000_0000

x000_0001

x000_0010

x000_0011

x000_0100

x000_0101

x000_0110

x000_0111

x000_1000

x000_1001

x000_1010

x000_1011

x000_1100

x000_1101

x000_1110

x000_1111

x001_0000

x001_0001

x001_0010

x001_0011

x001_0100

x001_0101

x001_0110

x001_0111

x001_1000

x001_1001

x001_1010

x001_1011

x001_1100

x001_1101

x001_1110

x001_1111

x1xx_xxxx

26.67

25

63.16

62.35

61.52

60.70

59.87

59.06

58.23

57.40

56.59

55.78

54.94

54.12

53.28

52.46

51.64

50.82

50

2

23.33

21.67

20

3

4

5

18.33

16.67

15

6

7

8

13.33

11.67

10

9

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

8.33

6.67

5

3.33

1.67

0

-1.67

-3.33

-5

49.16

48.31

47.46

46.61

45.78

44.93

44.08

43.25

42.42

41.58

40.74

39.90

39.08

38.21

-6.67

-8.33

-10

-11.67

-13.33

-15

-16.67

-18.33

-20

-21.67

-23.33

-25

37.44

VID OFF

Table 3 – Vtt Margining (Default in Gray)

Pre-ENABLE VREF1 Codes

VID1

VID0

VDDR

1.05

1.2

0

1

0

1

0

1

1.35

1.5

Table 4 – Pre-Enable VDDR program Codes

Page 16

V3.01

IR3522

Response

Open

Daisy

Open

Sense

Open

Control

Tracking UVLO

Fault (VCCL)

OC

Over

Voltage

Disable VID_OFF UVLO

(Vout)

SVID

Latch

Reset

UVLO CLEARED Latch

Recycle VCCL

ENABLE CLEARED Latch

SS Latch

No

Recycle EN or Cycle VID_OFF through

SVID

SS discharge below

0.22V

Outputs

Affected

Both

none

No

Disables

EA

Yes

No

Soft Stop

CROWBAR

No

Yes

No

Yes

Flags

PGood

Yes

Delays

32

Clock

Pulses

No

8

PHSOUT

No

Delay

Counter

No

250ns

No

Pulses

Blanking

Time

Additional

Yes,

Flagged

IIN1 pin is pulled-up to VCCL when SS discharge below 0.35V. This action latches on the Phase IC(s)

Diode Emulation Mode which insure proper current sharing during soft start**.

Response

*Pulse number range depends on Rosc value selected (See Specifications Table)

** IIN1 is pulled low when SS charges above 0.4V.

Table 5 – IR3522 Fault protocol

.

Page 17

V3.01

IR3522

Serial VID Interface Protocol and VID-on-the-fly Transition

The IR3522 supports the SVI bus protocol which is based on Fast-mode I²C. SVID commands from a processor

are communicated through SVID bus pins SCL and SDA.

The SMBus send byte protocol is used by the IR3522 VID-on-the-fly transactions. The IR3522 will wait until it

detects a start bit which is defined as an SDA falling edge while SCL is high. A 7bit address code plus one write bit

(low) should then follow the start bit. This address code will be compared against an internal address table and the

IR3522 will reply with an acknowledge ACK bit if the address is one of the two stored addresses otherwise the ACK

bit will not be sent out. The SDA pin is pulled low by the IR3522 to generate the ACK bit. Table 1 has the list of

addresses recognized by the IR3522.

The processor should then transmit the 8-bit data word immediately following the ACK bit. The first bit is ignored

(bit 7). The IR3522 replies again with an ACK bit once the data is received. If the received data is not a VID-OFF

command, the IR3522 immediately changes the VREF1 analog outputs to the new target. VOUT1 and VOUT2 then

slew to the new VID voltages. See Figure 9 for a send byte example.

Figure 9 Send Byte Example

Page 18

V3.01

IR3522

Remote Voltage Sensing

VOSEN_X+ and VOSEN_X- are used for remote sensing and are connected directly to the load. The remote sense

differential amplifiers are high speed, have low input offset and low input bias currents to ensure accurate voltage

sensing and fast transient response.

Start-up Sequence

The IR3522 is designed as a chipset with the IR3506 Phase IC to achieve output voltage tracking. VOUT2’s

internal reference (VREF_TRACK) is generated by a divided-by-half internal resistor divider. This will ensure

VOUT2 remains half the value of VOUT1 preventing possible damage to some DDR system’s microprocessors. In

addition, a track-fault comparator is implemented to monitor both outputs which will further guarantee the outputs

remain at least 1.0 V apart and will generate a fault if this limit is surpassed, further protecting the DDR system.

When VCCL is applied to the IC and the SS/DEL is below 0.3V, IIN1 (only) is pulled up to VCCL through an internal

PFET enabling a diode emulation preset latch on the IR3506 phase IC. Diode emulation mode ensures proper

current sharing during system soft-start by turning off the bottom sync FET when negative inductor current is

sensed via the CSIN- and CSIN+ pins. The IIN1 pin is release once SS/DEL charges above 0.3 V. Once VOUT1

reaches 75% of its final operating value, the diode emulation mode is reset allowing the phase ICs to sink current.

The IR3522 has a programmable soft-start and soft-stop function. The soft-start helps limit the surge current during

A

the converter start-up, whereas the soft-stop is needed to maintain output tracking during system turn-off.

capacitor connected between the SS/DEL and LGND pins controls timing. A constant source and sink current

control the charge and discharge rates of the SS/DEL.

Figure 10 depicts the SVID start-up sequence. When the ENABLE input is asserted and there are no faults, the

SS/DEL pin will begin charging. If the IC receives a SVID communication prior to the ENABLE pin going high, the

output ramps up to the program value listed in Table 2, otherwise the VOUT1 and VOUT2 default to 1.5 V and 0.75

V, respectively. The error amplifier output, EAOUT_x,is clamped low until SS/DEL reaches 1.4V. The error amplifier

will then regulate the converter’s output voltage to match the V(SS/DEL)-1.4V offset until the converter output

reaches the SVID code or default state. The SS/DEL voltage continues to increase until it rises above the threshold

of Delay Comparator where the PGOOD output is allowed to go high.

A low signal on the ENABLE or VID_OFF input immediately sets the fault latch, which causes the EAOUT pin to

drive low, thereby turning off the phase IC drivers. The PGOOD pin also drives low and SS/DEL discharges to 0.2V.

If the fault has cleared, the fault latch will be reset by the SS/DEL discharge comparator allowing another soft start

charge cycle to occur.

All other faults (See Table 5) will set a different fault latch that can only be reset by cycling ENABLE or the

VID_OFF SVID command. These faults discharge SS/DEL, pull down EAOUT_X, pull up CROWBAR to VCCLDRV

and drive PGOOD low. The CROWBAR circuit is design to drive an external NMOS device to pull the output

voltage to ground. This feature minimizes negative voltage undershoots at the output by reducing sync FET current

during fault events.

The converter can be disabled by pulling the SS/DEL pins below 0.6V

Page 19

V3.01

IR3522

VCCL

(6.8V)

ENABLE

Vtt Margining

VDDR Margining

CLOCK

SVID OFF COMMAND

SVID ON COMMAND

SVC

SVID TRANSITION

SVID ON COMMAND

SVD

READ

&

STORE

VREF1

SVID programmed voltage

VREF_TRACK

0.8V

VREF1/Track

Tracks

4.0V

3.92V

1.4V

SS/DEL

EAOUT1

EAOUT2

EAOUTx

VOUT1

Soft Stop

VOUT2

PGOOD

VOUT1 ON

THE FLY

MARGINING

SVID OFF TRANSITION SVID ON TRANSITION

VOUT2 ON

THE FLY

MARGINING

NORMAL

OPERATION

START

DELAY

TIME

STARTUP

Figure 10 SVID Start-up Sequence Transitions

Page 20

V3.01

IR3522

Over-Current Protection

The over current limit threshold is set by a resistor connected between OCSET_Xand VREF1 pin. An over current

fault is flagged after a delay programmed by Rocs (see Electrical Specification). The delay is required since over-

current conditions can occur as part of normal operation due to load transients or VID transitions.

If the IIN_Xpin voltage, which is proportional to the average current plus VREF1 voltage, exceeds the OCSETx

voltage, the OCDELAY counter starts counting the PHSOUT pulses. If the over-current condition persists long

enough for the counter to reach the program number, the fault latch will be set which will then pull the error

amplifier’s output low to stop phase IC switching and will also de-assert the PGOOD signal. The SS/DEL capacitor

will then discharge by a 55 uA current. The output current is not controlled during the delay time. This latch can only

reset by either recycling the ENABLE pin or VID_OFF command.

VCCL Under Voltage Lockout (UVLO)

The IR3522 monitors the VCCL supply voltage to determine if the amplitude is proper to adequately drive the top

and bottom gates. As VCCL begins to rise during power up, the IC is allowed to power up when VCCL reaches 4.43

V (Typical). The ENABLE CLEARED fault latches will be released. If VCCL voltage drops below 3.99V (Typical) of

the set value, the ENABLE CLEARED fault latch will be set.

VID OFF Codes

SVID OFF codes will turn off the converter keeping the error amplifiers active and discharging SS/DEL through the

50uA discharge current allowing the outputs to discharge in a control manner (soft-stop). Upon receipt of a non-off

SVID code the converter will turn on and transition to the voltage represented by the SVID as shown in Figure 10.

Power Good (PGOOD)

The PGOOD pin is an open-drain output and should have an external pull-up resistor. During soft start, PGOOD

remains low until the output voltage is in regulation and SS/DEL is above 3.9V. The PGOOD pin becomes low if any

fault is registered (see TABLE 5 for details). A high level at the PGOOD pin indicates that the converter is in

operation with no fault and ensures the output voltage is within regulation.

PGOOD monitors the output voltage. If any of the voltage planes fall out of regulation, PGOOD will become low, but

the VR continues to regulate its output voltages. Output voltage out-of-spec is defined as 315mV to 275mV below

nominal voltage. VID on-the-fly transition which is a voltage plane transitioning between one voltage associated with

one VID code and a voltage associated with another VID code is not considered to be out of specification.

Open Voltage Loop Detection

The output voltage range of error amplifier is continuously monitored to ensure the voltage loop is in regulation. If

any fault condition forces the error amplifier output above VCCL-1.08V for 8 PHSOUT switching cycles, the fault

latch is set. The fault latch can only be cleared by cycling the ENABLE or the VID_OFF command.

Enable Input

Pulling the ENABLE pin below 0.8V sets the Fault Latch. Forcing ENABLE to a voltage above 1.65V allows the

SS/DEL pin to begin a power-up cycle.

Over Voltage Protection (OVP)

Output over-voltage might occur due to a high side MOSFET short or if the output voltage sense path is

compromised. If the over-voltage protection comparators sense that either VOUT1 pin voltage exceeds VREF1 by

260mV or VOUT2 exceeds VREF1, the over voltage fault latch is set which pulls the error amplifier output low to

turn off the converter power stage. The IR3522 communicates an OVP condition to the system by raising the

CROWBAR pin voltage to within V(VCCL) – 0.2 V. With the error amplifiers outputs low, the low-side MOSFET

Page 21

V3.01

IR3522

turn-on within approximately 150ns. The low side MOSFET will remain low until the over voltage fault condition latch

cleared. This latch is cleared by cycling the ENABLE pin or the VID_OFF command.

The overall system must be considered when designing for OVP. In many cases the over-current protection of the

AC-DC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection

without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If

this is not possible, a fuse can be added in the input supply to the multiphase converter.

Open Remote Sense Line Protection

If either remote sense line VOSEN_X+ or VOSEN_X- is open, the output of Remote Sense Amplifier (VOUT_X) drops.

The IR3522 continuously monitors the VOUT_Xpin and if VOUT_Xis lower than 200 mV, two separate pulse currents

are applied to the VOSEN_X+ and VOSEN_X- pins to check if the sense lines are open. If VOSEN_X+ is open, a voltage

higher than 90% of V(VCCL) will be present at VOSEN_X+ pin and the output of Open Line Detect Comparator will

be high. If VOSEN_X- is open, a voltage higher than 400mV will be present at VOSEN_X- pin and the Open Line

Detect Comparator output will be high. With either sense line open, the Open Sense Line Fault Latch will be set to

force the error amplifier output low and immediately shut down the converter. SS/DEL will be discharged and the

Open Sense Fault Latch can only be reset by cycling the ENABLE pin or the VID_OFF command.

Open Daisy Chain Protection

The IR3522 checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and

detects the feedback at PHSIN pin. If no pulse comes back after 30 CLKOUT pulses, the pulse is restarted again. If

the pulse fails to come back the second time, the Open Daisy Chain fault is registered, and SS/DEL_Xis not allowed

to charge. The fault latch can only be reset by cycling the ENABLE pin or the VID_OFF command.

After powering up, the IR3522 monitors PHSIN pin for a phase input pulse equal or less than the number of phases

detected. If PHSIN pulse does not return within the number of phases in the converter, another pulse is started on

PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an Open Daisy Chain fault is

registered.

Phase Number Determination

After a daisy chain pulse is started, the IR3522 checks the timing of the input pulse at PHSIN pin to determine the

phase number.

Page 22

V3.01

IR3522

DESIGN PROCEDURES - IR3522 AND IR3506 CHIPSET

IR3522 EXTERNAL COMPONENTS

All the output components are selected using one output but suitable for both unless otherwise specified.

Oscillator Resistor RRosc

The only one oscillator of IR3522 generates square-wave pulses to synchronize the phase ICs. The switching

frequency of the each phase converter equals the PHSOUT frequency, which is set by the external resistor

RROSC, use Figure 11 to determine the RROSC value. The CLKOUT frequency equals the switching frequency

multiplied by the phase number.

PHSOUT FREQUENCY vs. RROSC

1600

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

5

10

15

20

25

30

35

40

45

50

55

RROSC (KOhm)

Figure 11 - PHSOUT Frequency vs. RROSC chart

Soft Start Capacitor CSS/DEL

The Soft Start capacitor CSS/DEL programs three different time parameters, soft start delay time, soft start time,

and soft stop time.

SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 10. Once the

ENABLE pin rises above 1.65V, there is a soft-start delay time TD1 during which SS/DEL pin is charged from

zero to 1.4V. Once SS/DEL reaches 1.4V the error amplifier output is released to allow the soft start. The soft

start time TD2 represents the time during which converter voltage rises from zero to SVID voltage (or default

voltage) and the SS/DEL pin voltage rises from 1.4V to SVID voltage plus 1.4V. Power good time, TD3, is the

time period from VR reaching the SVID voltage to the PGOOD signal being issued.

Calculate CSS/DEL based on the required soft start time TD2.

Page 23

V3.01

IR3522

TD2*45*10⁻⁶

TD2* I_CHG

(1)

C_{SS / DEL}

=

SVID

The soft start delay time TD1, power good time TD3, and soft stop time are determined by equation (2), (3) and

(4) respectively.

C_{SS / DEL}*1.4 C_{SS / DEL}*1.4

=

I_CHG

(2)

TD1 =

TD3 =

45*10⁻⁶

C_{SS / DEL}* (3.92 − SVIC −1.4) C_{SS / DEL}* (3.92 − SVID −1.4)

=

I_CHG

(3)

45 *10⁻⁶

C_{SS / DEL}* SVIS C_{SS / DEL}* SVID

=

I_CHG

(4)

TD4 =

55*10⁻⁶

VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC

The slew rate of VREF1 down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in

(5), where ISINK is the sink current of VREF1 pin. The resistor RVDAC is used to compensate VDAC circuit and is

determined by (6)

I _SINK

C_VDAC

=

(5)

SR_DOWN

3.2 ∗10⁻¹⁵

(6)

R_VDAC= 0.5 +

2

C_VDAC

Over Current Setting Resistor ROCSET

The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset

(VCS_OFST) of the amplifier itself and that created by the amplifier input bias current flowing through the current

sense resistor RCS.

V_{CS _ TOFST}= V_{CS _ OFST}+ I_CSIN+∗ R_CS

(7)

The inductor DC resistance is utilized to sense the inductor current. RL is the inductor DCR.

The over-current limit is set by the external resistor, ROCSET, as defined in (9). ILIMIT is the required over current

limit. IOCSET is the bias current of OCSET pin and can be calculated with the equation in the ELECTRICAL

CHARACTERISTICS Table. GCS is the gain of the current sense amplifier of the IR3506 phase IC. KP is the ratio

of inductor peak current over average current in each phase and can be calculated from (10).

I_LIMIT

(9)

∗ R_L∗ (1+ K_P) +V_{CS _ TOFST}]∗ G_CS/ I_OCSET

R_OCSET= [

n

(V_I−V_O)∗V_O/(L∗V_I∗ f_SW∗ 2)

I_O/ n

K_P=

(10)

Page 24

V3.01

IR3522

IR3506 EXTERNAL COMPONENTS

Inductor Current Sensing Capacitor CCS and Resistor RCS

The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor

CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage

across the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC

component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch

does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as

well as the output voltage during the load current transient if adaptive voltage positioning is adopted.

Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as

follows.

L R_L

R_CS

=

(11)

C_CS

Bootstrap Capacitor CBST

Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is

needed for the bootstrap circuit.

Decoupling Capacitors for Phase IC

0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs.

Type III Compensation

Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase, the desired

phase margin θc and Rfb1 (see Figure 12). Determine the component values based on the equations below. wc is

2*π*fc (the crossover angular frequency), Le is the equivalent inductance of the converter, C is the output

capacitance, Rst is the total equivalent resistance in series with the inductor, Rc is the output capacitance ESR

and R is the load resistance.

1

(12)

(13)

(14)

(15)

Ccp =

Rcp =

Cfb =

Ccp1 =

K ⋅ Rfb1

1

Ccp ⋅ wz1

1

wz2 ⋅ Rfb1

1

wp2 ⋅ Rcp

1

Rfb2 =

(16)

wp1⋅Cfb

Page 25

V3.01

IR3522

where,

wc

wz1 =

(17)

(18)

10

1− sin(θc)

1+ sin(θc)

wz2 = wc ⋅

wp1 = wc ⋅

1+ sin(θc)

1− sin(θc)

(19)

wp2 = 1.4⋅ wp1

(wc ⁴⋅t₄²+ wc ²⋅t₂²)((1− b ⋅ wc ²)²+ a²⋅ wc²)(R + Rst)

K =

(20)

(21)

Gpwm ⋅ H ⋅t₅⋅t₆⋅ R

where, Gpwm is the gain of the PWM generator, H is the gain of the feedback filter and

Le + C(R ⋅ Rst + R ⋅ Rc + Rst ⋅ Rc)

a =

(22)

(23)

R + Rst

R + Rc

R + Rst

wc ²

b = Le⋅ C

(24)

(25)

t₁= 1−

wz1⋅ wz2

wc²

t₂= 1−

wp1⋅ wp2

1

t₃=

+

wz1 wz2

(26)

(27)

1

t₄=

+

wp1 wp2

t₅= (1− b ⋅ wc²+ wc²⋅ Rc ⋅C ⋅ a)²+ wc²(Rc ⋅C(1− b ⋅ wc²) − a)²(28)

t₆= wc⁴(t₂⋅t₃− t₁⋅t₄)²+ wc ²(t₁⋅t₂+ wc²⋅t₃⋅t₄)²

(29)

Figure 12 Voltage Loop Compensation Network

Page 26

V3.01

IR3522

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC.

•

Dedicate at least one middle layer for a ground plane LGND.

Connect the ground tab under the control IC to LGND plane through a via.

Separate analog bus (EAIN, DACIN and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce

the noise coupling.

•

Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins.

Place the following critical components on the same layer as control IC and position them as close as

possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for

the connection.

•

Place the compensation components on the same layer as control IC and position them as close as possible

to EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection.

Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over

the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.

Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes.

Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation

components.

•

Page 27

V3.01

IR3522

PCB METAL AND COMPONENT PLACEMENT

• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should

be ≥ 0.2mm to prevent shorting.

• Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm

inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard

extension will accommodate any part misalignment and ensure a fillet.

• Center pad land length and width should be equal to maximum part pad length and width. However, the

minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥

0.23mm for 3 oz. Copper)

• A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to

minimize the noise effect on the IC.

• No pcb traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so

can cause the IC to rise up from the pcb resulting in poor solder joints to the IC leads.

Page 28

V3.01

IR3522

SOLDER RESIST

• The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder

resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non

Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.

• The minimum solder resist width is 0.13mm.

• At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a

fillet so a solder resist width of ≥ 0.17mm remains.

• The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto

the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable

to have the solder resist opening for the land pad to be smaller than the part pad.

• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high

aspect ratio of the solder resist strip separating the lead lands from the pad land.

• The single via in the land pad should be tented or plugged from bottom boardside with solder resist.

Page 29

V3.01

IR3522

STENCIL DESIGN

• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.

Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm

pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower;

openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.

• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead

land.

• The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit

approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad

the part will float and the lead lands will be open.

• The maximum length and width of the land pad stencil aperture should be equal to the solder resist

opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the

lead lands when the part is pushed into the solder paste.

Page 30

V3.01

IR3522

PACKAGE INFORMATION

32L MLPQ (5 x 5 mm Body) θ_JA=24.4 ^oC/W, θ_JC=0.86 ^oC/W

Page 31

V3.01

IR3522

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.

www.irf.com

Page 32

V3.01


型号：	IR3522MPBF
厂家：	Infineon
描述：	XPHASE3TM DDR & VTT CONTROL IC XPHASE3TM DDR VTT与控制IC 稳压器开关式稳压器或控制器电源电路开关式控制器双倍数据速率
文件：	总32页 (文件大小：751K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IR3522MPBF [INFINEON]

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