ZL2102_14 [INTERSIL]
6A Digital Integrated Synchronous Step-Down DC/DC Regulator with Auto Compensation;
| 型号： | ZL2102_14 |
| 厂家： | 
Intersil |
| 描述： | 6A Digital Integrated Synchronous Step-Down DC/DC Regulator with Auto Compensation |
| 文件： | 总58页 (文件大小：940K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
6A Digital Integrated Synchronous Step-Down DC/DC
Regulator with Auto Compensation
ZL2102
Features
The ZL2102 is an integrated digital power regulator with auto
compensation and power management functions in a small
package, resulting in a flexible and integrated solution, which
can be configured using the PowerNavigator™ graphical user
interface. This synchronous buck converter operates from a
4.5V to 14V input supply and provides from 0.54V to 5.5V
output voltage at up to 6A.
• Integrated MOSFET switches
• 6A continuous output current
• Adjustable 0.54V to 5.5V output range
• 4.5V to 14V input range
• Up to 90% efficiency
• Auto compensation for fast transient response
• SMBus compliant serial interface
• Snapshot™ parametric capture
• Internal nonvolatile memory
• Small footprint QFN package (6mmx6mm)
The ZL2102 can be configured for most applications using only
hardware pin straps to adjust switching frequency, output
voltage, UVLO, soft-start ramp/delay settings, sequencing
options, and SMBus address. For more advanced
configurations, the ZL2102 supports over 70 PMBus
commands. Output voltage/current is factory calibrated.
Internal synchronous power MOSFETs enable the ZL2102 to
deliver continuous loads up to 6A with high efficiency. An
internal Schottky bootstrap diode reduces discrete component
count. The ZL2102 also supports phase spreading to reduce
system input capacitance.
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
The ZL2102 uses the SMBus™ with PMBus™ protocol for
communication with a host controller and the Intersil's
proprietary Digital-DC™ bus for interoperability between other
Intersil devices.
Related Literature
• AN2010 "Thermal and Layout Guidelines for Digital-DC™
Products"
• AN2035 "Compensation Using CompZL™"
• TB389 "PCB Land Pattern and Surface Mount Guidelines for
QFN Packages"
10µF
4.7µF
4.7µF
V2P5
VRA
DDC Bus
SMBus
DDC
SCL
INTERFACE
VR
VDDS
VDDP
SDA
ZL2102
SALRT
V
IN
12V
PG
CB
0.1µF
C
IN
HARDWARE
CONTROL
MGN
100µF
BST
EN
LOUT
2.2µH
VOUT
3.3V
6A
SW
SYNC
VSET
SA
VSEN
COUT
200µF
PGND
SGND
HARDWARE
CONFIG
FC
DGND
ePAD
CFG
SS
FIGURE 1. TYPICAL APPLICATION DIAGRAM
November 20, 2014
FN8440.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013, 2014. All Rights Reserved
Intersil (and design), PowerNavigator and Digital-DC are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ZL2102
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Digital-DC Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Conversion Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SMBus Device Address Selection (SA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Voltage and VOUT_MAX Selection (VSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Automatic Loop Compensation (FC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Synchronization and Sequencing Configuration Settings (CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching Frequency Setting (SYNC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Soft-Start and UVLO Settings (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Management Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Monitoring via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Snapshot™ Parametric Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Train Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Design Goal Trade-offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PMBus Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PMBus Command Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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ZL2102
FIGURE 2. BLOCK DIAGRAM
Pin Configuration
ZL2102
(36 LD 6x6 QFN)
TOP VIEW
PG
DGND
SYNC
VSET
SA
1
2
3
4
5
6
7
8
9
27 VDDP
26 BST
25 SW
24 SW
23 SW
22 SW
21 SW
20 SW
19 PGND
EXPOSED PADDLE
CONNECT TO SGND
SCL
SDA
SALRT
FC
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ZL2102
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
PG
Output
Power-good indicator output pin. This pin transitions high after the output voltage stabilizes within the regulation
band. Selectable open-drain or push-pull output. Default is open drain.
2
3
DGND
SYNC
Ground Digital ground. This is the common return for digital signals. Connect to low impedance ground plane.
Multimode Clock synchronization I/O pin. Used to set switching frequency of internal clock or for synchronization to an external
clock, depending on the setting of the CFG pin. Configured during start-up by pin strap.
4
5
6
VSET
SA
Multimode Output voltage select pin. Used to set V
set-point and V
max. Configured during start-up by pin strap.
Multimode Serial address select pin. Used to assign a unique SMBus address to the device. Configured during start-up by pin strap.
OUT
OUT
SCL
I/O
Serial clock pin for SMBus communication. Connect to external host interface. A pull-up resistor is required for
operation.
7
SDA
I/O
Serial data pin for SMBus communication. Connect to external host interface. A pull-up resistor is required for
operation.
8
9
SALRT
FC
Output
Serial alert output pin for SMBus communication. Connect to external host interface if desired.
Multimode Auto compensation configuration pin. Used to set up auto compensation configuration. Configured during start-up
by pin strap.
10
11
12
13
14
CFG
SS
Multimode Configuration pin. Used to configure the SYNC pin and sequencing options. Configured during start-up by pin strap.
Multimode Soft-start pin. Sets the ramp delay/ramp time and UVLO. Configured during start-up by pin strap.
No Connect Do not connect to pin. Leave floating.
DNC
VSEN
SGND
PGND
Input
Ground Common return for analog signals. Connect to low impedance ground plane at one point directly at PGND pins.
Ground Power ground. Common return for internal switching MOSFETs and external C /C . Connect to low impedance
Output voltage positive feedback sense pin.
15, 16,
IN OUT
17, 18, 19
ground plane.
20, 21,
22, 23,
24, 25
SW
Output
Output switch node to the inductor.
26
BST
Input
Power
Power
Power
Boosted floating driver supply pin. The bootstrap capacitor connects from the switch node to this pin.
Supply voltage for internal switching MOSFETs.
27, 28, 29 VDDP
30
31
VDDS
VR
Supply voltage for the IC.
Regulated bias from internal 7V low-dropout regulator. Decouple with a 4.7μF capacitor to GND. Not for use with
external circuits.
32
33
VRA
Power
Power
Regulated bias from internal 5V low-dropout regulator for internal analog circuitry. Decouple with a 4.7μF capacitor
to GND. Not for use with external circuits.
V2P5
Regulated bias from internal 2.5V low-dropout regulator for internal digital circuitry. Decouple with a 10µF capacitor
to GND. Connect the device's multimode pins to this supply pin for logic HIGH pin strap settings.
34
35
DDC
I/O
Digital-DC Bus pin. Allows interoperability between other Intersil devices. A pull-up resistor is required for operation.
MGN
Input
Margin setting pin, used to enable margining of the output voltage. Logic HIGH sets the device to margin high, logic
LOW sets the device to margin low, and leaving the pin floating sets the device to nominal voltage output.
36
EN
Input
Enable pin, used to enable the output. Default is active high.
ePad
SGND
Ground Exposed thermal pad. Common return for analog signals. Connect to low impedance ground plane.
Ordering Information
PART NUMBER
TEMP RANGE
(°C)
PACKAGE
Tape & Reel (Pb-free)
PKG.
DWG. #
(Notes 1, 2, 3
PART MARKING
2102
ZL2102ALAFTK
NOTES:
-40 to +85
36 Ld Exposed Pad 6x6 QFN
L36.6x6A
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ZL2102. For more information on MSL, please see tech brief TB363.
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4
ZL2102
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage for VDDP, VDDS Pins . . . . . . . . . . . . . . . . . . -0.3V to 17V
High-Side Supply Voltage for BST Pin. . . . . . . . . . . . . . . . . . . . -0.3V to 25V
High-Side Boost Voltage for BST, SW Pins. . . . . . . . . . . . . . . . . . -0.3V to 8V
Internal MOSFET Reference for VR Pin . . . . . . . . . . . . . . . . . . -0.3V to 8.5V
Internal Analog Reference for VRA Pin . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Internal 2.5V Reference for V2P5 Pin . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Logic I/O Voltage for EN, CFG, DDC, FC, MGN, PG, SDA, SCL,
SA, SALRT, SS, SYNC, VSET, VSEN Pins . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Ground Differential for DGND - SGND, PGND - SGND Pins . . . . . . . . ±0.3V
MOSFET Drive Reference Current for VR Pin Internal Bias Usage . . . 20mA
Switch Node Current for SW Pin Peak (Sink Or Source) . . . . . . . . . . . . 10A
ESD Rating
Thermal Resistance (Typical)
36 Ld QFN Package (Notes 4, 5) . . . . . . . .
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Dissipation Limits (Note 6)
JA (°C/W)
28
JC (°C/W)
1.7
T
= +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5W
= +55°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W
= +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4W
A
T
A
T
A
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . . 200V
Latch-up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Input Supply Voltage Range, VDDP, VDDS (see Figure 10 on page 10)
VDDS tied to VR, VRA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
VDDS tied to VR, VRA Floating . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V to 7.5V
VR, VRA Floating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5V to 14V
Output Voltage Range, V
(Note 7) . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V
Operating Junction Temperature Range, T . . . . . . . . . . . .-40°C to +125°C
OUT
J
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance ground
JA
plane using multiple vias.
5. For , the "case temp" location is the center of the exposed metal pad on the package underside.
JC
6. Thermal impedance is dependent upon PCB layout.
7. Includes margin limits.
Electrical Specifications VDDP = VDDS = 12V, T = -40°C to +85°C unless otherwise noted (Note 9). Typical values are at
A
T = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C.
A
MIN
MAX
PARAMETER
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNIT
IC INPUT AND BIAS SUPPLY CHARACTERISTICS
I
Supply Current
f
f
= 200kHz, no load
–
–
–
15
15
25
30
1
mA
mA
mA
DD
SW
= 1MHz, no load
SW
I
Shutdown Current
EN = 0 V, no SMBus activity, low power standby
mode
0.6
DD
VR Reference Output Voltage
VRA Reference Output Voltage
V2P5 Reference Output Voltage
OUTPUT CHARACTERISTICS
Output Current
V
V
> 8V, IVR < 10mA
6.5
4.5
7.0
5.1
2.5
7.5
5.5
V
V
V
DD
> 5.5V, IVRA < 20mA
DD
IV2P5 < 20mA
2.25
2.75
I
, continuous
–
–
–
–
6
9
A
A
RMS
Peak (Note 11)
> V
Output Voltage Adjustment Range (Note 10)
Output Voltage Set-point Accuracy
Output Voltage Set-point Resolution
VSEN Input Bias Current
V
0.6
-1
–
–
5.0
1
V
IN
OUT
Across line, load, temperature variation
Set using PMBus command
–
%
±2
110
mV
µA
–
V
= 5.5V
–
200
SEN
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ZL2102
Electrical Specifications VDDP = VDDS = 12V, T = -40°C to +85°C unless otherwise noted (Note 9). Typical values are at
A
T = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
A
MIN
MAX
PARAMETER
LOGIC INPUT/OUTPUT CHARACTERISTICS
Logic Input Leakage Current
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNIT
Logic I/O - multimode pins
-250
–
–
–
250
0.8
–
nA
V
Logic Input Low, V
IL
Logic input Open (N/C)
Logic Input High, V
Multimode logic pins
–
1.4
–
V
2.0
–
–
V
IH
Logic Output Low, V
I
I
≤ 4mA
≥ -2mA
–
0.4
–
V
OL
Logic Output High, V
OL
2.25
–
V
OH
OH
OSCILLATOR AND SWITCHING CHARACTERISTICS
Switching Frequency Range
200
-5
-
1000
5
kHz
%
Switching Frequency Set-Point Accuracy
PWM Duty Cycle
-
0
-
-
95
-
%
Minimum SYNC Pulse Width
150
-13
-
ns
Input Clock Frequency Drift Tolerance
External clock source
-
13
85
65
%
r
of High-Side N-channel FETs
of Low-Side N-channel FETs
I
= 6A, V = 6.5V
60
43
mΩ
mΩ
DS(ON)
DS(ON)
SW
GS
r
I
= 6A, V = 12V
-
SW
GS
SMBUS CHARACTERISTICS
SMBus Clock Rate
-
100
-
-
-
kHz
ms
Wait Time Between Consecutive Commands
2
POWER MANAGEMENT
SOFT-START RAMP CHARACTERISTICS
Soft-Start Ramp Delay Range
Soft-Start Ramp Delay Accuracy
Soft-Start Ramp Duration Range
Soft-Start Ramp Duration Accuracy
POWER-GOOD
Set using PMBus command
Turn-on, turn off delay
5
-1
5
-
-
30000
+5
ms
ms
ms
ms
±1
-
Set using PMBus command
Turn-on, turn off delay
200
-
±1
Power-Good V
Threshold
Hysteresis
Factory default
-
-
90
5
-
% V
OUT
OUT
OUT
Power-Good V
Factory default
-
%
Power-Good Delay
Applies to Turn-On Only (Low-to-High transition)
Factory default
-
1
-
ms
ms
Set using PMBus command
1
30000
MONITORING AND FAULT MANAGEMENT
INPUT VOLTAGE MONITOR AND FAULT DETECTION
V
V
Monitor Accuracy
-150
4.5
-
-
-
150
16
-
mV
V
IN
IN
UVLO Threshold Range
Set using PMBus command
Factory default
UVLO Hysteresis
3
%
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ZL2102
Electrical Specifications VDDP = VDDS = 12V, T = -40°C to +85°C unless otherwise noted (Note 9). Typical values are at
A
T = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
A
MIN
MAX
PARAMETER
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNIT
OUTPUT VOLTAGE MONITOR AND FAULT DETECTION
V
Undervoltage Hysteresis
Factory default
-
-
5
-
-
% V
OUT
OUT
OUT
V
UV/OV Fault Response Delay
30
µs
OUTPUT CURRENT SENSE MONITOR AND FAULT DETECTION
I
I
I
Monitor Accuracy
-
-
-
±10
±3
-
±5
-
%
% FS
µs
OUT
OUT
OUT
Threshold Accuracy
Fault Response Delay
15
TEMPERATURE SENSE
Internal Temperature Range
Internal Temperature Accuracy
Thermal protection Hysteresis
NOTES:
-55
-5
-
-
125
5
°C
°C
°C
Tested at +100°C
Factory default
–
15
–
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. Refer to Safe Operating Area in Figure 8 and thermal design guidelines in AN2010.
10. Does not include margin limits.
11. Switch node current should not exceed I
of 6A.
RMS
Typical Performance Curves
For some applications, ZL2102 operating conditions (input voltage, output voltage, switching frequency, temperature) may require derating to remain
within the Safe Operating Area (SOA). V = V
= V
, T = +125°C
IN
DDP
DDS J
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0
25
50
T
75
100
0
25
50
T
75
100
(°C)
(°C)
J
J
FIGURE 3. LOW-SIDE r
DS(ON)
vs T NORMALIZED FOR T = +25°C
= 0.3A)
FIGURE 4. HIGH-SIDE r
DS(ON)
vs T NORMALIZED FOR T = +25°C
J
J
J
J
(V
= 12V, I
(V
= 12V, BST – SW = 6.5V, I = 0.3A)
DDS
DRAIN
DDS
DRAIN
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ZL2102
Typical Performance Curves
For some applications, ZL2102 operating conditions (input voltage, output voltage, switching frequency, temperature) may require derating to remain
within the Safe Operating Area (SOA). V = V
= V
, T = +125°C (Continued)
IN
DDP
DDS J
70
65
60
6
5
4
3
2
1
0
V
= 7.5V
IN
V
= 6V
IN
T
= +110°C
J
55
50
45
40
T
= +80°C
J
V
= 8.6V TO 14V
IN
T
= +50°C
J
T
= +25°C
8
J
6
7
9
10
11
12
13
0.2
0.3
0.4
0.5
0.6 0.7
0.8
0.9
1.0
V
(V)
f
(MHz)
SW
DDS
FIGURE 6. SAFE OPERATING AREA, T +125°C
J
FIGURE 5. LOW-SIDE r
vs V
WITH T
DDS
DS(ON)
J
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
V
MAY NOT EXCEED
OUT
5.5V AT ANY TIME
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
f
(MHz)
SW
FIGURE 7. MAXIMUM CONVERSION RATIO, T +125°C
J
Once enabled, the ZL2102 is immediately ready to regulate
power and perform power management tasks with no
programming required. Advanced configuration options and
realtime configuration changes are available via the SMBus
interface if desired and continuous monitoring of multiple
operating parameters is possible with minimal interaction from a
host controller. Integrated sub regulation circuitry enables single
supply operation from any external supply between 4.5V and 14V
with no additional bias supplies needed.
Digital-DC Architecture Overview
The ZL2102 is an innovative mixed-signal power conversion and
power management IC based on Intersil patented Digital-DC
technology that provides an integrated, high performance
stepdown regulator for point of load applications. The ZL2102
integrates all necessary PWM control circuitry as well as low
r
synchronous power MOSFETs to provide an extremely
DS(ON)
small solution for supplying load currents up to 6A.
Its unique PWM loop utilizes an ideal mix of analog and digital
blocks to enable precise control of the entire power conversion
process with no software required, resulting in a very flexible
device that is also very easy to use. An extensive set of power
management functions are fully integrated and can be
configured using simple pin connections. The user configuration
can be saved in an internal nonvolatile memory (NVM).
Additionally, all functions can be configured and monitored via
the SMBus hardware interface using standard PMBus
commands, allowing ultimate flexibility.
The ZL2102 can be configured by simply connecting its pins
according to the tables provided in the following sections.
Additionally, a comprehensive set of application notes are
available to help simplify the design process. An evaluation
board is also available to help the user become familiar with the
device. This board can be evaluated as a standalone platform
using pin configuration settings. A Windows™-based GUI is also
provided to enable full configuration and monitoring capability
via the SMBus interface using a computer and the included USB
cable.
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ZL2102
The maximum conversion ratio is shown in Figure 7. Typically,
Power Conversion Overview
buck converters specify a maximum duty cycle that effectively
limits the maximum output voltage that can be realized for a
given input voltage and switching frequency. This duty cycle limit
ensures that the low-side MOSFET is allowed to turn on for a
minimum amount of time during each switching cycle, which
enables the bootstrap capacitor to be charged up and provide
adequate gate drive voltage for the high-side MOSFET.
The ZL2102 operates as a voltage-mode, synchronous buck
converter with a selectable constant frequency pulse width
modulator (PWM) control scheme. The ZL2102 integrates dual
low r
synchronous MOSFETs and a high-side driver to
DS(ON)
minimize the circuit footprint. Figure 8 illustrates the basic
synchronous buck converter topology showing the primary power
train components. This converter is also called a step-down
converter, as the output voltage must always be lower than the
input voltage.
The block diagram for the ZL2102 is illustrated in Figure 2. In
this circuit, the target output voltage is regulated by connecting
the VSEN pin directly to the output regulation point. The VSEN
signal is then compared to an internal reference voltage that had
been set to the desired output voltage level by the user. The error
signal derived from this comparison is converted to a digital
value with an analog-to-digital (A/D) converter. The digital signal
is also applied to an adjustable digital compensation filter and
the compensated signal is used to derive the appropriate PWM
duty cycle for driving the internal MOSFETs in a way that
produces the desired output.
VIN
CIN
DB
LDO
CB
QH
QL
L1
VOUT
PWM
COUT
ZL2102
Power Management Overview
The ZL2102 incorporates a wide range of configurable power
management features that are simple to implement with no
external components. Additionally, the ZL2102 includes circuit
protection features that continuously safeguard the device and
load from damage due to unexpected system faults. The ZL2102
can continuously monitor input voltage, output voltage/current,
and internal temperature. A power-good output signal is also
included to enable power-on reset functionality for an external
processor.
FIGURE 8. STEP DOWN CONVERTER
The ZL2102 integrates two N-channel power MOSFETs; QH is the
top control MOSFET and QL is the bottom synchronous MOSFET.
The amount of time that QH is on as a fraction of the total
switching period is known as duty cycle D, which is described by
Equation 1:
V
OUT
(EQ. 1)
---------------
D
V
IN
All power management functions can be configured using either
pin configuration techniques described in this document or via
the SMBus interface using PMBus commands. Monitoring
parameters can also be preconfigured to provide alerts for
specific conditions. “PMBus Command Summary” on page 19
contains a listing of all the PMBus commands supported by the
ZL2102 and a detailed description of the use of each of these
commands.
During time D, QH is on and V to V
IN OUT
is applied across the
inductor. The output current ramps up as shown in Figure 9.
VIN - VOUT
ILPK
Functional Description and Configuration
INTERNAL BIAS REGULATORS AND INPUT SUPPLY
CONNECTIONS
IO
0
The ZL2102 employs three internal LDO regulators, allowing
operation from a single input supply from 4.5V to 14V. The
regulators are as follows:
ILV
-VOUT
• VR is derived from VDDS and provides a 7V bias supply for the
internal high-side MOSFET driver circuit. A 4.7µF capacitor is
required for the VR pin.
D
1 - D
TIME
• VRA is derived from VDDS and provides a 5V bias supply for
the internal analog circuitry. A 4.7µF capacitor is required for
the VR pin.
FIGURE 9. OUTPUT CURRENT
When QH turns off (time 1-D), the current flowing in the inductor
must continue to flow from the ground up through QL, during
• V2P5 is derived from VRA and provides a 2.5V bias supply for
the digital circuitry. A 10µF capacitor is required at the V2P5
pin.
which the current ramps down. Since the output capacitor C
exhibits low impedance at the switching frequency, the AC
OUT
component of the inductor current is filtered from the output
voltage so the load sees nearly a DC voltage.
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ZL2102
Input voltage ranges and connections are shown in Figure 10.
VIN
VIN
VIN
LOGIC
HIGH
VDDS
VDDS
VDDS
MULTIMODE
PIN
MULTIMODE
PIN
OPEN
VR
VR
VR
LOGIC
LOW
VRA
VRA
VRA
VIN
=
VIN
=
VIN
=
4.5V TO 5.5V
5.5V TO 7.5V
7.5V TO 14V
PIN STRAP
SETTINGS
RESISTOR
SETTINGS
FIGURE 10. INPUT SUPPLY CONNECTIONS
The internal bias regulators, VR and VRA, are not designed to be
outputs for powering other circuitry. Do not attach external loads
to any of these pins. Only the multimode pins may be connected
to the V2P5 pin for logic HIGH settings.
FIGURE 11. PIN STRAP AND RESISTOR SETTING EXAMPLES
SMBus: Most ZL2102 functions/parameters can be configured
via the SMBus interface using standard PMBus commands.
“PMBus Command Summary” on page 19 explains the use of
the available PMBus commands in detail.
MULTIMODE PINS
In order to simplify circuit design, the ZL2102 incorporates
patented multimode pins that allow the user to easily configure
many aspects of the device with no programming. Most power
management features can be configured using these pins. The
multimode pins can respond to four different connections as
shown in Table 1. These pins are sampled once when power is
applied or by issuing a PMBus Restore command.
CONFIGURABLE PINS
Many operating parameters can be set using the multimode pin
setup method: SMBus address (SA), output voltage (VSET), clock
synchronization and sequencing options (CFG), switching
frequency (SYNC), soft-start delay, soft-start ramp, input
undervoltage lock-out (SS), and automatic loop compensation
settings (FC). These pins are checked once during start-up only.
Changes to the settings of these pins will not be read until the
device's power supply has been cycled off and on.
Pin Strap Settings: This is the simplest implementation method,
as no external components are required. Using this method, each
pin can take on one of three possible states: LOW, OPEN, or
HIGH. These pins can be connected to the V25 pin for logic HIGH
settings. Using a single pin, one of three settings can be selected.
The device's SMBus address is the only parameter that must be
set by the multimode pins. All others are configurable using
PMBus commands.
Resistor Settings: This method allows a greater range of
adjustability when connecting a finite value resistor (in a
specified range) between the multimode pin and SGND.
Standard 1% resistor values are used, and only every fourth E96
resistor value is used so the device can reliably recognize the
value of resistance connected to the pin while eliminating the
error associated with the resistor accuracy. Up to 31 unique
selections are available using a single resistor.
SMBus Device Address Selection (SA)
The ZL2102 provides an SMBus digital interface that enables the
user to configure all aspects of the device operation as well as
monitor the input and output parameters. The ZL2102 is
compatible with SMBus version 2.0 and includes an SALRT line
to help mitigate bandwidth limitations related to continuous fault
monitoring.
TABLE 1. MULTIMODE PIN CONFIGURATION
When communicating with multiple devices using the SMBus
interface, each device must have its own unique address so the
host can distinguish between the devices. The device address
can be set according to the pin strap options listed in Table 2. The
SMBus address cannot be changed with a PMBus command.
PIN TIED TO
LOW (Logic LOW)
OPEN (N/C)
VALUE
<0.8 VDC
No connection
>2.0 VDC
HIGH (Logic HIGH)
Resistor to SGND
Set by resistor value
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ZL2102
TABLE 3. (Continued)
TABLE 2. PIN STRAP OPTIONS
R
V
R
(kΩ)
V
OUT
SET
OUT
SET
R
SMBus
ADDRESS
R
SMBus
ADDRESS
SA
SA
(kΩ)
26.1
28.7
31.6
34.8
38.3
42.2
46.4
(V)
1.2
1.25
1.3
1.4
1.5
1.6
1.7
(V)
2.9
3
(kΩ)
10 or LOW
11 or OPEN
12.1 or HIGH
13.3
(kΩ)
42.2
46.4
51.1
56.2
61.9
68.1
75
121
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
133
30h
31h
HIGH
147
3.3
4
32h
33h
34h
35h
36h
37h
162
4.5
5
14.7
OPEN
16.2
17.8
19.6
82.5
91
In addition to the VOUT_COMMAND and VOUT_MAX settings, this
pin strap setting is also used to set several other V
settings including:
related
21.5
OUT
23.7
100
110
121
133
147
162
38h
39h
3Ah
3Bh
3Ch
3Dh
• VOUT_UV_FAULT_LIMIT = 85% of VSET
• POWER_GOOD_ON = 90% of VSET
• VOUT_MARGIN_LOW = 95% of VSET
• VOUT_MARGIN_HIGH = 105% of VSET
• VOUT_OV_FAULT_LIMIT = 115% of VSET
26.1
28.7
31.6
34.8
38.3
The above parameters are automatically adjusted by the VSET
pin strap selection. If the value of VOUT_COMMAND is adjusted
via PMBus, the values of these commands may also need to be
Output Voltage and VOUT_MAX Selection
(VSET)
The output voltage may be set to any voltage between 0.6V and
5.5V provided that the input voltage is higher than the desired
output voltage by an amount sufficient to prevent the device
adjusted to compensate for the V
change. The configured
OUT
voltage relationships must follow: VOUT_UV_FAULT_LIMIT <
POWER_GOOD_ON < VOUT_MARGIN_LOW < VOUT_COMMAND <
VOUT_MARGIN_HIGH < VOUT_OV_FAULT_LIMIT.
from exceeding its maximum duty cycle specification. V
can
can
OUT
be set to any of the pin strap options shown in Table 3. V
OUT
also be set using the VOUT_COMMAND PMBus command.
Automatic Loop Compensation (FC)
The ZL2102 has an automatic loop compensation feature that
measures the characteristics of the power train and calculates
the proper PID tap coefficients. Auto compensation is configured
using the FC pin as shown in Table 4.
The maximum accepted value of V is limited by VOUT_MAX.
OUT
The default value of VOUT_MAX is 110% of the VSET pin strap
setting, but it can also be set using the VOUT_MAX PMBus
command.
TABLE 4.
TABLE 3.
R
AUTO COMP GAIN
(%)
FC
R
V
R
V
OUT
(kΩ)
LOW
10
PG ASSERT
SET
OUT
SET
(kΩ)
(V)
(kΩ)
LOW
51.1
56.2
61.9
68.1
75
(V)
1.8
1.9
2
Auto Comp Disabled
10
0.6
After Auto Comp
After PG Delay
After Auto Comp
After PG Delay
After Auto Comp
After PG Delay
After Auto Comp
After PG Delay
After Auto Comp
After PG Delay
100
90
80
70
60
11
0.7
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
0.75
0.8
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
2.1
2.2
2.4
2.5
2.6
2.7
2.8
0.9
1
1.05
1.1
82.5
91
1.125
1.15
100
110
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ZL2102
TABLE 4. (Continued)
TABLE 5.
SYNC PIN
R
AUTO COMP GAIN
FC
R
CFG
(kΩ)
OPEN
HIGH
26.1
28.7
31.6
34.8
38.3
42.2
46.4
51.1
PG ASSERT
(%)
(kΩ)
LOW
OPEN
HIGH
14.7
16.2
17.8
CONFIGURATION
SEQUENCING CONFIGURATION
Sequencing Disabled.
After Auto Comp
After PG Delay
After Auto Comp
After PG Delay
After Auto Comp
After PG Delay
After Auto Comp
After PG Delay
After Auto Comp
After PG Delay
50
Input
Auto detect
Output
40%
30%
20%
10%
Input
Device is FIRST in Nested
Sequence.
Auto detect
Output
21.5
23.7
26.1
31.6
34.8
38.3
Input
Device is LAST in Nested
Sequence.
Auto detect
Output
Input
Device is MIDDLE in Nested
Sequence.
Auto detect
Output
When Auto Comp is enabled, it will run once each time the part is
enabled. Auto Comp runs a series of tests on the output and
calculates the optimal tap coefficients immediately after the
V
ramp completes. The calculated tap coefficients are stored
OUT
Switching Frequency Setting (SYNC)
The ZL2102's switching frequency can be set from 200kHz to
1000kHz using the SYNC pin strap options shown in Table 6.
in the Auto Comp Store and may be read back through the
PID_TAPS PMBus command. If auto compensation is disabled,
the device will use the tap coefficients that are stored in the
USER_STORE.
TABLE 6.
If the PG Assert parameter is set to "Use PG Delay", the PG pin
will be asserted according to the POWER_GOOD_DELAY
command. When Auto Comp is enabled and the "Use PG Delay"
option is selected, the user must ensure that the output
perturbation from the Auto Comp test cycle is acceptable before
PG is asserted. If PG Assert is set to "After Auto Comp", PG will
be asserted immediately after the Auto Comp cycle completes
(POWER_GOOD_DELAY will be ignored in this case).
R
FREQ
(kHz)
R
FREQ
(kHz)
SYNC
SYNC
(kΩ)
LOW
10
(kΩ)
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
HIGH
200
222
242
267
296
320
364
400
421
445
471
500
533
571
615
667
727
800
889
1000
11
12.1
13.3
14.7
16.2
OPEN
17.8
19.6
The Auto Comp Gain control scales the Auto Comp results to
allow a trade-off between transient response and steady-state
duty cycle jitter. A setting of 100% will provide the fastest
transient response while a setting of 10% will produce the lowest
jitter. For best results, V must be stable before Auto Comp
IN
begins as shown in Equation 2:
V
100%
IN
(EQ. 2)
-----------------------
-----------------------------------------
in%
VIN
256 V
NOM
OUT
-------------------------------
1 +
VIN
NOM
The switching frequency can also be set to any value between
200kHz and 1MHz using the FREQUENCY_SWITCH PMBus
command. The available frequencies below 1MHz are defined by
The auto compensation function can also be configured via the
AUTO_COMP_CONFIG PMBus command and controlled using the
AUTO_COMP_CONTROL PMBus command. Compensation values
can be programmed manually by disabling Auto Comp and
writing preferred values to the PID_TAPS PMBus command.
f
= 8MHz/N, where 8 ≤ N ≤ 40.
SW
If a value other than f
= 8MHz/N is entered using the PMBus
SW
command, the device will select the switching frequency value
using N as a whole number to achieve a value nearest to the
entered value. For example, if 810kHz is entered, the device will
select 800kHz (N = 10).
Synchronization and Sequencing
Configuration Settings (CFG)
The ZL2102 supports several options of clock synchronization
and output sequencing. The ZL2102's configuration settings can
be set using the CFG pin strap options shown in Table 5. The
operation of these functions is covered in their respective
sections of this document.
Note: The switching frequency read back using the appropriate
PMBus command may differ slightly from the programmed
value. The difference is due to hardware quantization.
The SYNC pin can also be configured to perform synchronization
between devices. The CFG pin is used to configure the SYNC pin
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ZL2102
as an input, an output, or auto-detect mode. The ZL2102
incorporates an internal phase-locked loop (PLL) to clock the
internal circuitry. The PLL can be driven by an external clock
source connected to the SYNC pin, or it can be configured to drive
the internal clock out of the SYNC pin to other devices.
TABLE 7.
TON/TOFF DELAY
TON/TOFF
RAMP TIME
(ms)
R
(kΩ)
TIME
(ms)
UVLO
(V)
SS
10
5
SYNC OUTPUT: When the SYNC pin is configured as an output, the
device will run from its internal oscillator and will drive the
selected switching frequency onto the SYNC pin so that other
devices can be synchronized to it.
11
10
20
5
5
12.1
LOW or 13.3
14.7
SYNC INPUT: When the SYNC pin is configured as an input, the
device will check for an external clock signal on the SYNC pin
each time the output is enabled. The internal oscillator will then
synchronize with the rising edge of the external clock. The
incoming clock signal must be in the range of 200kHz to 1MHz
and must be stable when the enable pin is asserted. The clock
signal must have a minimum width of 150ns, and it must stay
within 10% of its initial value. In the event of a loss of the
external clock signal, will automatically switch to its internal
oscillator and switch at a frequency close to the previous
incoming frequency. The output voltage may show a transient
overshoot/undershoot if this occurs.
10
20
5
10
20
5
4.5
5.5
7.5
16.2
17.8
19.6
10
20
5
21.5
23.7
26.1
10
20
5
HIGH or 28.7
31.6
SYNC AUTO DETECT: When the SYNC pin is configured in
auto-detect mode, the device will check for a clock signal on the
SYNC pin each time EN is asserted. If there is a valid clock, the
pin will run as a sync input.
34.8
10
20
5
10
20
5
38.3
42.2
If no incoming clock signal is present, the device will switch at
the selected internal clock rate.
46.4
10
20
5
51.1
Soft-Start and UVLO Settings (SS)
56.2
The ZL2102 supports variable turn-on/off delay times,
turn-on/off ramp rates, and input undervoltage lockout (UVLO)
functions. These features may be used as part of an overall
in-rush current management strategy or to precisely control how
fast a load is turned on. The ZL2102 provides several options for
precisely and independently controlling both the delay and ramp
time periods.
OPEN or 61.9
68.1
10
20
5
75
82.5
10
20
5
10
20
91
The soft-start delay period begins when the EN pin is asserted
and ends when the delay time expires. The soft-start ramp timer
enables a precisely controlled monotonic ramp to the nominal
100
110
10
20
V
value that begins once the delay period has expired. This
OUT
121
process is also followed for ramp down after the EN pin has been
deasserted.
These functions can also be set independently using TON_DELAY,
TON_RISE, TOFF_DELAY, and TOFF_FALL PMBus commands. The
UVLO threshold can be adjusted using the VIN_UV_FAULT_LIMIT
PMBus command. The ramp down function is disabled by
default, but it can be enabled using the ON_OFF_CONFIG or
OPERATION PMBus commands depending on the desired device
enable method.
The input undervoltage lockout (UVLO) prevents the ZL2102 from
operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range.
The ZL2102's TON/TOFF delay time, TON/TOFF ramp time, and
UVLO functions can be configured using the SS pin strap options
shown in Table 7.
Start-up Procedure
The ZL2102 follows a specific internal start-up procedure after
power is applied. Figure 12 describes the start-up sequence.
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ZL2102
Power Management Function
Internal Memory Check
~35ms
Device will ignore an
enable signal or PMBus
commands
Description
Input Power Applied
Input Undervoltage Lockout
The input undervoltage lockout feature (UVLO) prevents the
ZL2102 from operating when the input falls below a preset
threshold, indicating the input supply is out of its specified range.
The UVLO threshold can be set to 4.5V, 5.5V, or 7.5V using the SS
pin. The UVLO voltage can also be adjusted using the
VIN_UV_FAULT_LIMIT PMBus command.
Pre-ramp Delay
~5ms
Delay between enable signal
and start of output ramp.
Additional delay may be
added with PMBus
command
Device Ready
The default response from a UVLO fault is an immediate
shutdown of the device during the fault and an automatic restart
when the fault condition has cleared. The UVLO fault response
can be configured using the VIN_UV_FAULT_RESPONSE PMBus
command.
FIGURE 12. START-UP SEQUENCE
If the device is to be synchronized to an external clock source, the
clock frequency must be stable prior to asserting the EN pin. The
device requires approximately 35ms to check for specific values
stored in its internal memory. If the user has stored values in
memory, those values will be loaded. If Auto Comp is enabled,
start-up time increases to ~55ms.
Output Overvoltage Protection
The ZL2102 offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry from
being subjected to a voltage higher than its prescribed limits. A
hardware comparator is used to compare the actual output
voltage (seen at the VSEN pin) to a threshold set above the target
output voltage. The default setting is 115% of the pin strap
setting for VOUT, but this value can be adjusted using the
VOUT_OV_FAULT_LIMIT PMBus command. If the VSEN voltage
exceeds this threshold, the PG pin will deassert and the device
response can be set using the VOUT_OV_FAULT_RESPONSE
PMBus command. The default response is an immediate
shutdown of the device during the fault and an automatic restart
when the fault has cleared. For continuous overvoltage
protection when operating from an external clock, the only
allowed response is an immediate shutdown with no automatic
restart.
Once this process is completed, the device is ready to accept
commands via the serial interface and the device is ready to be
enabled. Once enabled, the device requires approximately 5ms
before its output voltage may be allowed to start its ramp-up
process. If a soft-start delay period less than 5ms has been
configured (using PMBus commands), the device will default to a
5ms delay period. If a delay period greater than 5ms is
configured, the device will wait for the configured delay period
prior to starting to ramp its output.
After the delay period has expired, the output will begin to ramp
towards its target voltage according to the preconfigured
soft-start ramp time.
Output Prebias Protection
An output prebias condition exists when an externally applied
voltage is present on a power supply's output before the power
supply's control IC is enabled. Certain applications require that
the converter not be allowed to sink current during start-up if a
prebias condition exists at the output. The ZL2102 provides
prebias protection by sampling the output voltage prior to
initiating an output ramp.
Power-Good
The ZL2102 provides a Power-Good (PG) signal that indicates the
output voltage is within a specified tolerance of its target level
and no fault condition exists. By default, the PG pin will assert if
the output reaches 90% of the target voltage. The limit and drive
configuration of the pin may be changed using the
POWER_GOOD_ON and MFR_CONFIG PMBus commands.
If a prebias voltage exists after the preconfigured delay period
has expired, the ramp start voltage will be set to match the
existing prebias voltage and the output will be enabled. The
output voltage will then ramp to the final regulation value at the
ramp rate set by the SS pin strap setting or the TON_RISE PMBus
command.
A PG delay period is defined as the time from when all conditions
for asserting PG are met to when the PG pin is actually asserted.
This feature is commonly used instead of using an external reset
controller to control external digital logic. By default, the ZL2102
PG delay is set equal to 1ms. The PG delay can be adjusted using
the POWER_GOOD_DELAY PMBus command.
The actual time the output will take to ramp up from the prebias
voltage to the target voltage will vary depending on the prebias
voltage, but the total time from enable to when the output
reaches its target value will match the preconfigured delay and
ramp times. When ramping down from a prebias higher than the
target voltage, the device will wait until after SS ramp time is
complete and will then ramp down to the target voltage at an
approximate rate of 0.1V/ms (see Figure 13).
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ZL2102
an immediate shutdown of the device during the fault and an
VOUT
TARGET
automatic restart when the fault has cleared, but the response
can be adjusted using the OT_FAULT_RESPONSE PMBus
command.
VOLTAGE
If the device is configured to restart, it will wait 250ms and will
then check the device temperature. Once the temperature has
dropped below the over-temperature warning limit, the device
will attempt to restart. The default value of the over-temperature
warning limit is +110°C, providing +15°C of hysteresis, but the
value can be adjusted using the OT_WARN_LIMIT PMBus
command.
PREBIAS
VOLTAGE
TIME
SS
DELAY
SS
RAMP
Voltage Margining
VPREBIAS < VTARGET
The ZL2102 provides a simple method to vary its output higher or
lower than its nominal voltage setting in order to determine
whether the load device is capable of operating over its specified
supply voltage range. The voltage margin range can be set by
driving the MGN pin or using the OPERATION PMBus command.
The MGN pin is a tri-level input that is continuously monitored
and can be driven directly by a processor I/O pin or other
logic-level output.
VOUT
PREBIAS
VOLTAGE
TARGET
VOLTAGE
The ZL2102's output will be forced higher than its nominal set
point when the MGN command is set HIGH, and the output will be
forced lower than its nominal set point when the MGN command is
set LOW. The default margin settings are ±5% of the pin strapped
TIME
SS
DELAY
SS
RAMP
value of V , but the margin settings can be adjusted using the
OUT
VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW PMBus
VPREBIAS > VTARGET
FIGURE 13. OUTPUT RESPONSES TO PREBIAS VOLTAGES
commands. The default transition rate between the nominal
output voltage and either margin limit is 0.5V/ms, but it can be
adjusted using the VOUT_TRANSITION_RATE PMBus command.
If the prebias voltage is higher than the output overvoltage limit
set in VOUT_OV_FAULT_LIMIT, the device will declare an
overvoltage fault condition and it will respond based on the
output overvoltage response method that has been selected in
the VOUT_OV_FAULT_RESPONSE PMBus command.
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to
communicate between Intersil Digital-DC devices. This dedicated
bus provides the communication channel between devices for
features such as sequencing and fault spreading. The DDC pin on
all Digital-DC devices in an application should be connected
together. A pull-up resistor is required on the DDC bus in order to
Output Overcurrent Protection
The ZL2102 incorporates a patented "lossless" current sensing
method across the internal low-side MOSFET that is independent
guarantee the rise time as follows: Rise time = R * C
≈ 1µs,
is the
PU LOAD
of r
variations, including temperature. This current limiting
DS(ON)
where R is the DDC bus pull-up resistance and C
PU LOAD
mechanism is used to protect the power supply from damage
and prevent excessive current from being drawn from the input
supply in the event that the output is overloaded or shorted to
ground. Current limiting is accomplished by sensing the current
through the circuit during a portion of the duty cycle. The current
limit threshold is set to 7.2A by default, but it can be adjusted
using the IOUT_AVG_OC_FAULT_LIMIT PMBus command. The
default response of an overcurrent fault is an immediate
shutdown of the device during the fault and an automatic restart
when the fault has cleared, but it can be adjusted using the
MFR_IOUT_OC_RESPONSE PMBus command.
bus loading. The pull-up resistor may be tied to VR or to an
external 3.3V or 5V supply as long as this voltage is present prior
to or during device power-up. As a rule of thumb, each device
connected to the DDC bus presents approximately 10pF of
capacitive loading, and each inch of FR4 PCB trace introduces
approximately 2pF. The ideal design will use a central pull-up
resistor that is well-matched to the total load capacitance. In
power module applications, the user should consider whether to
place the pull-up resistor on the module or on the PCB of the end
application. The minimum pull-up resistance should be limited to
a value that enables any device to assert the bus to a voltage that
will ensure a logic 0 (typically 0.8V at the device monitoring
point) given the pull-up voltage (5V if tied to VR5) and the
pull-down current capability of the ZL2102 (nominally 4mA).
Thermal Overload Protection
The ZL2102 includes an on-chip thermal sensor that
continuously measures the internal temperature of the die and
shuts down the device when the temperature exceeds the preset
limit. The default temperature limit is set to +125°C in the
factory, but it can be adjusted using the OT_FAULT_LIMIT PMBus
command. The default response to an over-temperature fault is
Phase Spreading
When multiple power converters share a common DC input
supply, it is desirable to adjust the clock phase offset of each
device, such that not all devices start to switch simultaneously.
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ZL2102
Setting each converter to start its switching cycle at a different
Fault Spreading
point in time can dramatically reduce input capacitance
requirements and efficiency losses. Since the peak current
drawn from the input supply is effectively spread out over a
Digital-DC devices can be configured to broadcast a fault event
over the DDC bus to the other devices in the group. When a fault
occurs and the device is configured to shut down on a fault, the
device will shut down and broadcast the fault event over the DDC
bus. The other devices on the DDC bus can be configured to
respond to the broadcast in several ways including group
shutdown/restart. Fault spreading mode can be enabled through
the USER_CONFIG PMBus command, and the fault spreading
group can be defined through the DDC_GROUP PMBus
command.
period of time, the peak current drawn at any given moment is
2
reduced and the power losses proportional to the I
reduced dramatically.
are
RMS
In order to enable phase spreading, all converters must be
synchronized to the same switching clock. This can be
accomplished by setting the CFG pin strap or by using the
INTERLEAVE PMBus command.
Selecting the phase offset for the device is accomplished by
selecting a device address according to Equation 3:
Monitoring via SMBus
A system controller can monitor a wide variety of different
ZL2102 parameters through the SMBus interface. The device can
monitor for fault conditions by monitoring the SALRT pin, which
will be asserted when any number of preconfigured fault
conditions occur.
(EQ. 3)
Phase offset = device address 45
For example:
• A device address of 0x20 would configure no phase offset
• A device address of 0x21 would configure 45° of phase offset
• A device address of 0x22 would configure 90° of phase offset
The device can also be monitored continuously for many power
conversion parameters including input voltage, output voltage,
output current, internal junction temperature, switching
frequency, duty cycle, fault status information.
The phase offset of each device may also be set to any value
between 0° and 360° in 22.5° increments via the INTERLEAVE
PMBus command.
The PMBus Host should respond to SALRT as follows:
• ZL device pulls SALRT Low.
Output Sequencing
• PMBus Host detects that SALRT is now low, performs
transmission with Alert Response Address to find which ZL
device is pulling SALRT low.
Intersil devices may be configured to power-up as a group in a
predetermined sequence. This feature is especially useful when
powering advanced processors, FPGA’s and ASIC’s that require
one supply to reach its operating voltage prior to another supply
reaching its operating voltage in order to avoid latch-up from
occurring. Multidevice sequencing can be achieved by
configuring each device through the SEQUENCE PMBus
command or by using Intersil patented autonomous sequencing
mode.
• PMBus Host talks to the ZL device that has pulled SALRT low.
The actions that the host performs are up to the System
Designer.
If multiple devices are faulting, SALRT will still be low after doing
the above steps and will require transmission with the Alert
Response Address repeatedly until all faults are cleared.
Autonomous sequencing mode configures sequencing by using
events transmitted between devices over the DDC bus. The
sequencing order is determined using each device's SMBus
address. Using autonomous sequencing mode (configured using
the CFG pin), the devices must be assigned sequential SMBus
addresses with no missing addresses in the chain, the enable
pins must be tied together, and the sync pins of all devices must
be tied together. The first device in the sequence will become the
clock master, and the other devices will sync to this clock. This
mode will also constrain each device to have a phase offset
according to its SMBus address as described in the “Phase
Spreading” on page 15.
Nonvolatile Memory
The ZL2102 has internal nonvolatile memory where user settings
are stored. There are two storage locations; the factory store and
the user store. During the initialization process, the ZL2102
checks for any stored values in the user store. If user
programmed settings are found, they will be used for those
parameters. If there are no user settings stored, the factory
settings and pin strap values are used for those parameters.
Snapshot™ Parametric Capture
The ZL2102 offers a special feature that enables the user to
capture parametric data during normal operation or following a
fault. The Snapshot function can be enabled through the
MISC_CONFIG PMBus command, and the data can be read back
as a block read transfer using the SNAPSHOT PMBus command.
The enable (EN) line is driven high to initiate a sequenced turn-on
of the group. Enable is driven low to initiate a sequenced turnoff
of the group. During enable, the sequencing group will enable in
order starting with the device with the lowest SMBus address and
will continue through to turn on each device in the address chain
until all devices connected have been turned on. During disable,
the device with the highest SMBus address will turn off first
followed in reverse order by the other devices in the group. The
PG threshold is used to determine when the following device is
enabled.
The SNAPSHOT_CONTROL PMBus command enables the user to
store the snapshot parameters to NV memory in response to a
fault as well as to read the stored data from NV memory after a
fault has occurred.
Automatic writes to NV memory following a fault are triggered
when any fault threshold level is exceeded, provided that the
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ZL2102
specific fault's response is to shut down. Writing to NV memory is
not allowed if the device is configured to retry following the
specific fault condition.
Inductor Selection
The output inductor selection process must include several
trade-offs. A high inductance value will result in a low ripple
The device's VDD voltage must remain valid during the time
when the device is writing the data to NV memory; a process that
requires up to 2ms.
current (I ), which will reduce output capacitance and produce
opp
a low output ripple voltage, but may also compromise output
transient load performance. Therefore, a balance must be struck
between output ripple and optimal load transient performance. A
good starting point is to select the output inductor ripple equal to
Power Train Component Selection
the expected load transient step magnitude (I
): I
= I
.
ostep opp ostep
The ZL2102 is a synchronous buck converter with MOSFETs that
uses an external inductor and capacitors to perform the power
conversion process. The proper selection of the external
components is critical for optimized performance.
Now the output inductance can be calculated using Equation 4,
where V
is the maximum input voltage:
INM
V
OUT
---------------
V
1 –
To select the appropriate external components for the desired
performance goals, the power supply requirements listed in
Table 8 must be known.
OUT
V
INM
(EQ. 4)
-----------------------------------------------------
L
=
OUT
f
I
opp
SW
The average inductor current is equal to the maximum output
TABLE 8. TABLE SUPPLY REQUIREMENTS
current. The peak inductor current (I ) is calculated using
Lpk
is the maximum output current:
PARAMETER
RANGE
4.5V to 14.0V
0.6V to 5.0V
0A to 6A
EXAMPLE VALUE
Equation 5, where I
OUT
Input voltage (V
)
12V
3.3V
4A
IN
I
opp
2
(EQ. 5)
----------
I
= I
+
OUT
Lpk
Output voltage (V
)
OUT
Select an inductor rated for the average DC current with a peak
current rating above the peak current computed in Equation 5.
Output current (I
)
OUT
Output voltage ripple
(V
<3% of V
1% of V
OUT
OUT
)
In overcurrent or short-circuit conditions, the inductor may have
currents greater than 2x the normal maximum rated output
current. It is desirable to use an inductor that still provides some
inductance at maximum current to protect the load and the
internal MOSFETs from damaging currents in this situation.
orip
Output load step (I
)
<Io
±25% of I
2.5A/µs
ostep
o
Output load step rate
-
-
Output deviation due to load step
Maximum PCB temp.
Desired efficiency
±3% of V
OUT
Once an inductor is selected, the DCR and core losses in the
inductor are calculated. Use the DCR specified in the inductor
manufacturer's datasheet.
+120°C
+85°C
85%
-
-
Other considerations
Optimize for small
size
2
(EQ. 6)
P
= DCR I
Lrms
LDCR
I
is given by:
Lrms
Design Goal Trade-offs
The design of the buck power stage requires several
compromises among size, efficiency, and cost. The inductor core
loss increases with frequency, so there is a trade-off between a
small output filter made possible by a higher switching frequency
and getting better power supply efficiency. Size can be decreased
by increasing the switching frequency at the expense of
efficiency. Cost can be minimized by using through-hole
inductors and capacitors; however these components are
physically large.
2
I
opp
12
(EQ. 7
-------------------
=
I
2 +
OUT
Lrms
where I
is the maximum output current. Next, calculate the
OUT
core loss of the selected inductor. Since this calculation is
specific to each inductor and manufacturer, refer to the chosen
inductor datasheet. Add the core loss and the ESR loss and
compare the total loss to the maximum power dissipation
recommendation in the inductor datasheet.
To start the design, select a switching frequency based on
Table 9. This frequency is a starting point and may be adjusted as
the design progresses.
TABLE 9. CIRCUIT DESIGN CONSIDERATION
Output Capacitor Selection
Several trade-offs must also be considered when selecting an
output capacitor. Low ESR values are needed to have a small
FREQUENCY RANGE
200kHz to 400kHz
400kHz to 800kHz
800kHz to 1MHz
EFFICIENCY
Highest
CIRCUIT SIZE
Larger
Moderate
Lower
Smaller
output deviation during transient load steps (V
) and low
osag
output voltage ripple (V ). However, capacitors with low ESR,
Smallest
orip
such as semi-stable (X5R and X7R) dielectric ceramic capacitors,
also have relatively low capacitance values. Many designs can
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ZL2102
use a combination of high capacitance devices and low ESR
devices in parallel.
ceramic with a low ESR (less than 10mΩ) and should have a
rating of 4V or more.
For high ripple currents, a low capacitance value can cause a
significant amount of output voltage ripple. Likewise, in high
transient load steps, a relatively large amount of capacitance is
needed to minimize the output voltage deviation while the
inductor current ramps up or down to the new steady state
output current value.
CVR SELECTION
This capacitor is used to both stabilize and provide noise filtering
for the 7V reference supply. It should be 4.7µF, should use a
semi-stable X5R or X7R dielectric ceramic capacitor with a low
ESR (less than 10mΩ) and should have a rating of 10V or more.
CVRA SELECTION
As a starting point, apportion one-half of the output ripple
voltage to the capacitor ESR and the other half to capacitance, as
shown in the following equations:
This capacitor is used to both stabilize and provide noise filtering
for the analog 5V reference supply. It should be 4.7µF, should use
a semi-stable X5R or X7R dielectric ceramic capacitor with a low
ESR (less than 10mΩ) and should have a rating of 6.3V or more.
I
opp
(EQ. 8)
----------------------------------------
C
=
OUT
V
orip
-------------
8 f
SW
2
THERMAL CONSIDERATIONS
V
In typical applications, the ZL2102's high efficiency will limit the
internal power dissipation inside the package. However, in
applications that require a high ambient operating temperature
the user must perform some thermal analysis to ensure that the
ZL2102's maximum junction temperature is not exceeded.
orip
(EQ. 9)
--------------------
ESR =
2 I
opp
Use these values to make an initial capacitor selection, using a
single capacitor or several capacitors in parallel.
After a capacitor has been selected, the resulting output voltage
ripple can be calculated using Equation 10:
The ZL2102 has a maximum junction temperature limit of
+125°C, and the internal over-temperature limiting circuitry will
force the device to shut down if its junction temperature exceeds
this threshold. In order to calculate the maximum junction
temperature, the user must first calculate the power dissipated
inside the IC (PQ) as expressed in Equation 12:
I
opp
C
OUT
(EQ. 10)
------------------------------------------
V
= I
ESR +
opp
orip
8 f
SW
Because each part of this equation was made to be less than or
equal to half of the allowed output ripple voltage, the V
be less than the desired maximum output ripple.
should
orip
2
(EQ. 12)
P
= I
r
D + r
1 – D
DSONQL
Q
LOAD
DSONQH
The operating junction temperature can then be calculated using
Equation 13:
Input Capacitor
It is highly recommended that dedicated input capacitors be
used in any point of load design, even when the supply is
powered from a heavily filtered 5V or 12V "bulk" supply from an
off-line power supply. This is because of the high RMS ripple
current that is drawn by the buck converter topology. This ripple
(EQ. 13)
T
= T
+ P
pcb Q JC
i
Where T
pcb
is the printed circuit board temperature (under the
package) and is the junction-to-case thermal resistance for
JC
(I
) can be determined from Equation 11:
CINrms
the ZL2102 package.
(EQ. 11)
I
= I
D 1 – D
OUT
CINrms
PCB Layout Recommendation
Without capacitive filtering near the power supply circuit, this
current would flow through the supply bus and return planes,
coupling noise into other system circuitry. The input capacitors
should be rated at 1.2x the ripple current calculated above to
avoid overheating of the capacitors due to the high ripple current,
which can cause premature failure. Ceramic capacitors with X7R
or X5R dielectric with low ESR and 1.1x the maximum expected
input voltage are recommended.
The PCB layout is a very important step to make sure the
designed converter works well. For ZL2102, the power system is
composed of the input capacitor, VDDP pins, output inductor,
SWITCH pins, output capacitor, and the PGND pins. It is
necessary to group these connections as closely as possible and
the connecting traces among them should be direct, short and
wide. The switching node of the ZL2102 should connect directly
to the inductor with minimal distance. The ZL2102 PGND pins,
input and output capacitors should be connected as closely as
possible to each other on the power GND plane. The input
capacitor should be tightly coupled to the VIN pin. The VSEN
voltage feedback trace should be routed to avoid the switch
node, and should be connected directly to the pad of the output
capacitor. The thermal pad is connected to SGND, and PGND
must be isolated from SGND aside from a single connection
point at the SGND pin.
BOOTSTRAP CAPACITOR SELECTION
The high-side driver boost circuit utilizes an internal Schottky
diode (DB) and an external bootstrap capacitor (CB) to supply
sufficient gate drive for the high-side MOSFET driver. CB should
be a 0.1µF ceramic type rated for at least 10V.
CV2P5 SELECTION
This capacitor is used to both stabilize and provide noise filtering
for the 2.5V internal power supply. It should be between 4.7µF
and 10µF, should use a semi-stable X5R or X7R dielectric
The heat of the IC is mainly dissipated through the thermal pad.
It is recommended to pass the heat from the thermal pad
through the PCB using a large number of thermal vias. Connect
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ZL2102
2
as much copper as possible to these thermal vias throughout the
PCB layers to help dissipate the heat, but do not route this SGND
connection underneath any of the power components. The
bottom layer is the best conductor of heat, so it should have at
least 25mm of copper connected to these vias. Any traces that
must be routed in this copper area should be radial in nature so
that the thermal path from the thermal vias outward is not
interrupted.
PMBus Command Summary
DATA
FORMAT
DEFAULT
VALUE
CODE
COMMAND NAME
DESCRIPTION
TYPE
R/W
DEFAULT SETTING
01h OPERATION
Enable/disable, margin settings
BIT
04h
immediate off, nominal
margin
02h ON_OFF_CONFIG
On/off configuration settings
R/W
BIT
17h
ENABLE pin control, active
high
03h CLEAR_FAULTS
15h STORE_USER_ALL
16h RESTORE_USER_ALL
20h VOUT_MODE
Clears faults
Write
Write
Write
Read
N/A
N/A
N/A
BIT
Stores values to user store
Restores values from user store
Reports V
OUT
mode and exponent
13h
Linear Mode,
Exponent = -13
21h VOUT_COMMAND
24h VOUT_MAX
Sets nominal V
OUT
setpoint
setpoint
R/W
R/W
L16u
L16u
Pin strap setting
sets maximum V
OUT
1.1 X VOUT_COMMAND pin
strap setting
25h VOUT_MARGIN_HIGH
26h VOUT_MARGIN_LOW
27h VOUT_TRANSITION_RATE
Sets V
Sets V
Sets V
setpoint during margin high
setpoint during margin low
transition rate during margin
R/W
R/W
R/W
L16u
L16u
L11
1.05 x VOUT_COMMAND pin
strap setting
OUT
OUT
OUT
0.95 x VOUT_COMMAND pin
strap setting
B200h 0.5V/ms
commands
33h FREQUENCY_SWITCH
37h INTERLEAVE
Sets switching frequency
R/W
R/W
L11
BIT
Pin strap setting
Configures phase offset during group
operation
Group number 0, group size
16, position = 4 LSB's of
SMBus address
40h VOUT_OV_FAULT_LIMIT
Sets the V
overvoltage fault threshold
R/W
L16u
1.15 x VOUT_COMMAND pin
strap setting
OUT
41h VOUT_OV_FAULT_RESPONSE
44h VOUT_UV_FAULT_LIMIT
Sets the V
Sets the V
overvoltage fault response
undervoltage fault threshold
R/W
R/W
BIT
BFh
BFh
Restart continuously
OUT
L16u
0.85 x VOUT_COMMAND pin
strap setting
OUT
45h VOUT_UV_FAULT_RESPONSE
46h IOUT_OC_FAULT_LIMIT
4Bh IOUT_UC_FAULT_LIMIT
Sets the V
undervoltage fault response
R/W
BIT
L11
L11
Restart continuously
OUT
OUT
OUT
Sets the I
peak overcurrent fault threshold R/W
D240h 9A
D5C0h -9A
Sets the I
threshold
valley undercurrent fault
R/W
4Fh OT_FAULT_LIMIT
Sets the over-temperature fault limit
Sets the over-temperature fault response
Sets the over-temperature warning limit
Sets the under-temperature warning limit
Sets the under-temperature fault limit
Sets the under-temperature fault response
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
L11
BIT
EBE8h +125˚C
50h OT_FAULT_RESPONSE
51h OT_WARN_LIMIT
BFh
Restart continuously
L11
L11
L11
BIT
EB70h +110°C
E4E0h -50°C
E490h -55°C
52h UT_WARN_LIMIT
53h UT_FAULT_LIMIT
54h UT_FAULT_RESPONSE
55h VIN_OV_FAULT_LIMIT
56h VIN_OV_FAULT_RESPONSE
57h VIN_OV_WARN_LIMIT
BFh
Restart continuously
Sets the V overvoltage fault threshold
IN
L11
BIT
D380h 14V
Sets the V overvoltage fault response
IN
BFh
Restart continuously
Sets the V overvoltage warning threshold
IN
L11
D360h 13.5V
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ZL2102
PMBus Command Summary(Continued)
DATA
FORMAT
DEFAULT
VALUE
CODE
COMMAND NAME
DESCRIPTION
Sets the V undervoltage warning threshold
TYPE
R/W
DEFAULT SETTING
58h VIN_UV_WARN_LIMIT
L11
1.03 x VIN_UV_FAULT_LIMIT
pin strap setting
IN
59h VIN_UV_FAULT_LIMIT
5Ah VIN_UV_FAULT_RESPONSE
5Eh POWER_GOOD_ON
Sets the V undervoltage fault threshold
IN
R/W
R/W
R/W
L11
BIT
Pin strap setting
Sets the V undervoltage fault response
IN
BFh
Restart continuously
Sets the voltage threshold for Power-Good
indication
L16u
0.9 x VOUT_COMMAND pin
strap setting
60h TON_DELAY
61h TON_RISE
Sets the delay time from enable to V
rise
after ENABLE and
R/W
R/W
L11
L11
Pin strap setting
Pin strap setting
OUT
Sets the rise time of V
TON_DELAY
OUT
64h TOFF_DELAY
65h TOFF_FALL
Sets the delay time from DISABLE to start of
R/W
after DISABLE and R/W
Read
L11
L11
1 x TON_DELAY pin strap
value
V
fall
OUT
Sets the fall time for V
TOFF_DELAY
1 x TON_RISE pin strap
setting
OUT
79h STATUS_WORD
7Ah STATUS_VOUT
Summary of critical faults
BIT
BIT
BIT
BIT
BIT
BIT
BIT
Reports V
warnings/faults
Read
Read
Read
Read
OUT
7Bh STATUS_IOUT
Reports I
warnings/faults
OUT
7Ch STATUS_INPUT
7Dh STATUS_TEMPERATURE
7Eh STATUS_CML
Reports input warnings/faults
Reports temperature warnings/faults
Reports Communication, memory, logic errors Read
80h STATUS_MFR_SPECIFIC
Reports voltage monitoring/clock
synchronization faults
Read
88h READ_VIN
Reports input voltage measurement
Reports output voltage measurement
Reports output current measurement
Reports internal temperature measurement
Reports actual duty cycle
Read
Read
Read
Read
Read
Read
Read
L11
L16u
L11
L11
L11
L11
BIT
8Bh READ_VOUT
8Ch READ_IOUT
8Dh READ_TEMPERATURE_1
94h READ_DUTY_CYCLE
95h READ_FREQUENCY
98h PMBUS_REVISION
Reports actual switching frequency
Reports PMBus revision compliance
01h
Part 1 Revision 1.0, Part II
Revision 1.1
99h MFR_ID
Sets a user defined identification
Reports device identification information
Reports device revision information
Sets a user defined data
R/W
Read
Read
R/W
R/W
Write
R/W
ASC
CUS
CUS
ASC
BIT
<null>
ADh IC_DEVICE_ID
AEh IC_DEVICE_REV
B0h USER_DATA_00
BCh AUTO_COMP_CONFIG
BDh AUTO_COMP_CONTROL
D0h MFR_CONFIG
<null>
Sets auto compensation configuration
Initiates auto compensation algorithm
Pin strap setting
N/A
BIT
Configures several manufacturer-level
features
4801h
D1h USER_CONFIG
D3h DDC_CONFIG
Configures several user-level features
Configures the DDC bus
R/W
R/W
BIT
BIT
Pin strap setting
Broadcast group = 0,
DDC ID = 5 LSBs of SMBus
address
D4h POWER_GOOD_DELAY
Sets the delay between PG threshold and PG R/W
assertion
L11
BA00h 1ms
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ZL2102
PMBus Command Summary(Continued)
DATA
FORMAT
DEFAULT
VALUE
CODE
COMMAND NAME
DESCRIPTION
TYPE
R/W
DEFAULT SETTING
D5h PID_TAPS
Configures the control loop compensator
coefficients
CUS
Dependent upon autocomp
settings
E0h SEQUENCE
DDC rail sequencing configuration
R/W
CUS
BIT
Pin strap setting
E2h DDC_GROUP
sets which rail DDC IDs are monitored for fault R/W
spreading
00h
E4h DEVICE_ID
Returns the device identifier string
Read
ASC
<part number/die
revision/firmware revision>
E5h MFR_IOUT_OC_FAULT_RESPONSE Configures the I
OUT
overcurrent fault response R/W
BIT
BIT
BFh
BFh
Restart continuously
Restart continuously
E6h MFR_IOUT_UC_FAULT_RESPONSE Configures the I
response
undercurrent fault
R/W
R/W
R/W
OUT
E7h IOUT_AVG_OC_FAULT_LIMIT
Sets the I
threshold
average overcurrent fault
average undercurrent fault
L11
L11
CB99h 7.2A
CC67h -7.2A
00h
OUT
E8h IOUT_AVG_UC_FAULT_LIMIT
Sets the I
threshold
OUT
E9h MISC_CONFIG
EAh SNAPSHOT
Sets options pertaining to advanced features R/W
BIT
BIT
32-byte read-back of parametric and status
values
Read
EBh BLANK_PARAMS
Indicates user saved parameter values
Snapshot feature control command
Read
R/W
Write
BIT
BIT
F3h SNAPSHOT_CONTROL
F4h RESTORE_FACTORY
00h
Restores device to the hard-coded default
values and pin strap definitions
N/A
PMBus Data Formats
LINEAR-11 (L11)
L11 data format uses 5-bit two's compliment exponent (N) and 11-bit two's compliment mantissa (Y) to represent real world decimal
value (X).
Data Byte High
Data Byte Low
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Exponent (N)
Mantissa (Y)
N
Relation between real world decimal value (X), N and Y is: X = Y·2
Linear-16 Unsigned (L16u)
L16u data format uses a fixed exponent (hardcode to N = -13) set by VOUT_MODE Command and 16-bit unsigned integer mantissa (Y)
to represent real world decimal value (X).
-13
Relation between real world decimal value (X), N and Y is: X = Y·2
Bit Field (BIT)
Break down of Bit field is provided in “PMBus Command Summary” on page 19.
Custom (CUS)
Break down of Custom data format is provided in “PMBus Command Summary” on page 19. A combination of Bit field and integer are
common type of Custom data format.
ASCII (ASC)
A variable length string of text characters uses ASCII data format.
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ZL2102
PMBus Command Detail
OPERATION (01h)
Definition: Enable/disable command and VOUT Margin settings. The MGN pin has priority over the margin state of the device. Data
values of OPERATION that force margin high or low only take effect when the MGN pin is left open (i.e., in the NOMINAL margin state).
When the MGN pin has been set either high or low, bits 5:4 only report the margin state. When ON_OFF_CONFIG command is set for pin
enable, Bits 7:6 only report the enable/disable status that has been set by the enable pin. All margin settings are "Act on Fault" type.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 04h (immediate off, nominal margin)
Units: N/A
Reference: N/A
COMMAND
Format
OPERATION (01h)
Bit Field
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
1
0
0
BITS 7:6
BITS 5:4
BITS 3:2
BITS 1:0
(ENABLE)
(MARGIN)
(FAULT RESPONSE)
(NOT USED)
UNIT ON OR OFF
MARGIN STATE
OFF
00
01
00
01
01
00
00
Immediate off
(No sequencing)
00
Soft off
OFF
(With sequencing)
10
10
10
00
01
10
01
01
01
00
00
00
ON
ON
ON
Nominal
Margin Low
Margin High
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ZL2102
ON_OFF_CONFIG (02h)
Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 17h (ENABLE pin control, active high)
Units: N/A
Reference: N/A
COMMAND
Format
ON_OFF_CONFIG (02h)
Bit Field
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
1
0
1
1
1
BIT NUMBER
PURPOSE
BIT VALUE
MEANING
7:5
4:2
Not Used
000
000
Not Used
Device enable setting
Device starts anytime power is present regardless of ENABLE
pin or OPERATION command states
101
110
0
Device starts from ENABLE pin only
Device starts from OPERATION command only
Active low (Pull pin low to start the device)
Active high (Pull pin high to start the device)
Use the programmed ramp down settings
Turn off the output immediately
1
0
Polarity of the ENABLE pin
1
ENABLE pin action when commanding the unit to
turn off
0
1
CLEAR_FAULTS (03h)
Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the
bit will reassert immediately. This command will not restart a device if it has shut down, it will only clear the faults.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
Reference: N/A
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ZL2102
STORE_USER_ALL (15h)
Definition: Stores all PMBus settings from the operating memory to the nonvolatile USER store memory. To clear the USER store,
perform a RESTORE_FACTORY then STORE_USER_ALL. To add to the USER store, perform a RESTORE_USER_ALL, write commands to
be added, then STORE_USER_ALL. This command can be used during device operation, but the device will be unresponsive for up to
20ms while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
Reference: N/A
RESTORE_USER_ALL (16h)
Definition: Restores all PMBus settings from the USER store memory to the operating memory. This command is performed
automatically at power-up. This command can be used during device operation, but the device will be unresponsive for up to 20ms
while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
Reference: N/A
VOUT_MODE (20H)
Definition: Reports the V
Data Length in Bytes: 1
Data Format: BIT
mode and provides the exponent used in calculating several V
settings.
OUT
OUT
Type: Read-only
Default Value: 13h (Linear Mode, Exponent = -13)
Units: N/A
Reference: N/A
COMMAND
Format
VOUT_MODE (20h)
Bit Field
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
1
0
0
1
1
MODE
Linear
BITS 7:5
000
BITS 4:0 (PARAMETER)
Five bit two’s complement exponent for the mantissa delivered as the data bytes for an output
voltage related command.
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ZL2102
VOUT_COMMAND (21h)
Definition: This command sets or reports the target output voltage. The integer value is multiplied by 2 raised to the power of
VOUT_MODE. This command cannot be set to be higher than the value of VOUT_MAX. This command can be written while the device is
enabled, but the adjusted value must be within 10% of the value that was selected prior to enable.
Data Length in Bytes: 2
Data Format: L16u.
Type: R/W
Default Value: Pin strap setting (VSET)
Units: Volts
Equation: V
-13
= VOUT_COMMAND×2
OUT
Range: 0.6V to 5.5V or the value of VOUT_MAX
Reference: N/A
Example: VOUT_MODE = 13h (Since the value is 5-bit signed 13h = -13)
VOUT_COMMAND = 699Ah = 27,034
-13
Target voltage equals: 27034× 2
= 3.3V
COMMAND
Format
VOUT_COMMAND (21h)
Linear, unsigned binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
Pin strap setting
VOUT_MAX (24h)
Definition: The VOUT_ MAX command sets an upper limit on the output voltage the unit can command regardless of any other
commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output
voltage to a possibly destructive level rather than to be the primary output overprotection. If a VOUT_COMMAND is sent with a value
higher than VOUT_MAX, the device will set the output voltage to VOUT_MAX. The initial value of VOUT_MAX is 110% of the pin strap
value of VOUT.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.10 x VOUT_COMMAND pin strap setting
Units: Volts
Equation: V
-13
max = VOUT_MAX×2
OUT
Range: 0V to 5.5V
Reference: N/A
COMMAND
Format
VOUT_MAX (24h)
Linear, unsigned binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
1.10 x VOUT_COMMAND Pin Strap Setting
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ZL2102
VOUT_MARGIN_HIGH (25h)
Definition: Sets the value of the VOUT when OPERATION or the MGN pin is set for “margin high”. This command can be written while the
device is enabled, but the adjusted value must be within 10% of the value of VOUT that was selected prior to enable.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default value: 1.05 x VOUT_COMMAND pin strap setting
Units: Volts
N
Equation: VOUT_MARGIN_HIGH = Y×2
Range: 0.54V to the value of VOUT_MAX
Reference: N/A
COMMAND
Format
VOUT_MARGIN_HIGH (25h)
Linear, unsigned binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
1.05 x VOUT_COMMAND
VOUT_MARGIN_LOW (26h)
Definition: Sets the value of the VOUT when OPERATION or the MGN pin is set for “margin low”. This command can be written while the
device is enabled, but the adjusted value must be within 10% of the value of VOUT that was selected prior to enable.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default value: 0.95 x VOUT_COMMAND pin strap setting
Units: Volts
N
Equation: VOUT_MARGIN_LOW = Y×2
Range: 0.54V to the value of VOUT_MAX
Reference: N/A
COMMAND
Format
VOUT_MARGIN_LOW (26h)
Linear, unsigned binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
0.95 x VOUT_COMMAND
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ZL2102
VOUT_TRANSITION_RATE (27h)
Definition: Sets the rate at which the output should change voltage when the device receives an OPERATION command (Margin High,
Margin Low) or VOUT_COMMAND command that causes the output voltage to change. The maximum possible positive value of the two
data bytes indicates that the device should make the transition as quickly as possible.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default value: B200h (0.5V/ms)
Units: V/ms
N
Equation: VOUT_TRANSITION_RATE = Y×2
Range: 0.1V/ms to 2V/ms
Reference: N/A
COMMAND
Format
VOUT_TRANSITION_RATE (27h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
FREQUENCY_SWITCH (33h)
Definition: Sets the switching frequency of the device. Initial default value is defined by a pin strap and this value can be overridden by
writing this command. If an external SYNC is utilized, this value should be set as close as possible to the external clock value. The
output must be disabled when writing this command.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting (SYNC)
Units: kHz
N
Equation: FREQUENCY_SWITCH = Y×2
Range: 200kHz to 1MHz
Reference: N/A
COMMAND
Format
FREQUENCY_SWITCH (33h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
Pin Strapped Value
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ZL2102
INTERLEAVE (37h)
Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. Note that a value of 0 for
the Number in Group field is interpreted as 16, to allow for phase spreading groups of up to 16 devices.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value:
Default Group Number: 0 (00h)
Default Number in Group: 16 (00h)
Default Position in Group: Four LSB's of SMBus address
Units: N/A
Reference: AN2034 - Configuring Current Sharing on the ZL2004 and ZL2006.
COMMAND
Format
INTERLEAVE (37h)
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
Four LSB’s of SMBus Address
BITS
15:2
11:8
7:4
PURPOSE
Not Used
VALUE
0
DESCRIPTION
Not Used
Group Number
Number in Group
Position in Group
0 to 15
0 to 15
0 to 15
Sets a number to a group of interleaved rails
Sets the number of rails in the group. A value of 0 is interpreted as 16.
Sets the position of the device’s rail within the group
3:0
VOUT_OV_FAULT_LIMIT (40h)
Definition: Sets the VOUT overvoltage fault threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.15 x VOUT_COMMAND pin strap setting
Units: Volts
-13
Equation: VOUT OV fault limit = VOUT_OV_FAULT_LIMIT×2
Range: 0V to 6V
Reference: N/A
COMMAND
Format
VOUT_OV_FAULT_LIMIT (40h)
Linear, unsigned binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
1.15 x VOUT_COMMAND
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ZL2102
VOUT_OV_FAULT_RESPONSE (41h)
Definition: Configures the V overvoltage fault response. Only two settings are valid: 80h (immediate shutdown until commanded to
OUT
restart) and BFh (immediate shutdown, 80ms delay, and then automatic restart once the fault condition has cleared).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: BFh (Disable and retry continuously)
Units: N/A
Reference: N/A
COMMAND
FORMAT
VOUT_OV_FAULT_RESPONSE (41h)
BIT FIELD
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
1
1
1
1
1
1
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior
During a fault, the device:
• Pulls SALRT low
Not Used
Disable and Retry according to the setting in bits [5:3].
Not Used
7:6
11
• Sets the related fault bit in the
status registers.
000
No Retry. The output remains disabled until the device is restarted.
001-110 Not Used
5:3
2:0
Retry Setting
Retry Time
111
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down. The time between retries is set by bits [2:0].
111
The device will wait 80ms between disable and restart. 111 is the only valid entry for this field.
VOUT_UV_FAULT_LIMIT (44h)
Definition: Sets the VOUT undervoltage fault threshold. This fault is masked during ramps (when PG is not set).
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.85 x VOUT_COMMAND pin strap setting
Units: Volts
Equation: V
-13
UV fault limit = VOUT_UV_FAULT_LIMIT×2
OUT
Range: 0V to 6V
Reference: N/A
COMMAND
Format
VOUT_UV_FAULT_LIMIT (44h)
Linear, unsigned binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
0.85 x VOUT_COMMAND
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ZL2102
VOUT_UV_FAULT_RESPONSE (45h)
Definition: Configures the VOUT undervoltage fault response. Only two settings are valid: 80h (immediate shutdown until commanded
to restart) and BFh (immediate shutdown, 80ms delay, and then automatic restart once the fault condition has cleared).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: BFh (Disable and retry continuously)
Units: N/A
Reference: N/A
COMMAND
FORMAT
VOUT_UV_FAULT_RESPONSE (45h)
BIT FIELD
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
1
1
1
1
1
1
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior
During a fault, the device:
• Pulls SALRT low
Not Used
Disable and Retry according to the setting in bits [5:3].
Not Used
7:6
11
• Sets the related fault bit in the
status registers.
000
No Retry. The output remains disabled until the device is restarted.
001-110 Not Used
5:3
2:0
Retry Setting
Retry Time
111
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down. The time between retries is set by bits [2:0].
111
The device will wait 80ms between disable and restart. 111 is the only valid entry for this field.
IOUT_OC_FAULT_LIMIT (46h)
Definition: Sets the IOUT peak overcurrent fault threshold. For down-slope sensing, this corresponds to the first current sample after the
Current Sense Blanking Time has expired during the (1-D) time interval. For up-slope sensing, this corresponds to the last current
sample of the D time interval. This feature shares the OC fault bit operation (in STATUS_IOUT) and OC fault response with
IOUT_AVG_OC_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: D240h (9A)
Units: A
N
Equation: IOUT_OC_FAULT_LIMIT = Y×2
Range: 0A to 9A
Reference: N/A
COMMAND
Format
IOUT_OC_FAULT_LIMIT (46h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
0
0
1
0
0
1
0
0
0
0
0
0
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ZL2102
IOUT_UC_FAULT_LIMIT (4Bh)
Definition: Sets the IOUT valley undercurrent fault threshold. For down-slope sensing, this corresponds to the last current sample of the
(1-D) time interval. For up-slope sensing, this corresponds to the first current sample of the D time interval, excluding the Current Sense
Blanking time (which occurs at the beginning of the D interval). This feature shares the UC fault bit operation (in STATUS_IOUT) and UC
fault response with IOUT_AVG_UC_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: D5C0h (-9A)
Units: A
N
Equation: IOUT_OC_FAULT_LIMIT = Y×2
Range: 0A to -9A
Reference: N/A
COMMAND
Format
IOUT_UC_FAULT_LIMIT (4Bh)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
OT_FAULT_LIMIT (4Fh)
Definition: Sets the over temperature fault threshold. Note that the temperature must drop below OT_WARN_LIMIT before the device
will automatically restart.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: EBE8h (+125°C)
Units: Celsius
N
Equation: OT_FAULT_LIMIT = Y×2
Range: 0°C to +125°C
Reference: N/A
COMMAND
Format
OT_FAULT_LIMIT (4Fh)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
1
0
1
0
1
1
1
1
1
0
1
0
0
0
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ZL2102
OT_FAULT_RESPONSE (50h)
Definition: Configures the over temperature fault response. Only two settings are valid: 80h (immediate shutdown until commanded to
restart) and BFh (immediate shutdown, 250ms delay, and then automatic restart once the fault condition has cleared). The
temperature must drop below OT_WARN_LIMIT before the device will restart.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: BFh (Disable and retry continuously)
Units: N/A
Reference: N/A
COMMAND
FORMAT
OT_FAULT_RESPONSE (50h)
BIT FIELD
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
BIT
1
0
1
1
1
1
1
1
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior
Not Used
During a fault, the device:
• Pulls SALRT low
Disable and Retry according to the setting in bits [5:3].
Not Used
7:6
11
• Sets the related fault bit in the
status registers.
000
No Retry. The output remains disabled until the device is restarted.
001-110 Not Used
5:3
2:0
Retry Setting
Retry Time
111
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down. The time between retries is set by bits [2:0].
111
The device will wait 250ms between disable and restart. 111 is the only valid entry for this field.
OT_WARN_LIMIT (51h)
Definition: Sets the over temperature warning alarm threshold. In response to the threshold being exceeded, the device:
• Sets the TEMPERATURE bit in STATUS_WORD,
• Sets the OT_WARNING bit in STATUS_TEMPERATURE, and
• Notifies the host by setting the SALRT pin.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: EB70h (+110°C)
Units: Celsius
N
Equation: OT_WARN_LIMIT = Y×2
Range: 0°C to +125°C
Reference: N/A
COMMAND
Format
OT_WARN_LIMIT (51h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
1
0
1
0
1
1
0
1
1
1
0
0
0
0
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ZL2102
UT_WARN_LIMIT (52h)
Definition: Sets the under-temperature warning alarm threshold. In response to the threshold being exceeded, the device:
• Sets the TEMPERATURE bit in STATUS_WORD,
• Sets the UT_WARNING bit in STATUS_TEMPERATURE, and
• Notifies the host by setting the SALRT pin.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: E4E0h (-50°C)
Units: Celsius
N
Equation: UT_WARN_LIMIT = Y×2
Range: -55°C to +25°C
Reference: N/A
COMMAND
Format
UT_WARN_LIMIT (52h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
1
0
0
1
0
0
1
1
1
0
0
0
0
0
UT_FAULT_LIMIT (53h)
Definition: Sets the under-temperature fault threshold. Note that the temperature must rise above UT_WARN_LIMIT before the device
will automatically restart.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: E490h (-55°C)
Units: Celsius
N
Equation: UT_FAULT_LIMIT = Y×2
Range: -55°C to +25°C
Reference: N/A
COMMAND
Format
UT_FAULT_LIMIT (53h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
1
0
0
1
0
0
1
0
0
1
0
0
0
0
UT_FAULT_RESPONSE (54h)
Definition: Configures the under-temperature fault response. Only two settings are valid: 80h (immediate shutdown until commanded
to restart) and BFh (immediate shutdown, 250ms delay, and then automatic restart once the fault condition has cleared). The
temperature must rise above UT_WARN_LIMIT before the device will automatically restart.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: BFh (Disable and retry continuously)
Units: N/A
Reference: N/A
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ZL2102
COMMAND
FORMAT
UT_FAULT_RESPONSE (54h)
BIT FIELD
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
1
1
1
1
1
1
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior
During a fault, the device:
• Pulls SALRT low
Not Used
Disable and Retry according to the setting in bits [5:3].
Not Used
7:6
11
• Sets the related fault bit in the
status registers.
000
No Retry. The output remains disabled until the device is restarted.
001-110 Not Used
5:3
2:0
Retry Setting
Retry Time
111
111
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down. The time between retries is set by bits [2:0].
The device will wait 250ms between disable and restart. 111 is the only valid entry for this field.
VIN_OV_FAULT_LIMIT (55h)
Definition: Sets the VIN overvoltage fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: D380h (14V)
Units: Volts
N
Equation: VIN_OV_FAULT_LIMIT = Y×2
Range: 4.5V to 16V
Reference: N/A
COMMAND
Format
VIN_OV_FAULT_LIMIT (55h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
0
0
1
1
1
0
0
0
0
0
0
0
VIN_OV_FAULT_RESPONSE (56h)
Definition: Configures the V overvoltage fault response as defined by the following table. Only two settings are valid: 80h (immediate
IN
shutdown until commanded to restart) and BFh (immediate shutdown, 80ms delay, and then automatic restart once the fault condition
has cleared).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: BFh (Disable and retry continuously)
Units: N/A
Reference: N/A
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ZL2102
COMMAND
FORMAT
VIN_OV_FAULT_RESPONSE (56h)
BIT FIELD
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
1
1
1
1
1
1
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior
During a fault, the device:
• Pulls SALRT low
Not Used
Disable and Retry according to the setting in bits [5:3].
Not Used
7:6
11
• Sets the related fault bit in the
status registers.
000
No Retry. The output remains disabled until the device is restarted.
001-110 Not Used
5:3
2:0
Retry Setting
Retry Time
111
111
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down. The time between retries is set by bits [2:0].
The device will wait 80ms between disable and restart. 111 is the only valid entry for this field.
VIN_OV_WARN_LIMIT (57h)
Definition: Sets the V overvoltage warning threshold as defined by the following table. In response to the OV_WARN_LIMIT being
IN
exceeded, the device:
• Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD
• Sets the VIN_OV_WARNING bit in STATUS_INPUT, and
• Notifies the host by setting the SALRT pin.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: D360h (13.5V)
Units: Volts
N
Equation: VIN_OV_FAULT_LIMIT = Y×2
Range: 4.5V to 16V
Reference: N/A
COMMAND
Format
VIN_OV_WARN_LIMIT (57h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
0
0
1
1
0
1
1
0
0
0
0
0
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ZL2102
VIN_UV_WARN_LIMIT (58h)
Definition: Sets the VIN undervoltage warning threshold. If a VIN_UV_FAULT occurs, the input voltage must rise above
VIN_UV_WARN_LIMIT to clear the fault, which provides hysteresis to the fault threshold. In response to the UV_WARN_LIMIT being
exceeded, the device:
• Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD,
• Sets the VIN_UV_WARNING bit in STATUS_INPUT, and
• Notifies the host by setting the SALRT pin.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 1.03 x VIN_UV_FAULT_LIMIT pin strap setting
Units: V
N
Equation: VIN_UV_WARN_LIMIT = Y×2
Range: 4.5V to 16V
Reference: N/A
COMMAND
Format
VIN_UV_WARN_LIMIT (58h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
1.03 x VIN_UV_FAULT_LIMIT
Default Value
VIN_UV_FAULT_LIMIT (59h)
Definition: Sets the VIN undervoltage fault threshold. Also referred to as undervoltage lockout (UVLO).
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting (SS)
Units: Volts
N
Equation: VIN_UV_FAULT_LIMIT = Y×2
Range: 4.5V to 16V
Reference: N/A
COMMAND
Format
VIN_UV_FAULT_LIMIT (59h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
Pin Strapped Value
VIN_UV_FAULT_RESPONSE (5Ah)
Definition: Configures the V undervoltage fault response as defined by the following table. Only two settings are valid: 80h
IN
(immediate shutdown until commanded to restart) and BFh (immediate shutdown, 80ms delay, and then automatic restart once the
fault condition has cleared).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: BFh (Disable and retry continuously)
Units: N/A
Reference: N/A
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ZL2102
COMMAND
FORMAT
VIN_UV_FAULT_RESPONSE (5Ah)
BIT FIELD
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
1
1
1
1
1
1
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior
During a fault, the device:
• Pulls SALRT low
Not Used
Disable and Retry according to the setting in bits [5:3].
Not Used
7:6
11
• Sets the related fault bit in the
status registers.
000
No Retry. The output remains disabled until the device is restarted.
001-110 Not Used
5:3
2:0
Retry Setting
Retry Time
111
111
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down. The time between retries is set by bits [2:0].
The device will wait 80ms between disable and restart. 111 is the only valid entry for this field.
POWER_GOOD_ON (5Eh)
Definition: Sets the voltage threshold for Power-Good indication. Power-Good asserts when the output voltage exceeds
POWER_GOOD_ON and deasserts when the output voltage is less than VOUT_UV_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.9 x VOUT_COMMAND pin strap setting
Units: Volts
-13
Equation: Power-good on threshold = POWER_GOOD_ON×2
Range: 0V to 5V
Reference: N/A
COMMAND
Format
POWER_GOOD_ON (5Eh)
Linear, unsigned binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
0.9 x VOUT_COMMAND
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ZL2102
TON_DELAY (60h)
Definition: Sets the delay time from when the device is enabled to the start of V
rise.
OUT
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting (SS)
Units: ms
N
Equation: TON_DELAY = Y×2
Range: 5ms to 30s
Reference: N/A
COMMAND
Format
TON_DELAY (60h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
Pin Strapped Value
TON_RISE (61h)
Definition: Sets the rise time of V
Data Length in Bytes: 2
Data Format: L11
after ENABLE and TON_DELAY.
OUT
Type: R/W
Default Value: Pin strap setting (SS)
Units: ms
N
Equation: TON_RISE = Y×2
Range: 5ms to 200ms
Reference: N/A
COMMAND
Format
TON_RISE (61h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
Pin Strapped Value
TOFF_DELAY (64h)
Definition: Sets the delay time from DISABLE to start of V
fall.
OUT
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 1 x TON_DELAY pin strap value
Units: ms
N
Equation: TON_DELAY = Y×2
Range: 5ms to 30s
Reference: N/A
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ZL2102
COMMAND
Format
TOFF_DELAY (64h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1 x TON_DELAY
TOFF_FALL (65h)
Definition: Sets the fall time for V
Data Length in Bytes: 2
Data Format: L11
after DISABLE and TOFF_DELAY.
OUT
Type: R/W
Default Value: 1 x TON_RISE pin strap setting
Units: ms
N
Equation: TOFF_FALL = Y×2
Range: 5ms to 200ms
Reference: N/A
COMMAND
Format
TOFF_FALL (65h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1 x TON_RISE
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ZL2102
STATUS_WORD (79h)
Definition: Returns fault condition status information. Based on the information in these bytes, the host can get more information by
reading the appropriate status registers. Status bits are only cleared by a forced restart or by writing to the CLEAR_FAULTS PMBus
command.
Data Length in Bytes: 2
Data Format: BIT
Type: Read-only
Default Value: N/A
Units: N/A
Reference: N/A
COMMAND
Format
STATUS_WORD (79h)
Bit Field
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
BIT NUMBER
STATUS BIT NAME
VOUT
MEANING
15
14
13
An output voltage fault or warning has occurred.
An output current or output power fault or warning has occurred.
IOUT
INPUT
An input voltage, input current, or input power fault or warning has
occurred.
12
11
10
9
MFG_SPECIFIC
POWER_GOOD #
NOT USED
A manufacturer specific fault or warning has occurred.
The POWER_GOOD signal, if present, is negated. (Note 12)
OTHER
A bit in STATUS_VOUT, STATUS_IOUT,STATUS_MFR_SPECIFIC, or
STATUS_VIN is set.
8
7
6
UNKNOWN
BUSY
A fault type not given in bits 15:1 of the STATUS_WORD has been
detected.
A fault was declared because the device was busy and unable to
respond.
OFF
This bit is asserted if the unit is not providing power to the output,
regardless of the reason, including simply not being enabled.
5
4
3
2
1
0
VOUT_OV_FAULT
IOUT_OC_FAULT
VIN_UV_FAULT
TEMPERATURE
CML
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
An input undervoltage fault has occurred.
A temperature fault or warning has occurred.
A communications, memory or logic fault has occurred.
A fault or warning not listed in bits 7:1 has occurred.
NONE OF THE ABOVE
NOTE:
12. If the POWER_GOOD# bit is set, this indicates that the POWER_GOOD signal, if present, is signaling that the output power is not good.
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ZL2102
STATUS_VOUT (7Ah)
Definition: Returns output voltage status information. Status bits are only cleared by a forced restart or by writing to the CLEAR_FAULTS
PMBus command.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: N/A
Units: N/A
Reference: N/A
COMMAND
FORMAT
STATUS_VOUT (7Ah)
BIT FIELD
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
BIT NUMBER
STATUS BIT NAME
MEANING
7
VOUT_OV_FAULT
N/A
Indicates an output overvoltage fault.
These bits are not used.
6:5
4
VOUT_UV_FAULT
N/A
Indicates an output undervoltage fault.
These bits are not used.
3:0
STATUS_IOUT (7Bh)
Definition: Returns the output current status information. Status bits are only cleared by a forced restart or by writing to the
CLEAR_FAULTS PMBus command.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: N/A
Units: N/A
Reference: N/A
COMMAND
FORMAT
STATUS_IOUT (7Bh)
BIT FIELD
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
BIT NUMBER
STATUS BIT NAME
MEANING
7
IOUT_OC_FAULT
N/A
Indicates an output overcurrent fault has occurred.
These bits are not used.
6:5
4
IOUT_UC_FAULT
N/A
Indicates an output undercurrent fault has occurred.
These bits are not used.
3:0
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ZL2102
STATUS_INPUT (7Ch)
Definition: Returns input voltage and input current status information. Status bits are only cleared by a forced restart or by writing to the
CLEAR_FAULTS PMBus command.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: N/A
Units: N/A
Reference: N/A
COMMAND
FORMAT
STATUS_INPUT (7Ch)
BIT FIELD
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
BIT NUMBER
STATUS BIT NAME
MEANING
7
6
VIN_OV_FAULT
VIN_OV_WARNING
VIN_UV_WARNING
VIN_UV_FAULT
N/A
Indicates an input overvoltage fault has occurred.
Indicates an input overvoltage warning has occurred.
Indicates an input undervoltage warning has occurred.
Indicates an input undervoltage fault has occurred.
These bits are not used.
5
4
3:0
STATUS_TEMPERATURE (7Dh)
Definition: Returns temperature related status information. Status bits are only cleared by a forced restart or by writing to the
CLEAR_FAULTS PMBus command.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: N/A
Units: N/A
Reference: N/A
COMMAND
FORMAT
STATUS_TEMPERATURE (7Dh)
BIT FIELD
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
BIT NUMBER
STATUS BIT NAME
MEANING
7
6
OT_FAULT
Indicates an over-temperature fault has occurred.
Indicates an over-temperature warning has occurred.
Indicates an under-temperature warning has occurred.
Indicates an under-temperature fault has occurred.
These bits are not used.
OT_WARNING
UT_WARNING
UT_FAULT
N/A
5
4
3:0
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ZL2102
STATUS_CML (7Eh)
Definition: Returns Communications, Logic and/or Memory status information. Status bits are only cleared by a forced restart or by
writing to the CLEAR_FAULTS PMBus command.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: N/A
Units: N/A
Reference: N/A
COMMAND
FORMAT
STATUS_CML (7Eh)
BIT FIELD
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
BIT NUMBER
MEANING
Invalid or unsupported PMBus Command was received.
7
6
The PMBus command was sent with Invalid or Unsupported data.
A packet error was detected in the PMBus command.
Not used.
5
4:2
1
A PMBus command tried to write to a read-only or protected command or a communication fault
other than other than the ones listed in this table has occurred.
0
Not used.
STATUS_MFR_SPECIFIC (80h)
Definition: Returns clock synchronization status. Only bit 3 is used on this command for this device. Status bits are only cleared by a
forced restart or by writing to the CLEAR_FAULTS PMBus command.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default value: N/A
Units: N/A
Reference: N/A
COMMAND
FORMAT
STATUS_MFR_SPECIFIC (80h)
BIT FIELD
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
BIT NUMBER
FIELD NAME
MEANING
7:4
3
Not Used
External Switching Period Fault
Not Used
Loss of external clock synchronization has occurred.
2:0
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ZL2102
READ_VIN (88h)
Definition: Returns the input voltage reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Default Value: N/A
Units: Volts
N
Equation: READ_VIN = Y×2
Range: N/A
Reference: N/A
COMMAND
FORMAT
READ_VIN (88h)
LINEAR, TWO'S COMPLEMENT BINARY
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
Signed Mantissa, Y
READ_VOUT (8Bh)
Definition: Returns the output voltage reading.
Data Length in Bytes: 2
Data Format: L16u
Type: Read-only
Default Value: N/A
Units: Volts
-13
= READ_VOUT×2
Equation: Read V
Reference: N/A
OUT
COMMAND
Format
READ_VOUT (8Bh)
Linear, unsigned binary
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
2
1
r
0
r
r
r
READ_IOUT (8Ch)
Definition: Returns the output current reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Default Value: N/A
Units: A
N
Equation: READ_IOUT = Y×2
Range: N/A
Reference: N/A
COMMAND
Format
READ_IOUT (8Ch)
Linear, two’s complement binary
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
Signed Mantissa, Y
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ZL2102
READ_TEMPERATURE_1 (8Dh)
Definition: Returns the temperature reading internal to the device.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Default Value: N/A
Units: °C
N
Equation: READ_TEMPERATURE_1 = Y×2
Range: N/A
Reference: N/A
COMMAND
Format
READ_TEMPERATURE_1 (8Dh)
Linear, two’s complement binary
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
Signed Mantissa, Y
READ_DUTY_CYCLE (94h)
Definition: Reports the actual duty cycle of the converter during the enable state.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: N/A
Units: %
N
Equation: READ_DUTY_CYCLE = Y×2
Range: N/A
Reference: N/A
COMMAND
Format
READ_DUTY_CYCLE (94h)
Linear, two’s complement binary
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
Signed Mantissa, Y
READ_FREQUENCY (95h)
Definition: Reports the actual switching frequency of the converter during the enable state.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: N/A
Units: kHz
N
Equation: READ_FREQUENCY = Y×2
Range: N/A
Reference: N/A
COMMAND
Format
READ_FREQUENCY (95h)
Linear, two’s complement binary
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
Signed Mantissa, Y
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ZL2102
PMBUS_REVISION (98h)
Definition: The PMBUS_REVISION command returns the revision of the PMBus specification to which the device is compliant.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 01h (Part 1 Revision 1.0, Part 2 Revision 1.1)
Units: N/A
Reference: N/A
COMMAND
Format
PMBUS_REVISION (98h)
Bit Field
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
0
0
0
0
1
BITS 7:4 PART 1 REVISION BITS 3:0 PART 2 REVISION
0000
0001
0010
1.0
1.1
1.2
0000
0001
0010
1.0
1.1
1.2
MFR_ID (99h)
Definition: Sets a user defined identification. The sum total of characters in MFR_ID and USER_DATA_00 plus one byte per command
cannot exceed 128 characters. This limitation includes multiple writes of this command before a STORE command. To clear multiple
writes, perform a RESTORE, write this command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: <null>
Units: N/A
Reference: N/A
IC_DEVICE_ID (ADH)
Definition: Reports device identification information.
Data Length in Bytes: 4
Data Format: CUS
Type: Block Read
Default Value: 49A01200h
Units: N/A
Reference: N/A
COMMAND
Format
IC_DEVICE_ID (ADh)
Block Read
Byte Position
Function
3
2
1
0
MFR Code ID High Byte ID Low Byte Reserved
49h A0h 12h 00h
Default Value
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ZL2102
IC_DEVICE_REV (AEH)
Definition: Reports device revision information.
Data Length in Bytes: 4
Data Format: CUS
Type: Block Read
Default Value:
Units: N/A
Reference: N/A
COMMAND
Format
IC_DEVICE_REV (AEh)
Block Read
Byte Position
Function
3
2
1
0
Firmware
Major
Firmware
Minor
Factory
Config
Reserved
Default Value
00h
00h
00h
00h
USER_DATA_00 (B0h)
Definition: Sets a user defined data. The sum total of characters in MFR_ID and USER_DATA_00 plus one byte per command cannot
exceed 128 characters. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes,
perform a RESTORE, write this command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: <null>
Units: N/A
Reference: N/A
AUTO_COMP_CONFIG (BCh)
Definition: Configures the auto compensation algorithm.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: Pin strap setting (FC)
Units: N/A
Reference: N/A
COMMAND
Format
AUTO_COMP_CONFIG (BCh)
Bit Field
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Pin Strapped Value
Default Value
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ZL2102
BIT
7:4
FIELD NAME
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
0
SETTING
DESCRIPTION
10%
20%
30%
40%
50%
Auto Comp Gain
Auto Comp Gain Percentage
60%
70%
80%
90%
100%
Use PG Delay
Assert after auto comp
Choose when PGOOD pin asserts, whether to use
PG DELAY or wait until after auto comp
completes.
3
Power-Good Assertion
1
2:1
0
Not Used
00
0
Disabled
Enabled
Operational mode for auto comp. If disabled,
PID_TAPS is used for compensation
Auto Comp Mode
1
AUTO_COMP_CONTROL (BDh)
Definition: Writing the AUTO_COMP_CONTROL command will initiate the auto compensation algorithm, provided that it has been
enabled in AUTO_COMP_CONFIG.
Data Length in Bytes: 0 Byte
Type: Write only
Default Value: N/A
Units: N/A
Reference: N/A
MFR_CONFIG (D0h)
Definition: Configures several manufacturer-level features.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W word
Default Value: 4801h
Units: N/A
Range: N/A
Reference: N/A
COMMAND
FORMAT
MFR_CONFIG (D0h)
BIT FIELD
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
BIT
FIELD NAME
VALUE
01001000000000 Not Used
SETTING
DESCRIPTION
15:2 Not Used
Not Used
0
1
0
1
Open Drain
1
0
PGOOD Config
Configuration of PGOOD pin
Configuration of SYNC pin
Push-pull
Open Drain
Push-pull
SYNC Pin Config
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ZL2102
USER_CONFIG (D1h)
Definition: Configures several user-level features.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: Pin strap setting
Units: N/A
COMMAND
Format
USER_CONFIG (D1h)
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
Pin Strap
0
0
0
0
1
BIT
12
FIELD NAME
VALUE
SETTING
DESCRIPTION
0
1
Ramp Down
High-Z
Alternate Ramp
Down
Determines whether output follows TOFF_FALL time during ramp down or goes
high impedance once VOUT_UV threshold is reached
11:9 Not Used
000
0
0 = If sequencing is disabled, this device will ignore faults from other devices. If
sequencing is enabled, the devices will sequence down from the failed device
outward.
1
8
Fault Spreading Mode
1 = Faults received from any device selected by the DDC_GROUP command will
cause this device to shut down immediately
7
6
Not Used
0
0
Auto-configure
Auto-configure using the SYNC pin strap setting and FREQUENCY_SWITCH
parameter
SYNC Utilization
Control
1
SYNC Setting
Input Only
Switch using external clock on the SYNC input pin
0
1
5
SYNC Output Control
Configuration setting of SYNC pin
Output Internal Clock
4:1 Not Used
0000
0
0
Standby mode
Low Power
Monitor
Enter low power mode when output is disabled. Telemetry will not be available.
Monitor for faults when output is disabled.
1
DDC_CONFIG (D3h)
Definition: Configures the DDC bus.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: Broadcast Group: 0; DDC ID: Lowest five bits of the SMBus Address.
Units: N/A
Reference: N/A
COMMAND
Format
DDC_CONFIG (D3h)
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
0
0
Lowest 5 bits of SMBus Address
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ZL2102
BIT
FIELD NAME
VALUE
0000
SETTING
Not Used
DESCRIPTION
15:13 Not Used
Not Used
12:8 Broadcast Group
0 to 31
(00 to 1Fh)
0
Group number used for broadcast events (i.e., Broadcast Enable and
Broadcast Margin). Set this number to the same value for all rails/devices
that should respond to each other’s broadcasted event. This function is
enabled by bits 15 and 14 in the MISC_CONFIG command.
7:6
5
Not Used
00
1
Not Used
Inhibited
Enabled
Not Used
DDC Transmission Inhibited
DDC Transmission Enabled
DDC TX Inhibit
DDC ID
0
4:0
0 to 31
Lowest 5 bits of Sets the rail’s DDC ID for sequencing and fault spreading.
(00 to 1Fh)
the SMBus
address
POWER_GOOD_DELAY (D4h)
Definition: Sets the delay applied between the output exceeding the PG threshold (POWER_GOOD_ON) and asserting the PG pin. The
delay time can range from 1ms up to 30s. When auto comp is enabled and is set to assert the PG pin after completion, this command
will be ignored.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: BA00h (1ms)
Units: ms
N
Equation: POWER_GOOD_DELAY = (Y×2 )
Range: 1ms to 30s
Reference: N/A
COMMAND
Format
POWER-GOOD_DELAY (D4h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
PID_TAPS (D5h)
Definition: This command configures the control loop compensator coefficients. The PID algorithm implements the following Z-domain:
–1
–2
A + Bz + Cz
-------------------------------------------
(EQ. 14)
–1
1 – z
The coefficients A, B, and C are represented using a pseudo-floating point format similar to the VOUT parameters (with the addition of a
sign bit), defined as Equation 15:
S
E
(EQ. 15)
A = –1 2 M
where M is a two-byte unsigned mantissa, S is a sign-bit, and E is a 7-bit two's-complement signed integer. The 9 byte data field is
defined in the following table. S is stored as the MSB of the E byte.
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BYTE
8
PURPOSE
DEFINITION
Tap C-E
Coefficient C exponent + S
7
Tap C-M [15:8]
Tap C-M [7:0]
Tap B-E
Coefficient C mantissa, high-byte
Coefficient C mantissa, low-byte
Coefficient B exponent + S
6
5
4
Tap B-M [15:8]
Tap B-M [7:0]
Tap A-E
Coefficient B mantissa, high-byte
Coefficient B mantissa, low-byte
Coefficient A exponent + S
3
2
1
Tap A-M [15:8]
Tap A-M [7:0]
Coefficient A mantissa, high-byte
Coefficient A mantissa, low-byte
0
NOTE: Data bytes are transmitted on the PMBus in the order of Byte 0 through Byte 8.
Data Length in Bytes: 9
Data Format: CUS
Type: Block R/W
Default Value:
Auto Comp Off, taps stored - (A, B, C) = stored values
Auto Comp Off, no taps stored - (A, B, C) correspond to (G, Q, fn) = (20dB, 2, f /10)
SW
Auto Comp On - (A, B, C) = Auto Comp results
Units: N/A
Reference: AN2035 - Compensation Using CompZL™
SEQUENCE (E0h)
Definition: Identifies the Rail DDC ID of the prequel and sequel rails when performing multi-rail sequencing. The device will enable its
output when its EN or OPERATION enable state, as defined by ON_OFF_CONFIG, is set and the prequel device has issued a Power-Good
event on the DDC bus. The device will disable its output (using the programmed delay values) when the sequel device has issued a
Power-Down event on the DDC bus.
The data field is a two-byte value. The most-significant byte contains the 5-bit Rail DDC ID of the prequel device. The least-significant
byte contains the 5-bit Rail DDC ID of the sequel device. The most significant bit of each byte contains the enable of the prequel or
sequel mode. This command overrides the corresponding sequence configuration set by the CONFIG pin settings.
Data Length in Bytes: 2
Data Format: CUS
Type: R/W
Default Value: Pin strap setting (CFG)
Units: N/A
Reference: N/A
COMMAND
Format
SEQUENCE (E0h)
Custom
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Pin Strapped Value
Default Value
BIT
15
FIELD NAME
Prequel Enable
Reserved
VALUE
SETTING
Disable
Enable
DESCRIPTION
Disable, no prequel preceing this rail
0
1
0
Enable, prequel to this rail is defined by bits 12:8
Reserved
14:13
12:8
Reserved
DDC ID
Prequel Rail DDC ID
0 to 31
Set to the DDC ID of the prequel rail
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BIT
7
FIELD NAME
VALUE
SETTING
Disable
Enable
DESCRIPTION
Disable, no sequel following this rail
Enable, sequel to this rail is defined by bits 4:0
Reserved
0
Sequel Enable
1
0
6:5
4:0
Reserved
Reserved
DDC ID
Sequel Rail DDC ID
0 to 31
Set to the DDC ID of the sequel rail
DDC_GROUP (E2h)
Definition: Sets which rail DDC IDs are monitored for fault spreading information. The data sent is a 4-byte, 32-bit, bit vector where
every bit represents a rail's DDC ID. Setting a bit to 1 will include that rail's DDC ID in the group. All DDC ID's that are selected will be
monitored. If fault spread mode is enabled in USER_CONFIG (Bit 8 set to 1), the rail will respond to any fault spreading events within the
group. The device will immediately shut down if one of its DDC_GROUP members fails. The device/rail will attempt its configured
restart only after all devices/rails within the DDC_GROUP have cleared their faults.
Note: The device/rail's own DDC ID should not be set within the DDC_GROUP command for that device/rail.
All devices in a current share rail must shutdown for the rail to report a shutdown.
If fault spread mode is disabled in USER_CONFIG (Bit 8 cleared to 0), the device will perform a sequenced shutdown as defined by the
SEQUENCE command setting. The rails/devices in a sequencing set only attempt their configured restart after all faults have cleared
within the DDC_GROUP.
Data Length in Bytes: 4
Data Format: BIT
Type: R/W
Default Value: 00000000h
Units: N/A
Reference: N/A
COMMAND
Format
DDC_GROUP (E2h)
Bit Field
Bit
Position
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
DDC ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Default
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DEVICE_ID (E4h)
Definition: Returns the 16-byte (character) device identifier string.
Data Length in Bytes: 16
Data Format: ASC
Type: Block Read
Default Value: <part number/die revision/firmware revision>
Units: N/A
Reference: N/A
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Definition: Configures the I
OUT
overcurrent fault response as defined by the following table. Only two settings are valid: 80h (immediate
shutdown until commanded to restart) and BFh (immediate shutdown, 80ms delay, and then automatic restart once the fault condition
has cleared). The command format is the same as the PMBus standard fault responses except that it sets the overcurrent status bit in
STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: BFh (Disable and retry continuously)
Units: N/A
Reference: N/A
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COMMAND
Format
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Bit Field
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
1
1
1
1
1
1
BIT
7:6
FIELD NAME
VALUE
DESCRIPTION
Response Behavior
During a fault, the device:
• Pulls SALRT low
00-01
10
Not Used
Disable and Retry according to the setting in bits [5:3].
Not Used
11
• Sets the related fault bit in the
status registers.
000
No Retry. The output remains disabled until the device is restarted.
001-110 Not Used
5:3
2:0
Retry Setting
Retry Time
111
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down. The time between retries is set by bits [2:0].
111
The device will wait 80ms between disable and restart. 111 is the only valid entry for this field.
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Definition: Configures the IOUT undercurrent fault response as defined by the following table. Only two settings are valid: 80h
(immediate shutdown until commanded to restart) and BFh (immediate shutdown, 80ms delay, and then automatic restart once the
fault condition has cleared). The command format is the same as the PMBus standard fault responses except that it sets the
undercurrent status bit in STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: BFh (Disable and retry continuously)
Units: N/A
Reference: N/A
COMMAND
Format
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Bit Field
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
1
1
1
1
1
1
BIT
7:6
FIELD NAME
VALUE
DESCRIPTION
Response Behavior
During a fault, the device:
• Pulls SALRT low
00-01
10
Not Used
Disable and Retry according to the setting in bits [5:3].
Not Used
11
• Sets the related fault bit in the
status registers.
000
No Retry. The output remains disabled until the device is restarted.
001-110 Not Used
5:3
2:0
Retry Setting
Retry Time
111
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down. The time between retries is set by bits [2:0].
111
The device will wait 80ms between disable and restart. 111 is the only valid entry for this field.
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IOUT_AVG_OC_FAULT_LIMIT (E7h)
Definition: Sets the IOUT average overcurrent fault threshold. For down-slope sensing, this corresponds to the average of all the current
samples taken during the (1-D) time interval, excluding the Current Sense Blanking time (which occurs at the beginning of the 1-D
interval). For up-slope sensing, this corresponds to the average of all the current samples taken during the D time interval, excluding the
Current Sense Blanking time (which occurs at the beginning of the D interval). This feature shares the OC fault bit operation (in
STATUS_IOUT) and OC fault response with IOUT_ OC_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: CB99h (7.2A)
Units: Amperes
N
Equation: IOUT_AVG_OC_FAULT_LIMIT = Y×2
Range: 0A to 9A
Reference: N/A
COMMAND
Format
IOUT_AVG_OC_FAULT_LIMIT (E7h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
0
1
0
1
1
1
0
0
1
1
0
0
1
IOUT_AVG_UC_FAULT_LIMIT (E8h)
Definition: Sets the IOUT average undercurrent fault threshold. For down-slope sensing, this corresponds to the average of all the
current samples taken during the (1-D) time interval, excluding the Current Sense Blanking time (which occurs at the beginning of the
1-D interval). For up-slope sensing, this corresponds to the average of all the current samples taken during the D time interval,
excluding the Current Sense Blanking time (which occurs at the beginning of the D interval). This feature shares the UC fault bit
operation (in STATUS_IOUT) and UC fault response with IOUT_ UC_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: CC67h (-7.2A)
Units: Amperes
N
Equation: IOUT_AVG_UC_FAULT_LIMIT = Y×2
Range: 0A to -9A
Reference: N/A
COMMAND
Format
IOUT_AVG_UC_FAULT_LIMIT (E8h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
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ZL2102
MISC_CONFIG (E9h)
Definition: Sets options pertaining to advanced features.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: 00h
Units: N/A
Reference: N/A
COMMAND
Format
MISC_CONFIG (E9h
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BITS
15
PURPOSE
VALUE
DESCRIPTION
Disabled
Enabled
0
Broadcast Margin
1
0
Disabled
Enabled
14
Broadcast Enable
Not Used
1
13:2
00...00
Not Used
Disabled
Enabled
0
1
0
1
Snapshot
0
Not Used
Not Used
SNAPSHOT (EAh)
Definition: The SNAPSHOT command is a 32-byte read-back of parametric and status values. It allows monitoring and status data to be
stored to NV memory either during a fault condition or via a system-defined time using the SNAPSHOT_CONTROL command.
1. To use the snapshot feature, it must first be enabled by setting bit 1 (Snapshot) in MISC_CONFIG to 1 (Enabled).
2. By default, snapshot is continuously updated in RAM and can be read using the SNAPSHOT command.
3. When a fault occurs, the latest snapshot in RAM is stored to NV memory. After this, one can read back the snapshot stored in NV
memory by writing a 01h to the SNAPSHOT_CONTROL command, then reading SNAPSHOT. This step must be performed while the
device's operation is disabled, or when snapshot is temporarily disabled (via MISC_CONFIG).
Data Length in Bytes: 32
Data Format: CUS
Type: Block Read
Default Value: N/A
Units: N/A
BYTE NUMBER
VALUE
PMBUS COMMAND
FORMAT
31:22
21
Not Used
Manufacturer Specific Status Byte
CML Status Byte
STATUS_MFR_SPECIFIC (80h)
BIT
BIT
BIT
BIT
BIT
BIT
L11
20
STATUS_CML (7Eh)
19
Temperature Status Byte
Input Status Byte
STATUS_TEMPERATURE (7Dh)
STATUS_INPUT (7Ch)
STATUS_IOUT (7Bh)
18
17
Iout Status Byte
16
Vout Status Byte
STATUS_VOUT (7Ah)
15:14
13:12
Switching Frequency
Not Used
READ_FREQUENCY (95h)
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BYTE NUMBER
VALUE
PMBUS COMMAND
READ_TEMPERATURE_1 (8Dh)
FORMAT
L11
11:10
9:8
Internal Temperature
Duty Cycle
Peak Current
Load Current
Vout
READ_DUTY_CYCLE (94h)
N/A
L11
7:6
L11
5:4
READ_IOUT (8Ch)
READ_VOUT (8Bh)
READ_VIN (88h)
L11
3:2
L16u
L11
1:0
Vin
BLANK_PARAMS (EBh)
Definition: Returns a 16-byte string that indicates which parameter values were either retrieved by the last RESTORE operation or have
been written since that time. Reading BLANK_PARAMS immediately after a restore operation allows the user to determine which
parameters are stored in that store. A one indicates the parameter is not present in the store and has not been written since the
RESTORE operation. This command is used internally to determine if pin strap values should be used. Contact the factory for the
BLANK_PARAMS bit-map if needed.
Data Length in Bytes: 16
Data Format: BIT
Type: Block Read
Default Value: FF…FFh
Units: N/A
Reference: N/A
SNAPSHOT_CONTROL (F3h)
Definition: Writing a 1h will cause the device to copy the current SNAPSHOT values from NV memory to the 32-byte SNAPSHOT
command parameter. Writing a 2h will cause the device to write the current SNAPSHOT values to NV memory. All other values will be
ignored. Output must be disabled when writing to NV memory.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 00h
Units: N/A
COMMAND
Format
SNAPSHOT_CONTROL (F3h)
Bit Field
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
VALUE
01h
DESCRIPTION
Copy SNAPSHOT values to SNAPSHOT command
Copy SNAPSHOT values to NV memory
02h
RESTORE_FACTORY (F4h)
Definition: Restores the device to the hard-coded Default values and pin strap definitions. The device retains the USER store for
restoring. Output must be disabled when writing this command.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
Reference: N/A
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ZL2102
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN8440.2
CHANGE
November 20, 2014
Page 7 - Added note “Compliance to datasheet limits is assured by one or more methods: production test,
characterization and/or design.” Reference to this note added to MIN/MAX column headings.
Page 13, replaced Table 7.
Page 19, PMBus Command Summary table, changed VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW data
format from L11 to L16u.
Page 26, changed VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW data format from L11 to L16u. Also updated
both tables.
Page 40, bit table, bit 9 meaning, changed from "A bit in STATUS_OTHER is set." to "A bit in STATUS_VOUT,
STATUS_IOUT,STATUS_MFR_SPECIFIC, or STATUS_VIN is set."
POD correction - changed L36.6x6C to L36.6x6A
Initial Release
August 22, 2013
FN8440.1
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ZL2102
Package Outline Drawing
L36.6x6A
36 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 9/09
4X
4.0
0.50
36X
6.00
A
6
B
PIN #1
INDEX AREA
28
36
6
27
PIN 1
INDEX AREA
1
4 .10 ± 0.10
9
19
(4X)
0.15
18
10
TOP VIEW
36X 0.60 ± 0.10
BOTTOM VIEW
4
36X 0.25
0.10 M C A B
C
C
0.10
MAX 0.90
0.08 C
( 5. 60 TYP )
( 36 X 0 . 50 )
SIDE VIEW
(
4. 10 )
5
C
0 . 2 REF
(36X 0.25 )
0 . 00 MIN.
0 . 05 MAX.
( 36X 0.80 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
Compliant to JEDEC MO-220VJJD.
7.
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