X9C102PI [INTERSIL]
Digitally Controlled Potentiometer; 数字控制电位器
| 型号： | X9C102PI |
| 厂家： | 
Intersil |
| 描述： | Digitally Controlled Potentiometer |
| 文件： | 总11页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9C102, X9C103, X9C104, X9C503
®
Data Sheet
December 20, 2006
FN8222.1
DESCRIPTION
Digitally Controlled Potentiometer
(XDCP™)
The X9Cxxx are Intersil digitally controlled (XDCP)
potentiometers. The device consists of a resistor
array, wiper switches, a control section, and nonvola-
tile memory. The wiper position is controlled by a
three-wire interface.
FEATURES
• Solid-state potentiometer
• 3-wire serial interface
• 100 wiper tap points
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switch-
ing network. Between each element and at either end
are tap points accessible to the wiper terminal. The
position of the wiper element is controlled by the CS,
U/D, and INC inputs. The position of the wiper can be
stored in nonvolatile memory and then be recalled
upon a subsequent power-up operation.
—Wiper position stored in nonvolatile memory
and recalled on power-up
• 99 resistive elements
—Temperature compensated
—End to end resistance, ±20%
—Terminal voltages, ±5V
• Low power CMOS
—VCC = 5V
—Active current, 3mA max.
—Standby current, 750µA max.
• High reliability
The device can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including:
—Endurance, 100,000 data changes per bit
—Register data retention, 100 years
• X9C102 = 1kΩ
• X9C103 = 10kΩ
• X9C503 = 50kΩ
– control
– parameter adjustments
– signal processing
• X9C104 = 100kΩ
• Packages
—8 Ld SOIC and 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
U/D
INC
CS
7-Bit
RH/VH
99
98
97
96
Up/Down
Counter
VCC (Supply Voltage)
Up/Down
(U/D)
7-Bit
Nonvolatile
Memory
VH/RH
One
of
Control
and
Increment
(INC)
RW/VW
One-
Hundred
Decoder
Resistor
Array
Transfer
Gates
Memory
Device
(CS)
Select
VL/RL
2
1
0
Store and
Recall
Control
Circuitry
VSS (Ground)
VCC
GND
General
RL/VL
RW/VW
Detailed
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
X9C102, X9C103, X9C104, X9C503
PIN CONFIGURATION
DIP/SOIC
INC
U/D
1
2
3
4
8
7
6
5
VCC
CS
X9C102/103/104/503
VH/RH
VL/RL
VW/RW
VSS
ORDERING INFORMATION
RTOTAL
(kΩ)
TEMPERATURE RANGE
(°C)
PART NUMBER
X9C102P
PART MARKING
PACKAGE
8 Ld PDIP
PKG. DWG. #
MDP0031
X9C102P
1
0 to 70
0 to 70
X9C102PZ (Note)
X9C102PI
X9C102P Z
X9C102P I
X9C102P ZI
X9C102S
8 Ld PDIP (Pb-free)
8 Ld PDIP
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
-40 to 85
-40 to 85
0 to 70
X9C102PIZ (Note)
X9C102S*, **
8 Ld PDIP (Pb-free)
8 Ld SOIC
X9C102SZ* (Note)
X9C102SI*, **
X9C102SIZ*, ** (Note)
X9C102S Z
X9C102S I
X9C102S ZI
X9C103P
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to 85
-40 to 85
0 to 70
8 Ld SOIC (Pb-free)
8 Ld PDIP
X9C103P
10
X9C103PZ (Note)
X9C103PI
X9C103P Z
X9C103P I
X9C103P ZI
X9C103S
0 to 70
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to 85
-40 to 85
0 to 70
X9C103PIZ (Note)
X9C103S*, **
X9C103SZ*, ** (Note)
X9C103SI*, **
8 Ld PDIP (Pb-free)
8 Ld SOIC
X9C103S Z
X9C103S I
X9C103S ZI
X9C503P
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X9C103SIZ*, ** (Note)
8 Ld SOIC (Pb-free)
8 Ld PDIP
X9C503P
50
X9C503PZ (Note)
X9C503PI
X9C503P Z
X9C503P I
X9C503P ZI
X9C503S
0 to 70
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to 85
-40 to 85
0 to 70
X9C503PIZ (Note)
X9C503S*
8 Ld PDIP (Pb-free)
8 Ld SOIC
X9C503SZ* (Note)
X9C503SI*, **
X9C503SIZ*, ** (Note)
X9C503S Z
X9C503S I
X9C503S ZI
X9C104P
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to 85
-40 to 85
0 to 70
8 Ld SOIC (Pb-free)
8 Ld PDIP
X9C104P
100
X9C104PI
X9C104P I
X9C104P ZI
X9C104S
-40 to 85
-40 to 85
0 to 70
8 Ld PDIP
X9C104PIZ (Note)
X9C104S*, **
X9C104SZ*, ** (Note)
X9C104SI*, **
8 Ld PDIP (Pb-free)
8 Ld SOIC
X9C104S Z
X9C104S I
X9C104S ZI
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to 85
-40 to 85
X9C104SIZ*, ** (Note)
8 Ld SOIC (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "T1" suffix for tape and reel.
**Add "T2" suffix for tape and reel.
FN8222.1
December 20, 2006
2
X9C102, X9C103, X9C104, X9C503
PIN DESCRIPTIONS
Pin
Symbol
Brief Description
1
INC
Increment . The INC input is negative-edge triggered. Toggling INC will move the wiper and either
increment or decrement the counter in the direction indicated by the logic level on the U/D input.
2
3
U/D
Up/Down. The U/D input controls the direction of the wiper movement and whether the counter
is incremented or decremented.
RH/VH
RH/VH. The high (VH/RH) terminals of the X9C102/103/104/503 are equivalent to the fixed
terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V.
The terminology of VH/RH and VL/R references the relative position of the terminal in
relation to wiper movement directioLn selected by the U/D input and not the voltage potential on
the terminal.
4
5
VSS
VSS
VW/RW
VW/RW. VW/RW is the wiper terminal, and is equivalent to the movable terminal of a mechanical
potentiometer. The position of the wiper within the array is determined by the control inputs. The
wiper terminal series resistance is typically 40Ω.
6
R /V
L
R /V . The low (V /R ) terminals of the X9C102/103/104/503 are equivalent to the fixed
L
L
L
L
terminals of a mecLhanical potentiometer. The minimum voltage is -5V and the maximum is +5V.
The terminology of VH/RH and VL/R references the relative position of the terminal in
relation to wiper movement directioLn selected by the U/D input and not the voltage potential on
the terminal.
7
8
CS
CS. The device is selected when the CS input is LOW. The current counter value is stored in
nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store op-
eration is complete the X9C102/103/104/503 device will be placed in the low power standby mode
until the device is selected once again.
VCC
VCC
FN8222.1
December 20, 2006
3
X9C102, X9C103, X9C104, X9C503
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Voltage on CS, INC, U/D and V
CC
with respect to VSS .................................. -1V to +7V
Voltage on VH/RH and VL/RL
referenced to V ................................... -8V to +8V
SS
ΔV = |VH/RH - VL/RL|
X9C102 ...............................................................4V
X9C103, X9C503, and X9C104 .........................10V
Lead temperature (soldering, 10 seconds)...... +300°C
I
(10 seconds).................................................8.8mA
W
Power rating X9C102 ........................................16mW
Power rating X9C103/104/503 ..........................10mW
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage (V
)
Limits
CC
X9C102/103/104/503
5V ±10%
-40°C
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
RTOTAL
VVH/RH
VVL/RL
IW
Parameter
End to end resistance variation
VH terminal voltage
Min.
-20
-5
Typ.
Max.
+20
+5
Unit
%
Test Conditions/Notes
V
VL terminal voltage
-5
+5
V
Wiper current
-4.4
4.4
mA
Ω
RW
Wiper resistance
Noise (5)
40
-120
1
100
Wiper Current = ±1mA
Ref. 1kHz
dBV
Resolution
%
Absolute linearity(1)
Relative linearity(2)
-1
+1
MI(3)
MI(3)
VW(n)(actual) - VW(n)(expected)
-0.2
+0.2
VW(n + 1)(actual) - [VW(n) + MI]
RTOTAL temperature coefficient
RTOTAL temperature coefficient
Ratiometric temperature coefficient
±300(5)
±600(5)
±20
ppm/°C X9C103/503/104
ppm/°C X9C102
ppm/°C
CH/CL/CW Potentiometer capacitances
10/10/25
pF
See Circuit #3, Macro Model
(5)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [VW(n)(actual) - VW(n)(expected )] = ±1 MI Maximum.
(2) Relative linearity is a measure of the error in step size between taps = VW(n + 1) - [VW(n) + MI] = +0.2 MI.
(3) 1 MI = Minimum Increment = RTOT/99
(4) Typical values are for T = +25°C and nominal supply voltage.
A
(5) This parameter is not 100% tested.
FN8222.1
December 20, 2006
4
X9C102, X9C103, X9C104, X9C503
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
(4)
Symbol
Parameter
Min. Typ.
Max.
Unit
Test Conditions
ICC
VCC active current
1
3
mA
CS = V , U/D = VIL or VIH and
IL
INC = 0.4V to 2.4V @ max. tCYC
ISB
ILI
Standby supply current
200
750
±10
µA
µA
V
CS = VCC - 0.3V, U/D and INC = VSS
or VCC - 0.3V
CS, INC, U/D input leakage
current
VIN = VSS to VCC
VIH
VIL
CS, INC, U/D input HIGH
voltage
2
CS, INC, U/D input LOW
voltage
0.8
V
(5)
CIN
CS, INC, U/D input
capacitance
10
pF
VCC = 5V, VIN = VSS, TA = 25°C, f = 1MHz
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Unit
Data changes per bit per register
years
100,000
100
Test Circuit #1
Test Circuit #2
Test Circuit #3
Macro Model
RTOTAL
VH/RH
V
/R
H
R
Test Point
RH
RL
CL
10pF
CH
10pF
VS
Test Point
VW/RW
VW/RW
CW
Force
Current
25pF
VL/RL
VL/RL
RW
A.C. CONDITIONS OF TEST
Input pulse levels
0V to 3V
10ns
Input rise and fall times
Input reference levels
1.5V
FN8222.1
December 20, 2006
5
X9C102, X9C103, X9C104, X9C503
A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified)
Limits
(6)
Symbol
tCl
Parameter
CS to INC setup
Min.
100
100
2.9
1
Typ.
Max.
Unit
ns
tlD
INC HIGH to U/D change
U/D to INC setup
ns
tDI
µs
tlL
INC LOW period
µs
tlH
INC HIGH period
1
µs
tlC
INC inactive to CS inactive
CS deselect time (STORE)
CS deselect time (NO STORE)
INC to VW/RW change
INC cycle time
1
µs
tCPH
tCPH
20
ms
ns
100
(5)
tIW
100
500
µs
tCYC
2
µs
(5)
tR
t
INC input rise and fall time
Power-up to wiper stable
VCC power-up rate
500
50
µs
,
F
(5)
tPU
µs
(5)
tR VCC
0.2
V/ms
POWER-UP AND DOWN REQUIREMENTS
At all times, voltages on the potentiometer pins must be less than ±V . The recall of the wiper position from nonvola-
CC
tile memory is not in effect until the V supply reaches its final value. The V ramp rate spec is always in effect.
CC
CC
A.C. TIMING
CS
tCYC
tCI
tIL
tIH
tIC
tCPH
90%
90%
INC
10%
tID
tDI
tF
tR
U/D
VW
tIW
(8)
MI
Notes: (6) Typical values are for T = 25°C and nominal supply voltage.
A
(7) This parameter is periodically sampled and not 100% tested.
(8) MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position.
FN8222.1
December 20, 2006
6
X9C102, X9C103, X9C104, X9C503
DETAILED PIN DESCRIPTIONS
R /V and R /V
PIN NAMES
Symbol
Description
High Terminal
L
H
H
L
VH /RH
The high (VH/RH) and low (VL/RL) terminals of the
X9C102/103/104/503 are equivalent to the fixed termi-
nals of a mechanical potentiometer. The minimum
voltage is -5V and the maximum is +5V. The terminol-
ogy of VH/RH and VL/RL references the relative position
of the terminal in relation to wiper movement direction
selected by the U/D input and not the voltage potential
on the terminal.
VW/RW
VL/RL
VSS
Wiper Terminal
Low Terminal
Ground
VCC
U/D
Supply Voltage
Up/Down Control Input
Increment Control Input
Chip Select Control Input
No Connection
INC
CS
RW/V
W
NC
VW/RW is the wiper terminal, and is equivalent to the
movable terminal of a mechanical potentiometer. The
position of the wiper within the array is determined by
the control inputs. The wiper terminal series resistance is
typically 40Ω.
PRINCIPLES OF OPERATION
There are three sections of the X9Cxxx: the input con-
trol, counter and decode section; the nonvolatile mem-
ory; and the resistor array. The input control section
operates just like an up/down counter. The output of
this counter is decoded to turn on a single electronic
switch connecting a point on the resistor array to the
wiper output. Under the proper conditions the contents
of the counter can be stored in nonvolatile memory
and retained for future use. The resistor array is com-
prised of 99 individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that
point to the wiper.
Up/Down (U/D)
The U/D input controls the direction of the wiper move-
ment and whether the counter is incremented or dec-
remented.
Increment (INC)
The INC input is negative-edge triggered. Toggling
INC will move the wiper and either increment or decre-
ment the counter in the direction indicated by the logic
level on the U/D input.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the
last position. That is, the counter does not wrap
around when clocked to either extreme.
Chip Select (CS)
The device is selected when the CS input is LOW.
The current counter value is stored in nonvolatile
memory when CS is returned HIGH while the INC
input is also HIGH. After the store operation is com-
plete the X9C102/103/104/503 device will be placed
in the low power standby mode until the device is
selected once again.
The electronic switches on the device operate in a
“make before break” mode when the wiper changes
tap positions. If the wiper is moved several positions,
multiple taps are connected to the wiper for t (INC to
IW
V /R change). The R value for the device can
W
W
TOTAL
temporarily be reduced by a significant amount if the
wiper is moved several positions.
PIN CONFIGURATION
DIP/SOIC
When the device is powered-down, the last wiper posi-
tion stored will be maintained in the nonvolatile mem-
ory. When power is restored, the contents of the
memory are recalled and the wiper is set to the value
last stored.
INC
U/D
1
2
3
4
8
7
6
5
VCC
CS
X9C102/103/104/503
VH/RH
VL/RL
VW/RW
VSS
FN8222.1
December 20, 2006
7
X9C102, X9C103, X9C104, X9C503
INSTRUCTIONS AND PROGRAMMING
MODE SELECTION
The INC, U/D and CS inputs control the movement of
the wiper along the resistor array. With CS set LOW
the device is selected and enabled to respond to the
U/D and INC inputs. HIGH to LOW transitions on INC
will increment or decrement (depending on the state of
the U/D input) a seven-bit counter. The output of this
counter is decoded to select one of one-hundred wiper
positions along the resistive array.
CS
L
INC U/D
Mode
H
L
Wiper Up
L
Wiper Down
H
X
L
L
L
X
X
X
H
L
Store Wiper Position
H
Standby Current
No Store, Return to Standby
Wiper Up (not recommended)
Wiper Down (not recommended)
The value of the counter is stored in nonvolatile mem-
ory whenever CS transitions HIGH while the INC input
is also HIGH.
SYMBOL TABLE
The system may select the X9Cxxx, move the wiper,
and deselect the device without having to store the lat-
est wiper position in nonvolatile memory. After the
wiper movement is performed as described above and
once the new position is reached, the system must
keep INC LOW while taking CS HIGH. The new wiper
position will be maintained until changed by the sys-
tem or until a power-down/up cycle recalled the previ-
ously stored data.
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
This procedure allows the system to always power-up
to a preset value stored in nonvolatile memory; then
during system operation minor adjustments could be
made. The adjustments might be based on user pref-
erence: system parameter changes due to tempera-
ture drift, etc...
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
The state of U/D may be changed while CS remains
LOW. This allows the host system to enable the
device and then move the wiper up and down until the
proper trim is attained.
FN8222.1
December 20, 2006
8
X9C102, X9C103, X9C104, X9C503
PERFORMANCE CHARACTERISTICS
Contact the factory for more information.
APPLICATIONS INFORMATION
Electronic digitally controlled (XCDP) potentiometers provide three powerful application advantages; (1) the variability
and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity
of nonvolatile memory used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
VR
VR
VH/RH
VW/RW
VL/RL
I
Three terminal potentiometer;
Two terminal variable resistor;
variable voltage divider
variable current
Basic Circuits
Noninverting Amplifier
Buffered Reference Voltage
Cascading Techniques
+5V
R1
+V
+V
+V
LM308A
VS
+
–
+V
VO
+5V
OP-07
VW
+
–
-5V
VREF
X
VOUT
VW/RW
R2
-5V
OUT = VW/RW
R1
VW/RW
V
(a)
(b)
VO = (1+R2/R1)VS
Voltage Regulator
Offset Voltage Adjustment
Comparator with Hysteresis
LT311A
R1
R2
VS
–
+
VS
VO
VIN
VO (REG)
317
100kΩ
R1
–
+
VO
Iadj
TL072
R1
R2
R2
10kΩ
10kΩ
+12V
V
V
UL = {R1/(R1 + R2)} VO(max)
LL = {R1/(R1 + R2)} VO(min)
10kΩ
-12V
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
(for additional circuits see AN115)
FN8222.1
December 20, 2006
9
X9C102, X9C103, X9C104, X9C503
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8222.1
December 20, 2006
10
X9C102, X9C103, X9C104, X9C503
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8222.1
December 20, 2006
11
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