X98017_06 [INTERSIL]
170MHz Triple Video Digitizer with Digital PLL; 170MHz的三路视频数字化仪，数字锁相环
| 型号： | X98017_06 |
| 厂家： | 
Intersil |
| 描述： | 170MHz Triple Video Digitizer with Digital PLL |
| 文件： | 总29页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X98017
®
ta Sheet
March 8, 2006
FN8218.3
170MHz Triple Video Digitizer with
Digital PLL
Features
• 170MSPS maximum conversion rate
The X98017 3-channel, 8-bit Analog Front End (AFE)
contains all the components necessary to digitize analog
RGB or YUV graphics signals from personal computers,
workstations and video set-top boxes. The fully differential
analog design provides high PSRR and dynamic
performance to meet the stringent requirements of the
graphics display industry. The AFE’s 170MSPS conversion
rate supports resolutions up to UXGA at 60Hz refresh rate,
while the front end's high input bandwidth ensures sharp
images at the highest resolutions.
• Low PLL clock jitter (250ps p-p @ 170MSPS)
• 64 interpixel sampling positions
• 0.35V
to 1.4V
video input range
p-p
p-p
• Programmable bandwidth (100MHz to 780MHz)
• 2 channel input multiplexer
• RGB and YUV 4:2:2 output formats
• 5 embedded voltage regulators allow operation from
single 3.3V supply and enhance performance, isolation
To minimize noise, the X98017's analog section features 2
sets of pseudo-differential RGB inputs with programmable
input bandwidth, as well as internal DC restore clamping
(including mid-scale clamping for YUV signals). This is
followed by the programmable gain/offset stage and the
three 170MSPS Analog-to-Digital Converters (ADCs).
Automatic Black Level Compensation (ABLC™) eliminates
part-to-part offset variation, ensuring perfect black level
performance in every application.
• Completely independent 8 bit gain/10 bit offset control
• CSYNC and SOG support
• Trilevel sync detection
• 1.05W typical P @ 170MSPS
D
• Pb-free plus anneal available (RoHS compliant)
Applications
• LCD Monitors and Projectors
The X98017's digital PLL generates a pixel clock from the
analog source's HSYNC or SOG (Sync-On-Green) signals.
Pixel clock output frequencies range from 10MHz to 170MHz
with sampling clock jitter of 250ps peak to peak.
• Digital TVs
• Plasma Display Panels
• RGB Graphics Processing
• Scan Converters
Simplified Block Diagram
Offset
DAC
ABLC™
Voltage
Clamp
3
8 or 16
x3
RGB/YPbPr
RGB/YPbPr
1
2
IN
RGB/YUV
+
PGA
8 bit ADC
OUT
3
IN
HSYNC
VSYNC
OUT
OUT
SOG 1/2
IN
HS
OUT
PIXELCLK
Sync
Processing
HSYNC 1/2
IN
Digital PLL
OUT
VSYNC 1/2
IN
AFE Configuration and Control
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X98017
Ordering Information
MAXIMUM PIXEL
TEMP RANGE
(°C)
PART NUMBER
X98017L128-3.3
PART MARKING
X98017L-3.3
X98017L-3.3Z
RATE
PACKAGE
128 MQFP
128 MQFP (Pb-free)
170MHz
170MHz
0 to 70
0 to 70
X98017L128-3.3-Z (See Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
VCLAMP
Offset
DAC
10
ABLC™
RIN
1
2
VIN
+
-
8
8
RP[7:0]
RS[7:0]
8
8
8
8 bit ADC
PGA
PGA
PGA
+
+
+
VIN
RIN
VCLAMP
Offset
DAC
10
ABLC™
GIN1
VIN
+
-
8
8
RGBGND1
GP[7:0]
GS[7:0]
8 bit ADC
VIN
GIN2
RGBGND
2
VCLAMP
Offset
DAC
10
ABLC™
BIN
1
2
VIN
+
-
8
8
BP[7:0]
BS[7:0]
8 bit ADC
VIN
BIN
DATACLK
DATACLK
SOGIN
1
SOGIN
2
HSYNCIN
1
Sync
AFE Configuration
and Control
HSOUT
VSOUT
HSYNCIN
2
1
Processing
VSYNCIN
VSYNCIN2
HSYNCOUT
VSYNCOUT
CLOCKINV
Digital PLL
XTALIN
XTALOUT
XTALCLKOUT
SCL
SDA
Serial
Interface
SADDR
FN8218.3
2
March 8, 2006
X98017
Absolute Maximum Ratings
Recommended Operating Conditions
Voltage on V , V , or V
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
A
D
X
(referenced to GND =GND =GND ) . . . . . . . . . . . . . . . . . . . 4.0V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . V = V = V = 3.3V
A
D
X
A
D
X
Voltage on any analog input pin
(referenced to GND ) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
A
A
Voltage on any digital input pin
(referenced to GND ) . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
D
Current into any output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20mA
Operating Temperature range . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
T
Electrical Specifications Specifications apply for V = V = V = 3.3V, pixel rate = 170MHz, f
= 25MHz, T = 25°C,
A
A
D
X
XTAL
unless otherwise noted
PARAMETER
SYMBOL
COMMENT
MIN
TYP
MAX
UNIT
FULL CHANNEL CHARACTERISTICS
ADC Resolution
8
Bits
Missing Codes
Guaranteed monotonic
Per Channel
None
170
Conversion Rate
10
MHz
LSB
DNL
INL
Differential Non-Linearity
±0.5
+1.0
-0.9
Integral Non-Linearity
±1.1
±6
±3.25
LSB
dB
Gain Adjustment Range
Gain Adjustment Resolution
Gain Matching Between Channels
8
Bits
%
Percent of full scale
±1
Full Channel Offset Error, ABLC™ enabled ADC LSBs, over time and temperature
±0.125
±127
±0.5
LSB
LSB
Offset Adjustment Range, ABLC™
enabled or disabled
ADC LSBs (see ABLC™ applications
information section)
Overvoltage Recovery Time
For 150% overrange, maximum bandwidth
setting
5
ns
ANALOG VIDEO INPUT CHARACTERISTICS (R 1, G 1, B 1, R 2, G 2, B 2)
IN IN IN IN IN IN
Input Range
0.35
0.7
±0.01
5
1.4
±1
V
P-P
Input Bias Current
Input Capacitance
Full Power Bandwidth
DC restore clamp off
Programmable
µA
pF
780
MHz
INPUT CHARACTERISTICS (SOG 1, SOG 2)
IN IN
V
/V
IH IL
Input Threshold Voltage
Programmable - See Register Listing for
Details
0 to
-0.3
V
Hysteresis
Centered around threshold voltage
40
5
mV
pF
Input capacitance
INPUT CHARACTERISTICS (HSYNC 1, HSYNC 2)
IN IN
V
/V
IH IL
Input Threshold Voltage
Programmable - See Register Listing for
Details
0.4 to 3.2
V
Hysteresis
Centered around threshold voltage
240
1.2
mV
R
Input impedance
kΩ
IN
FN8218.3
3
March 8, 2006
X98017
Electrical Specifications Specifications apply for V = V = V = 3.3V, pixel rate = 170MHz, f
= 25MHz, T = 25°C,
A
A
D
X
XTAL
unless otherwise noted (Continued)
SYMBOL
PARAMETER
Input capacitance
DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINV , RESET)
COMMENT
MIN
TYP
MAX
UNIT
5
pF
IN
V
Input HIGH Voltage
Input LOW Voltage
Input leakage current
Input capacitance
2.0
V
V
IH
V
0.8
IL
I
RESET has a 70kΩ pullup to V
±10
5
nA
pF
D
SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNC 1, VSYNC 2)
IN IN
V +
Low to High Threshold Voltage
High to Low Threshold Voltage
Input leakage current
1.45
2.4
V
V
T
V -
T
0.95
I
±10
5
nA
pF
Input capacitance
DIGITAL OUTPUT CHARACTERISTICS (DATACLK, DATACLK)
Output HIGH Voltage, I = 16mA
V
V
V
OH
O
V
Output LOW Voltage, I = -16mA
0.4
0.4
OL
O
DIGITAL OUTPUT CHARACTERISTICS (R , G , B , R , G , B , HS
, VS
OUT
, HSYNC
OUT
, VSYNC )
OUT
P
P
P
S
S
S
OUT
V
Output HIGH Voltage, I = 8mA
2.4
V
V
OH
O
V
Output LOW Voltage, I = -8mA
O
OL
R
Pulldown to GND when three-state
R , G , B , R , G , B only
58
kΩ
TRI
D
P
P
P
S
S
S
DIGITAL OUTPUT CHARACTERISTICS (SDA, XTALCLK
)
OUT
V
Output HIGH Voltage, I = 4mA
XTALCLK
only; SDA is open-drain
OUT
2.4
V
V
OH
O
V
Output LOW Voltage, I = -4mA
0.4
OL
O
POWER SUPPLY REQUIREMENTS
V
Analog Supply Voltage
3
3
3
3.3
3.3
3.3
185
135
0.7
1.05
50
3.6
3.6
3.6
195
145
2
V
V
A
V
Digital Supply Voltage
D
X
V
Crystal Oscillator Supply Voltage
Analog Supply Current
V
I
Operating
mA
mA
mA
W
A
I
Digital Supply Current
Operating (grayscale)
D
I
Crystal Oscillator Supply Current
Total Power Dissipation
X
P
Operating (average)
Power-down Mode
1.25
80
D
mW
°C/W
Θ
Thermal Resistance, Junction to Ambient
30
JA
AC TIMING CHARACTERISTICS
PLL Jitter
250
450
ps p-p
Sampling Phase Steps
Sampling Phase Tempco
5.6° per step
64
±1
±3
ps/°C
°
Sampling Phase Differential Nonlinearity
Degrees out of 360°
HSYNC Frequency Range
Crystal Frequency Range
10
23
150
27
kHz
MHz
f
25
XTAL
FN8218.3
4
March 8, 2006
X98017
Electrical Specifications Specifications apply for V = V = V = 3.3V, pixel rate = 170MHz, f
= 25MHz, T = 25°C,
A
A
D
X
XTAL
unless otherwise noted (Continued)
SYMBOL
PARAMETER
COMMENT
MIN
TYP
MAX
UNIT
t
DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
1.3
ns
SETUP
t
DATA valid after rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
2.0
ns
HOLD
AC TIMING CHARACTERISTICS (2 WIRE INTERFACE)
f
SCL Clock Frequency
0
400
kHz
ns
SCL
Maximum width of a glitch on SCL that will 2 XTAL periods min
be suppressed
80
t
SCL LOW to SDA Data Out Valid
5 XTAL periods plus SDA’s RC time
constant
See
comment
µs
µs
AA
t
Time the bus must be free before a new
transmission can start
1.3
BUF
t
Clock LOW Time
1.3
0.6
0.6
0.6
100
0
µs
µs
µs
µs
ns
ns
µs
ns
LOW
t
Clock HIGH Time
HIGH
t
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
t
t
t
Data In Hold Time
t
Stop Condition Setup Time
Data Output Hold Time
0.6
160
t
4 XTAL periods min
DH
NOTES:
1. Setup and hold times are at a 140MHz DATACLK rate.
t
t
t
t
R
F
HIGH
LOW
SCL
SDA IN
t
SU:DAT
t
t
t
SU:STO
SU:ST
HD:DAT
t
HD:STA
t
t
t
BUF
AA
DH
SDA OUT
FIGURE 1. 2 WIRE INTERFACE TIMING
DATACLK
DATACLK
t
HOLD
t
SETUP
Pixel Data
FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING
FN8218.3
5
March 8, 2006
X98017
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
HSYNCIN
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL
Analog
Video In
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
DATACLK
RP/GP/BP[7:0]
RS/GS/BS[7:0]
HSOUT
8.5 DATACLK Pipeline Latency
D0
D1
D2
D3
Programmable
Width and Polarity
FIGURE 3. 24 BIT OUTPUT MODE
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
HSYNCIN
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL
Analog
Video In
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
DATACLK
GP[7:0]
RP[7:0]
BP[7:0]
HSOUT
8.5 DATACLK Pipeline Latency
G0 (Yo) G1 (Y1) G2 (Y2)
B
0 (Uo)
R1 (V1)
B2 (U2)
Programmable
Width and Polarity
FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
FN8218.3
6
March 8, 2006
X98017
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
HSYNC
IN
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +10.5)*tPIXEL
Analog
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
Video In
DATACLK
RP/GP/BP[7:0]
RS/GS/BS[7:0]
HSOUT
D0
D2
D3
D1
Programmable
Width and Polarity
FIGURE 5. 48 BIT OUTPUT MODE
rltltt tlt.
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
HSYNC
IN
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL
Analog
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P0
Video In
DATACLK
RP/GP/BP[7:0]
RS/GS/BS[7:0]
HSOUT
D0
D2
D1
Programmable
Width and Polarity
FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING
FN8218.3
7
March 8, 2006
X98017
Pinout
X98017
(128-PIN MQFP)
TOP VIEW
NC
NC
1
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
R
R
R
V
5
6
7
S
S
2
GND
3
A
S
V
4
BYPAS S
D
GND
V
5
GND
D
A
6
G
G
G
G
G
G
G
G
V
0
1
2
3
4
5
6
7
A
1
P
P
P
P
P
P
P
P
D
R
7
IN
GND
8
A
V
9
BYPAS S
GND
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A
A
1
G
IN
R GB
1
1
GND
S OG
IN
GND
GND
D
A
V
G
G
G
G
G
G
G
G
V
0
1
2
3
4
5
6
7
BYPAS S
S
S
S
S
S
S
S
S
GND
V
A
A
1
B
IN
V
A
GND
A
2
R
IN
GND
A
2
G
IN
COR E
R GB
2
2
GND
GND
D
S OG
V
D
IN
GND
GND
A
2
D
B
B
B
B
B
B
B
B
B
V
0
1
2
3
4
5
6
7
IN
V
P
P
P
P
P
P
P
P
D
A
A
GND
V
COR E ADC
GND
D
1
2
HS YNC
HS YNC
IN
IN
V
A
A
X
X
GND
GND
V
GND
D
VR E G
IN
FN8218.3
8
March 8, 2006
X98017
Pin Descriptions
SYMBOL
PIN
7
DESCRIPTION
R
G
1
Analog input. Red channel 1. DC couple or AC couple through 0.1µF.
Analog input. Green channel 1. DC couple or AC couple through 0.1µF.
Analog input. Blue channel 1. DC couple or AC couple through 0.1µF.
IN
1
12
19
13
IN
B
1
IN
RGB
1
Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND .
GND
A
SOG
1
14
33
Analog input. Sync on Green. Connect to G 1 through a 0.01µF capacitor in series with a 500Ω resistor.
IN
IN
HSYNC
1
1
Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND . Connect to channel 1's HSYNC
IN
A
signal through a 680Ω series resistor.
VSYNC
44
22
24
28
25
Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 1's VSYNC signal.
Analog input. Red channel 2. DC couple or AC couple through 0.1µF.
Analog input. Green channel 2. DC couple or AC couple through 0.1µF.
Analog input. Blue channel 2. DC couple or AC couple through 0.1µF.
IN
R
G
2
IN
2
IN
B
2
IN
RGB
2
Analog input. Ground reference for the R, G, and B inputs of channel 2 in the DC coupled configuration.
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
GND
AC-coupled configuration, but the pin should still be tied to GND .
A
SOG
2
26
34
Analog input. Sync on Green. Connect to G 1 through a 0.01µF capacitor in series with a 500Ω resistor.
IN
IN
HSYNC
2
2
Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND . Connect to channel 2's HSYNC
IN
A
signal through a 680Ω series resistor.
VSYNC
45
41
Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 2's VSYNC signal.
IN
CLOCKINV
Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180 degrees. Toggle at frame
rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to
IN
D
if unused.
GND
RESET
46
39
40
47
48
Digital input, 5V tolerant, active low, 70kΩ pull-up to V . Take low for at least 1µs and then high again to
D
reset the X98017. This pin is not necessary for normal use and may be tied directly to the V supply.
D
XTAL
IN
Analog input. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
centered around 0.5V.
P-P
XTAL
OUT
Analog output. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
centered around 0.5V.
P-P
XTALCLK
3.3V digital output. Buffered crystal clock output at f
system components.
or f
/2. May be used as system clock for other
OUT
XTAL
XTAL
SADDR
Digital input, 5V tolerant. Address = 0x4C (0x98 including R/W bit) when tied low. Address = 0x4D (0x9A
including R/W bit) when tied high.
SCL
SDA
50
49
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
3.3V digital output. Red channel, primary pixel data. 58K pulldown when three-stated.
3.3V digital output. Red channel, secondary pixel data. 58K pulldown when three-stated.
3.3V digital output. Green channel, primary pixel data. 58K pulldown when three-stated.
3.3V digital output. Green channel, secondary pixel data. 58K pulldown when three-stated.
3.3V digital output. Blue channel, primary pixel data. 58K pulldown when three-stated.
3.3V digital output. Blue channel, secondary pixel data. 58K pulldown when three-stated.
R [7:0]
112-119
100-107
90-97
80-87
68-75
55-62
121
P
R [7:0]
S
G [7:0]
P
G [7:0]
S
B [7:0]
P
B [7:0]
S
DATACLK
3.3V digital output. Data clock output. Equal to pixel clock rate in 24 bit mode, one half pixel clock rate in 48
bit mode.
DATACLK
122
3.3V digital output. Inverse of DATACLK.
FN8218.3
9
March 8, 2006
X98017
Pin Descriptions (Continued)
SYMBOL
PIN
DESCRIPTION
HS
125
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals)
OUT
OUT
VS
126
127
3.3V digital output.Artificial VSYNC output aligned with pixel data. VSYNC is generated 8 pixel clocks after
the trailing edge of HS
. This signal is usually not needed - use VSYNC
as VSYNC source.
OUT
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used to measure HSYNC
period. HS should be used to detect the beginning of a line. This output will pass composite sync signals
OUT
HSYNC
OUT
OUT
OUT
and Macrovision signals if present on HSYNC or SOG
.
IN IN
VSYNC
128
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used to detect the beginning of a
frame and measure the VSYNC period.
V
6, 11, 18, 20, Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND with 0.1µF.
A
A
29, 35
GND
3, 5, 8, 10, 15, Ground return for V and V
A
.
BYPASS
A
D
X
17, 21, 23, 27,
30, 36
V
54, 67, 77, 89, Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND with 0.1µF.
D
D
99, 111, 124
GND
32, 43, 51, 53, Ground return for V , V
D
, V
, and V
.
PLL
CORE COREADC
66, 76, 78, 88,
98, 108, 110,
120, 123
V
38
37
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND with 0.1µF.
X
X
GND
Ground return for V .
X
V
4, 9, 16
65
Bypass these pins to GND with 0.1µF. Do not connect these pins to each other or anything else.
A
BYPASS
VREG
3.3V input voltage for V
voltage regulator. Connect to a 3.3V source, and bypass to GND with 0.1µF.
D
IN
CORE
VREG
64
Regulated output voltage for V
COREADC
output can only supply power to V
, V
PLL COREADC
and V
; typically 1.9V. Connect only to V
CORE
,
PLL
OUT
V
and V
CORE
and bypass at input pins as instructed below. Do not connect to anything else - this
, V
PLL COREADC
and V
.
CORE
V
31
42
Internal power for the ADC’s digital logic. Connect to VREG
with 0.1µF.
through a 10Ω resistor and bypass to GND
COREADC
OUT
D
V
Internal power for the PLL’s digital logic. Connect to VREG
with 0.1µF.
through a 10Ω resistor and bypass to GND
PLL
OUT
D
V
52, 79, 109
1, 2, 63
Internal power for core logic. Connect to VREG and bypass each pin to GND with 0.1µF.
OUT D
CORE
NC
Reserved. Do not connect anything to these pins.
FN8218.3
10
March 8, 2006
X98017
Register Listing
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(s)
FUNCTION NAME
DESCRIPTION
0x01
SYNC Status
(read only)
0
HSYNC1 Active
0: HSYNC1 is Inactive
1: HSYNC1 is Active
1
2
3
4
5
6
7
0
1
2
3
4
5
HSYNC2 Active
VSYNC1 Active
VSYNC2 Active
SOG1 Active
SOG2 Active
PLL Locked
0: HSYNC2 is Inactive
1: HSYNC2 is Active
0: VSYNC1 is Inactive
1: VSYNC1 is Active
0: VSYNC2 is Inactive
1: VSYNC2 is Active
0: SOG1 is Inactive
1: SOG1 is Active
0: SOG2 is Inactive
1: SOG2 is Active
0: PLL is unlocked
1: PLL is locked to incoming HSYNC
CSYNC Detected at
Sync Splitter Output
0: Composite Sync signal not detected
1: Composite Sync signal is detected
0x02
SYNC Polarity
(read only)
HSYNC1
Polarity
0: HSYNC1 is Active High
1: HSYNC1 is Active Low
HSYNC2
Polarity
0: HSYNC2 is Active High
1: HSYNC2 is Active Low
VSYNC1
Polarity
0: VSYNC1 is Active High
1: VSYNC1 is Active Low
VSYNC2
Polarity
0: VSYNC2 is Active High
1: VSYNC2 is Active Low
HSYNC1
Trilevel
0: HSYNC1 is Standard Sync
1: HSYNC1 is Trilevel Sync
HSYNC2
Trilevel
0: HSYNC2 is Standard Sync
1: HSYNC2 is Trilevel Sync
7:6
2:0
N/A
Returns 0
0x03
0x04
HSYNC Slicer (0x44)
HSYNC1 Threshold
000 = lowest (0.4V) All values referred to
100 = default (2.0V) voltage at HSYNC input
111 = highest (3.2V) pin, 240mV hysteresis
3
Reserved
Set to 00
6:4
7
HSYNC2 Threshold
Disable Glitch Filter
See HSYNC1
0: HSYNC/VSYNC Digital Glitch Filter Enabled (default)
1: HSYNC/VSYNC Digital Glitch Filter Disabled
SOG Slicer (0x08)
3:0
SOG1 and SOG2
Threshold
0x0 = lowest (0mV)
40mV hysteresis at
0x8 = default (160mV) all settings
0xF = highest (300mV) 20mV step size
4
SOG Filter
Enable
0: SOG low pass filter disabled (default)
1: SOG low pass filter enabled, 14MHz corner
5
SOG Hysteresis
Disable
0: 40mV SOG hysteresis enabled
1: 40mV SOG hysteresis disabled (default)
7:6
Reserved
Set to 00.
FN8218.3
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March 8, 2006
X98017
Register Listing (Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(s)
FUNCTION NAME
DESCRIPTION
0x05
Input configuration (0x00)
0
Channel Select
0: VGA1
1: VGA2
1
Input Coupling
RGB/YUV
0: AC coupled (positive input connected to clamp DAC
during clamp time, negative input disconnected from outside
pad and always internally tied to appropriate clamp DAC)
1: DC coupled (+ and - inputs are brought to pads and never
connected to clamp DACs). Analog clamp signal is turned off
in this mode.
2
0: RGB inputs (Clamp DAC = 300mV for R, G, B, half scale
analog shift for R, G, and B, base ABLC™ target code = 0x00
for R, G, and B)
1: YUV inputs (Clamp DAC = 600mV for R and B, 300mV for
G, half scale analog shift for G channel only, base ABLC™
target code = 0x00 for G, = 0x80 for R and B)
3
4
Sync Type
0: Separate HSYNC/VSYNC
1: Composite (from SOG or CSYNC on HSYNC)
Composite Sync
Source
0: SOG
IN
1: HSYNC
IN
Note: If Sync Type = 0, the multiplexer will pass HSYNC
regardless of the state of this bit.
IN
5
COAST CLAMP
enable
0: DC restore clamping and ABLC™ suspended during
COAST
1: DC restore clamping and ABLC™ continue during COAST
7:6
7:0
Reserved
Red Gain
Set to 00.
0x06
0x07
0x08
Red Gain (0x55)
Green Gain (0x55)
Blue Gain (0x55)
Channel gain, where:
gain (V/V) = 0.5 + [7:0]/170
0x00: gain = 0.5 V/V
(1.4VP-P input = full range of ADC)
7:0
7:0
Green Gain
Blue Gain
0x55: gain = 1.0 V/V
(0.7VP-P input = full range of ADC)
0xFF: gain = 2.0 V/V
(0.35VP-P input = full range of ADC)
0x09
0x0A
0x0B
Red Offset (0x80)
Green Offset (0x80)
Blue Offset (0x80)
7:0
7:0
7:0
Red Offset
Green Offset
Blue Offset
ABLC™ enabled: digital offset control. A 1 LSB change in
this register will shift the ADC output by 1 LSB.
ABLC™ disabled: analog offset control. These bits go to the
upper 8 bits of the 10 bit offset DAC. A 1LSB change in this
register will shift the ADC output approximately 1 LSB (Offset
DAC range = 0) or 0.5LSBs (Offset DAC range = 1).
0x00 = min DAC value or -0x80 digital offset,
0x80 = mid DAC value or 0x00 digital offset,
0xFF = max DAC value or +0x7F digital offset
0x0C
Offset DAC Configuration (0x00)
0
Offset DAC Range
Reserved
0: ±1/2 ADC fullscale (1 DAC LSB ~ 1 ADC LSB)
1: ±1/4 ADC fullscale (1 DAC LSB ~ 1/2 ADC LSB)
1
Set to 0.
3:2
5:4
Red Offset DAC LSBs These bits are the LSBs necessary for 10 bit manual offset
DAC control.
Green Offset DAC
Combine with their respective MSBs in registers 0x09, 0x0A,
LSBs
and 0x0B to achieve 10 bit offset DAC control.
7:6
Blue Offset DAC
LSBs
FN8218.3
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March 8, 2006
X98017
Register Listing (Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(s)
FUNCTION NAME
Unused
DESCRIPTION
0x0D
AFE Bandwidth (0x0E)
0
Value doesn’t matter
3:1
AFE BW
3dB point for AFE lowpass filter
000: 100MHz
111: 780MHz (default)
7:4
Peaking
0000: Disabled (default) See Bandwidth and Peaking
Control section for more information
0x0E
0x0F
PLL Htotal MSB (0x03)
PLL Htotal LSB (0x20)
5:0
7:0
PLL Htotal MSB
PLL Htotal LSB
14 bit HTOTAL (number of active pixels) value
The minimum HTOTAL value supported is 0x200.
HTOTAL to PLL is updated on LSB write only.
0x10
PLL Sampling Phase (0x00)
5:0
PLL Sampling Phase Used to control the phase of the ADC’s sample point relative
to the period of a pixel. Adjust to obtain optimum image
quality. One step = 5.625° (1.56% of pixel period).
0x11
PLL Pre-coast (0x08)
7:0
Pre-coast
Number of lines the PLL will coast prior to the start of
VSYNC. Applies only to internally generated COAST
signals.
0x12
0x13
PLL Post-coast (0x00)
PLL Misc (0x00)
7:0
0
Post-coast
Number of lines the PLL will coast after the end of VSYNC.
Applies only to internally generated COAST signals.
PLL Lock Edge
HSYNC1
0: Lock on trailing edge of HSYNC1 (default)
1: Lock on leading edge of HSYNC1
1
PLL Lock Edge
HSYNC2
0: Lock on trailing edge of HSYNC2 (default)
1: Lock on leading edge of HSYNC2
2
3
Reserved
Set to 0.
CLKINV Pin
IN
0: CLKINV pin enabled (default)
IN
Disable
1: CLKINV pin disabled (internally forced low)
IN
5:4
CLKINV Pin
IN
00: CLKINV (default)
Function
01: External CLAMP (see Note)
10: External COAST
11: External PIXCLK
Note: the CLAMP pulse is used to
- perform a DC restore (if enabled)
- start the ABLC™ function (if enabled), and
- update the data to the Offset DACs (always).
When in the default internal CLAMP mode, the X98017
automatically generates the CLAMP pulse. If External
CLAMP is selected, the Offset DAC values will only change
on the leading edge of CLAMP. If there is no internal clamp
signal, there will be up to a 100ms delay between when the
PGA gain or offset DAC register is written to, and when the
PGA or offset DAC is actually updated.
6
XTALCLKOUT
Frequency
0: XTALCLK
1: XTALCLK
= f
OUT CRYSTAL
(default)
/2
= f
OUT CRYSTAL
7
Disable
XTALCLKOUT
0 = XTALCLK
1 = XTALCLK
enabled
is logic low
OUT
OUT
0x14
0x15
0x16
DC Restore and ABLC™ starting
pixel MSB (0x00)
4:0
DC Restore and
ABLC™ starting
pixel (MSB)
Pixel after HSYNC trailing edge to begin
IN
DC restore and ABLC™ functions. 13 bits.
Set this register to the first stable black pixel following the
trailing edge of HSYNC
.
IN
DC Restore and ABLC™ starting
pixel LSB (0x00)
7:0
7:0
DC Restore and
ABLC™ starting
pixel (LSB)
DC Restore Clamp Width
(0x10)
DC Restore clamp
width (pixels)
Width of DC restore clamp used in AC-coupled
configurations. Has no effect on ABLC™. Minimum value is
0x02 (a setting of 0x01 or 0x00 will not generate a clamp
pulse).
FN8218.3
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March 8, 2006
X98017
Register Listing (Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(s)
FUNCTION NAME
DESCRIPTION
0x17
ABLC™ Configuration (0x40)
0
ABLC™ disable
0: ABLC™ enabled (default)
1: ABLC™ disabled
1
Reserved
Set to 0.
3:2
ABLC™ pixel width
Number of black pixels averaged every line for ABLC™
function
00: 16 pixels [default]
01: 32 pixels
10: 64 pixels
11: 128 pixels
(5+[6:4])
6:4
ABLC™ bandwidth
ABLC™ Time constant (lines) = 2
000 = 32 lines
100 = 512 lines (default)
111 = 4096 lines
7
0
Reserved
Bus Width
Set to 0.
0x18
Output Format (0x00)
0: 24 bits: Data output on R , G , B only; R , G , B are all
P P P S S S
driven low (default)
1: 48 bits: Data output on R , G , B , R , G , B
S
P
P
P
S
S
1
2
Interleaving
0: No interleaving: data changes on same edge of DATACLK
(default)
(48 bit mode only)
1: Interleaved: Secondary databus data changes on
opposite edge of DATACLK from primary databus
Bus Swap
(48 bit mode only)
0: First data byte after trailing edge of HSOUT appears on
R , G , B (default)
P P P
1: First data byte after trailing edge of HSOUT appears on
R , G , B (primary and secondary busses are reversed)
S
S
S
3
4
Reserved
Set to 0.
422
0: Data is formatted as 4:4:4 (RGB, default)
1: Data is decimated to 4:2:2 (YUV), blue channel is driven
low
(24 bit mode only)
5
DATACLK
Polarity
0: HS
, VS
OUT
, and Pixel Data change on falling edge of
OUT
DATACLK (default)
1: HS , VS , and Pixel Data change on rising edge of
OUT OUT
DATACLK
6
VSOUT Polarity
HSOUT Polarity
HSOUT Width
0: Active High (default)
1: Active Low
7
0: Active High (default)
1: Active Low
0x19
0x1A
HSOUT Width (0x10)
7:0
HSOUT width, in pixels. Minimum value is 0x01 for 24 bit
modes, 0x02 for 48 bit modes.
Output Signal Disable (0x00)
0
1
2
3
4
5
6
Three-state R [7:0]
0 = Output byte enabled
P
1 = Output byte three-stated
These bits override all other I/O settings
Three-state R [7:0]
S
Output data pins have 58kΩ pulldown resistors to GND .
Three-state G [7:0]
D
P
Three-state G [7:0]
S
Three-state B [7:0]
P
Three-state B [7:0]
S
Three-state
DATACLK
0 = DATACLK enabled
1 = DATACLK three-stated
7
Three-state
DATACLK
0 = DATACLK enabled
1 = DATACLK three-stated
FN8218.3
March 8, 2006
14
X98017
Register Listing (Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(s)
FUNCTION NAME
DESCRIPTION
0x1B
Power Control (0x00)
0
Red
Power-down
0 = Red ADC operational (default)
1 = Red ADC powered down
1
2
3
Green
0 = Green ADC operational (default)
1 = Green ADC powered down
Power-down
Blue
Power-down
0 = Blue ADC operational (default)
1 = Blue ADC powered down
PLL
Power-down
0 = PLL operational (default)
1 = PLL powered down
7:4
7:0
3:0
6:4
Reserved
Reserved
Reserved
Set to 0
0x1C
0x23
Reserved (0x47)
Set to 0x49 for best performance with NTSC and PAL video
Set to 1000
DC Restore Clamp (0x08)
DC Restore Clamp
Impedance
DC Restore clamp's ON resistance.
Shared for all three channels
0: Infinite (clamp disconnected) (default)
1: 1600Ω
2: 800Ω
3: 533Ω
4: 400Ω
5: 320Ω
6: 267Ω
7: 228Ω
7
Reserved
Set to 0
generates 64 phase steps per pixel (vs. the industry
standard 32), for fine, accurate positioning of the sampling
point. The crystal-locked NCO inside the DPLL completely
eliminates drift due to charge pump leakage, so there is
inherently no frequency or phase change across a line. An
intelligent all-digital loop filter/controller eliminates the need
for the user to have to program or change anything (except
for the number of pixels) to lock over a range from interlaced
video (10MHz or higher) to UXGA 60Hz (170MHz).
Technical Highlights
The X98017 provides all the features of traditional triple
channel video AFEs, but adds several next-generation
enhancements, bringing performance and ease of use to
new levels.
DPLL
All video AFEs must phase lock to an HSYNC signal,
supplied either directly or embedded in the video stream
(Sync On Green). Historically this function has been
implemented as a traditional analog PLL. At SXGA and
lower resolutions, an analog PLL solution has proven
adequate, if somewhat troublesome (due to the need to
adjust charge pump currents, VCO ranges and other
parameters to find the optimum trade-off for a wide range of
pixel rates).
The DPLL eliminates much of the performance limitations
and complexity associated with noise-free digitization of high
speed signals.
Automatic Black Level Compensation (ABLC™)
and Gain Control
Traditional video AFEs have an offset DAC prior to the ADC,
to both correct for offsets on the incoming video signals and
add/subtract an offset for user “brightness control”. This
solution is adequate, but it places significant requirements
on the system's firmware, which must execute a loop that
detects the black portion of the signal and then servos the
offset DACs until that offset is nulled (or produces the
desired ADC output code). Once this has been
accomplished, the offset (both the offset in the AFE and the
offset of the video card generating the signal) is subject to
drift - the temperature inside a monitor or projector can
easily change 50°C between power-on/offset calibration on a
cold morning and the temperature reached once the monitor
and the monitor's environment have reached steady state.
As display resolutions and refresh rates have increased,
however, the pixel period has decreased. An XGA pixel at a
60Hz refresh rate has 15.4ns to change and settle to its new
value. But at UXGA 75Hz, the pixel period is 4.9ns. Most
consumer graphics cards spend most of that time slewing to
the new pixel value. The pixel may settle to its final value
with 1ns or less before it begins slewing to the next pixel. In
many cases it never settles at all. So precision, low-jitter
sampling is a fundamental requirement at these speeds, and
a difficult one for an analog PLL to meet.
The X98017's DPLL has less than 250ps of jitter, peak to
peak, and independent of the pixel rate. The DPLL
FN8218.3
15
March 8, 2006
X98017
Offset can drift significantly over 50°C, reducing image
quality and requiring that the user do a manual calibration
once the monitor has warmed up.
Functional Description
Inputs
The X98017 digitizes analog video inputs in both RGB and
Component (YPbPr) formats, with or without embedded sync
(SOG).
In addition to drift, many AFEs exhibit interaction between
the offset and gain controls. When the gain is changed, the
magnitude of the offset is changed as well. This again
increases the complexity of the firmware as it tries to
optimize gain and offset settings for a given video input
signal. Instead of adjusting just the offset, then the gain, both
have to be adjusted interactively until the desired ADC
output is reached.
RGB Inputs
For RGB inputs, the black/blank levels are identical and
equal to 0V. The range for each color is typically 0V to 0.7V
from black to white. HSYNC and VSYNC are separate
signals.
The X98017 simplifies offset and gain adjustment and
completely eliminates offset drift using its Automatic Black
Level Compensation (ABLC™) function. ABLC™ monitors
the black level and continuously adjusts the X98017's 10 bit
offset DACs to null out the offset. Any offset, whether due to
the video source or the X98017's analog amplifiers, is
eliminated with 10 bit (1/4 of an 8 bit ADC LSB) accuracy.
Any drift is compensated for well before it can have a visible
effect. Manual offset adjustment control is still available - an
8 bit register allows the firmware to adjust the offset ±64
codes in exactly 1 ADC LSB increments. And gain is now
completely independent of offset - adjusting the gain no
longer affects the offset, so there is no longer a need to
program the firmware to cope with interactive offset and gain
controls.
Component YUV Inputs
In addition to RGB and RGB with SOG, the X98017 has an
option that is compatible with the component YPbPr and
YCbCr video inputs typically generated by DVD players.
While the X98017 digitizes signals in these color spaces, it
does not perform color space conversion; if it digitizes an
RGB signal, it outputs digital RGB, while if it digitizes a
YPbPr signal, it outputs digital YPbPr. For simplicity’s sake
we will call these non-RGB signals YUV.
The Luminance (Y) signal is applied to the Green Channel
and is processed in a manner identical to the Green input
with SOG described previously. The color difference signals
U and V are bipolar and swing both above and below the
black level. When the YUV mode is enabled, the black level
output for the color difference channels shifts to a mid scale
value of 0x80. Setting configuration register 0x05[2] = 1
enables the YUV signal processing mode of operation.
Finally, there should be no concerns over ABLC™ itself
introducing visible artifacts; it doesn't. ABLC™ operates at a
very low frequency, changing the offset in 1/4 LSB
TABLE 1. YUV MAPPING (4:4:4)
increments, so it doesn't cause visible brightness
X98017
INPUT
X98017
OUTPUT
fluctuations. And once ABLC™ is locked, if the offset doesn't
drift, the DACs won't change. If desired, ABLC™ can be
disabled, allowing the firmware to work in the traditional way,
with 10 bit offset DACs under the firmware's control.
INPUT
OUTPUT
SIGNAL
SIGNAL
CHANNEL
ASSIGNMENT
Y
U
V
Green
Blue
Green
Blue
Y Y Y Y
1 2 3
0
U U U U
0
1
2
3
3
Gain and Offset Control
Red
Red
V V V V
0 1 2
To simplify image optimization algorithms, the X98017
features fully-independent gain and offset adjustment.
Changing the gain does not affect the DC offset, and the
weight of an Offset DAC LSB does not vary depending on
the gain setting.
The X98017 can optionally decimate the incoming data to
provide a 4:2:2 output stream (configuration register
0x18[4] = 1) as shown in Table 2.
TABLE 2. YUV MAPPING (4:2:2)
The full-scale gain is set in the three 8-bit registers (0x06-
0x08). The X98017 can accept input signals with amplitudes
X98017
INPUT
X98017
OUTPUT
INPUT
OUTPUT
SIGNAL
ranging from 0.35V
to 1.4V .
P-P
P-P
SIGNAL
CHANNEL
ASSIGNMENT
The offset controls shift the entire RGB input range,
changing the input image brightness. Three separate
registers provide independent control of the R, G, and B
channels. Their nominal setting is 0x80, which forces the
ADC to output code 0x00 (or 0x80 for U and V channels in
YUV mode) during the back porch period when ABLC™ is
enabled.
Y
U
V
Green
Blue
Green
Blue
Y Y Y Y
0 1 2 3
driven low
U V U V
1 2 3
Red
Red
0
FN8218.3
March 8, 2006
16
X98017
If DC-coupled operation is desired, the input to the ADC will
Input Coupling
be the difference between the input signal (R 1, for
IN
Inputs can be either AC-coupled (default) or DC-coupled
(see register 0x05[1]). AC coupling is usually preferred since
it allows video signals with substantial DC offsets to be
accurately digitized. The X98017 provides a complete
internal DC-restore function, including the DC restore clamp
(See Figure 7) and programmable clamp timing (registers
0x14, 0x15, 0x16, and 0x23).
example) and that channel’s ground reference (RGB
that example).
1 in
GND
SOG
For component YUV signals, the sync signal is embedded
on the Y channel’s video, which is connected to the green
input, hence the name SOG (Sync on Green). The horizontal
sync information is encoded onto the video input by adding
the sync tip during the blanking interval. The sync tip level is
typically 0.3V below the video black level.
When AC-coupled, the DC restore clamp is applied every
line, a programmable number of pixels after the trailing edge
of HSYNC. If register 0x05[5] = 0 (the default), the clamp will
not be applied while the DPLL is coasting, preventing any
clamp voltage errors from composite sync edges,
To minimize the loading on the green channel, the SOG
input for each of the green channels should be AC-coupled
to the X98017 through a series combination of a 10nF
capacitor and a 500Ω resistor. Inside the X98017, a window
comparator compares the SOG signal with an internal 4 bit
programmable threshold level reference ranging from 0mV
to 300mV below the minimum sync level. The SOG
threshold level, hysteresis, and low-pass filter is
equalization pulses, or Macrovision signals.
After the trailing edge of HSYNC, the DC restore clamp is
turned on after the number of pixels specified in the DC
Restore and ABLC™ Starting Pixel registers (0x14 and
0x15) has been reached. The clamp is applied for the
number of pixels specified by the DC Restore Clamp Width
Register (0x16). The clamp can be applied to the back porch
of the video, or to the front porch (by increasing the DC
Restore and ABLC™ Starting Pixel registers so all the active
video pixels are skipped).
programmed via register 0x04. If the Sync-On-Green
function is not needed, the SOG pin(s) may be left
IN
unconnected.
Automatic Black Level
Compensation (ABLC™) Loop
DC Restoration
10
Fixed
Offset
Offset
Control
To
ABLC
Block
CLAMP
GENERATION
Registers
10
Offset
ADC
0x00
8
V
8
CLAMP
DC Restore
Clamp DAC
10
ABLC™
ABLC™
Fixed
Offset
ABLC™
R(GB)
IN
1
1
8
V
V
+
–
VGA1
VGA2
IN
R(GB)
GND
8
8
To Output
Formatter
Input
Bandwidth
8 bit ADC
PGA
IN
R(GB)
2
2
IN
Bandwidth
Control
R(GB)
GND
FIGURE 7. VIDEO FLOW (INCLUDING ABLC™)
FN8218.3
March 8, 2006
17
X98017
ACTIVITY 0x01[6:0]
&
POLARITY 0x02[5:0]
DETECT
HSYNC1
SLICER
0x03[2:0]
HSYNCOUT
CSYNC
HSYNCIN
1
SOURCE
0:
00, 10,
SYNC
TYPE
VSYNCIN
1
1
HSYNCIN
VGA1
11:
HSYNCIN
SOG
SLICER
0x1C
VSYNC
SYNC
SOGIN
1:
0x05[4:3]
SPLITTER
SYNC
SPLTR
SOGIN
0x05[0]
HSYNC2
SLICER
0x03[6:4]
01:
SOGIN
HSYNCIN
2
2
VSYNCOUT
0x05[3]
VSYNCIN
1:
VGA2
0:
VSYNCIN
VSYNCIN
SOG
SLICER
0x1C
SOGIN2
COAST
RP[7:0]
RS[7:0]
GP[7:0]
GENERATION
0x11, 0x12, 0x13[2]
Pixel Data
from AFE
24
CLOCKINVIN
GS[7:0]
BP[7:0]
Output
HS
Formatter
PLL
BS[7:0]
XTALIN
0x18,
0x19,
0x1A
0x0E through 0x13
DATACLK
DATACLK
PIXCLK
0: ÷1
XTALOUT
0x13
[6]
HSOUT
VSOUT
1: ÷2
÷2
XTALCLOCKOUT
FIGURE 8. SYNC FLOW
The PGAs are updated by the internal clamp signal once per
line. In normal operation this means that there is a maximum
delay of one HSYNC period between a write to a Gain
register for a particular color and the corresponding change
in that channel’s actual PGA gain. If there is no regular
HSYNC/SOG source, or if the external clamp option is
enabled (register 0x13[5:4]) but there is no external clamp
signal being generated, it may take up to 100ms for a write
to the Gain register to update the PGA. This is not an issue
in normal operation with RGB and YUV signals.
SYNC Processing
The X98017 can process sync signals from 3 different
sources: discrete HSYNC and VSYNC, composite sync on
the HSYNC input, or composite sync from a Sync-On-Green
(SOG) signal embedded on the Green video input. The
X98017 has SYNC activity detect functions to help the
firmware determine which sync source is available.
PGA
The X98017’s Programmable Gain Amplifier (PGA) has a
nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB).
The transfer function is:
Bandwidth and Peaking Control
Register 0x0D[3:1] controls a low pass filter allowing the
input bandwidth to be adjusted with three bit resolution
between its default value (0x0E = 780MHz) and its minimum
bandwidth (0x00, for 100MHz). Typically the higher the
resolution, the higher the desired input bandwidth. To
minimize noise, video signals should be digitized with the
minimum bandwidth setting that passes sharp edges.
V
---
GainCode
Gain
= 0.5 + ----------------------------
V
170
where GainCode is the value in the Gain register for that
particular color. Note that for a gain of 1 V/V for GainCode
should be 85 (0x55). This is a different center value than the
128 (0x80) value used by some other AFEs, so the firmware
should take this into account when adjusting gains.
FN8218.3
18
March 8, 2006
X98017
Table 3 shows the corner frequency for different register
settings.
interaction between the PGA (controlling “contrast”) and the
Offset DAC (controlling “brightness”).
TABLE 3. BANDWIDTH CONTROL
In normal operation, the Offset DAC is controlled by the
ABLC™ circuit, ensuring that the offset is always reduced
to sub-LSB levels (See the following ABLC™ section for
more information). When ABLC™ is enabled, the Offset
registers (0x09, 0x0A, 0x0B) control a digital offset added
to or subtracted from the output of the ADC. This mode
provides the best image quality and eliminates the need for
any offset calibration.
0x0D[3:0] VALUE
(LSB = “x” = “don’t care”)
AFE BANDWIDTH
100MHz
000x
001x
010x
011x
100x
101x
110x
111x
130MHz
150MHz
180MHz
If desired, ABLC™ can be disabled (0x17[0]=1) and the
Offset DAC programmed manually, with the 8 most
significant bits in registers 0x09, 0x0A, 0x0B, and the 2 least
significant bits in register 0x0C[7:2].
230MHz
320MHz
480MHz
780MHz
The default Offset DAC range is ±127 ADC LSBs. Setting
0x0C[0]=1 reduces the swing of the Offset DAC by 50%,
making 1 Offset DAC LSB the weight of 1/8th of an ADC
LSB. This provides the finest offset control and applies to
both ABLC™ and manual modes.
Register 0x0D[7:4] controls a programmable zero, allowing
high frequencies to be boosted, restoring some of the
harmonics lost due to excessive EMI filtering, cable losses, etc.
This control has a very large range, and can introduce high
frequency noise into the image, so it should be used judiciously,
or as an advanced user adjustment.
Automatic Black Level Compensation (ABLC™)
ABLC is a function that continuously removes all offset
errors from the incoming video signal by monitoring the
offset at the output of the ADC and servoing the 10 bit
analog DAC to force those errors to zero. When ABLC is
enabled, the user offset control is a digital adder, with 8 bit
resolution (See Table 5).
Table 4 shows the corner frequency of the zero for different
peaking register settings.
TABLE 4. PEAKING CORNER FREQUENCIES
0X0D[7:4] VALUE
ZERO CORNER FREQUENCY
Peaking disabled
800MHz
When the ABLC function is enabled (0x17[0]=0), the ABLC
function is executed every line after the trailing edge of
HSYNC. If register 0x05[5] = 0 (the default), the ABLC
function will not be triggered while the DPLL is coasting,
preventing any composite sync edges, equalization pulses,
or Macrovision signals from corrupting the black data and
potentially adding a small error in the ABLC accumulator.
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
400MHz
265MHz
200MHz
160MHz
After the trailing edge of HSYNC, the start of ABLC is delayed
by the number of pixels specified in registers 0x14 and 0x15.
After that delay, the number of pixels specified by register
0x17[3:2] are averaged together and added to the ABLC’s
accumulator. The accumulator stores the average black levels
for the number of lines specified by register 0x17[6:4], which
is then used to generate a 10 bit DAC value.
135MHz
115MHz
100MHz
90MHz
80MHz
70MHz
The default values provide excellent results with offset
stability and absolute accuracy better than 1 ADC LSB for
most input signals. Increasing the ABLC pixel width or the
ABLC bandwidth settings decreases the ABLC’s absolute
DC error further.
65MHz
60MHz
55MHz
50MHz
ADC
The X98017 features 3 fully differential, 170MSPS 8 bit
ADCs.
Offset DAC
The X98017 features a 10 bit Digital-to-Analog Converter
(DAC) to provide extremely fine control over the full channel
offset. The DAC is placed after the PGA to eliminate
FN8218.3
19
March 8, 2006
X98017
TABLE 5. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT
USER OFFSET CONTROL
USER OFFSET CONTROL
RESOLUTION USING REGISTERS
0x09 - 0x0B AND 0x0C[7:2]
OFFSET DAC
RANGE
10 BIT
RESOLUTION USING REGISTERS
OFFSET DAC
RESOLUTION
ABLC™
0x17[0]
0x09 - 0x0B ONLY
0x0C[0]
(8 BIT OFFSET CONTROL)
(10 BIT OFFSET CONTROL)
0
1
0
1
0.25 ADC LSBs
(0.68mV)
0
1 ADC LSB
N/A
N/A
(ABLC on)
(digital offset control)
0.125 ADC LSBs
(0.34mV)
0
1 ADC LSB
(digital offset control)
(ABLC on)
0.25 ADC LSBs
(0.68mV)
1
1.0 ADC LSB
(analog offset control)
0.25 ADC LSB
(analog offset control)
(ABLC off)
0.125 ADC LSBs
(0.34mV)
1
0.5 ADC LSB
(analog offset control)
0.125 ADC LSB
(analog offset control)
(ABLC off)
Clock Generation
SOG Slicer
A Digital Phase Lock Loop (DPLL) is employed to generate
the pixel clock frequency. The HSYNC input and the external
XTAL provide a reference frequency to the PLL. The PLL
then generates the pixel clock frequency that is equal to the
incoming HSYNC frequency times the HTOTAL value
programmed into registers 0x0E and 0x0F.
The SOG input has programmable threshold, 40mV of
hysteresis, and an optional low pass filter than can be used
to remove high frequency video spikes (generated by
overzealous video peaking in a DVD player, for example)
that can cause false SOG triggers. The SOG threshold sets
the comparator threshold relative to the sync tip (the bottom
of the SOG pulse). A good default SOG slicer threshold
setting is 0x16 (hysteresis and low pass filter enabled,
threshold lowered slightly to accommodate weak sync tips).
The stability of the clock is very important and correlates
directly with the quality of the image. During each pixel time
transition, there is a small window where the signal is
slewing from the old pixel amplitude and settling to the new
pixel value. At higher frequencies, the pixel time transitions
at a faster rate, which makes the stable pixel time even
smaller. Any jitter in the pixel clock reduces the effective
stable pixel time and thus the sample window in which pixel
sampling can be made accurately.
SYNC Status and Polarity Detection
The SYNC Status register (0x01) and the SYNC Polarity
register (0x02) continuously monitor all 6 sync inputs
(VSYNC , HSYNC , and SOG for each of 2 channels)
IN IN IN
and report their status. However, accurate sync activity
detection is always a challenge. Noise and repetitive video
patterns on the Green channel may look like SOG activity
when there actually is no SOG signal, while non-standard
SOG signals and trilevel sync signals may have amplitudes
below the default SOG slicer levels and not be easily
detected. As a consequence, not all of the activity detect bits
in the X980xx are correct under all conditions.
Sampling Phase
The X98017 provides 64 low-jitter phase choices per pixel
period, allowing the firmware to precisely select the optimum
sampling point. The sampling phase register is 0x10.
HSYNC Slicer
To further minimize jitter, the HSYNC inputs are treated as
analog signals, and brought into a precision slicer block with
thresholds programmable in 400mV steps with 240mV of
hysteresis, and a subsequent digital glitch filter that ignores
any HSYNC transitions within 100ns of the initial transition.
This processing greatly increases the AFE’s rejection of
ringing and reflections on the HSYNC line and allows the
AFE to perform well even with pathological HSYNC signals.
Table 6 shows how to use the SYNC Status register (0x01)
to identify the presence of and type of a sync source. The
firmware should go through the table in the order shown,
stopping at the first entry that matches the activity indicators
in the SYNC Status register.
Final validation of composite sync sources (SOG or
Composite sync on HSYNC) should be done by setting the
Input Configuration register (0x05) to the composite sync
source determined by this table, and confirming that the
CSYNC detect bit is set.
Voltages given above and in the HSYNC Slicer register
description are with respect to a 3.3V sync signal at the
HSYNC input pin. To achieve 5V compatibility, a 680Ω
IN
The accuracy of the Trilevel Sync detect bit can be increased
by multiple reads of the Trilevel Sync detect bit. See the
Trilevel Sync Detect section for more details.
series resistor should be placed between the HSYNC source
and the HSYNC input pin. Relative to a 5V input, the
IN
hysteresis will be 240mV*5V/3.3V = 360mV, and the slicer
step size will be 400mV*5V/3.3V = 600mV per step.
For best SOG operation, the SOG low pass filter (register
0x04[4]) should always be enabled to reject the high
frequency peaking often seen on video signals.
The best HSYNC slicer threshold is generally 800mV (001b)
when locking on the rising edge of an HSYNC signal, or 2.4V
(110b) when locking on the falling edge.
FN8218.3
20
March 8, 2006
X98017
TABLE 6. SYNC SOURCE DETECTION TABLE
HSYNC
VSYNC
SOG
TRILEVEL
DETECT
DETECT
DETECT
DETECT
RESULT
1
1
1
0
X
X
X
X
Sync is on HSYNC and VSYNC
Sync is composite sync on HSYNC. Set Input configuration register to CSYNC on HSYNC
and confirm that CSYNC detect bit is set.
0
0
1
0
Sync is composite sync on SOG. It is possible that trilevel sync is present but amplitude is
too low to set trilevel detect bit. Use video mode table to determine if this video mode is
likely to have trilevel sync, and set clamp start, width values appropriately if it is.
0
0
0
0
1
0
1
Sync is composite sync on SOG. Sync is likely to be trilevel.
No valid sync sources on any input.
X
Detect should only be considered valid if HSYNC Activity
HSYNC and VSYNC Activity Detect
Activity on these bits always indicates valid sync pulses, so
they should have the highest priority and be used even if the
SOG activity bit is also set.
Detect = 0 and SOG Activity Detect = 1.
If there is a SOG signal, the TriLevel Detect bit will operate
correctly for standard trilevel sync levels (600mVp-p). In
some real-world situations, the peak-to-peak sync amplitude
may be significantly smaller, sometimes 300mVp-p or less.
In these cases the sync slicer will continue to operate
correctly, but the TriLevel Detect bit may not be set. Trilevel
detection accuracy can be enhanced by polling the trilevel
bit multiple times. If HSYNC is inactive, SOG is present, and
the TriLevel Sync Detect bit is read as a 1, there is a high
likelihood there is trilevel sync.
SOG Activity Detect
The SOG activity detect bit monitors the output of the SOG
slicer, looking for 64 consecutive pulses with the same
period and duty cycle. If there is no signal on the Green
(or Y) channel, the SOG slicer will clamp the video to a DC
level and will reject any sporadic noise. There should be no
false positive SOG detects if there is no video on Green
(or Y).
CSYNC Present
If there is video on Green (or Y) with no valid SOG signal,
the SOG activity detect bit may sometimes report false
positives (it will detect SOG when no SOG is actually
present). This is due to the presence of video with a
repetitive pattern that creates a waveform similar to SOG.
For example, the desktop of a PC operating system is black
during the front porch, horizontal sync, and back porch, then
increases to a larger value for the visible portion of the
screen. This creates a repetitive video waveform very
similar to SOG that may falsely trigger the SOG Activity
detect bit. However, in these cases where there is active
video without SOG, the SYNC information will be provided
If a composite sync source (either CSYNC on HSYNC or
SOG) is selected through bits 3 and 4 of register 0x05, the
CSYNC Present bit in register 0x01 should be set. CSYNC
Present detects the presence of a low frequency, repetitive
signal inside HSYNC, which indicates a VSYNC signal. The
CSYNC Present bit should be used to confirm that the signal
being received is a reliable composite sync source.
SYNC Output Signals
The X98017 has 2 pairs of HSYNC and VSYNC output
signals, HSYNC
and VSYNC
, and HS
and
OUT
OUT
OUT
VS
.
OUT
either as separate H and V sync on HSYNC and
IN
VSYNC , or composite sync on HSYNC . HSYNC and
HSYNC
OUT
and VSYNC
are buffered versions of the
OUT
IN
IN
IN
VSYNC should therefore be used to qualify SOG. The
IN
incoming sync signals; no synchronization is done. These
signals should be used for mode detection.
SOG Active bit should only be considered valid if HSYNC
Activity Detect = 0. Note: Some pattern generators can
output HSYNC and SOG simultaneously, in which case both
the HSYNC and the SOG activity bits will be set, and valid.
Even in this case, however, the monitor should still choose
HSYNC over SOG.
HS
OUT
and VS
are generated by the X98017’s logic
OUT
and are synchronized to the output DATACLK and the digital
pixel data on the output databus. HS is used to signal
OUT
the start of a new line of digital data. VS
most applications.
is not needed in
OUT
TriLevel Sync Detect
Both HSYNC
OUT
and VSYNC
(including the sync
OUT
Unlike SOG detect, the TriLevel Sync detect function does
not check for 64 consecutive trilevel pulses in a row, and is
therefore less robust than the SOG detect function. It will
report false positives for SOG-less video for the same
reasons the SOG activity detect does, and should therefore
be qualified with both HSYNC and SOG. TriLevel Sync
separator function) remain active in power-down mode. This
allows them to be used in conjunction with the Sync Status
registers to detect valid video without powering up the
X98017.
FN8218.3
21
March 8, 2006
X98017
HSYNC
TABLE 7. HS
WIDTH
OUT
is an unmodified, buffered version of the
OUT
HSYNC
OUT
HS
WIDTH (PIXEL CLOCKS)
OUT
incoming HSYNC or SOG signal of the selected
IN IN
REGISTER
24 BIT MODE, 24 BIT MODE,
ALL 48 BIT
MODES
channel, with the incoming signal’s period, polarity, and
width to aid in mode detection. HSYNC will be the same
0x19 VALUE
RGB
YUV
OUT
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
1
3
3
5
5
7
7
0
0
2
2
4
4
6
6
format as the incoming sync signal: either horizontal or
composite sync. If a SOG input is selected, HSYNC
output the entire SOG signal, including the VSYNC portion,
pre-/post-equalization pulses if present, and Macrovision
pulses if present. HSYNC
X98017 is in power-down mode. HSYNC
used for mode detection.
will
OUT
remains active when the
OUT
is generally
OUT
VSYNC
OUT
VSYNC
OUT
is an unmodified, buffered version of the
incoming VSYNC signal of the selected channel, with the
IN
original VSYNC period, polarity, and width to aid in mode
detection. If a SOG input is selected, this signal will output
the VSYNC signal extracted by the X98017’s sync slicer.
Extracted VSYNC will be the width of the embedded VSYNC
pulse plus pre- and post-equalization pulses (if present).
Macrovision pulses from an NTSC DVD source will lengthen
the width of the VSYNC pulse. Macrovision pulses from
other sources (PAL DVD or videotape) may appear as a
second VSYNC pulse encompassing the width of the
Macrovision. See the Macrovision section for more
VS
OUT
VS
is generated by the X98017’s control logic and is
OUT
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its leading and trailing edges are
aligned with pixel 7 (8 pixels after HSYNC trailing edge). Its
width, in units of lines, is equal to the width of the incoming
VSYNC (see the VSYNC
description). Its polarity is
OUT
determined by register 0x18[6]. This output is not needed in
most applications.
information. VSYNC
(including the sync separator
Macrovision
OUT
function) remains active in power-down mode. VSYNC
is generally used for mode detection, start of field detection,
and even/odd field detection.
OUT
The X98017 will synchronize to and digitize Macrovision-
encoded YUV video if the source is an NTSC DVD.
Macrovision from PAL DVD, or from all video tape sources,
is incompatible with the sync slicer, requiring that the
Macrovision pulses either be stripped from the video prior to
HS
OUT
HS
is generated by the X98017’s control logic and is
OUT
the SOG input, or an external COAST signal be generated
and applied to the CLKINV pin that will coast the X98017’s
PLL during the VSYNC and Macrovision period.
IN
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its trailing edge is aligned with
pixel 0. Its width, in units of pixels, is determined by register
0x19, and its polarity is determined by register 0x18[7]. As
the width is increased, the trailing edge stays aligned with
pixel 0, while the leading edge is moved backwards in time
Standby Mode
The X98017 can be placed into a low power standby mode
by writing a 0x0F to register 0x1B, powering down the triple
ADCs, the DPLL, and most of the internal clocks.
relative to pixel 0. HS
is used by the scaler to signal the
OUT
start of a new line of pixels.
The HSOUT Width register (0x19) controls the width of the
HS pulse. The pulse width is nominally 1 pixel clock
To allow input monitoring and mode detection during power-
down, the following blocks remain active:
OUT
• Serial interface (including the crystal oscillator) to enable
register read/write activity
period times the value in this register. In the 48 bit output
mode (register 0x18[0] = 1), or the YUV input mode (register
0x05[2] = 1), the HS
width is incremented in 2 pixel clock
• Activity and polarity detect functions (registers 0x01 and
0x02)
OUT
(1 DATACLK) increments (see Table 7).
• The HSYNC
detection)
and VSYNC
pins (for mode
OUT
OUT
FN8218.3
March 8, 2006
22
X98017
HSYNCIN
DPLL Lock Edge
(to A and B)
Analog Video In
(to A and B)
PN-3 PN-2 PN-1 PN P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12
DATACLK (A)
DATA (A)
DN-3
DN-1
D0
D2
HSOUT (A)
CLKINVIN (A) = GNDD
½ DATACLK Delay
DATACLK (B)
DATA (B)
DN-2
DN
D1
D3
HSOUT (B)
CLKINVIN (B) = VD
FIGURE 9. ALTERNATE PIXEL SAMPLING (24 BIT MODE)
If EMI is a problem in the final design, increase the value of
the digital output series resistors to reduce slew rates on the
bus. This can only be done as long as the scaler’s setup and
hold timing requirements continue to be met.
Crystal Oscillator
An external 23MHz to 27MHz crystal supplies the low-jitter
reference clock to the DPLL. The absolute frequency of this
crystal within this range is unimportant, as is the crystal’s
temperature coefficient, allowing use of less expensive,
lower-grade crystals.
Alternate Pixel Sampling
Two X98017s (AFE and AFE ) may be used
A
B
simultaneously to achieve effective sample rates greater
than 170MHz. Each AFE is programmed with an HTOTAL
value equal to one-half of the total number of pixels in a line.
EMI Considerations
There are two possible sources of EMI on the X98017:
• Crystal oscillator. The EMI from the crystal oscillator is
negligible. This is due to an amplitude-regulated, low
voltage sine wave oscillator circuit, instead of the typical
high-gain square wave inverter-type oscillator, so there
are no harmonics. The crystal oscillator is not a significant
source of EMI.
The CLOCKINV pin for AFE is tied to ground, AFE is
IN
A
B
tied to V . Both AFEs are otherwise programmed identically,
D
though some minor phase adjustment may be needed to
compensate for any propagation delay mismatch between
the two AFEs.
The CLOCKINV setting shifts the phase of AFE by 180
IN
• Digital output switching. This is the largest potential
source of EMI. However, the EMI is determined by the
PCB+ layout and the loading on the databus. The way to
control this is to put series resistors on the output of all the
digital pins. These resistor values should be adjusted to
optimize signal quality on the bus. Intersil recommends
starting with 22Ω and adjusting as necessary for the
particular PCB layout and device loading.
B
degrees from AFE . AFE now samples the even pixels on
A
A
the rising edge of its DATACLK, while AFE samples the odd
B
pixels on the rising edge of its clock. With each AFE in 24 bit
mode, two 24 bit data streams are generated (Figure 9).
With both AFEs configured for 48 bit mode, a 96 bit
datastream is generated (Figure 10).
In both cases, AFE and AFE are on different DATACLK
A
B
Recommendations for minimizing EMI are:
• Minimize the databus trace length
domains. In 24 bit mode, the data from each AFE must be
latched on the rising edge of that AFE’s DATACLK. In 48 bit
mode, the frequencies are low enough that the rising edge of
• Minimize the databus capacitive loading.
AFE B can be used to capture both AFE and AFE data.
B
A
FN8218.3
March 8, 2006
23
X98017
HSYNCIN
DPLL Lock Edge
(to A and B)
Analog Video In
(to A and B)
PN-3 PN-2 PN-1 PN P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12
PIXELCLK (A)
(Internal)
DATACLK (A)
DATAPRI (A)
DATASEC (A)
HSOUT (A)
DN-3
DN-1
D0
D2
CLKINVIN (A) = GNDD
½ PIXELCLK = ¼ DATACLK Delay
PIXELCLK (B)
(Internal)
DATACLK (B)
DATAPRI (B)
DATASEC (B)
HSOUT (B)
DN-2
D1
D3
DN
CLKINVIN (B) = GNDD
FIGURE 10. ALTERNATE PIXEL SAMPLING (48 BIT MODE)
.
having to cycle the power supplies. The RESET pin does not
need to be used in normal operation and can be tied high.
Initialization
The X98017 initializes with default register settings for an
AC-coupled, RGB input on the VGA1 channel, with a 24 bit
output.
Rare CSYNC Considerations
Intersil has discovered one anomaly in its sync separator
function. If the CSYNC signal shown in Figure 11 is present
on the HSYNC input, and the sync source is set to CSYNC
The following registers should be written to fully enable the
chip:
on HSYNC, HS
may sporadically lock to the wrong edge
to have the wrong
OUT
• Register 0x1C should be set to 0x49 to improve DPLL
performance in video modes
of HSYNC . This will cause the HS
IN OUT
position relative to pixel 0, resulting in the image shifting left
• Register 0x23 should be set to 0x78 to enable the DC
Restore function
or right by the width of the HSYNC signal for about 1
IN
second before it corrects itself.
Reset
This only happens with the exact waveshape shown in
Figure 11. If the polarity of the sync signal is inverted from
that shown in Figure 11, the problem will not occur. If there
are any serrations during the VSYNC period, the problem
will not occur. The problem also will not occur if the sync
signal is on the SOG input.
The X98017 has a Power-On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the Register Listing. The external
RESET pin duplicates the reset function of the POR without
FN8218.3
March 8, 2006
24
X98017
Conditions required: negative polarity VSYNC, with no serrations, and t1 = t2
t1
t2
HSYNCIN
FIGURE 11. CSYNC ON HSYNC THAT MAY CAUSE SPORADIC IMAGE SHIFTS
This is a rarely used composite sync format; in most
applications it will never be encountered. However if this
CSYNC waveform must be supported, there is a simple
applications solution using an XOR gate.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 12).
The X98017 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7 bit serial address plus a R/W bit, indicating if the next
transaction will be a Read (R/W = 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(Figure 13).
The output of the XOR gate is connected to the HSYNC
IN
input of the X98017. One of the XOR inputs is connected to
the HSYNC/CSYNC source, and the other input is
connected to a general purpose I/O. For all sync sources
except the CSYNC shown in Figure 11, the input connected
to the GPIO should be driven low.
If the system microcontroller detects a mode corresponding
to the sync type and polarity shown in Figure 11, it should
drive the GPIO pin high. This will invert the CSYNC signal
seen by the X98017 and prevent any spontaneous image
shifting.
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (Figure 12), or a second START command, which is
commonly used to reverse data direction without
relinquishing the bus.
X98017 Serial Communication
Overview
The X98017 uses a 2 wire serial bus for communication with
its host. SCL is the Serial Clock line, driven by the host, and
SDA is the Serial Data line, which can be driven by all
devices on the bus. SDA is open drain to allow multiple
devices to share the same bus simultaneously.
Data on the serial bus must be valid for the entire time SCL
is high (Figure 14). To achieve this, data being written to the
X98017 is latched on a delayed version of the rising edge of
SCL. SCL is delayed and deglitched inside the X98017 for 3
crystal clock periods (120ns for a 25MHz crystal) to eliminate
spurious clock pulses that could disrupt serial
Communication is accomplished in three steps:
communication.
1. The Host selects the X98017 it wishes to communicate
with.
When the contents of the X98017 are being read, the SDA
line is updated after the falling edge of SCL, delayed and
deglitched in the same manner.
2. The Host writes the initial X98017 Configuration Register
address it wishes to write to or read from.
3. The Host writes to or reads from the X98017’s
Configuration Register. The X98017’s internal address
pointer auto increments, so to read registers 0x00
through 0x1B, for example, one would write 0x00 in step
2, then repeat step 3 28 times, with each read returning
the next register value.
The X98017 has a 7 bit address on the serial bus. The upper
6 bits are permanently set to 100110, with the lower bit
determined by the state of pin 48. This allows 2 X98017s to
be independently controlled while sharing the same bus.
Configuration Register Write
Figure 15 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 16 shows two views of the steps necessary to read
one or more words from the Configuration Register.
FN8218.3
25
March 8, 2006
X98017
SCL
SDA
Start
Stop
FIGURE 12. VALID START AND STOP CONDITIONS
SCL from
Host
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
SCL
SDA
Data Change
Data Stable
Data Stable
FIGURE 14. VALID DATA CHANGES ON THE SDA BUS
FN8218.3
26
March 8, 2006
X98017
Signals the beginning of serial I/O
START Command
X98017 Serial Bus Address
R/W
X98017 Serial Bus Address Write
This is the 7 bit address of the X98017 on the 2 wire bus. The
address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. Shift this
value to left when adding the R/W bit
A
0
0
1
1
0
0
1
(pin 48)
X98017 Register Address Write
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
This is the address of the X98017’s configuration register that
the following byte will be written to.
X98017 Register Data Write(s)
This is the data to be written to the X98017’s configuration register.
Note: The X98017’s Configuration Register’s address pointer auto
increments after each data write: repeat this step to write multiple
sequential bytes of data to the Configuration Register.
(Repeat if desired)
Signals the ending of serial I/O
STOP Command
S
T
A
R
T
S
T
O
P
Serial Bus
Address
Register
Address
Data
Write*
* The data write step may be repeated to write to the X98017’s
Configuration Register sequentially, beginning at the Register
Address written in the previous step.
Signals from
the Host
1 0 0 1 1 0A0 a a a a a a a a d d d d d d d d
SDA Bus
A
C
K
A
C
K
A
C
K
Signals from
the X98017
FIGURE 15. CONFIGURATION REGISTER WRITE
FN8218.3
27
March 8, 2006
X98017
Signals the beginning of serial I/O
START Command
X98017 Serial Bus Address
R/W
X98017 Serial Bus Address Write
This is the 7 bit address of the X98017 on the 2 wire bus. The
address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. R/W = 0,
indicating next transaction will be a write.
A
0
0
1
1
0
0
1
(pin 48)
X98017 Register Address Write
A7
A6
A5
A4
A3
A2
A1
A0
This sets the initial address of the X98017’s configuration
register for subsequent reading
Ends the previous transaction and starts a new one
START Command
X98017 Serial Bus Address
R/W
X98017 Serial Bus Address Write
This is the 7 bit address of the X98017 on the 2 wire bus. The
address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. R/W = 1,
indicating next transaction(s) will be a read.
A
1
1
1
0
0
0
1
(pin 48)
X98017 Register Data Read(s)
D7
D6
D5
D4
D3
D2
D1
D0
This is the data read from the X98017’s configuration register.
Note: The X98017’s Configuration Register’s address pointer auto
increments after each data read: repeat this step to read multiple
sequential bytes of data from the Configuration Register.
(Repeat if desired)
Signals the ending of serial I/O
STOP Command
R
E
S
T
A
R
T
S
T
A
R
T
S
Serial Bus
Address
Serial Bus
Address
Register
Address
Data
Read*
Signals from
the Host
* The data read step may be repeated to read
T
from the X98017’s Configuration Register
sequentially, beginning at the Register
Address written in the two steps previous.
O
P
A
C
K
1 0 0 1 1 0A0 a a a a a a a a
1 0 0 1 1 0A1
SDA Bus
A
C
K
A
C
K
A
C
K
d d d d d d d d
Signals from
the X98017
FIGURE 16. CONFIGURATION REGISTER READ
FN8218.3
28
March 8, 2006
X98017
128-Lead Metric Quad Flat Pack (MQFP)
R0.25 TYP
D
ALL AROUND
D1
128
PIN 1
0.200 MIN.
1
0 ° MIN.
0.13~0.30
SEATING
PLANE
T
L
e
12.500 REF.
b
L1
C0.600X0.350
(4X)
ddd
DETAIL Y
C
12° ALL AROUND
13.870 0.100
A
DIMENSION LIST ( FOOTPRINT: 3.200)
14.000 0.100
(D1)
A
1
S/N
1
SYM
A
DIMENSIONS
REMARKS
Y
MAX. 3.40
OVERALL HEIGHT
STANDOFF
2
A1
A2
D
0.250~0.500
2.750 0.250
17.200 0.250
14.000 0.100
23.200 0.250
20.000 0.100
0.880 0.150
1.600 REF.
ALL AROUND
3
PKG THICKNESS
LEAD TIP TO TIP
PKG LENGTH
4
NOTES :
5
D1
E
S/N
1
DESCRIPTION
SPECIFICATION
0.100
6
LEAD TIP TO TIP
PKG WIDTH
GENERAL TOLERANCE.
DISTANCE
ANGLE
7
E1
L
2.5°
8
FOOT LENGTH
2
3
MATTE FINISH ON PACKAGE BODY SURFACE
EXCEPT EJECTION AND PIN 1 MARKING.
Ra 0.8~2.0um
9
L1
T
LEAD LENGTH
1
1
1
10
11
12
13
14
15
16
17
FRAME THICKNESS
FRAME BASE METAL THICKNESS
FOOT ANGLE
0.170 0.060
0.152 0.040
0°~7°
ALL MOLDED BODY SHARP CORNER RADII
UNLESS OTHERWISE SPECIFIED.
MAX. R0.200
T1
a
b
4
5
6
PACKAGE/LEADFRAME MISALIGNMENT ( X, Y ):
TOP/BTM PACKAGE MISALIGNMENT ( X, Y ):
MAX. 0.127
MAX. 0.127
1
1
b
LEAD WIDTH
0.220 0.050
0.200 0.030
0.500 BASE
0.100
b1
e
LEAD BASE METAL WIDTH
LEAD PITCH
DRAWING DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION
OR CUTTING BURR.
ccc
ddd
FOOT COPLANARITY
FOOT POSITION
2
7
COMPLIANT TO JEDEC STANDARD:
MS-022
0.100
b1
1
SECTION A-A
Drawing #: MDP0055
Rev: 1
PACKAGE OUTLINE DRAWING
14 x 20 mm 128 LEAD MQFP (with or without Heat spreader)
DROP IN HEAT SPREADER
4 STAND POINTS EXPOSED
Date: 09/26/05
Units: mm
3.2 mm FOOTPRINT
SOLUTIONS IN SILICON
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN8218.3
29
March 8, 2006
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