X5165S8-2.7A [INTERSIL]
CPU Supervisor with 16Kbit SPI EEPROM Description; CPU监控与16Kbit的SPI EEPROM，说明
| 型号： | X5165S8-2.7A |
| 厂家： | 
Intersil |
| 描述： | CPU Supervisor with 16Kbit SPI EEPROM Description |
| 文件： | 总20页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X5163, X5165
®
Data Sheet
May 16, 2005
FN8128.1
CPU Supervisor with 16Kbit SPI EEPROM
Description
Features
• Selectable watchdog timer
• Low VCC detection and reset assertion
- Five standard reset threshold voltages
- Re-program low VCC reset threshold voltage using
special programming sequence
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
- Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a volatile
flag bit
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval, the
device activates the RESET/RESET signal. The user selects
the interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
• 16Kbits of EEPROM
• Built-in inadvertent write protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system when
Lock™ protection
- In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
V
CC falls below the minimum VCC trip point. RESET/RESET is
asserted until VCC returns to proper operating level and
stabilizes. Five industry standard VTRIP thresholds are
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom requirements
or to fine-tune the threshold for applications requiring higher
precision.
• Minimize EEPROM programming time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply operation
• Available packages
- 14-lead TSSOP, 8-lead SOIC
Pinouts
14-LEAD TSSOP
X5163, X5165
8-LEAD SOIC/PDIP
X5163, X5165
CS/WDI
V
1
14
CC
SO
NC
RESET/RESET
2
3
13
12
V
1
8
CS/WDI
SO
CC
NC
NC
NC
SCK
SI
2
3
7
6
RESET/RESET
SCK
NC
NC
WP
4
5
6
7
11
10
9
X5163, X5165
WP
V
SS
4
5
SI
V
SS
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X5163, X5165
Block Diagram
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
RESET/RESET
SI
Data
Register
Status
Register
SO
X5163 = RESET
X5165 = RESET
Command
Decode &
Control
Reset &
Watchdog
Timebase
SCK
4K Bits
4K Bits
CS/WDI
Logic
VCC Threshold
Reset Logic
8K Bits
Power-on and
Low Voltage
Reset
VCC
+
-
Generation
VTRIP
Pin Description
PIN
(SOIC/PDIP)
PIN TSSOP
NAME
FUNCTION
1
1
CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any
operation after power-up, a HIGH to LOW transition on CS is required
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET/RESET going active.
2
3
2
6
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
4
5
7
8
VSS
SI
Ground
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
6
7
9
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
13
RESET/ Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
RESET whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 200ms. RESET/
RESET goes active if the Watchdog Timer is enabled and CS remains either HIGH or LOW longer
than the selectable Watchdog time out period. A falling edge of CS will reset the Watchdog Timer.
RESET/RESET goes active on power-up at 1V and remains active for 200ms after the power
supply stabilizes.
8
14
VCC
NC
Supply Voltage
3-5,10-12
No internal connections
FN8128.1
2
May 16, 2005
X5163, X5165
To set the new VTRIP voltage, apply the desired VTRIP
Principles Of Operation
Power-on Reset
threshold to the VCC pin and tie the CS/WDI pin and the WP
pin HIGH. RESET and SO pins are left unconnected. Then
apply the programming voltage VP to both SCK and SI and
pulse CS/WDI LOW then HIGH. Remove VP and the
sequence is complete.
Application of power to the X516, /X5165 activates a Power-
on Reset Circuit. This circuit goes active at 1V and pulls the
RESET/RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. When VCC
exceeds the device VTRIP value for 200ms (nominal) the
circuit releases RESET/RESET, allowing the processor to
begin executing code.
CS
V
P
SCK
SI
Low Voltage Monitoring
During operation, the X5163, X5165 monitors the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
V
P
FIGURE 1. SET VTRIP VOLTAGE
Resetting the V
Voltage
TRIP
Watchdog Timer
This procedure sets the VTRIP to a “native” voltage level. For
example, if the current VTRIP is 4.4V and the VTRIP is reset,
the new VTRIP is something less than 1.7V. This procedure
must be used to set the voltage to a lower value.
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits, or
they may be “locked” by tying the WP pin LOW and setting
the WPEN bit HIGH.
To reset the VTRIP voltage, apply a voltage between 2.7 and
5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin, AND
THE SCK pin HIGH. RESET and SO pins are left
unconnected. Then apply the programming voltage VP to the
SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove VP
and the sequence is complete.
V
Threshold Reset Procedure
CC
The X5163, X5165 has a standard VCC threshold (VTRIP
)
CS
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard VTRIP is not exactly right, or for higher precision in
the VTRIP value, the X5163, X5165 threshold may be
adjusted.
V
CC
SCK
SI
V
P
Setting the V
Voltage
TRIP
This procedure sets the VTRIP to a higher voltage value. For
example, if the current VTRIP is 4.4V and the new VTRIP is
4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessary
to reset the trip point before setting the new value.
FIGURE 2. RESET VTRIP VOLTAGE
FN8128.1
3
May 16, 2005
X5163, X5165
V
PROGRAMMING
TRIP
EXECUTE
RESET V
TRIP
SEQUENCE
SET V = V APPLIED =
CC
CC
DESIRED V
TRIP
EXECUTE
SET V
SEQUENCE
NEW V APPLIED =
NEW V APPLIED =
CC
CC
TRIP
OLD V APPLIED + ERROR
OLD V APPLIED - ERROR
CC
CC
EXECUTE
APPLY 5V TO V
CC
RESET V
TRIP
SEQUENCE
DECREMENT V
CC
(V = V - 50MV)
CC
CC
NO
RESET PIN
GOES ACTIVE?
YES
ERROR > -EMAX
ERROR > EMAX
MEASURED V
–
TRIP
DESIRED V
TRIP
ERROR < EMAX
DONE
EMAX = MAXIMUM DESIRED ERROR
FIGURE 3. VTRIP PROGRAMMING SEQUENCE FLOW CHART
V
P
4.7K
NC
X5163, X5165
4.7K
RESET
1
2
3
4
8
7
6
5
NC
NC
V
TRIP
+
ADJ.
PROGRAM
RESET V
TRIP
10K
10K
TEST V
TRIP
SET V
TRIP
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
FN8128.1
4
May 16, 2005
X5163, X5165
Write Enable Latch
SPI Serial Memory
The device contains a Write Enable Latch. This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 7). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.
The memory portion of the device is a CMOS Serial EEPROM
array with Intersil’s block lock protection. The array is
internally organized as x 8. The device features a Serial
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
7
6
5
4
3
2
1
0
WPEN
FLB
WD1
WD0
BL1
BL0
WEL
WIP
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
WREN
INSTRUCTION FORMAT*
0000 0110
OPERATION
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
SFLB
0000 0000
WRDI/RFLB
RSDR
0000 0100
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
0000 0101
WRSR
0000 0001
Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
READ
0000 0011
WRITE
0000 0010
NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
TABLE 2. BLOCK PROTECT MATRIX
WREN CMD
STATUS REGISTER
DEVICE PIN
BLOCK
BLOCK
STATUS REGISTER
WPEN, BL0, BL1, WD0,
WD1
WEL
WPEN
WP#
PROTECTED BLOCK UNPROTECTED BLOCK
0
1
1
1
X
1
0
X
X
0
X
1
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Protected
Writable
Writable
FN8128.1
May 16, 2005
5
X5163, X5165
The Write Enable Latch (WEL) bit indicates the Status of
STATUS REGISTER BITS
WATCHDOG TIME OUT
(TYPICAL)
the Write Enable Latch. When WEL = 1, the latch is set
HIGH and when WEL = 0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
WD1
WD0
1
1
0
1
200 milliseconds
disabled
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of
the array that is block lock protected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.
The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The Flag bit is automatically reset upon power-
up. This flag can be used by the system to determine
whether a reset occurs as a result of a watchdog time out or
power failure.
STATUS
The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP pin to
provide an In-Circuit Programmable ROM function (Table
2). WP is LOW and WPEN bit programmed HIGH disables
all Status Register Write Operations.
REGISTER BITS
ARRAY ADDRESSES PROTECTED
BL1
0
BL0
0
X516X
None
0
1
$0600-$07FF
$0400-$07FF
$0000-$07FF
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog bits
from inadvertent corruption.
1
0
1
1
In the locked state (Programmable ROM Mode) the WP pin
is LOW and the nonvolatile bit WPEN is “1”. This mode
disables nonvolatile writes to the device’s Status Register.
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time Out Period. These nonvolatile bits are
programmed with the WRSR instruction.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress will
not stop this write operation, but the operation disables
subsequent write attempts to the Status Register.
STATUS REGISTER BITS
WATCHDOG TIME OUT
WD1
WD0
(TYPICAL)
1.4 seconds
0
0
0
1
600 milliseconds
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
SI
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
FIGURE 5. READ EEPROM ARRAY SEQUENCE
FN8128.1
6
May 16, 2005
X5163, X5165
When WP is HIGH, all functions, including nonvolatile
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the page and overwrite any data that may
have been previously written.
writes to the Status Register operate normally. Setting the
WPEN bit in the Status Register to “0” blocks the WP pin
function, allowing writes to the Status Register when WP is
HIGH or LOW. Setting the WPEN bit to “1” while the WP pin
is LOW activates the Programmable ROM mode, thus
requiring a change in the WP pin prior to subsequent Status
Register changes. This allows manufacturing to install the
device in a system with WP pin grounded and still be able
to program the Status Register. Manufacturing can then
load Configuration data, manufacturing time and other
parameters into the EEPROM, then set the portion of
memory to be protected by setting the block lock bits, and
finally set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought HIGH
at any other time, the write operation will not be completed
(Figure 8).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 9). Data bits 0 and
1 must be “0”.
Read Sequence
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address. After
the READ opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The address
is automatically incremented to the next higher address after
each byte of data is shifted out. When the highest address is
reached, the address counter rolls over to address $0000
allowing the read cycle to be continued indefinitely. The read
operation is terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 5).
While the write is in progress following a Status Register or
EEPROM Sequence, the Status Register may be read to
check the WIP bit. During this time the WIP bit will be high.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The Write Enable Latch is reset.
• The Flag Bit is reset.
To read the Status Register, the CS line is first pulled low to
select the device followed by the 8-bit RDSR instruction. After
the RDSR opcode is sent, the contents of the Status Register
are shifted out on the SO line. Refer to the Read Status
Register Sequence (Figure 6).
• Reset Signal is active for tPURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
Write Sequence
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 7). CS is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS must then be taken HIGH. If the
user continues the Write Operation without taking CS HIGH
after issuing the WREN instruction, the Write Operation will be
ignored.
• A WREN instruction must be issued to set the Write Enable
Latch.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
FN8128.1
7
May 16, 2005
X5163, X5165
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
FIGURE 7. WRITE ENABLE LATCH SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
INSTRUCTION
16 BIT ADDRESS
DATA BYTE 1
3
15 14 13
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
DATA BYTE 2
DATA BYTE 3
DATA BYTE N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
FIGURE 8. WRITE SEQUENCE
FN8128.1
8
May 16, 2005
X5163, X5165
CS
0
1
2
3
4
5
6
7
8
9
6
10 11 12 13 14 15
SCK
INSTRUCTION
DATA BYTE
5
4
3
2
1
0
7
SI
HIGH IMPEDANCE
SO
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM LWO TO
HIGH
WILL CHANGE
FROM LWO TO
HIGH
MAY CHANGE
WILL CHANGE
FROM HIGH TO FROM HIGH TO
LOW
LOW
DON’T CARE:
CHANGES
ALLWOED
CHANGING:
STATE NOT
KNOWN
N/A
CENTER LINE
IS HIGH
IMPEDANCE
FN8128.1
9
May 16, 2005
X5163, X5165
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Temperature under bias. . . . . . . . . . . . . . . . . . . . . . . .-65 to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150°C
Voltage on any pin with
respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +7V
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Specifications Over operating conditions unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
VCC Write Current (Active)
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO =
Open
5
mA
ICC2
VCC Read Current (Active)
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO =
Open
0.4
mA
ISB1
ISB2
ISB3
ILI
VCC Standby Current WDT = OFF CS = VCC, VIN = VSS or VCC, VCC = 5.5V
1
50
µA
µA
µA
µA
µA
V
VCC Standby Current WDT = ON
VCC Standby Current WDT = ON
Input Leakage Current
Output Leakage Current
Input LOW Voltage
CS = VCC, VIN = VSS or VCC, VCC = 5.5V
CS = VCC, VIN = VSS or VCC, VCC = 3.6V
VIN = VSS to VCC
20
0.1
0.1
10
ILO
VOUT = VSS to VCC
10
(1)
VIL
-0.5
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
Input HIGH Voltage
VCC x 0.7
V
VOL1
VOL2
VOL3
VOH1
VOH2
VOH3
VOLS
Output LOW Voltage
VCC > 3.3V, IOL = 2.1mA
2V < VCC ≤ 3.3V, IOL = 1mA
VCC ≤ 2V, IOL = 0.5mA
V
Output LOW Voltage
0.4
V
Output LOW Voltage
0.4
V
Output HIGH Voltage
VCC > 3.3V, IOH = –1.0mA
2V < VCC ≤ 3.3V, IOH = –0.4mA
VCC ≤ 2V, IOH = –0.25mA
VCC - 0.8
VCC - 0.4
VCC - 0.2
V
Output HIGH Voltage
V
Output HIGH Voltage
V
Reset Output LOW Voltage
I
OL = 1mA
0.4
V
Capacitance T = +25°C, f = 1MHz, V = 5V
A
CC
SYMBOL
TEST
MAX.
UNIT
CONDITIONS
VOUT = 0V
VIN = 0V
(2)
COUT
Output Capacitance (SO, RESET, RESET)
Input Capacitance (SCK, SI, CS, WP)
8
6
pF
pF
(2)
CIN
NOTES:
1. VIL min. and VIH max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
FN8128.1
May 16, 2005
10
X5163, X5165
5V
5V
A.C. Test Conditions
Input pulse levels
VCC x 0.1 to VCC x 0.9
10ns
3.3kΩ
1.64kΩ
Input rise and fall times
Input and output timing level
V
CC x0.5
OUTPUT
RESET/RESET
1.64kΩ
30pF
100pF
FIGURE 10. EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
AC Electrical Specifications Serial Input Timing (Over operating conditions unless otherwise specified.)
2.7-5.5V
SYMBOL
fSCK
tCYC
tLEAD
tLAG
tWH
PARAMETER
MIN
0
MAX
UNIT
MHz
ns
Clock Frequency
Cycle Time
2
500
250
250
200
200
50
CS Lead Time
CS Lag Time
ns
ns
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
ns
tWL
ns
tSU
ns
tH
50
ns
(3)
tRI
100
100
ns
(3)
tFI
ns
tCS
500
ns
(4)
tWC
10
ms
t
CS
CS
t
t
LAG
LEAD
SCK
t
t
t
t
FI
SU
H
RI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
FIGURE 11. SERIAL INPUT TIMING
FN8128.1
May 16, 2005
11
X5163, X5165
AC Electrical Specifications Serial Output Timing(Over operating conditions unless otherwise specified.)
2.7-5.5V
SYMBOL
fSCK
tDIS
PARAMETER
MIN
MAX
2
UNIT
MHz
ns
Clock Frequency
0
Output Disable Time
Output Valid from Clock Low
Output Hold Time
250
200
tV
ns
tHO
0
ns
(3)
tRO
Output Rise Time
100
100
ns
(3)
tFO
Output Fall Time
ns
NOTES:
3. This parameter is periodically sampled and not 100% tested.
4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
CS
t
t
t
LAG
CYC
WH
SCK
SO
SI
t
t
t
t
DIS
V
HO
WL
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
LSB IN
TABLE 3. SERIAL OUTPUT TIMING
V
V
TRIP
TRIP
V
CC
t
PURST
0 Volts
t
F
t
PURST
t
RPD
t
R
RESET (X5163)
RESET (X5165)
TABLE 4. POWER-UP AND POWER-DOWN TIMING
FN8128.1
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May 16, 2005
X5163, X5165
RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VTRIP
Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A
Reset Trip Point Voltage, X5163, X5165
Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A
Reset Trip Point Voltage, X5163-2.7, X5165-2.7
4.5
4.63
4.38
2.92
2.63
4.75
4.5
3.0
2.7
V
4.25
2.85
2.55
VTH
VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage)
20
mV
ms
ns
µs
µs
V
tPURST
Power-up Reset Time Out
VCC Detect to Reset/Output
VCC Fall Time
100
200
280
500
(5)
tRPD
(5)
tF
100
100
1
(5)
tR
VCC Rise Time
VRVALID
Reset Valid VCC
NOTES:
5. This parameter is periodically sampled and not 100% tested.
6. Typical values not tested.
CS/WDI
t
CST
RESET
t
t
t
t
RST
WDO
RST
WDO
RESET
FIGURE 12. CS/WDI VS. RESET/RESET TIMING
RESET/RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tWDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
200
600
1.4
300
800
2
ms
ms
sec
tCST
tRST
CS Pulse Width to Reset the Watchdog
Reset Time Out
400
100
ns
200
300
ms
FN8128.1
May 16, 2005
13
X5163, X5165
t
THD
V
V
CC
TRIP
t
TSU
t
RP
t
t
VPH
t
P
VPS
CS
t
t
t
VPO
VPH
VPS
V
P
SCK
SI
V
t
P
VPO
FIGURE 13. VTRIP SET CONDITIONS
t
THD
V
TRIP
V
CC
t
TSU
t
RP
t
t
VP1
t
P
VPS
CS
t
t
t
VPS
VPO
VPH
V
CC
SCK
SI
V
t
P
VPO
FIGURE 14. VTRIP RESET CONDITIONS
FN8128.1
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May 16, 2005
X5163, X5165
V
Programming Specifications: V = 1.7-5.5V; Temperature = 0°C to 70°C
CC
TRIP
PARAMETER
tVPS
tVPH
tP
DESCRIPTION
MIN
1
MAX
UNIT
µs
SCK VTRIP Program Voltage Setup time
SCK VTRIP Program Voltage Hold time
VTRIP Program Pulse Width
1
µs
1
µs
tTSU
tTHD
tWC
VTRIP Level Setup time
10
10
µs
VTRIP Level Hold (stable) time
VTRIP Write Cycle Time
ms
ms
ms
ms
V
10
tRP
VTRIP Program Cycle Recovery Period (Between successive programming cycles)
SCK VTRIP Program Voltage Off time before next cycle
Programming Voltage
10
0
tVPO
VP
15
18
5.0
VTRAN
Vta1
VTRIP Programed Voltage Range
1.7
-0.1
-25
-25
-25
V
Initial VTRIP Program Voltage accuracy (V
applied-VTRIP) (Programmed at 25°C.)
+0.4
+25
+25
+25
V
CC
Subsequent VTRIP Program Voltage accuracy [(V
Vta2
applied-Vta1)-VTRIP] (Programmed at 25°C.)
mV
mV
mV
CC
Vtr
VTRIP Program Voltage repeatability (Successive program operations.) (Programmed at 25°C.)
Vtv
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
V
TRIP programming parameters are periodically sampled and are not 100% tested.
FN8128.1
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May 16, 2005
X5163, X5165
18
16
1.9
WATCHDOG TIMER ON (V = 5V)
CC
1.8
1.7
1.6
14
12
10
8
-40°C
WATCHDOG TIMER ON (V = 5V)
CC
25°C
1.5
1.4
90°C
6
1.3
1.2
1.1
1
4
2
0
WATCHDOG TIMER OFF (V = 3V, 5V)
CC
-40
25
90
1.7
2.4
3.1
3.8
4.5
5.2
TEMP (°C)
VOLTAGE
FIGURE 15. VCC SUPPLY CURRENT VS. TEMPERATURE (ISB
)
FIGURE 16. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 1)
5.025
0.8
V
= 5V
TRIP
5.000
0.75
4.975
3.525
3.500
-40°C
0.7
0.65
0.6
25°C
V
V
= 3.5V
= 2.5V
TRIP
TRIP
90°C
3.475
0.55
0.5
2.525
2.500
2.475
0.45
1.7
2.4
3.1
3.8
4.5
5.2
0
25
85
VOLTAGE
TEMPERATURE
FIGURE 18. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 0)
FIGURE 17. VTRIP vs. Temperature (programmed at 25°C)
205
200
195
190
185
180
175
170
205
200
195
-40°C
25°C
190
185
90°C
180
175
170
165
165
160
160
1.7
2.4
3.1
VOLTAGE
3.8
4.5
5.2
-40
25
90
DEGREES °C
FIGURE 19. tPURST VS. TEMPERATURE
FIGURE 20. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1)
FN8128.1
May 16, 2005
16
X5163, X5165
Packaging Information
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" TYPICAL
X 45°
0.050"
TYPICAL
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
FOOTPRINT
8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8128.1
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May 16, 2005
X5163, X5165
Packaging Information
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
GAGE PLANE
0° - 8°
SEATING PLANE
.019 (.50)
.029 (.75)
DETAIL A (20X)
.031 (.80)
.041 (1.05)
SEE DETAIL “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8128.1
18
May 16, 2005
X5163, X5165
Ordering Information
VTRIP
OPERATING TEMPERATURE
RANGE
PART NUMBER RESET
(ACTIVE LOW)
PART NUMBER RESET
(ACTIVE HIGH)
VCC RANGE
RANGE
PACKAGE
4.5-5.5V
4.5.4.75
8-Pin PDIP
0°C - 70°C
-40°C - 85°C
0°C - 70°C
-40°C - 85°C
0°C - 70°C
-40°C - 85°C
0°C - 70°C
-40°C - 85°C
0°C - 70°C
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
0°C - 70°C
-40°C - 85°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
0°C - 70°C
-40°C - 85°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
X5163P-4.5A
X5163PI-4.5A
X5163S8-4.5A
X5163S8I-4.5A
X5163V14-4.5A
X5163V14I-4.5A
X5163P
X5165PI-4.5A
X5165S8-4.5A
X5165S8I-4.5A
X5165V14-4.5A
X5165V14I-4.5A
X5165P
8L SOIC
14L TSSOP
8-Pin PDIP
8L SOIC
4.5-5.5V
4.25.4.5
X5163PI
X5165PI
X5163S8
X5165S8
X51638S8
X5163S8T1
X5165S8T1
X5163S8T2
X5163S8I
X5165S8I
X5165S8IT1
X5165V14
X5163S8IT1
X5163V14
14L TSSOP
X5163V14T1
X5163V14I
X5165V14T1
X5165V14I
X5163V14IT1
X5163P-2.7A
X5163PI-2.7A
X5163S8-2.7A
X5163S8-2.7AT1
X5163S8I-2.7A
X5163S8I-2.7AT1
X5163V14-2.7A
X5163V14I-2.7A
X5163V14I-2.7T1
X5163P-2.7
X5165V14IT1
X5165P-2.7A
X5165PI-2.7A
X5165S8-2.7A
2.7-5.5V
2.85-3.0
8-Pin PDIP
8L SOIC
X5165S8I-2.7A
14L TSSOP
X5165V14-2.7A
X5165V14I-2.7A
X5165V14I-2.7T1
X5165P-2.7
2.7-5.5V
2.55-2.7
8-Pin PDIP
8L SOIC
X5163PI-2.7
X5163S8-2.7
X5163S8-2.7T1
X5163S8I-2.7
X5165PI-2.7
X5165S8-2.7
X5165S8-2.7T1
X5165S8I-2.7
X5165S8I-2.7T1
X5165V14-2.7
X5165V14-2.7T1
X5165V14I-2.7
14L TSSOP
X5163V14-2.7
X5163V14-2.7T1
X5163V14I-2.7
FN8128.1
May 16, 2005
19
X5163, X5165
Part Mark Information
X5163, X51665
Blank = 8-Lead SOIC
V = 14 Lead TSSOP
W
X
Blank = 5V ±10%, 0°C to +70°C, VTRIP = 4.25-4.5
A = 5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75
I = 5V ±10%, -40°C to +85°C, VTRIP = 4.25-4.5
IA = 5V ±10%, -40°C to +85°C, VTRIP = 4.5-4.75
F = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.55-2.7
FA = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.85-3.0
G = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.55-2.7
GA = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.85-3.0
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8128.1
20
May 16, 2005
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